January 2007 Rev 3 1/20
1
TDA7348
Digitally controlled audio processor
Features
Input multiplexer
Three stereo and one mono inputs
Selectable input gain for optimal
adaptation to different sources
Volume control in 0.3db steps including gain
up to 20dB
Zero crossing mute and direct mute
Pause detector with programmable threshold
Soft mute controlled by software or hardware
PIN
Bass and treble control
Four speaker attenuators
Four independent speakers control in
1.25dB steps for balance and fader
facilities
Independent mute function
All functions programmable via serial I
2
C bus
Description
The TDA7348 is an upgrade of the TDA7318
audioprocessor.
Thanks to the used BIPOLAR/CMOS technology,
very low distortion, low noise and DC-stepping
are obtained. Due to a highly linear signal
processing, using CMOS-switching techniques
instead of standard bipolar multipliers, very low
distortion and very low noise are obtained Several
new features like softmute, zero-crossing mute
and pause detector are implemented.
The Soft Mute function can be activated in two
ways, either via the serial bus (bit D0, Mute Byte),
or directly on pin 22 through an I/O line of the
microcontroller
Very low DC stepping is obtained by use of a
BICMOS technology.
SO-28
Order codes
Part number Package Packing
TDA7348D SO-28 Tube
TDA7348D013TR SO-28 Tape and reel
E-TDA7348D (1) SO-28 Tube
E-TDA7348D013TR (1) SO-28 Tape and reel
1. This device is Pb-free Ecopack , see Chapter 5 Package information.
www.st.com
Obsolete Product(s) - Obsolete Product(s)
Contents TDA7348
2/20
Contents
1 Block diagram and PIN connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3I
2C BUS interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1 Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2 Start and stop conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.3 Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.5 Transmission without acknowledgement . . . . . . . . . . . . . . . . . . . . . . . . . 10
4 Software specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1 Interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2 Auto increment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.3 Transmitted data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.4 Data byte specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Obsolete Product(s) - Obsolete Product(s)
TDA7348 List of tables
3/20
List of tables
Table 1. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 3. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 4. Quick reference data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 5. Subaddress (receive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 6. Send mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 7. Input Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 8. Loudness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 9. Mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 10. Speaker attenuators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 11. Bass/Treble. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 12. Volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 13. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Obsolete Product(s) - Obsolete Product(s)
List of figures TDA7348
4/20
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. PIN connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. Data validity on the I2C BUS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 4. Timing diagram of I2C BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 5. Acknowledge on the I2C BUS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 6. SO-28 mechanical, data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Obsolete Product(s) - Obsolete Product(s)
TDA7348 Block diagram and PIN connections
5/20
1 Block diagram and PIN connections
Figure 1. Block diagram
Figure 2. PIN connections
14
13
11
L1
L2
L1
L2
L4
10R1
R2
R1
R2
R4
9
INPUT
SELECTOR
+ GAIN
LEFT
INPUTS
RIGHT
INPUTS
SUPPLY
2
31
ZERO
CROSS +
MUTE
SOFT
MUTE
OUT(L) IN(L)
17 16
VOL
1, 2
ZERO
CROSS +
MUTE
VOL
1, 2
BASS
BASS
TREBLE
TREBLE
10μF
7
OUT(R)CREF IN(R)
6
BOUT(L) BIN(L)
19 18
BOUT(R) BIN(R)
21 20 5
TREBLE(R)
SPKR
ATT
MUTE
SPKR
ATT
MUTE
SPKR
ATT
MUTE
SPKR
ATT
MUTE
TREBLE(L)
4
24
28
27
25
26
23
OUT
LEFT FRONT
OUT
LEFT REAR
SCL
SDA
OUT
RIGHT FRONT
OUT
RIGHT REAR
D93AU100B
BUSSERIAL BUS DECODER + LATCHES
3 x
1μF
C1
C2
C4
C6
C5
AGND
V
S
C8
C10 2.2μF
C9 2.2μF
RB
C11
100nF
C12
100nF
R1
4.7K
C13
2.7nF
C14
100nF C15
100nF
C16
2.7nF
R2
4.7K
15
CSM
47nF
RB
CSM
12 L3
C3
L3
R3 R38
C7
3 x
1μF
22
SM
IN(R)
OUT(R)
IN R3
IN R2
IN R1
IN L3
AM MONO
IN L2
IN L1
1
3
2
4
5
6
7
8
9
CSM
IN(L)
OUT(L)
BOUT(L)
BIN(L)
BIN(R)
BOUT(R)
SM
OUT RR23
22
21
20
19
17
18
16
15
D94AU099
10
11
12
13
14
28
27
26
25
24
CREF
VS
GND
L
R OUT LR
OUT RF
OUT LF
SDA
SCL
TREBLE
BUS
INPUTS
BASS
Obsolete Product(s) - Obsolete Product(s)
Electrical characteristics TDA7348
6/20
2 Electrical characteristics
Table 1. Electrical characteristics
V
S
= 9V; R
L
= 10KΩ; Rg = 50Ω; T
amb
= 25°C; all controls flat (G = 0.3dB step
0dB); f = 1KHz. Refer to the test circuit, unless otherwise specified.
Symbol Parameter Test Condition Min. Typ. Max. Unit
Input selector
R
I
Input resistance 70 100 130 KΩ
V
CL
Clipping level d 0.3% 2.1 2.6 V
RMS
S
I
Input separation 80 100 dB
R
L
Output load resistance 2 KΩ
G
I MIN
Minimum input gain -0.75 0 0.75 dB
G
I MAX
Maximum input gain 10.25 11.25 12.25 dB
G
step
Step resolution 2.75 3.75 4.75 dB
e
N
Input noise 20Hz to 20 KHz unweighted 2.3 μV
V
DC
DC steps Adiacent gain steps 1.5 10 mV
G
IMIN
to G
IMAX
3 mV
Volume control (1 + 2)
R
I
Input resistance 35 50 KΩ
G
MAX
Maximum gain 18.75 20 21.25 dB
A
MAX
Maximum attenuation 78.45 dB
A
STEPC
Step resolution coarse
attenuation 0.51.252.0 dB
A
STEPF
Step resolution fine
attenuation 0.11 0.31 0.51 dB
E
A
Attenuation set error G = 20 to -20dB -1.25 0 1.25 dB
G = -20 to -58dB -3 2 dB
E
t
Tracking error 2 dB
V
DC
DC steps Adiacent attenuation steps -3 0 3 mV
From 0dB to A
MAX
0.5 5 mV
Zero crossing mute
V
TH
Zero crossing threshold
WIN = 11 20 mV
WIN = 10 40 mV
WIN = 01 80 mV
WIN = 00 160 mV
A
MUTE
Mute attenuation 80 100 dB
V
DC
DC step 0dB to Mute 0 3 mV
Obsolete Product(s) - Obsolete Product(s)
TDA7348 Electrical characteristics
7/20
Soft mute
A
MUTE
Mute attenuation 45 60 dB
T
DON
ON delay time C
CSM
= 22nF; 0 to -20dB; I =
I
MAX
0.7 1 1.7 ms
C
CSM
= 22nF; 0 to -20dB; I =
I
MIN
20 35 55 ms
T
DOFF
OFF delay time V
CSM
= 0V; I = I
MAX
25 50 75 μA
V
CSM
= 0V; I = I
MIN
1 μA
V
THSM
Soft mute threshold 1.5 2.5 3.5 V
R
INT
Pull-up resistor (pin 22) 35 50 65 KΩ
V
SMH
(pin 22) level high Soft Mute active 3.5 V
V
SML
(pin 22) level low 1 V
Bass control
B
BOOST
Max bass boost 15 18 20 dB
B
CUT
Max bass cut -8.5 -10 -11.5 dB
A
step
Step resolution 1 2 3 dB
R
g
Internal feedback resistance 45 65 85 KΩ
Treble control
C
RANGE
Control range ±13 ±14 ±15 dB
A
step
Step resolution 1 2 3 dB
Speaker attenuators
C
RANGE
Control range 35 37.5 40 dB
Astep Step resolution 0.5 1.25 2.0 dB
A
MUTE
Output mute attenuation Data word = XXX11111 80 100 dB
E
A
Attenuation set error 1.25 dB
V
DC
DC steps Adjacent attenuation steps 0 3 mV
Audio output
V
clip
Clipping level d = 0.3% 2.1 2.6 Vrms
R
L
Output load resistance 2 KΩ
R
O
Output impedance 30 100 W
V
DC
DC voltage level 3.5 3.8 4.1 V
General
V
CC
Supply voltage 6 9 10.2 V
Table 1. Electrical characteristics (continued)
V
S
= 9V; R
L
= 10KΩ; Rg = 50Ω; T
amb
= 25°C; all controls flat (G = 0.3dB step
0dB); f = 1KHz. Refer to the test circuit, unless otherwise specified.
Symbol Parameter Test Condition Min. Typ. Max. Unit
Obsolete Product(s) - Obsolete Product(s)
Electrical characteristics TDA7348
8/20
I
CC
Supply current 5 10 15 mA
PSRR Power supply rejection ratio f = 1KHz 60 80 dB
B = 20 to 20kHz "A" weighted 65 dB
eNO Output noise
Output Muted (B = 20 to
20kHz flat) 2.5 μV
All Gains 0dB (B = 20 to
20kHz flat) 5 15 μV
E
t
Total tracking error A
V
= 0 to -20dB 0 1 dB
A
V
= -20 to -60dB 0 2 dB
S/N Signal to noise ratio All Gains = 0dB; V
O
= 1Vrms 106 dB
S
C
Channel separation 80 100 dB
d Distortion V
in
= 1V 0.01 0.08 %
Bus inputs
V
IL
Input low voltage 1 V
V
lN
Input high voltage 3 V
I
lN
Input current V
IN
= 0.4V -5 5 μA
V
O
Output voltage SDA
acknowledge I
O
= 1.6mA 0.4 0.8 V
Table 2. Absolute maximum ratings
Symbol Parameter Value Unit
V
S
Operating supply voltage 10.5 V
T
amb
Operating ambient temperature -40 to 85 °C
T
stg
Storage temperature range -55 to 150 °C
Table 3. Thermal data
Symbol Parameter SO28 Unit
R
th j-amb
Thermal Resistance Junction pins 65 °C/W
Table 4. Quick reference data
Symbol Parameter Min. Typ. Max. Unit
VS Supply voltage 6 9 10.2 V
VCL Max. input signal handling 2.1 2.6 Vrms
THD Total harmonic distortion V = 1Vrms f = 1KHz 0.01 0.08 %
S/N Signal to noise ratio 106 dB
Table 1. Electrical characteristics (continued)
V
S
= 9V; R
L
= 10KΩ; Rg = 50Ω; T
amb
= 25°C; all controls flat (G = 0.3dB step
0dB); f = 1KHz. Refer to the test circuit, unless otherwise specified.
Symbol Parameter Test Condition Min. Typ. Max. Unit
Obsolete Product(s) - Obsolete Product(s)
TDA7348 Electrical characteristics
9/20
SC Channel separation f = 1KHz 100 dB
Volume control -
78.45 20 dB
Treble control 2dB step -14 +14 dB
Bass control 2dB step -10 +18 dB
Fader and balance control 1.25dB step -
38.75 0dB
Input gain 3.75dB step 0 11.2
5dB
Mute attenuation 100 dB
Table 4. Quick reference data (continued)
Symbol Parameter Min. Typ. Max. Unit
Obsolete Product(s) - Obsolete Product(s)
I2C BUS interface TDA7348
10/20
3 I2C BUS interface
Data transmission from microprocessor to the TDA7348 and vice-versa takes place through
the 2 wires of the I2C BUS interface, consisting of the two lines SDA and SCL (pull-up
resistors to the positive supply voltage must be externally connected).
3.1 Data validity
As shown in Figure 3., the data on the SDA line must be stable during the high period of the
clock. The HIGH and LOW state of the data line can only change when the clock signal on
the SCL line is LOW.
3.2 Start and stop conditions
As shown in Figure 4. a start condition is a HIGH to LOW transition of the SDA line while
SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is
HIGH.
A STOP conditions must be sent before each START condition.
3.3 Byte format
Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an
acknowledge bit. The MSB is transferred first.
3.4 Acknowledge
The master (microprocessor) puts a resistive HIGH level on the SDA line during the
acknowledge clock pulse (see Figure 5.). The peripheral (audioprocessor) that
acknowledges has to pull-down (LOW) the SDA line during the acknowledge clock pulse, so
that the SDA line is stable LOW during this clock pulse.
The audioprocessor which has been addressed has to generate an acknowledge after the
reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth
clock pulse time. In this case the master transmitter can generate the STOP information in
order to abort the transfer.
3.5 Transmission without acknowledgement
The microprocessor can use a simpler transmission, if it avoids detection of the
acknowledgement from the audio processor. It simply waits one clock pulse without
checking the slave acknowledgment, and sends the new data.
This approach of course is less protected from errors, increases the possibility of
interference, and decreases the immunity to noise.
Obsolete Product(s) - Obsolete Product(s)
TDA7348 I2C BUS interface
11/20
Figure 3. Data validity on the I2C BUS
Figure 4. Timing diagram of I2C BUS
Figure 5. Acknowledge on the I2C BUS
SDA
SCL
DATA LINE
STABLE, DATA
VALID
CHANGE
DATA
ALLOWED
D99AU1031
SCL
SDA
START
I
2
CBUS
STOP
D99AU1032
SCL 1
MSB
23789
SDA
START ACKNOWLEDGMENT
FROM RECEIVER
D99AU1033
Obsolete Product(s) - Obsolete Product(s)
Software specification TDA7348
12/20
4 Software specification
4.1 Interface protocol
The interface protocol comprises:
A start condition (s)
A chip address byte, (the LSB bit determines read/write transmission)
A subaddress byte.
A sequence of data (N-bytes + acknowledge)
A stop condition (P)
ACK = Acknowledge
S = Start
P = Stop
I = Auto Increment
X = Not used
Max clock speed 500kbits/s
4.2 Auto increment
If bit I in the subaddress byte is set to "1", the auto-increment of the subaddress is enabled
Chip address Subaddress Data 1 to data n
MSB LSB MSB LSB MSB LSB
S 1 000100R/WACK X XXIA3A2A1A0ACK DATA ACKP
Table 5. Subaddress (receive mode)
MSB LSB Function
X X X I A3 A2 A1 A0
0 0 0 0 Input selector
0 0 0 1 Loudness
0 0 1 0 Volume
0 0 1 1 Bass, Treble
0 1 0 0 Speaker attenuator LF
0 1 0 1 Speaker attenuator LR
0 1 1 0 Speaker attenuator RF
0 1 1 1 Speaker attenuator RR
1 0 0 0 Mute
Obsolete Product(s) - Obsolete Product(s)
TDA7348 Software specification
13/20
4.3 Transmitted data
ZM = Zero crossing muted (HIGH active)
SM = Soft mute activated (HIGH active)
X = Not used
The transmitted data is automatically updated after each ACK.
Transmission can be repeated without new chip address.
4.4 Data byte specification
X = not relevant; set to "1" during testing
For example to select the IN 2 input with a gain of 7.5dB the Data Byte is: X X 1 0 1 0 0 1
Table 6. Send mode
MSB LSB
X X X X X SM ZM X
Table 7. Input Selector
MSB LSB
Function
D7 D6 D5 D4 D3 D2 D1 D0
X X 1 0 0 0 not used
X X 1 0 0 1 IN 2
X X 1 0 1 0 IN 1
X X 1 0 1 1 AM mono
X X 1 1 0 0 not used
X X 1 1 0 1IN 3
X X 1 1 1 0 not allowed
X X 1 1 1 1 not allowed
X X 1 0 0 11.25dB gain
X X 1 0 1 7.5dB gain
X X 1 1 0 3.75dB gain
X X 1 1 1 0dB gain
Table 8. Loudness
MSB LSB
Function
D7 D6 D5 D4 D3 D2 D1 D0
X X X 1 0 0 0 0 0dB
X X X 1 0 0 0 1 -1.25dB
X X X 1 0 0 1 0 -2.5dB
Obsolete Product(s) - Obsolete Product(s)
Software specification TDA7348
14/20
For example to select -17.5dB attenuation, loudness OFF, the Data Byte is: X X X1 1 1 1 0
X X X 1 0 0 1 1 -3.75dB
X X X 1 0 1 0 0 -5dB
X X X 1 0 1 0 1 -6.25dB
X X X 1 0 1 1 0 -7.5dB
X X X 1 0 1 1 1 -8.75dB
X X X 1 1 0 0 0 -10dB
X X X 1 1 0 0 1 -11.25dB
X X X 1 1 0 1 0 -12.5dB
X X X 1 1 0 1 1 -13.75dB
X X X 1 1 1 0 0 -15dB
X X X 1 1 1 0 1 -16.25dB
X X X 1 1 1 1 0 -17.5dB
X X X 1 1 1 1 1 -18.75dB
Table 9. Mute
MSB LSB
Function
D7 D6 D5 D4 D3 D2 D1 D0
1 Soft mute on
0 1 Soft mute with fast slope (I = IMAX)
1 1 Soft mute with slow slope (I = IMIN)
1 Direct mute
0 1 Zero crossing mute on
0 0 Zero crossing mute off
(delayed until next zerocrossing)
1 Zero crossing mute and pause detector
reset
0 0 160mV ZC window threshold (WIN = 00)
0 1 80mV ZC window threshold (WIN = 01)
1 0 40mV ZC window threshold (WIN = 10)
1 1 20mV ZC window threshold (WIN = 11)
0 Non-symmetrical Bass Cut
1 Symmetrical Bass Cut
Table 8. Loudness (continued)
MSB LSB
Function
D7 D6 D5 D4 D3 D2 D1 D0
Obsolete Product(s) - Obsolete Product(s)
TDA7348 Software specification
15/20
An additional direct mute function is included in the speaker attenuators.
Note: Bass cut for very low frequencies should not be used at +16 & +18dB bass boost (DC gain)
For example an attenuation of 25dB on a selected output is given by: X X X1 0 1 0 0
Table 10. Speaker attenuators
MSB LSB
Speaker attenuator LF, LR, RF, RR
D7 D6 D5 D4 D3 D2 D1 D0
1.25dB step
X X X 0 0 0 0dB
X X X 0 0 1 -1.25dB
X X X 0 1 0 -2.5dB
X X X 0 1 1 -3.75dB
X X X 1 0 0 -5dB
X X X 1 0 1 -6.25dB
X X X 1 1 0 -7.5dB
X X X 1 1 1 -8.75dB
10dB step
X X X 0 0 0dB
X X X 0 1 -10dB
X X X 1 0 -20dB
X X X 1 1 -30dB
X X X 1 1 1 1 1 Speaker mute
Table 11. Bass/Treble
MSB LSB
Function
D7 D6 D5 D4 D3 D2 D1 D0
Treble step
0 0 0 0 -14dB
0 0 0 1 -12dB
0 0 1 0 -10dB
0 0 1 1 -8dB
0 1 0 0 -6dB
0 1 0 1 -4dB
0 1 1 0 -2dB
0 1 1 1 0dB
1 1 1 1 0dB
1 1 1 0 2dB
Obsolete Product(s) - Obsolete Product(s)
Software specification TDA7348
16/20
For example 12dB Treble and -8dB Bass give the following DATA BYTE: 0 0 1 1 1 0 0 1
1 1 0 1 4dB
1 1 0 0 6dB
1 0 1 1 8dB
1 0 1 0 10dB
1 0 0 1 12dB
1 0 0 0 14dB
BASS STEPS
0 0 1 0 -10dB
0 0 1 1 -8dB
0 1 0 0 -6dB
0 1 0 1 -4dB
0 1 1 0 -2dB
0 1 1 1 -0dB
1 1 1 1 -0dB
1 1 1 0 2dB
1 1 0 1 4dB
1 1 0 0 6dB
1 0 1 1 8dB
1 0 1 0 10dB
1 0 0 1 12dB
1 0 0 0 14dB
0 0 0 1 146B
0 0 0 0 18dB
Table 11. Bass/Treble (continued)
MSB LSB
Function
D7 D6 D5 D4 D3 D2 D1 D0
Obsolete Product(s) - Obsolete Product(s)
TDA7348 Software specification
17/20
For example to select -47.81dB volume the data byte is: 1 1 0 1 1 0 0 1
Power on RESET: All bytes set to 1 1 1 1 1 1 1 0
Table 12. Volume
MSB LSB
Function
D7 D6 D5 D4 D3 D2 D1 D0
0.31dB Fine attenuation steps
0 0 0dB
0 1 -0.31dB
1 0 -0.62dB
1 1 -0.94dB
1.25dB Coarse attenuation steps
0 0 0 0dB
0 0 1 -1.25dB
0 1 0 -2.5dB
0 1 1 -3.75dB
1 0 0 -5dB
1 0 1 -6.25dB
1 1 0 -7.5dB
1 1 1 -8.75dB
10dB Gain / attenuation steps
0 0 0 20dB
0 0 1 10dB
0 1 0 0dB
0 1 1 -10dB
1 0 0 -20dB
1 0 1 -30dB
1 1 0 -40dB
1 1 1 -50dB
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Package information TDA7348
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5 Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect. The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
Figure 6. SO-28 mechanical, data and package dimensions
SO-28
DIM. mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
A 2.65 0.104
a1 0.1 0.3 0.004 0.012
b 0.35 0.49 0.014 0.019
b1 0.23 0.32 0.009 0.013
C 0.5 0.020
c1 45° (typ.)
D 17.7 18.1 0.697 0.713
E 10 10.65 0.394 0.419
e 1.27 0.050
e3 16.51 0.65
F 7.4 7.6 0.291 0.299
L 0.4 1.27 0.016 0.050
S8° (max.)
OUTLINE AND
MECHANICAL DATA
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TDA7348 Revision history
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6 Revision history
Table 13. Document revision history
Date Revision Changes
14-Jan-2004 1Initial release.
21-Jun-2004 2 Technical migration from ST-PRESS to EDOCS DMS
26-Jan-20073 DIP28 package removed, block diagram changed, layout modified.
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TDA7348
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Obsolete Product(s) - Obsolete Product(s)