MITSUBISHI LSIs
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
MITSUBISHI
ELECTRIC
M5M5256DFP,VP,RV -10VLL,-12VLL,-15VLL,
-10VXL,-12VXL,-15VXL
'97.4.7
PACKAGE
M5M5256DFP : 28 pin 450 mil SOP
M5M5256DVP,RV : 28pin 8 X 13.4 mm TSOP
•Single +2.7~3.6V power supply
•No clocks, no refresh
•Data-Hold on +2.0V power supply
•Directly TTL compatible : all inputs and outputs
•Three-state outputs : OR-tie capability
•/OE prevents data contention in the I/O bus
•Common Data I/O
•Battery backup capability
•Low stand-by current··········0.05µA(typ.)
APPLICATION
Small capacity memory units
DESCRIPTION
The M5M5256DFP,VP,RV is 262,144-bit CMOS static RAMs
organized as 32,768-words by 8-bits which is fabricated using
high-performance 3 polysilicon CMOS technology. The use of
resistive load NMOS cells and CMOS periphery results in a high
density and low power static RAM. Stand-by current is small
enough for battery back-up application. It is ideal for the memory
systems which require simple interface.
Especially the M5M5256DVP,RV are packaged in a 28-pin thin
small outline package.Two types of devices are available,
M5M5256DVP(normal lead bend type package),
M5M5256DRV(reverse lead bend type package). Using both types of
devices, it becomes very easy to design a printed circuit board.
FEATURE
PIN CONFIGURATION (TOP VIEW)
1
12µA
(Vcc=3.6V)
(Vcc=3.6V)
2.4µA
(max) Stand-by
(max)
Active
(max)
Power supply current
Type
M5M5256DFP,VP,RV-10VLL
Access
time
100ns
20mA
M5M5256DFP,VP,RV-12VLL
M5M5256DFP,VP,RV-15VLL
120ns
150ns
M5M5256DFP,VP,RV-10VXL 100ns
M5M5256DFP,VP,RV-12VXL
M5M5256DFP,VP,RV-15VXL
120ns
150ns
2
(Vcc=3.0V,
Typical)
0.05µA
(Vcc=3.6V)
M5M5256DFP
1
A14 2
A12
4A6 5
A5 6
A4 7
A3 8A2 9A1 10
A0
3A7
11
DQ1 12
DQ2 13DQ3 14
GND
28 Vcc
26 A13
25 A8
24 A9
23 A11
21 A10
DQ8
18 DQ7
17 DQ6
16 DQ5
15 DQ4
27 /W
22 /OE
20 /S
19
M5M5256DVP
1A14
2A12
4 A6
5 A5
6 A4
7 A3
3A7
8A2 9
A1 10
A0 11
DQ112
DQ213DQ314
GND
Vcc28
A1326A825A924A11
23
/W
27
/OE
22 A10 21
DQ7 18
DQ6 17
DQ5 16
DQ415
/S 20
DQ8 19
M5M5256DRV
A14
A12
A6
A5
A4
A3
A7
A2
A1
A0
DQ1
DQ2
DQ3
GND
A10
DQ7
DQ6
DQ5
DQ4Vcc
A13
A8
A9
A11
/W
/OE /S
DQ8
Outline 28P2C-A (DVP)
Outline 28P2C-B (DRV)
Outline 28P2W-C (DFP)
28
27
25
24
23
22
26
21
20
19
18
17
16
15
1
3
4
5
6
2
78
11
12
13
14
9
10
MITSUBISHI LSIs
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
MITSUBISHI
ELECTRIC
M5M5256DFP,VP,RV -10VLL,-12VLL,-15VLL,
-10VXL,-12VXL,-15VXL
'97.4.7
FUNCTION
FUNCTION TABLE
The operation mode of the M5M5256DP,FP,VP,RV is
determined by a combination of the device control inputs /S,
/W and /OE. Each mode is summarized in the function table.
A write cycle is executed whenever the low level /W
overlaps with the low level /S. The address must be set up
before the write cycle and must be stable during the entire
cycle. The data is latched into a cell on the trailing edge of
/W, /S, whichever occurs first, requiring the set-up and hold
time relative to these edge to be maintained. The output
enable /OE directly controls the output stage. Setting the
/OE at a high level,the output stage is in a high-impedance
state, and the data bus contention problem in the write cycle
is eliminated.
Mode DQ Icc
/S /W /OE
Non selection
Write
Read
Stand-by
Active
Active
Active
High-impedance
DIN
DOUT
X X
L
L
L
L X
L
H
H
H
H
High-impedance
2
A read cycle is executed by setting /W at a high level and
/OE at a low level while /S are in an active state.
When setting /S at a high level, the chip is in a
non-selectable mode in which both reading and writing are
disabled. In this mode, the output stage is in a
high-impedance state, allowing OR-tie with other chips and
memory expansion by /S. The power supply current is
reduced as low as the stand-by current which is specified
as Icc3 or Icc4, and the memory data can be held at +2V
power supply, enabling battery back-up operation during
power failure or power-down operation in the non-selected
mode.
VCC
(3V)
GND
(0V)
27
20
22
2
3
4
6
5
7
25
26
1
8
9
10
21
23
24
2
12
11
13
15
16
17
18
19
ADDRESS INPUT
BUFFER
ROW DECODER
(512 ROWS X
512 COLUMNS)
32768 WORD
X 8BIT
SENSE ANPLIFIER
OUTPUT BUFFER
DATA INPUT
BUFFER
COLUMN
DECODER
ADDRESS INPUT
BUFFER
GENERATOR
CLOCK
A 14
A 13
A 8
A 12
A 6
A 7
A 10
A 0
A 1
A 2
A 3
A 4
A 5
A 11
A 9
/W
/OE
/S
28
14
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
ADDRESS
INPUT
DATA I/O
WRITE CONTROL
INPUT
OUTPUT ENABLE
INPUT
CHIP SELECTINPUT
BLOCK DIAGRAM
MITSUBISHI LSIs
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
MITSUBISHI
ELECTRIC
M5M5256DFP,VP,RV -10VLL,-12VLL,-15VLL,
-10VXL,-12VXL,-15VXL
'97.4.7
3
ABSOLUTE MAXIMUM RATINGS
CAPACITANCE (Ta=0~70°C, Vcc=2.7~3.6V, unless otherwise noted)
Symbol Parameter Test conditions pF
pF
Unit
Max
6
8
TypMin Limits
VI=GND, VI=25mVrms, f=1MHz
VO=GND,VO=25mVrms, f=1MHz
Input capacitance
Output capacitance
CI
CO
DC ELECTRICAL CHARACTERISTICS (Ta=0~70°C, Vcc=2.7~3.6V, unless otherwise noted)
Symbol Parameter
V
V
V
Limits
Test conditions Unit
V
uA
* -3.0V in case of AC ( Pulse width ≤ 30ns )
Note 0: Direction for current flowing into an IC is positive (no mark).
1: Typical value is one at Ta = 25°C.
2: CI, CO are periodically sampled and are not 100% tested.
mA
* -3.0V in case of AC ( Pulse width ≤ 30ns )
uA
uA
mA
V
Active supply current
(AC, MOS level )
Icc1
Icc2
Stand-by currentIcc4
VIH High-level input voltage
VIL Low-level input voltage
IOOutput current in off-state
Icc3Stand-by current
VOH1 High-level output voltage 1 IOH=-0.5mA
VOH2 High-level output voltage 2 IOH=-0.05mA
VOL Low-level output voltage IOL=1mA
IIInput current VI=0~Vcc
Vcc
+0.3
0.6
2.0
-0.3*
2.4
0.33
0.4
2011
12
2.4
Vcc
-0.5
±1
31.5
-VLL
-VXL
MaxTypMin
Parameter
Supply voltage
Input voltage
Output voltage
Power dissipation
Operating temperature
Storage temperature
Unit
V
V
V
mW
°C
Conditions
With respect to GND
Ta=25°C 700
0~70
-65~150
Ratings
Symbol
Vcc
VI
VO
Pd
Topr
Tstg
-0.3*~4.6
-0.3*~Vcc+0.3
0~Vcc
(Max 4.6)
/S=VIH,other inputs=0~Vcc
/S≥Vcc-0.2V,
other inputs=0~Vcc
/S=VIH or or /OE=VIH,
VI/O=0~Vcc
1MHz
mA
/S=VIL,
other inputs=VIH or VIL
Output-open Min. cycle
Active supply current
(AC, TTL level )
/S≤0.2V,
Other inputs<0.2V or >Vcc-0.2V
Output-open Min. cycle
°C
±1
0.05
Min.
cycle
2011
31.5
1MHz
Min.
cycle
MITSUBISHI LSIs
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
MITSUBISHI
ELECTRIC
M5M5256DFP,VP,RV -10VLL,-12VLL,-15VLL,
-10VXL,-12VXL,-15VXL
'97.4.7
4
(2) READ CYCLE
(3) WRITE CYCLE
Symbol Parameter
tCR Read cycle time
Address access time
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Limits
ta(S)
ta(OE)
tdis(S)
tdis(OE)
ten(S)
ten(OE)
tV(A)
ta(A)
-15VLL, VXL
AC ELECTRICAL CHARACTERISTICS (Ta = 0~70°C, Vcc=2.7~3.6V, unless otherwise noted )
(1) MEASUREMENT CONDITIONS
Chip select access time
Output enable access time
Output disable time after /S high
Output disable time after /OE high
Output enable time after /S low
Output enable time after /OE low
Data valid time after address
MaxMin
Input pulse level···················VIH=2.2V,VIL=0.4V
Input rise and fall time··········5ns
Reference level····················VOH=VOL=1.5V
Output loads·························Fig.1,CL=30pF (-10VLL,-10VXL )
CL=50pF (-12VLL,-12VXL )
CL=100pF (-15VLL,-15VXL )
CL=5pF (for ten,tdis)
Transition is measured ±500mV from steady
state voltage. (for ten,tdis)
120
10
10
10
Min
120
120
60
35
35
Max
100
10
10
10
Min
100
100
50
30
30
Max
-10VLL, VXL -12VLL, VXL
150
10
10
10
150
150
75
40
40
Symbol Parameter Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Limits
Write cycle time
Write pulse width
Address setup time
Address setup time with respect to /W high
Chip select setup time
Data setup time
Data hold time
Write recovery time
Output disable time from /W low
Output disable time from /OE high
Output enable time from /W high
Output enable time from /OE low
MaxMin
-15VLL, VXL-10VLL, VXL -12VLL, VXL
35
35
Max
120
80
0
90
90
45
0
0
10
10
Min
30
30
Max
100
70
0
80
80
40
0
0
10
10
Min
tCW
tw(W)
tsu(A)
tsu(A-WH)
tsu(S)
tsu(D)
th(D)
trec(W)
tdis(W)
tdis(OE)
ten(W)
ten(OE)
40
40
150
90
0
100
100
50
0
0
10
10
Fig.1 Output load
(Including
scope and JIG)
DQ
LC
MITSUBISHI LSIs
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
MITSUBISHI
ELECTRIC
M5M5256DFP,VP,RV -10VLL,-12VLL,-15VLL,
-10VXL,-12VXL,-15VXL
'97.4.7
ten (W)
5
Read cycle
Write cycle (/W control mode)
(4) TIMING DIAGRAMS
DATA VALID
(Note 3) (Note 3)
ta(A)
ta (S)
tv (A)
tdis (S)
ta (OE)
ten (OE)
tdis (OE)
(Note 3) (Note 3)
tCR
th (D)tsu (D)
DQ1~8
/S tsu (S)
/OE
tsu (A-WH)
ten(OE)
tdis (OE)
(Note 3) (Note 3)
/W
tw (W) trec (W)tsu (A)
tdis (W)
tCW
ten (S)
/W = "H" level
A0~14
DQ1~8
/S
/OE
A0~14
DATA IN
STABLE
(Note 3) (Note 3)
MITSUBISHI LSIs
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
MITSUBISHI
ELECTRIC
M5M5256DFP,VP,RV -10VLL,-12VLL,-15VLL,
-10VXL,-12VXL,-15VXL
'97.4.7
6
Write cycle ( /S control mode)
tsu (S) trec (W)
th (D)
tCW
(Note 5)
(Note 3) (Note 3)
tsu (A)
(Note 4)
tsu (D)
DATA IN
STABLE
DQ1~8
/S
/W
A0~14
Note 3 : Hatching indicates the state is "don't care".
5 : If /W goes low simultaneously with or prior to /S, the outputs remain in the high impedance state.
6 : Don't apply inverted phase signal externally when DQ pin is output mode.
4 : Writing is executed in overlap of /S and /W low.
7 : ten, tdis are periodically sampled and are not 100% tested.
MITSUBISHI LSIs
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
MITSUBISHI
ELECTRIC
M5M5256DFP,VP,RV -10VLL,-12VLL,-15VLL,
-10VXL,-12VXL,-15VXL
'97.4.7
7
(3) POWER DOWN CHARACTERISTICS
/S control mode
POWER DOWN CHARACTERISTICS
(1) ELECTRICAL CHARACTERISTICS (Ta = 0~70°C, Vcc=2.7~3.6V, unless otherwise noted)
Power down set up time
Power down recovery time
(2) TIMING REQUIREMENTS (Ta = 0~70°C, Vcc=2.7~3.6V, unless otherwise noted )
tsu (PD)
trec (PD)
Symbol Parameter ns
MaxTyp
Limits
Min
Test conditions Unit
0
tCR ns
2.0V
tsu (PD) 2.7V
2.0V
trec (PD)
/S≥Vcc-0.2V
Vcc
/S
Symbol Parameter
V
V
MaxTyp
Limits
Min
Test conditions Unit
uA
2
10
-VXL (Note 8)
0.05 2
Vcc (PD)
Icc (PD)
Power down supply voltage
Power down supply current
Note7: ICC (PD) = 1uA in case of Ta = 25°C
Note8: ICC (PD) = 0.2uA in case of Ta = 25°C
2
VI (/S) Chip select input /S
Vcc = 3V,/S≥Vcc-0.2V,
Other inputs=0~Vcc -VLL (Note 7)
2.7V
