DSC-11524
16-BIT HYBRID D/S AND D/R CONVERTER
PIN PROGRAMMABLE FOR SYNCHRO
OR RESOLVER OUTPUT
DESCRIPTION
The DSC-11524 is a versatile multi-
plying digital-to-analog converter.
The digital input represents an
angle, and the output is pin progr am-
mable for either resolver, sin/cos, or
three-line synchro type output. The
ref erence input will accept any w av e-
f orm, even a sawtooth for CR T drive.
Because the reference is DC cou-
pled to the output, the DSC-11524
can be used in many configurations,
such as:a digital-to-synchro/resolver
converter using a sinusoidal refer-
ence as an input; a digital-to-sin/cos
DC converter using a DC reference;
a polar-to-rectangular converter
using a reference input proportional
to the radius vector; a rotating cart-
wheel sweep generator for PPI dis-
plays using a sawtooth reference.
Packaged in a 36-pin DDIP, the
DSC-11524 is a complete D/S and
D/R conver ter in one hybrid module.
Hybrid technology results in low
weight, low po wer consumption, v ery
high reliability, and a wide operating
temperature range. The DSC-11524
circuit design allows for higher accu-
racy and reduces the output scale
factor variation so that the output
can drive displays directly. The out-
put line-to-line voltage can be scaled
by external resistors. Other features
include high ac and DC common
mode rejection at the reference
input, and output short circuit protec-
tion.
APPLICATIONS
Because of its high reliability, small
size and low power consumption the
hybrid DSC-11524 is ideal for the
most stringent and severe industrial
and military ground or a vionics appli-
cations. All units are available with
MIL-PRF-38534 processing as a
standard option.
Among the many possible applica-
tions are computer-based systems
in which digital information is
processed, such as simulators, flight
trainers, flight instrumentation, fire
control systems, radar and naviga-
tion systems, and PPI displays
including moving target indicators.
FEATURES
•
15 mA RMS Output
•
11.8 V
L-L
Synchro, 11.8 V
L-L
Resolver, or 6.81 V
L-L
Resolver
Output
•
8 Bit/2 Byte Double-Buffered
Transparent Latches
•
Pin Programmable for Synchro or
Resolver Output
•
16-Bit Resolutlon
•
Complete D/S and D/R Converter
•
Mate to DSC-36020 IBM
®
PC Card
•
DC-Coupled Reference Accepts Any
Waveform
•
Generates Sin/Cos DC or Rotating
PPI Sweep
•
High-Rel CMOS D/R Chip
•
No +5 V Supply Required
REFERENCE
INPUTS
26 V
ADJUSTABLE
1.3-26 V
100 KΩ
100 KΩ
5 KΩ
5 KΩ
D/R
CONVERTER
HIGH ACCURACY
LOW SCALE FACTOR
VARIATION ELECTRONIC
SCOTT-T OR
RESOLVER
SCALING
OUTPUT
AMPLIFIERS
S1
S2´
S2
S3
S3´
S4
SYNCHRO OR
RESOLVER
OUTPUT
(PIN JUMPER
PROGRAMMABLE)
BITS 9-16BITS 1-8
DIGITAL INPUTS
BITS 1-16
LM
LA LL
TEST POINT -R
TRANSPARENT LATCH
TRANSPARENT LATCH
REFERENCE
CONDITIONER
© 1995, 1999 Data Device Corporation FIGURE 1. DSC-11524 BLOCK DIAGRAM
® IBM is a registered trademark of International Business Machines Cor poration.
2
-55 to +125
0 to +70
-55 to +135
°C
°C
°C
TEMPERATURE RANGES (CASE)
Operation
n-1 Option
n-3 Option
Storage
TABLE 1. DSC-11524 SPECIFICATIONS
Apply over temperature range, power supply range, reference voltage and frequency range,
and 10% harmonic distortion in the reference.
PARAMETER UNIT VALUE
Bits 16
RESOLUTION
Minutes
LSB
µsec
ACCURACY and DYNAMICS
Output Accuracy
Differential Linearity
Output Setting Time
±4 to ±2 min. (See Ordering info.)
±1 max
Less than 20 for any digital step change
µA
DIGITAL INPUT
Logic Type
Load Current
Natural binary angle, parallel positive
logic CMOS and TTL compatable.
Inputs are CMOS transient protected.
Logic 0 = 0 to +1 V
Logic 1 = +2.2 V to +5 V
20 max to GND (bits 1-16)
20 max to +5 V (LL, LM, LA)
See Timing Diagrams (FIGURES 2A/2B.).
Hz
V
k ohm
k ohm
REFERENCE INPUT
Type
Frequency Range
Voltage
Input Impedance
nSingle Ended
nDifferential
Two differential solid-state inputs: one for
standard 26 V, one programmable.
DC to 1k (to 10k with reduced accuracy)
Standard Input Programmable Input
26 (Note 1)
100 ±0.5%
200 ±0.5%
1.3 minimum f or full output;
higher voltages are
scaled by adding two
series resistors
5 ±0.5%
10 ±0.5%
mA rms
VrmsL-L
VrmsL-L
%
%
mV
ANALOG OUTPUT
Type
Output Current
Output Voltage
nSynchro mode
nResolver mode
Transf orm. Ratio Tol.
Scale Factor Varation
DC Offset
(Each Line to Gnd)
Pin programmable for synchro or resolver
15 max
(Tracks Reference Input Voltage)
11.8 nominal
6.81 or 11.8 nominal
±0.5 max
±0.1 max
±15 max.Varies with input angle.
V
mA
POWER SUPPLIES
Voltage
Max voltage without damage
Max Current or Impedance
+15 ± 5%
+18 V
35+ load current
-15 ± 5%
-18 V
35+ load current
36-pin DDIP
0.78 x 1.9 x 0.21 (19.7 x 48.3 x 5.3)
0.85 (24)
in.(mm)
oz. (g)
PHYSICAL CHARACTERISTICS
Type
Size
Weight
Notes: 1) Maximum reference input voltage for RH/RL is 26 V +10%.
2) Differential is Line-to-Line (L-L); single-ended is Line-to-Ground (L-Gnd).
3
FIGURE 2A. LL, LM, LA TIMING DIAGRAM (16-BIT)
,,,
,,
DATA 1-16 BITS
200 ns MIN
LL / LM / LA LATCHED
TRANSPARENT
100 ns MIN50 ns MIN
INTRODUCTION
As shown in FIGURE 1, the signal conversion in the DSC-11524
is performed by a high-accuracy digital-to-resolver converter
whose sin and cos outputs have a low scale factor variation as a
function of the digital input angle. This resolver output is either
amplified by scaling amplifiers for resolver output, or is both
amplified and converted to a synchro output by an electronic
Scott-T. In both cases the output line currents can be 15 mA rms
max, which is sufficient for driving S/D converters, solid-state
control transformers and displays. Output power amplifiers will
be required, howe v er, for driving electromechanical devices such
as synchros and resolvers.
The reference conditioner has a differential input with high ac
and DC common mode rejection, so that a reference isolation
transformer will seldom be required. There are two sets of refer-
ence inputs.The RH, RL input provides the maximum synchro or
resolver output voltage for a standard 26 V r ms reference input.
The RH´, RL´ input is used to scale the output f or other ref erence
voltage levels. Series resistors can be added to the reference
input as described below, either to accommodate higher refer-
ence levels, or to reduce the output level. The reference condi-
tioner output -R is intended for test pur poses. A signal between
6 V and 7.5 V at -R indicates that a reference input signal is pre-
sent.
DIGITAL INPUT
The converter contains three input latches. The input is con-
trolled by LM and LL.Each of these enable the con v erter to inter-
face with an 8-bit bus. LM controls bits 1-8 and LL controls bits
9-16. Ensure that the data is stable for 50ns before enabling a
latch (LL, LM), and allow 100ns for the latch to input the data.
50 nsec
100 nsec
50 nsec
100 nsec
100 nsec
8-bit
LL
LM
LA
FIGURE 2B. LL, LM, LA TIMING DIAGRAM (8-BIT)
OUTPUT SCALING AND REF LEVEL ADJUSTMENT
The DSC-11524 operates like a multiplying D/A converter in that
the voltage of each output line is directly proportional to the ref-
erence voltage. The maximum line-to-line levels are determined
by the output amplifiers and are nominally 11.8 V f or synchro out-
put and 6.81 V or 11.8 V for resolver output. The RH, RL refer-
ence input is designed to provide this nominal output for the
standard 26 V ref erence le vel.The scaling adjustment is made b y
two internal 100k ohm resistors in ser ies with the reference con-
ditioner input (see FIGURE 1).
The RH´, RL´ reference input has only 5k ohm inter nal resistors
in series with the reference conditioner input, so that nominal
line-to-line output is obtained for a reference input of 1.3 V. For
higher reference voltages, two resistors, R’, must be inser ted in
series with the inputs as shown in FIGURE 3. These resistors
scale the DSC-11524 to accommodate higher reference levels,
or to reduce the output levels.
The magnitude of the resistors, R´, in ohms is calculated as follo ws:
Note: The above equation is for scaling the RH´, RL´ inputs. To
calculate R´ to scale the RH, RL input use 100,000 in place of
5,000 in the equation.
[ ]
R´ = 5000 (VR- 1.3) NOMINAL L-LVOLTAGE LEVEL
1.3 DESIRED L-LVOLTAGE LEVEL
••
4
DSC-11524
REF
INPUT
R´
R´
RH´
RL´
9
11
(VR)
34
S3’ 35
S3 S3
32
S1 S1
DSC-11524 36
S2 S2
31
S4 S4
33
S2’
11.8 V RESOLVER OUTPUT
32 35
S1 S1 S3 +SIN
36
S2 S2
33 36
DSC-11524 S2’ DSC-11524 S2 +COS
35
S3 S3
34 33
S3’ S2’ RTN
11.8 V SYNCHRO OUTPUT 6.81 V RESOLVER OUTPUT
FIGURE 4. OUTPUT PIN PROGRAMMING
•
•
•
•
FIGURE 3. REFERENCE LEVEL ADJUSTMENT
maximum v ariation in Aofrom all causes is ± 0.5%.The term A(θ)
represents the variation of the amplitude with the digital signal
input angle. A(θ), which is called the scale factor variation, is a
smooth function of (θ) without discontinuities and is less than
±0.1% for all values of (θ).The total maximum variation in Ao(1
+ A(θ)) is therefore ± 0.6%.
Because the amplitude f actor (RH - RL)Ao(1 + A(θ)) varies simul-
taneously on all output lines, it will not be a source of error when
the DSC-11524 is to drive a ratiometric system such as a syn-
chro or resolver. However, if the outputs are used independently,
as in x-y plotters, the amplitude variations must be taken into
account.
OUTPUT TRANSFORMER
The DSC-11524 uses the 51538 step-up transformer to dr ive 90
VL-Lsynchro loads. The 51538 transformer specifications are
shown in TABLE 2 and the schematic and mechanical outline
drawings are shown in FIGURE 5.
OUTPUT CONFIGURATION
The output amplifier section can be configured for Synchro and
Resolver outputs, as shown in FIGURE 4.
OUTPUT PHASING AND OUTPUT SCALE FACTOR
The analog output signals have the following phasing:
Synchro output:
S3—S1 = (RH - RL)Ao(1 + A(θ)) sin θ
S2—S3 = (RH - RL)Ao(1 + A(θ)) sin( θ+ 120°)
S1—S2 = (RH - RL)Ao(1 + A(θ)) sin( θ+ 240°)
Resolver output:
S3—S1 = (RH - RL)Ao(1 + A(θ)) sin θ
S2—S4 = (RH - RL)Ao(1 + A(θ)) cos θ
The output amplifiers simultaneously track reference voltage
fluctuations because they are proportional to (RH - RL). The
transformation ratio Aois 11.8/26 for 11.8 V r ms L-L output.The
5
7
1.63 MAX
(41.40)
1238
456
0.40
(10.16)
0.800
(20.32)
0.40
(10.16)
0.200
(5.08)
8 PLACES
1.130 MAX
(28.702)
1.00
(25.4) 2
0.042 DIA PIN
)
0.23 MIN
(5.842)
BOTTOM VIEW
SIDE VIEW
DOT THIS SIDE SIDE OPPOSITE PIN 1
MARKING
0.510 MAX
(12.954)
+0.076
-0.102
+0.003
-0.102
(1.067
0.800
(20.32)
SYNCHRO
OUTPUT
(90V)
SYNCHRO
OUTPUT
(11.8V)
S1
S3
1T1A
T1B
5
6
37S2
S1
S2
S3
FIGURE 5. 90 VL-L, 400 HZSYNCHRO OUTPUT TRANSFORMER (P/N 51538)
Synchro Input 11.8 Vr ms line-to-line ±10% at 400 Hz ±10%
Synchro Output 90 Vrms ±1% Full Scale with a line-to-line input voltage of 11.8 Vrms
Input Impedance 1000 Ohms minimum
Output Impedance 500 Ohms maximum
Accuracy The maximum additional error shall be 1.5 min. loaded with an SDC-14560 (130k Ohm)
HIPOT Between windings and windings-to-case 900 Vr ms at 60 Hz
TABLE 2. ELECTRICAL SPECIFICATIONS FOR THE 51538 TRANSFORMER
6
1.895 ±0.005
(48.1 ±0.13)
1.700 ±0.005
(43.2 ±0.13)
0.018 (0.46)
DIAM TYP
0.100 TYP(2.54)
TOL. NON-
CUMULATIVE
0.21 MAX
(5.3)
CONTRASTING
COLORED BEAD
IDENTIFIES
PIN 1
0.775 ±0.005
(19.7 ±0.13) 0.600 ±0.005
(15.2 ±0.13)
0.09 ±0.01
(2.3 ±0.25)
0.10 ±0.01
(2.5 ±0.3)
SIDE VIEW
BOTTOM VIEW
0.25 MIN
(6.4)
0.015 MAX
(0.39)
SEATING
PLANE
0.055 (1.4)
RAD TYP
0.086 TYP
RADIUS
181
1936
Notes:
1. Dimensions shown are in inches (millimeters).
2. Lead identification numbers are for referenced only.
3. Lead cluster shall be centered within of outline dimensions. Lead spacing dimensions apply only at seating plane.
4. Pin mater ial meets solderability requirements of MIL-STD-202E, Method 208C.
5. Package is Kovar with electroless nickel plating.
6. Case is electr ically floating.
FIGURE 6. DSC-11524 36-PIN DDIP MECHANICAL OUTLINE
TABLE 3. PIN CONNECTION TABLE
PIN
PINPINNAME NAMENAME
13
14
15
16
17
18
19
20
21
22
23
24
NC
+15V
GND
-15V
NC
NC
-R
RL
RL´
RH
RH´
Bit 14
1
2
3
4
5
6
7
8
9
10
11
12
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
25
26
27
28
29
30
31
32
33
34
35
36
Bit 1 (MSB)
Bit 15
Bit 16 (LSB)
LM
LL
LA
S4
S1
S2'
S3'
S3 (+SIN)
S2 (+COS)
Notes:
1. -R (Pin 7) can be used for test purposes to detect whether a reference signal
is present. See block diagram.
2. Functions LL, LA, and LM may be left unconnected when not used.
7
STANDARD DDC PROCESSING
TEST MIL-STD-883
METHOD(S) CONDITION(S)
INSPECTION 2009, 2010, 2017, and 2032 —
SEAL 1014 A and C
TEMPERATURE CYCLE 1010 C
CONSTANT ACCELERATION 2001 A
BURN-IN 1015, Tab le 1 —
ORDERING INFORMATION
DSC-11524-XXXX
Supplemental Process Requirements:
S = Pre-Cap Source Inspection
L = Pull Test
Q = Pull Test and Pre-Cap Inspection
K = One Lot Date Code
W = One Lot Date Code and Pre-Cap Source
Y = One Lot Date Code and 100% Pull Test
Z = One Lot Date Code, Pre-Cap Source and 100% Pull Test
Blank = None of the Above
Accuracy:
3 = ±4 minutes
4 = ±2 minutes
Process Requirements:
0 = Standard DDC Processing, no Burn-In (See table below.)
1 = MIL-PRF-38534 Compliant
2 = B*
3 = MIL-PRF-38534 Compliant with PIND Testing
4 = MIL-PRF-38534 Compliant with Solder Dip
5 = MIL-PRF-38534 Compliant with PIND Testing and Solder Dip
6 = B* with PIND Testing
7 = B* with Solder Dip
8 = B* with PIND Testing and Solder Dip
9 = Standard DDC Processing with Solder Dip, no Burn-In (See table below.)
Temperature Grade/Data Requirements:
1 = -55°C to +125°C
2 = -40°C to +85°C
3 = 0°C to +70°C
4 = -55°C to +125°C with Var iables Test Data
5 = -40°C to +85°C with Var iables Test Data
8 = 0°C to +70°C with Var iables Test Data
*Standard DDC Processing with burn-in and full temperature test — see table below.
8
The information in this data sheet is believed to be accurate; however, no responsibility is
assumed by Data Device Corporation for its use, and no license or rights are
granted by implication or otherwise in connection therewith.
Specifications are subject to change without notice.
F-08/99-500 PRINTED IN THE U.S.A.
ILC DATA DEVICE CORPORATION
REGISTERED TO ISO 9001
FILE NO. A5976
105 Wilbur Place, Bohemia, New York 11716-2482
For Technical Support - 1-800-DDC-5757 ext. 7389 or 7413
Headquarters - Tel: (631) 567-5600 ext.7389 or 7413, Fax: (631) 567-7358
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