\\\ SPICE Device Model Si4920DY
Vishay Siliconix
This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate
data sheet of the same number for guaranteed specification limits.
Document Number: 71008 www.vishay.com
18-May-04 1
Dual N-Channel 30-V (D-S) M OSFET
CHARACTERISTICS
•N-Channel Vertical DMOS
•Macro Model (Subcircuit Model)
•Level 3 MO S
•Apply f or both Linear and Switc hing Applic ation
•Accurate over the −55 to 125 °C Temperature Range
•Model the Gate Charge, T ransient, and Diode Reverse Recovery
Characteristics
DESCRIPTION
The attached spice model describes the typical electrical
characteristics of the n-channel vertical DMOS. The subcircuit
model is extracted and optimized over the −55 to 125°C
temperature ranges under the pulsed 0 to 10V gate drive. The
saturated output impedance is best fit at the gate bias near the
threshold voltage.
A novel gate-to-drain feedback capacitance network is used to model
the gate charge characteristics while avoiding convergence difficulties
of the switched Cgd model. All model parameter values are optimized
to provide a best fit to the measured electrical data and are not
intended as an exact physical interpretation of the device.
SUBCIRCUIT MODEL SCHEMATIC
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SPICE Device Model Si4920DY
Vishay Siliconix
www.vishay.com Document Number: 71008
218-May-04
SPECIFICATIONS (TJ = 25°C UNLESS OTHERW ISE NOTED)
Parameter Symbol Test Conditions Simulated
Data Measured
Data Unit
Static
Gate Threshold Voltage VGS(th) VDS = VGS, ID = 250 µA2 V
On-State Drain CurrentaID(on) VDS ≥ 5 V, VGS = 10 V 238 A
VGS = 10 V, ID = 6.9 A 0.020 0.020
Drain-Source On-State ResistancearDS(on) VGS = 4.5 V, ID = 5.8 A 0.023 0.026 Ω
Forward Transconductanceagfs VDS = 15 V, ID = 6.9 A 23 25 S
Diode Forward VoltageaVSD IS = 1.7 A, VGS = 0 V 0.72 V
Dynamicb
Total Gate Charge Qg29 30
Gate-Source Charge Qgs 7.5 7.5
Gate-Drain Charge Qgd
VDS = 15 V, VGS = 10 V, ID = 6.9 A
3.5 3.5
nC
Turn-On Delay Time td(on) 10 12
Rise Time tr13 10
Turn-Off Delay Time td(off) 15 60
Fall Time tf
VDD = 15 V, RL = 15 Ω
ID≅ 1 A, VGEN = 10 V, RG = 6 Ω
32 15
Ns
Source-Drain Rev erse Recov ery Time trr IF = 1.7 A, di/dt = 100 A/µs32 50
Notes
a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%
b. Guaranteed by design, not subject to production testing
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