MCIMX537CVV8CR2 - NXP SEMICONDUCTORS

Freescale Semiconductor

Data Sheet: Technical Data

Document Number: IMX53IEC

Rev. 7, 05/2015

MCIMX53xC

Package Information

Plastic Package

Case TEPBGA-2 19 x 19 mm, 0.8 mm pitch

Ordering Information

See Table 1 on page 2

1 Introduction

The i.MX53 processor features ARM Cortex™-A8

core, which operates at clock speeds as high as

800 MHz. It provides DDR2/LVDDR2-800,

LPDDR2-800, or DDR3-800 DRAM memories.

The flexibility of the i.MX53 architecture allows for its

use in a wide variety of applications. As the heart of the

application chipset, the i.MX53 processor provides all

the interfaces for connecting peripherals, such as

WLAN, Bluetooth™, GPS, hard drive, camera sensors,

and dual displays.

Features of the i.MX53 processor include the following:

• Applications processor—The i.MX53xD

processors boost the capabilities of high-tier

portable applications by satisfying the ever

increasing MIPS needs of operating systems and

games. Freescale’s Dynamic Voltage and

Frequency Scaling (DVFS) provides significant

power reduction, allowing the device to run at

lower voltage and frequency with sufficient

MIPS for tasks such as audio decode.

i.MX53 Applications

Processors for Industrial

Products

Silicon Version 2.1

1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1. Functional Part Differences and Ordering

Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2. Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.1. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3. Modules List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.1. Special Signal Considerations . . . . . . . . . . . . . . . 16

4. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 16

4.1. Chip-Level Conditions . . . . . . . . . . . . . . . . . . . . . 16

4.2. Power Supply Requirements and Restrictions . . . 23

4.3. I/O DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 26

4.4. Output Buffer Impedance Characteristics . . . . . . 32

4.5. I/O AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 36

4.6. System Modules Timing . . . . . . . . . . . . . . . . . . . . 43

4.7. External Peripheral Interfaces Parameters . . . . . 65

4.8. XTAL Electrical Specifications . . . . . . . . . . . . . . 141

5. Boot Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . 142

5.1. Boot Mode Configuration Pins . . . . . . . . . . . . . . 142

5.2. Boot Devices Interfaces Allocation . . . . . . . . . . . 143

5.3. Power Setup During Boot . . . . . . . . . . . . . . . . . . 144

6. Package Information and Contact Assignments . . . . . 145

6.1. 19x19 mm Package Information . . . . . . . . . . . . . 145

7. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

i.MX53 Applications Processors for Industrial Products, Rev. 7

2Freescale Semiconductor

Introduction

• Multilevel memory system—The multilevel memory system of the i.MX53 is based on the L1

instruction and data caches, L2 cache, internal and external memory. The i.MX53 supports many

types of external memory devices, including DDR2, low voltage DDR2, LPDDR2, DDR3, NOR

Flash, PSRAM, cellular RAM, NAND Flash (MLC and SLC), OneNAND™, and managed NAND

including eMMC up to rev 4.4.

• Smart speed technology—The i.MX53 device has power management throughout the IC that

enables the rich suite of multimedia features and peripherals to consume minimum power in both

active and various low power modes. Smart speed technology enables the designer to deliver a

feature-rich product requiring levels of power far lower than industry expectations.

• Multimedia powerhouse—The multimedia performance of the i.MX53 processor ARM core is

boosted by a multilevel cache system, Neon (including advanced SIMD, 32-bit single-precision

floating point support) and vector floating point coprocessors. The system is further enhanced by

a multi-standard hardware video codec, autonomous image processing unit (IPU), and a

programmable smart DMA (SDMA) controller.

• Powerful graphics acceleration— The i.MX53 processors provide two independent, integrated

graphics processing units: an OpenGL® ES 2.0 3D graphics accelerator (33 Mtri/s, 200 Mpix/s,

and 800 Mpix/s z-plane performance) and an OpenVG™ 1.1 2D graphics accelerator

(200 Mpix/s).

• Interface flexibility—The i.MX53 processor supports connection to a variety of interfaces,

including LCD controller for two displays and CMOS sensor interface, high-speed USB on-the-go

with PHY, plus three high-speed USB hosts, multiple expansion card ports (high-speed

MMC/SDIO host and others), 10/100 Ethernet controller, and a variety of other popular interfaces

(PATA, UART, I2C, and I2S serial audio, among others).

• Advanced security—The i.MX53 processors deliver hardware-enabled security features that

enable secure e-commerce, digital rights management (DRM), information encryption, secure

boot, and secure software downloads. For detailed information about the i.MX53 security features

contact a Freescale representative.

The i.MX53 application processor is a follow-on to the i.MX51, with improved performance, power

efficiency, and multimedia capabilities.

1.1 Functional Part Differences and Ordering Information

shows the functional differences between the different parts in the i.MX53 family.

Table 1 provides ordering information.

Table 1. Ordering Information

Part Number Mask Set CPU Frequency Notes Package1

1Case TEPBGA-2 is RoHS compliant, lead-free MSL (moisture sensitivity level) 3.

MCIMX537CVV8C 3N78C 800 MHz — 19 x 19 mm, 0.8 mm pitch BGA

Case TEPBGA-2

Introduction

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 3

1.2 Features

The i.MX53 multimedia applications processor (AP) is based on the ARM Platform, which has the

following features:

• MMU, L1 instruction and L1 data cache

• Unified L2 cache

• Maximum frequency of the core (including Neon, VFPv3 and L1 cache): 800 MHz

• Neon coprocessor (SIMD media processing architecture) and vector floating point (VFP-Lite)

coprocessor supporting VFPv3

• TrustZone

The memory system consists of the following components:

• Level 1 cache:

— Instruction (32 Kbyte)

— Data (32 Kbyte)

• Level 2 cache:

— Unified instruction and data (256 Kbyte)

• Level 2 (internal) memory:

— Boot ROM, including HAB (64 Kbyte)

— Internal multimedia/shared, fast access RAM (128 Kbyte)

— Secure/non-secure RAM (16 Kbyte)

• External memory interfaces:

— 16/32-bit DDR2-800, LV-DDR2-800 or DDR3-800 up to 2 Gbyte

— 32-bit LPDDR2

— 8/16-bit NAND SLC/MLC Flash, up to 66 MHz, 4/8/14/16-bit ECC

— 8/16-bit NOR Flash, PSRAM, and cellular RAM.

— 32-bit multiplexed mode NOR Flash, PSRAM & cellular RAM.

— 8-bit Asynchronous (DTACK mode) EIM interface.

— All EIM pins are muxed on other interfaces (data with NFC pins). I/O muxing logic selects

EIM port, as primary muxing at system boot.

— Samsung OneNAND™ and managed NAND including eMMC up to rev 4.4 (in muxed I/O

mode)

The i.MX53 system is built around the following system on chip interfaces:

• 64-bit AMBA AXI v1.0 bus—used by ARM platform, multimedia accelerators (such as VPU, IPU,

GPU3D, GPU2D) and the external memory controller (EXTMC) operating at 200 MHz.

• 32-bit AMBA AHB 2.0 bus—used by the rest of the bus master peripherals operating at 133 MHz.

• 32-bit IP bus—peripheral bus used for control (and slow data traffic) of the most system peripheral

devices operating at 66 MHz.

i.MX53 Applications Processors for Industrial Products, Rev. 7

4Freescale Semiconductor

Introduction

The i.MX53 makes use of dedicated hardware accelerators to achieve state-of-the-art multimedia

performance. The use of hardware accelerators provides both high performance and low power

consumption while freeing up the CPU core for other tasks.

The i.MX53 incorporates the following hardware accelerators:

• VPU, version 3—video processing unit

• GPU3D—3D graphics processing unit, OpenGL ES 2.0, version 3, 33 Mtri/s, 200 Mpix/s, and

800 Mpix/s z-plane performance, 256 Kbyte RAM memory

• GPU2D—2D graphics accelerator, OpenVG 1.1, version 1, 200 Mpix/s performance,

• IPU, version 3M—image processing unit

• ASRC—asynchronous sample rate converter

The i.MX53 includes the following interfaces to external devices:

NOTE

Not all interfaces are available simultaneously, depending on I/O

multiplexer configuration.

• Hard disk drives:

— PATA, up to U-DMA mode 5, 100 MB/s

— SATA II, 1.5 Gbps

•Displays:

— Five interfaces available. Total rate of all interfaces is up to 180 Mpixels/s, 24 bpp. Up to two

interfaces may be active at once.

— Two parallel 24-bit display ports. The primary port is up to 165 Mpix/s (for example,

UXGA at 60 Hz).

— LVDS serial ports: one dual channel port up to 165 Mpix/s or two independent single channel

ports up to 85 MP/s (for example, WXGA at 60 Hz) each.

— TV-out/VGA port up to 150 Mpix/s (for example, 1080p60).

• Camera sensors:

— Two parallel 20-bit camera ports. Primary up to 180-MHz peak clock frequency, secondary up

to 120-MHz peak clock frequency.

• Expansion cards:

— Four SD/MMC card ports: three supporting 416 Mbps (8-bit i/f) and one enhanced port

supporting 832 Mbps (8-bit, eMMC 4.4).

•USB

— High-speed (HS) USB 2.0 OTG (up to 480 Mbps), with integrated HS USB PHY

— Three USB 2.0 (480 Mbps) hosts:

– High-speed host with integrated on-chip high-speed PHY

– Two high-speed hosts for external HS/FS transceivers through ULPI/serial, support IC-USB

• Miscellaneous interfaces:

— One-wire (OWIRE) port

Introduction

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 5

— Three I2S/SSI/AC97 ports, supporting up to 1.4 Mbps, each connected to audio multiplexer

(AUDMUX) providing four external ports.

— Five UART RS232 ports, up to 4.0 Mbps each. One supports 8-wire, the other four support

4-wire.

— Two high speed enhanced CSPI (ECSPI) ports plus one CSPI port

— Three I2C ports, supporting 400 kbps

— Fast Ethernet controller, designed to be compliant with IEEE1588 V1, 10/100 Mbps

— Two controller area network (FlexCAN) interfaces, 1 Mbps each

— Sony Phillips Digital Interface (SPDIF), Rx and Tx

— Key pad port (KPP)

— Two pulse-width modulators (PWM)

— GPIO with interrupt capabilities

The system supports efficient and smart power control and clocking:

• Supporting DVFS (dynamic voltage and frequency scaling) technique for low power modes

• Power gating SRPG (State Retention Power Gating) for ARM core and Neon

• Support for various levels of system power modes

• Flexible clock gating control scheme

• On-chip temperature monitor

• On-chip oscillator amplifier supporting 32.768 kHz external crystal

• On-chip LDO voltage regulators for PLLs

Security functions are enabled and accelerated by the following hardware/features:

• ARM TrustZone including the TZ architecture (separation of interrupts, memory mapping, and so

on)

• Secure JTAG controller (SJC)—Protecting JTAG from debug port attacks by regulating or

blocking the access to the system debug features

• Secure real-time clock (SRTC)—Tamper resistant RTC with dedicated power domain and

mechanism to detect voltage and clock glitches

• Real-time integrity checker, version 3 (RTICv3)—RTIC type1, enhanced with SHA-256 engine

• SAHARAv4 Lite—Cryptographic accelerator that includes true random number generator

(TRNG)

• Security controller, version 2 (SCCv2)—Improved SCC with AES engine, secure/non-secure

RAM and support for multiple keys as well as TZ/non-TZ separation

• Central security unit (CSU)—Enhancement for the IIM (IC Identification Module). CSU is

configured during boot by eFUSEs, and determines the security level operation mode as well as

the TrustZone (TZ) policy

• Advanced High Assurance Boot (A-HAB)—HAB with the following embedded enhancements:

SHA-256, 2048-bit RSA key, version control mechanism, warm boot, CSU, and TZ initialization

• Tamper detection mechanism—Provides evidence of any physical attempt to remove the device

cover. Upon detection of such an attack, sensitive information can immediately be erased.

i.MX53 Applications Processors for Industrial Products, Rev. 7

6Freescale Semiconductor

Architectural Overview

2 Architectural Overview

The following subsections provide an architectural overview of the i.MX53 processor system.

2.1 Block Diagram

Figure 1 shows the functional modules in the i.MX53 processor system.

Figure 1. i.MX53 System Block Diagram

NOTE

The numbers in brackets indicate number of module instances. For example,

PWM (2) indicates two separate PWM peripherals.

Application Processor

Smart DMA

(SDMA)

Shared Peripherals

AP Peripherals

ARM Cortex A8

Platform

Timers

CSPI

UART (4)

GPT

PWM (2)

EPIT (2)

GPIOx32 (7)

WDOG (2)

OWIRE

C(3)

IOMUXC

IIM

AUDMUX

KPP

Boot

ROM

SSI (2)

RTICv3

SCCv2

SRTC

CSU

Fuse Box

Debug

DAP

TPIU

FIRI

SAHARAv4

Lite

Security

TZIC

Image Processing

USB OTG +

3 HS Ports

CTI (2) ECSPI

Internal

USB PHY2

USB PHY1

External

Memory I/F

RAM

144 KB

Subsystem

(IPU)

TV-EncoderLDB

LCD

Display-1,2

Domain (AP)

Composite CVBS/ S-Video

Component RGB, YCC

(HD TV-Out / VGA)

SJC

Neon, VFPv3

L2 cache 256 KB

ETM, CTI0,1

L1 I/D cache

IrDA

XVR WLAN USB OTG

(dev/host)

JTAG

(IEEE1149.1)

Bluetooth

Keypad Access.

Conn.

MMC/SD

eMMC/eSD

GPS

RF/IF

RF / IF

IC’s

Audio,

Power

Mngmnt.

SPBA

FlexCAN (2)

Digital

Audio

CAN i/f

eSDHCv2 (3)

UART

SPDIF Rx/Tx

ASRC

Video

Proc. Unit

(VPU)

3D Graphics

Proc. Unit

(GPU3D)

G-Memory

256 KB

2D Graphics

Proc. Unit

(

GPU2D

)

AXI and AHB Switch Fabric

LVDS

(WSXGA+)

Battery Ctrl

Device

NOR/NAND

Flash

Ethernet

10/100

Mbps

FEC

(IEEE1588)

Camera

(2)

64 KB

Clock and Reset

PLL (4)

CCM

GPC

SRC

XTALOSC(2)

CAMP (2)

Temperature

Sensor

eSDHCv3

Camera

(2)

(EXTMC)

LCD

Display (2)

SSI

ECSPI

ESAI

P-ATA

SATA

+ Temp Mon

SATA /

P-ATA

HDD

DDR2/DDR3/

LPDDR2

Modules List

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 7

3 Modules List

The i.MX53 processor contains a variety of digital and analog modules. Table 2 describes these modules

in alphabetical order.

Table 2. i.MX53 Digital and Analog Blocks

Block

Mnemonic Block Name Subsystem Brief Description

ARM ARM Platform ARM The ARM CortexTM A8 platform consists of the ARM processor version r2p5

(with TrustZone) and its essential sub-blocks. It contains the 32 Kbyte L1

instruction cache, 32 Kbyte L1 data cache, Level 2 cache controller and a

256 Kbyte L2 cache. The platform also contains an event monitor and

debug modules. It also has a NEON coprocessor with SIMD media

processing architecture, a register file with 32/64-bit general-purpose

registers, an integer execute pipeline (ALU, Shift, MAC), dual

single-precision floating point execute pipelines (FADD, FMUL), a load/store

and permute pipeline and a non-pipelined vector floating point (VFP Lite)

coprocessor supporting VFPv3.

ASRC Asynchronous

Sample Rate

Converter

Multimedia

Peripherals

The asynchronous sample rate converter (ASRC) converts the sampling

rate of a signal associated to an input clock into a signal associated to a

different output clock. The ASRC supports concurrent sample rate

conversion of up to 10 channels of about -120 dB THD+N. The sample rate

conversion of each channel is associated to a pair of incoming and outgoing

sampling rates. The ASRC supports up to three sampling rate pairs.

AUDMUX Digital Audio

Multiplexer

Multimedia

Peripherals

The AUDMUX is a programmable interconnect for voice, audio, and

synchronous data routing between host serial interfaces (for example, SSI1,

SSI2, and SSI3) and peripheral serial interfaces (audio and voice codecs).

The AUDMUX has seven ports (three internal and four external) with

identical functionality and programming models. A desired connectivity is

achieved by configuring two or more AUDMUX ports.

CAMP-1

CAMP-2

Clock Amplifier Clocks,

Resets, and

Power Control

Clock amplifier

CCM

GPC

SRC

Clock Control

Module

Global Power

Controller

System Reset

Controller

Clocks,

Resets, and

Power Control

These modules are responsible for clock and reset distribution in the

system, as well as for system power management.

The system includes four PLLs.

CSPI

ECSPI-1

ECSPI-2

Configurable

SPI, Enhanced

CSPI

Connectivity

Peripherals

Full-duplex enhanced synchronous serial interface, with data rates

16-60 Mbit/s. It is configurable to support master/slave modes. In Master

mode it supports four slave selects for multiple peripherals.

CSU Central Security

Unit

Security The central security unit (CSU) is responsible for setting comprehensive

security policy within the i.MX53 platform, and for sharing security

information between the various security modules. The security control

registers (SCR) of the CSU are set during boot time by the high assurance

boot (HAB) code and are locked to prevent further writing.

i.MX53 Applications Processors for Industrial Products, Rev. 7

8Freescale Semiconductor

Modules List

DEBUG Debug System System

Control

The debug system provides real-time trace debug capability of both

instructions and data. It supports a trace protocol that is an integral part of

the ARM Real Time Debug solution (RealView).

Real-time tracing is controlled by specifying a set of triggering and filtering

resources, which include address and data comparators, three

cross-system triggers (CTI), counters, and sequencers.

debug access port (DAP)— The DAP provides real-time access for the

debugger without halting the core to system memory, peripheral register,

debug configuration registers and JTAG scan chains.

EXTMC External Memory

Controller

Connectivity

Peripherals

The EXTMC is an external and internal memory interface. It performs

arbitration between multi-AXI masters to multi-memory controllers, divided

into four major channels, fast memories (DDR2/DDR3/LPDDR2) channel,

slow memories (NOR-FLASH / PSRAM / NAND-FLASH etc.) channel,

internal memory (RAM, ROM) channel and graphical memory (GMEM)

channel.

In order to increase the bandwidth performance, the EXTMC separates the

buffering and the arbitration between different channels so parallel

accesses can occur. By separating the channels, slow accesses do not

interfere with fast accesses.

EXTMC Features:

• 64-bit and 32-bit AXI ports

• Enhanced arbitration scheme for fast channel, including dynamic master

priority, and taking into account which pages are open or closed and what

type (read or write) was the last access

• Flexible bank interleaving

• Support 16/32-bit DDR2-800 or DDR3-800 or LPDDR2.

• Support up to 2 GByte DDR memories.

• Support NFC, EIM signal muxing scheme.

• Support 8/16/32-bit Nor-Flash/PSRAM memories (sync and async

operating modes), at slow frequency. (8-bit is not supported on

D[23]-D[16]).

• Support 4/8/14/16-bit ECC, page sizes of 512-B, 2-KB and 4-KB

Nand-Flash (including MLC)

• Multiple chip selects (up to 4).

• Enhanced DDR memory controller, supporting access latency hiding

• Support watermark for security (internal and external memories)

EPIT-1

EPIT-2

Enhanced

Periodic Interrupt

Timer

Peripherals

Each EPIT is a 32-bit “set and forget” timer that starts counting after the

EPIT is enabled by software. It is capable of providing precise interrupts at

regular intervals with minimal processor intervention. It has a 12-bit

prescaler for division of input clock frequency to get the required time setting

for the interrupts to occur, and counter values can be programmed on the fly.

ESAI Enhanced Serial

Audio Interface

Connectivity

Peripherals

The enhanced serial audio interface (ESAI) provides a full-duplex serial port

for serial communication with a variety of serial devices, including

industry-standard codecs, SPDIF transceivers, and other processors.

The ESAI consists of independent transmitter and receiver sections, each

section with its own clock generator.

The ESAI has 12 pins for data and clocking connection to external devices.

Table 2. i.MX53 Digital and Analog Blocks (continued)

Block

Mnemonic Block Name Subsystem Brief Description

Modules List

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 9

ESDHCV3-3 Ultra-High-

Speed eMMC /

SD Host

Controller

Connectivity

Peripherals

Ultra high-speed eMMC / SD host controller, enhanced to support eMMC

4.4 standard specification, for 832 MBps.

• Port 3 is specifically enhanced to support eMMC 4.4 specification, for

double data rate (832 Mbps, 8-bit port).

ESDHCV3 is backward compatible to ESDHCV2 and supports all the

features of ESDHCV2 as described below.

ESDHCV2-1

ESDHCV2-2

ESDHCv2-4

Enhanced

Multi-Media Card

Secure Digital

Host Controller

Enhanced multimedia card / secure digital host controller

• Ports 1, 2, and 4 are compatible with the “MMC System Specification”

version 4.3, full support and supporting 1, 4 or 8-bit data.

The generic features of the eSDHCv2 module, when serving as SD / MMC

host, include the following:

• Can be configured either as SD / MMC controller

• Supports eSD and eMMC standard, for SD/MMC embedded type cards

• Conforms to SD Host Controller Standard Specification, version 2.0, full

support.

• Compatible with the SD Memory Card Specification, version 1.1

• Compatible with the SDIO Card Specification, version 1.2

• Designed to work with SD memory, miniSD memory, SDIO, miniSDIO,

SD Combo, MMC and MMC RS cards

• Configurable to work in one of the following modes:

—SD/SDIO 1-bit, 4-bit

—MMC 1-bit, 4-bit, 8-bit

• Full/high speed mode.

• Host clock frequency variable between 32 kHz to 52 MHz

• Up to 200 Mbps data transfer for SD/SDIO cards using 4 parallel data

lines

• Up to 416 Mbps data transfer for MMC cards using 8 parallel data lines

FEC Fast Ethernet

Controller

Connectivity

Peripherals

The Ethernet media access controller (MAC) is designed to support both

10 Mbps and 100 Mbps Ethernet/IEEE Std 802.3™ networks. An external

transceiver interface and transceiver function are required to complete the

interface to the media. The i.MX53 also consists of HW assist for

IEEE1588™ standard. See, TSU and CE_RTC (IEEE1588) section for more

details.

FIRI Fast Infrared

Interface

Connectivity

Peripherals

Fast infrared interface

FLEXCAN-1

FLEXCAN-2

Flexible

Controller Area

Network

Connectivity

Peripherals

The controller area network (CAN) protocol was primarily, but not

exclusively, designed to be used as a vehicle serial data bus. Meets the

following specific requirements of this application: real-time processing,

reliable operation in the EXTMC environment of a vehicle,

cost-effectiveness and required bandwidth. The FLEXCAN is a full

implementation of the CAN protocol specification, Version 2.0 B (ISO

11898), which supports both standard and extended message frames at

1Mbps.

Table 2. i.MX53 Digital and Analog Blocks (continued)

Block

Mnemonic Block Name Subsystem Brief Description

i.MX53 Applications Processors for Industrial Products, Rev. 7

10 Freescale Semiconductor

Modules List

GPIO-1

GPIO-2

GPIO-3

GPIO-4

GPIO-5

GPIO-6

GPIO-7

General Purpose

I/O Modules

System

Control

Peripherals

These modules are used for general purpose input/output to external ICs.

Each GPIO module supports up to 32 bits of I/O.

GPT General Purpose

Timer

Peripherals

Each GPT is a 32-bit “free-running” or “set and forget” mode timer with a

programmable prescaler and compare and capture register. A timer counter

value can be captured using an external event, and can be configured to

trigger a capture event on either the leading or trailing edges of an input

pulse. When the timer is configured to operate in “set and forget” mode, it is

capable of providing precise interrupts at regular intervals with minimal

processor intervention. The counter has output compare logic to provide the

status and interrupt at comparison. This timer can be configured to run either

on an external clock or on an internal clock.

GPU3D Graphics

Processing Unit

Multimedia

Peripherals

The GPU, version 3, provides hardware acceleration for 2D and 3D graphics

algorithms with sufficient processor power to run desk-top quality interactive

graphics applications on displays up to HD1080 resolution. It supports color

representation up to 32 bits per pixel. GPU enables high-performance

mobile 3D and 2D vector graphics at rates up to 33 Mtriangles/s,

200 Mpix/s, 800 Mpix/s (z).

GPU2D Graphics

Processing

Unit-2D

Multimedia

Peripherals

The GPU2D version 1, provides hardware acceleration for 2D graphic

algorithms with sufficient processor power to run desk-top quality interactive

graphics applications on displays up to HD1080 resolution.

I2C-1

I2C-2

I2C-3

I2C Controller Connectivity

Peripherals

I2C provides serial interface for controlling peripheral devices. Data rates of

up to 400 kbps are supported.

IIM IC Identification

Module

Security The IC identification module (IIM) provides an interface for reading,

programming, and/or overriding identification and control information stored

in on-chip fuse elements. The module supports electrically programmable

poly fuses (e-Fuses). The IIM also provides a set of volatile

software-accessible signals that can be used for software control of

hardware elements not requiring non-volatility. The IIM provides the primary

user-visible mechanism for interfacing with on-chip fuse elements. Among

the uses for the fuses are unique chip identifiers, mask revision numbers,

cryptographic keys, JTAG secure mode, boot characteristics, and various

control signals requiring permanent non-volatility. The IIM also provides up

to 28 volatile control signals. The IIM consists of a master controller, a

software fuse value shadow cache, and a set of registers to hold the values

of signals visible outside the module.

IIM interfaces to the electrical fuse array (split to banks). Enabled to set up

boot modes, security levels, security keys and many other system

parameters.

i.MX53A consists of 4 x 256-bit + 1 x 128-bit fuse-banks (total 1152 bits)

through IIM interface.

Table 2. i.MX53 Digital and Analog Blocks (continued)

Block

Mnemonic Block Name Subsystem Brief Description

Modules List

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 11

IOMUXC IOMUX Control System

Control

Peripherals

This module enables flexible I/O multiplexing. Each I/O pad has default as

well as several alternate functions. The alternate functions are software

configurable.

IPU Image

Processing Unit

Multimedia

Peripherals

Version 3M IPU enables connectivity to displays, relevant processing and

synchronization. It supports two display ports and two camera ports, through

the following interfaces:

• Legacy parallel interfaces

• Single/dual channel LVDS display interface

• Analog TV or VGA interfaces

The processing includes:

• Image enhancement—color adjustment and gamut mapping, gamma

correction and contrast enhancement

• Video/graphics combining

• Support for display backlight reduction

• Image conversion—resizing, rotation, inversion and color space

conversion

• Hardware de-interlacing support

• Synchronization and control capabilities, allowing autonomous operation.

KPP Keypad Port Connectivity

Peripherals

The KPP supports an 8 ×8 external keypad matrix. The KPP features are

as follows:

• Open drain design

• Glitch suppression circuit design

• Multiple keys detection

• Standby key press detection

LDB LVDS Display

Bridge

Connectivity

Peripherals

LVDS display bridge is used to connect the IPU (image processing unit) to

external LVDS display interface. LDB supports two channels; each channel

has following signals:

• 1 clock pair

•4 data pairs

On-chip differential drivers are provided for each pair.

OWIRE One-Wire

Interface

Connectivity

Peripherals

One-wire support provided for interfacing with an on-board EEPROM, and

smart battery interfaces, for example, Dallas DS2502.

PATA Parallel ATA Connectivity

Peripherals

The PATA block is a AT attachment host interface. Its main use is to interface

with hard disk drives and optical disc drives. It interfaces with the ATA-6

compliant device over a number of ATA signals. It is possible to connect a

bus buffer between the host side and the device side.

PWM-1

PWM-2

Pulse Width

Modulation

Connectivity

Peripherals

The pulse-width modulator (PWM) has a 16-bit counter and is optimized to

generate sound from stored sample audio images. It can also generate

tones. The PWM uses 16-bit resolution and a 4 x 16 data FIFO to generate

sound.

INTRAM Internal RAM Internal

Memory

Internal RAM, shared with VPU.

The on-chip memory controller (OCRAM) module, is an interface between

the system’s AXI bus, to the internal (on-chip) SRAM memory module. It is

used for controlling the 128 KB multimedia RAM, through a 64-bit AXI bus.

BOOTROM Boot ROM Internal

Memory

Supports secure and regular boot modes.

The ROM controller supports ROM patching.

Table 2. i.MX53 Digital and Analog Blocks (continued)

Block

Mnemonic Block Name Subsystem Brief Description

i.MX53 Applications Processors for Industrial Products, Rev. 7

12 Freescale Semiconductor

Modules List

RTIC Run-Time

Integrity Checker

Security Protecting read only data from modification is one of the basic elements in

trusted platforms. The run-time integrity checker, version 3 (RTIC) block is

a data-monitoring device responsible for ensuring that the memory content

is not corrupted during program execution. The RTIC mechanism

periodically checks the integrity of code or data sections during normal OS

run-time execution without interfering with normal operation. The purpose of

the RTIC is to ensure the integrity of the peripheral memory contents,

protect against unauthorized external memory elements replacement and

assist with boot authentication.

SAHARA SAHARA

Security

Accelerator

Security SAHARA (symmetric/asymmetric hashing and random accelerator),

version 4, is a security coprocessor. It implements symmetric encryption

algorithms, (AES, DES, 3DES, RC4 and C2), public key algorithms (RSA

and ECC), hashing algorithms (MD5, SHA-1, SHA-224 and SHA-256), and

a hardware true random number generator. It has a slave IP Bus interface

for the host to write configuration and command information, and to read

status information. It also has a DMA controller, with an AHB bus interface,

to reduce the burden on the host to move the required data to and from

memory.

SATA Serial ATA Connectivity

Peripherals

SATA HDD interface, includes the SATA controller and the PHY. It is a

complete mixed-signal IP solution for SATA HDD connectivity.

SCCv2 Security

Controller, ver. 2

Security The security controller is a security assurance hardware module designed

to safely hold sensitive data, such as encryption keys, digital right

management (DRM) keys, passwords and biometrics reference data. The

SCCv2 monitors the system’s alert signal to determine if the data paths to

and from it are secure, that is, it cannot be accessed from outside of the

defined security perimeter. If not, it erases all sensitive data on its internal

RAM. The SCCv2 also features a key encryption module (KEM) that allows

non-volatile (external memory) storage of any sensitive data that is

temporarily not in use. The KEM utilizes a device-specific hidden secret key

and a symmetric cryptographic algorithm to transform the sensitive data into

encrypted data.

SDMA Smart Direct

Memory Access

System

Control

Peripherals

The SDMA is multi-channel flexible DMA engine. It helps in maximizing

system performance by off loading various cores in dynamic data routing.

The SDMA features list is as follows:

• Powered by a 16-bit instruction-set micro-RISC engine

• Multi-channel DMA supports up to 32 time-division multiplexed DMA

channels

• 48 events with total flexibility to trigger any combination of channels

• Memory accesses including linear, FIFO, and 2D addressing

• Shared peripherals between ARM and SDMA

• Very fast context-switching with two-level priority-based preemptive

multi-tasking

• DMA units with auto-flush and prefetch capability

• Flexible address management for DMA transfers (increment, decrement,

and no address changes on source and destination address)

• DMA ports can handle unidirectional and bidirectional flows (copy mode)

• Up to 8-word buffer for configurable burst transfers to / from the EXTMC

• Support of byte swapping and CRC calculations

• A library of scripts and API is available

Table 2. i.MX53 Digital and Analog Blocks (continued)

Block

Mnemonic Block Name Subsystem Brief Description

Modules List

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 13

SECRAM Secure /

Non-secure RAM

Internal

Memory

Secure / non-secure Internal RAM, controlled by SCC.

SJC Secure JTAG

Interface

System

Control

Peripherals

JTAG manipulation is a known hacker’s method of executing unauthorized

program code, getting control over secure applications, and running code in

privileged modes. The JTAG port provides a debug access to several

hardware blocks including the ARM processor and the system bus.

The JTAG port must be accessible during platform initial laboratory bring-up,

manufacturing tests and troubleshooting, as well as for software debugging

by authorized entities. However, in order to properly secure the system,

unauthorized JTAG usage should be strictly forbidden.

In order to prevent JTAG manipulation while allowing access for

manufacturing tests and software debugging, the i.MX53 processor

incorporates a mechanism for regulating JTAG access. SJC provides four

different JTAG security modes that can be selected through an e-fuse

configuration.

SPBA Shared

Peripheral Bus

Arbiter

System

Control

Peripherals

SPBA (shared peripheral bus arbiter) is a two-to-one IP bus interface (IP

bus) arbiter.

SPDIF Sony Philips

Digital Interface

Multimedia

Peripherals

A standard digital audio transmission protocol developed jointly by the Sony

and Philips corporations. Both transmitter and receiver functionalists are

supported.

SRTC Secure Real

Time Clock

Security The SRTC incorporates a special system state retention register (SSRR)

that stores system parameters during system shutdown modes. This

NVCC_SRTC_POW. The NVCC_SRTC_POW can be energized separately

even if all other supply rails are shut down. This register is helpful for storing

warm boot parameters. The SSRR also stores the system security state. In

case of a security violation, the SSRR mark the event (security violation

indication).

SSI-1

SSI-2

SSI-3

I2S/SSI/AC97

Interface

Connectivity

Peripherals

The SSI is a full-duplex synchronous interface used on the i.MX53A

processor to provide connectivity with off-chip audio peripherals. The SSI

interfaces connect internally to the AUDMUX for mapping to external ports.

The SSI supports a wide variety of protocols (SSI normal, SSI network, I2S,

and AC-97), bit depths (up to 24 bits per word), and clock/frame sync

options.

Each SSI has two pairs of 8 x 24 FIFOs and hardware support for an

external DMA controller in order to minimize its impact on system

performance. The second pair of FIFOs provides hardware interleaving of a

second audio stream, which reduces CPU overhead in use cases where two

time slots are being used simultaneously.

Table 2. i.MX53 Digital and Analog Blocks (continued)

Block

Mnemonic Block Name Subsystem Brief Description

i.MX53 Applications Processors for Industrial Products, Rev. 7

14 Freescale Semiconductor

Modules List

IPTP IEEE1588

Precision Time

Protocol

Connectivity

Peripherals

The IEEE 1588-2002 (version 1) standard defines a precision time protocol

(PTP) - which is a time-transfer protocol that enables synchronization of

networks (for example, Ethernet), to a high degree of accuracy and

precision.

The IEEE1588 hardware assist is composed of the two blocks: time stamp

unit and real time clock, which provide the timestamping protocol’s

functionality, generating and reading the needed timestamps.

The hardware-assisted implementation delivers more precise clock

synchronization at significantly lower CPU load compared to purely software

implementations.

Temperature

Monitor

(Part of SATA

Block)

System

Control

Peripherals

The temperature sensor is an internal module to the i.MX53 that monitors

the die temperature. The monitor is capable in generating SW interrupt, or

trigger the CCM, to reduce the core operating frequency.

TVE TV Encoder Multimedia The TV encoder, version 2.1 is implemented in conjunction with the image

processing unit (IPU) allowing handheld devices to display captured still

images and video directly on a TV or LCD projector. It supports composite

PAL/NTSC, VGA, S-video, and component up to HD1080p analog video

outputs.

TZIC TrustZone Aware

Interrupt

Controller

ARM/Control The TrustZone interrupt controller (TZIC) collects interrupt requests from all

i.MX53 sources and routes them to the ARM core. Each interrupt can be

configured as a normal or a secure interrupt. Software Force Registers and

software Priority Masking are also supported.

UART-1

UART-2

UART-3

UART-4

UART-5

UART Interface Connectivity

Peripherals

Each of the UART blocks supports the following serial data transmit/receive

protocols and configurations:

• 7 or 8-bit data words, 1 or 2 stop bits, programmable parity (even, odd, or

none)

• Programmable bit-rates up to 4 Mbps. This is a higher max baud rate

relative to the 1.875 Mbps, which is specified by the TIA/EIA-232-F

standard.

• 32-byte FIFO on Tx and 32 half-word FIFO on Rx supporting auto-baud

• IrDA 1.0 support (up to SIR speed of 115200 bps)

• Option to operate as 8-pins full UART, DCE, or DTE

USB USB Controller Connectivity

Peripherals

USB supports USB2.0 480 MHz, and contains:

• One high-speed OTG sub-block with integrated HS USB PHY

• One high-speed host sub-block with integrated HS USB PHY

• Two identical high-speed Host modules

The high-speed OTG module, which is internally connected to the HS USB

PHY, is equipped with transceiver-less logic to enable on-board USB

connectivity without USB transceivers

All the USB ports are equipped with standard digital interfaces (ULPI, HS

IC-USB) and transceiver-less logic to enable onboard USB connectivity

without USB transceivers.

Table 2. i.MX53 Digital and Analog Blocks (continued)

Block

Mnemonic Block Name Subsystem Brief Description

Modules List

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 15

VPU Video Processing

Unit

Multimedia

Peripherals

A high-performing video processing unit (VPU) version 3, which covers

many SD-level video decoders and SD-level encoders as a multi-standard

video codec engine as well as several important video processing such as

rotation and mirroring.

VPU Features:

• MPEG-2 decode, Mail-High profile, up to 1080i/p resolution, 40 Mbps bit

rate

• MPEG4/XviD decode, SP/ASP profile, up to 1080 i/p resolution, 40 Mbps

bit rate

• H.263 decode, P0/P3 profile, up to 16CIF resolution, 20 Mbps bit rate

• H.264 decode, BP/MP/HP profile, up to 1080 i/p resolution, 40 Mbps bit

rate

• VC1 decode, SP/MP/AP profile, up to 1080 i/p resolution, 40 Mbps bit

rate

• RV10 decode, 8/9/2010 profile, up to 1080 i/p resolution, 40 Mbps bit rate

• DivX decode, 3/4/5/6 profile, up to 1080 i/p resolution, 40 Mbps bit rate

• MJPEG decode, Baseline profile, up to 8192 x 8192 resolution,

40 Mpixel/s bit rate for 4:4:4 format

• MPEG4 encode, Simple profile, up to 720p resolution, 12 Mbps bit rate1

• H.263 encode, P0/P3 profile, up to 4CIF resolution, 8 Mbps bit rate1

• H.264 encode, Baseline profile, up to 720p resolution, 14 Mbps bit rate1

• MJPEG encode, Baseline profile, up to 8192 x 8192 resolution,

80 Mpixel/s bit rate for 4:2:2 format

WDOG-1 Watch Dog Timer

Peripherals

The watch dog timer supports two comparison points during each counting

period. Each of the comparison points is configurable to evoke an interrupt

to the ARM core, and a second point evokes an external event on the

WDOG line.

WDOG-2

(TZ)

Watch Dog

(TrustZone)

Timer

Peripherals

The TrustZone watchdog (TZ WDOG) timer module protects against

TrustZone starvation by providing a method of escaping normal mode and

forcing a switch to the TZ mode. TZ starvation is a situation where the

normal OS prevents switching to the TZ mode. This situation should be

avoided, as it can compromise the system’s security. Once the TZ WDOG

module is activated, it must be serviced by TZ software on a periodic basis.

If servicing does not take place, the timer times out. Upon a time-out, the TZ

WDOG asserts a TZ mapped interrupt that forces switching to the TZ mode.

If it is still not served, the TZ WDOG asserts a security violation signal to the

CSU. The TZ WDOG module cannot be programmed or deactivated by a

normal mode SW.

XTALOSC 24 MHz Crystal

Oscillator

Clocking Provides a crystal oscillator amplifier that supports a 24 MHz external crystal

XTALOSC_

32K

32.768 kHz

Crystal Oscillator

I/F

Clocking Provides a crystal oscillator amplifier that supports a 32.768 kHz external

crystal.

1VPU can generate higher bit rate than the maximum specified by the corresponding standard.

Table 2. i.MX53 Digital and Analog Blocks (continued)

Block

Mnemonic Block Name Subsystem Brief Description

i.MX53 Applications Processors for Industrial Products, Rev. 7

16 Freescale Semiconductor

Electrical Characteristics

3.1 Special Signal Considerations

The package contact assignments can be found in Section 6, “Package Information and Contact

Assignments.” Signal descriptions are defined in the i.MX53 Reference Manual. Special signal

considerations information is contained in Chapter 1 of i.MX53 System Development User's Guide

(MX53UG).

4 Electrical Characteristics

This section provides the device and module-level electrical characteristics for the i.MX53 processor.

4.1 Chip-Level Conditions

This section provides the device-level electrical characteristics for the IC. See Table 3 for a quick reference

to the individual tables and sections.

4.1.1 Absolute Maximum Ratings

CAUTION

Stresses beyond those listed under Table 4 may affect reliability or cause

permanent damage to the device. These are stress ratings only. Functional

operation of the device at these or any other conditions beyond those

indicated in the Operating Ranges table is not implied.

Table 3. i.MX53 Chip-Level Conditions

For these characteristics, … Topic appears …

Absolute Maximum Ratings Table 4 on page 16

TEPBGA-2 Package Thermal Resistance Data Table 5 on page 17

i.MX53 Operating Ranges Table 6 on page 18

External Clock Sources Table 7 on page 20

Maximal Supply Currents Table 8 on page 20

USB Interface Current Consumption Table 9 on page 23

Table 4. Absolute Maximum Ratings

Parameter Description Symbol Min Max Unit

Peripheral Core Supply Voltage VCC -0.3 1.35 V

ARM Core Supply Voltage VDDGP -0.3 1.4 V

Supply Voltage UHVIO Supplies denoted as I/O Supply -0.5 3.6 V

Supply Voltage for non UHVIO Supplies denoted as I/O Supply -0.5 3.3 V

USB VBUS VBUS — 5.25 V

Electrical Characteristics

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 17

4.1.2 Thermal Resistance

4.1.2.1 TEPBGA-2 Package Thermal Resistance

Table 5 provides the TEPBGA-2 package thermal resistance data.

Input voltage on USB_OTG_DP, USB_OTG_DN,

USB_H1_DP, USB_H1_DN pins

USB_DP/USB_DN -0.3 3.631V

Input/Output Voltage Range Vin/Vout -0.5 OVDD +0.32V

ESD Damage Immunity: Vesd V

• Human Body Model (HBM)

• Charge Device Model (CDM)

—

2000

500

Storage Temperature Range TSTORAGE -40 150 oC

1USB_DN and USB_DP can tolerate 5 V for up to 24 hours.

2The term OVDD in this section refers to the associated supply rail of an input or output. The association is described in

Table 111 on page 148. The maximum range can be superseded by the DC tables.

Table 5. TEPBGA-2 Package Thermal Resistance Data

Rating Board Symbol Value Unit

Junction to Ambient (natural convection)1, 2

1Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)

temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal

resistance.

2Per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9 specification.

Single layer board

(1s)

RθJA 28 °C/W

Junction to Ambient (natural convection)1, 2, 3

3Per JEDEC JESD51-6 with the board horizontal.

Four layer board

(2s2p)

RθJA 16 °C/W

Junction to Ambient (at 200 ft/min)1, 3 Single layer board

(1s)

RθJMA 21 °C/W

Junction to Ambient (at 200 ft/min)1, 3 Four layer board

(2s2p)

RθJMA 13 °C/W

Junction to Board4

4Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on

the top surface of the board near the package.

—R

θJB 6°C/W

Junction to Case5

5Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method

1012.1).

—R

θJC 4°C/W

Junction to Package Top (natural convection)6

6Thermal characterization parameter indicating the temperature difference between package top and the junction temperature

per JEDEC JESD51-2.

—ΨJT 4°C/W

Table 4. Absolute Maximum Ratings (continued)

Parameter Description Symbol Min Max Unit

i.MX53 Applications Processors for Industrial Products, Rev. 7

18 Freescale Semiconductor

Electrical Characteristics

4.1.3 Operating Ranges

Table 6 provides the operating ranges of i.MX53 processor.

Table 6. i.MX53 Operating Ranges

Symbol Parameter Minimum1Nominal2Maximum1Unit

VDDGP3ARM core supply voltage

fARM ≤400 MHz

0.9 0.95 1.15 V

ARM core supply voltage

fARM ≤800 MHz

1.05 1.1 1.15 V

ARM core supply voltage

Stop mode

0.8 0.85 1.15 V

VCC Peripheral supply voltage41.25 1.3 1.35 V

Peripheral supply voltage—Stop mode 0.9 0.95 1.35 V

VDDA5Memory arrays voltage 1.25 1.30 1.35 V

Memory arrays voltage—Stop mode 0.9 0.95 1.35 V

VDDAL15L1 Cache Memory arrays voltage 1.25 1.30 1.35 V

L1 Cache Memory arrays voltage—Stop mode 0.9 0.95 1.35 V

VDD_DIG_PLL6PLL Digital supplies—external regulator option 1.25 1.3 1.35 V

VDD_ANA_PLL7PLL Analog supplies—external regulator option 1.75 1.8 1.95 V

NVCC_CKIH ESD protection of the CKIH pins, FUSE read Supply

and 1.8V bias for the UHVIO pads

1.65 1.8 1.95 V

NVCC_LCD

NVCC_JTAG

GPIO digital power supplies 1.65 1.8 or

2.775

3.1 V

NVCC_LVDS LVDS interface Supply 2.375 2.5 2.75 V

NVCC_LVDS_BG LVDS Band Gap Supply 2.375 2.5 2.75 V

NVCC_EMI_DRAM DDR Supply DDR2 range 1.7 1.8 1.9 V

DDR Supply LPDDR2 range 1.14 1.2 1.3

DDR Supply LV-DDR2 range

1.47 1.55 1.63

1.42 1.5 1.58

DDR Supply DDR3 range 1.42 1.5 1.58

VDD_FUSE8Fusebox Program Supply (Write Only) 3.0 — 3.3 V

NVCC_NANDF

NVCC_SD1

NVCC_SD2

NVCC_PATA

NVCC_KEYPAD

NVCC_GPIO

NVCC_FEC

NVCC_EIM_MAIN

NVCC_EIM_SEC

NVCC_CSI

Ultra High voltage I/O (UHVIO) supplies: V

• UHVIO_L 1.65 1.8 1.95

• UHVIO_H 2.5 2.775 3.1

• UHVIO_UH 3.0 3.3 3.6

Electrical Characteristics

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 19

TVDAC_DHVDD9

TVDAC_AHVDDRGB9

TVE digital and analog power supply, TVE-to-DAC

level shifter supply, cable detector supply, analog

power supply to RGB channel

2.69 2.75 2.91 V

For GPIO use only, when TVE is not in use 1.65 1.8 or

2.775

3.1 V

NVCC_SRTC_POW SRTC Core and slow I/O Supply (GPIO)10 1.25 1.3 1.35 V

NVCC_RESET LVIO 1.65 1.8 or

2.775

3.1 V

USB_H1_VDDA25

USB_OTG_VDDA25

NVCC_XTAL

USB_PHY analog supply, oscillator amplifier analog

supply11

2.25 2.5 2.75 V

USB_H1_VDDA33

USB_OTG_VDDA33

USB PHY I/O analog supply 3.0 3.3 3.6 V

VBUS See Ta b l e 4 on page 16 and Table 104 on page 141

for details. Note that this is not a power supply.

————

VDD_REG12 Power supply input for the integrated linear

regulators

2.37 2.5 2.63 V

VP SATA PHY core power supply 1.25 1.3 1.35 V

VPH SATA PHY I/O supply voltage 2.25 2.5 2.75 V

TJJunction temperature -40 10513 125 oC

1Voltage at the package power supply contact must be maintained between the minimum and maximum voltages. The design

must allow for supply tolerances and system voltage drops.

2The nominal values for the supplies indicate the target setpoint for a tolerance no tighter than ± 50 mV. Use of supplies with

a tighter tolerance allows reduction of the setpoint with commensurate power savings.

3A voltage transition is allowed for the required supply ramp up to the nominal value prior to achieving a clock speed increase.

Similarly, to accommodate a frequency reduction, a voltage transition is allowed for a supply ramp down to the nominal value

after the frequency is decreased.

4For BSDL mode, the minimum operating temperature is 20 oC and the maximum operating temperature is the maximum

temperature specified for the particular part grade.

5VDDA and VDDAL1 can be driven by the VDD_DIG_PLL internal regulator using external connections. When operating in this

configuration, the regulator is still operating at the default 1.2 V, as bootup start. During bootup initialization, software should

increase this regulator voltage to match VCC (1.3 V nominal) in order to reduce internal leakage current.

6By default, VDD_DIG_PLL is driven from internal on-die 1.2 V linear regulator (LDO). In this case, there is no need driving this

supply externally. LDO output to VDD_DIG_PLL should be configured by software after power-up to 1.3 V output. A bypass

capacitor of minimal value 22 μF should be connected to this pad in any case whether it is driven internally or externally. Use

of the on-chip LDO is preferred. See i.MX53 System Development User’s Guide.

7By default, the VDD_ANA_PLL is driven from internal on-die 1.8 V linear regulator (LDO). In this case there is no need driving

this supply externally. A bypass capacitor of minimal value 22 μF should be connected to this pad in any case whether it is

driven internally or externally. Use of the on-chip LDO is preferred. See i.MX53 System Development User’s Guide.

8After fuses are programmed, Freescale strongly recommends the best practice of reading the fuses to verify that they are

written correctly. In Read mode, VDD_FUSE should be floated or grounded. Tying VDD_FUSE to a positive supply (3.0 V–3.3

V) increases the possibility of inadvertently blowing fuses and is not recommended in read mode.

9If not using the TVE module or other pads in this power domain for the product, the TVDAC_DHVDD and

TVDAC_AHVDDRGB can be kept floating or tied to GND—the recommendation is to float.

10 GPIO pad operational at low frequency

Table 6. i.MX53 Operating Ranges (continued)

Symbol Parameter Minimum1Nominal2Maximum1Unit

i.MX53 Applications Processors for Industrial Products, Rev. 7

20 Freescale Semiconductor

Electrical Characteristics

4.1.4 External Clock Sources

The i.MX53 device has four external input system clocks, a low frequency (CKIL), a high frequency

(XTAL), and two general purpose CKIH1 and CKIH2 clocks.

The CKIL is used for low-frequency functions. It supplies the clock for wake-up circuit, power-down real

time clock operation, and slow system and watch-dog counters. The clock input can be connected to either

external oscillator or a crystal using internal oscillator amplifier.

The system clock input XTAL is used to generate the main system clock. It supplies the PLLs and other

peripherals. The system clock input can be connected to either external oscillator or a crystal using internal

oscillator amplifier.

CKIH1 and CKIH2 provide additional clock source option for peripherals that require specific and

accurate frequencies.

Table 7 shows the interface frequency requirements. See Chapter 1 of i.MX53 System Development

User's Guide (MX53UG) for additional clock and oscillator information.

4.1.5 Maximal Supply Currents

Table 8 represents the maximal momentary current transients on power lines, and should be used for power

supply selection. Maximal currents higher by far than the average power consumption of typical use cases.

For typical power consumption information, see i.MX53 power consumption application note.

11 The analog supplies should be isolated in the application design. Use of series inductors is recommended.

12 VDD_REG is power supply input for the integrated linear regulators of VDD_ANA_PLL and VDD_DIG_PLL when they are

configured to the internal supply option. VDDR_REG still has to be tied to 2.5 V supply when VDD_ANA_PLL and

VDD_DIG_PLL are configured for external power supply mode although in this case it is not used as supply source.

13 Lifetime of 87,600 hours based on 105 oC junction temperature at nominal supply voltages.

Table 7. External Input Clock Frequency

Parameter Description Symbol Min Typ Max Unit

CKIL Oscillator1

1External oscillator or a crystal with internal oscillator amplifier.

fckil — 32.7682/32.0

2Recommended nominal frequency 32.768 kHz.

—kHz

CKIH1, CKIH2 Operating

Frequency

fckih1,

fckih2

See Table 32, "CAMP Electrical Parameters (CKIH1,

CKIH2)," on page 44

MHz

XTAL Oscillator fxtal 22 24 27 MHz

Table 8. Maximal Supply Currents

Power Line Conditions Max Current Unit

VDDGP 800 MHz ARM clock 1450 mA

VCC 800 mA

VDDA+VDDAL1 100 mA

VDD_DIG_PLL 10 mA

Electrical Characteristics

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 21

VP 20 mA

VDD_ANA_PLL 10 mA

NVCC_XTAL 25 mA

VDD_REG 325 mA

VDD_FUSE Fuse Write Mode

operation

120 mA

NVCC_EMI_DRAM1

1.8V (DDR2) 800 mA

1.5V (DDR3) 650 mA

1.2V (LPDDR2) 250 mA

TVDAC_DHVDD + TVDAC_AHVDDRGB 200 mA

NVCC_SRTC_POW 502μA

USB_H1_VDDA25 +

USB_OTG_VDDA25

50 mA

USB_H1_VDDA33 +

USB_OTG_VDDA33

20 mA

VPH 60 mA

NVCC_CKIH Use maximal I/O Eq3, N=4

NVCC_CSI Use maximal I/O Eq3, N=20

NVCC_EIM_MAIN Use maximal I/O Eq3, N=39

NVCC_EIM_SEC Use maximal I/O Eq3, N=16

NVCC_FEC Use maximal I/O Eq3, N=11

NVCC_GPIO Use maximal I/O Eq3, N=13

NVCC_JTAG Use maximal I/O Eq3, N=6

NVCC_KPAD Use maximal I/O Eq3, N=11

NVCC_LCD Use maximal I/O Eq3, N=29

NVCC_LVDS Use maximal I/O Eq3, N=20

NVCC_LVDS_BG Use maximal I/O Eq3, N=1

NVCC_NANDF Use maximal I/O Eq3, N=8

NVCC_PATA Use maximal I/O Eq3, N=29

NVCC_REST Use maximal I/O Eq3, N=5

Table 8. Maximal Supply Currents (continued)

Power Line Conditions Max Current Unit

i.MX53 Applications Processors for Industrial Products, Rev. 7

22 Freescale Semiconductor

Electrical Characteristics

NVCC_SD1 Use maximal I/O Eq3, N=6

NVCC_SD2 Use maximal I/O Eq3, N=6

1The results are based on calculation assuming the following conditions:

—Four 16-bit DDR devices

—Heavy use profile

—On-Die Termination (ODT) of 50 Ω for DDR2 and 40 Ω for DDR3

—Dual rank termination schema

—Command and Address line termination to NVCC_EMI_DRAM/2 voltage

These numbers include both i.MX53 DDR controller I/O current consumption and DDR memory I/O power

consumption for data and DQS lines.

250 μA current is the worst case for fast silicon at 125 °C. The typical current is 3 μA for typical silicon at 25 °C.

3General Equation for estimated, maximal power consumption of an I/O power supply:

Imax = N x C x V x (0.5 x F)

Where:

N - Number of I/O pins supplies by the power line

C - Equivalent external capacitive load

V - I/O voltage

(0.5 x F) - Data change rate. Up to 0.5 of the clock rate (F).

Table 8. Maximal Supply Currents (continued)

Power Line Conditions Max Current Unit

Electrical Characteristics

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 23

4.1.6 USB-OH-3 (OTG + 3 Host ports) Module and the Two USB PHY (OTG

and H1) Current Consumption

Table 9 shows the USB interface current consumption.

4.2 Power Supply Requirements and Restrictions

The system design must comply with power-up sequence, power-down sequence and steady state

guidelines as described in this section to guarantee the reliable operation of the device. Any deviation from

these sequences may result in the following situations:

• Excessive current during power-up phase

• Prevention of the device from booting

• Irreversible damage to the i.MX53 processor (worst-case scenario)

4.2.1 Power-Up Sequence

The following observations should be considered:

• The consequent steps in power up sequence should not start before the previous step supplies have

been stabilized within 90-110% of their nominal voltage, unless stated otherwise.

• NVCC_SRTC_POW should remain powered ON continuously, to maintain internal real-time

clock status. Otherwise, it has to be powered ON together with VCC, or preceding VCC.

• The VCC should be powered ON together, or any time after NVCC_SRTC_POW.

• NVCC_CKIH should be powered ON after VCC is stable and before other I/O supplies

(NVCC_xxx) are powered ON.

Table 9. USB Interface Current Consumption

Parameter Conditions Typical at 25 °C Max Unit

Analog Supply 3.3 V

USB_H1_VDDA33

USB_OTG_VDDA33

Full Speed

RX 5.5 6 mA

TX 7 8

High Speed

RX 5 6

TX 5 6

Analog Supply 2.5 V

USB_H1_VDDA25

USB_OTG_VDDA25

Full Speed

RX 6.5 7 mA

TX 6.5 7

High Speed

RX 12 13

TX 21 22

Digital Supply

VCC (1.2 V)

Full Speed

RX 8 — mA

TX 8 —

High Speed

RX 8 —

TX 8 —

i.MX53 Applications Processors for Industrial Products, Rev. 7

24 Freescale Semiconductor

Electrical Characteristics

• I/O Supplies (NVCC_xxx) below or equal to 2.8 V nom./3.1 V max. should not precede

NVCC_CKIH. They can start powering ON during NVCC_CKIH ramp-up, before it is stabilized.

Within this group, the supplies can be powered-up in any order.

Alternatively, the on-chip regulator VDD_ANA_PLL can be used to power NVCC_CKIH and

NVCC_RESET. In this case, the sequence defined in the “Interfacing the i.MX53 Processor with

LTC3589-1” section of the i.MX53 System Development User's Guide (MX53UG) must be

followed.

• I/O Supplies (NVCC_xxx) above 2.8 V nom./3.1 V max. should be powered ON only after

NVCC_CKIH is stable.

• In case VDD_DIG_PLL and VDD_ANA_PLL are powered ON from internal voltage regulator

(default case for i.MX53), there are no related restrictions on VDD_REG, as it is used as their

internal regulators power source.

If VDD_DIG_PLL and VDD_ANA_PLL are powered on externally, to reduce current leakage

during the power-up, it is recommended to activate the VDD_REG before or at the same time with

VDD_DIG_PLL and VDD_ANA_PLL. If this sequencing is not possible, make sure that the 2.5 V

VDD_REG supply shut-off output impedance is higher than 1 kΩ when it is inactive.

• VDD_REG supply is required to be powered ON to enable DDR operation. It must be powered on

after VCC and before NVCC_EMI_DRAM. The sequence should be:

VCC →VDD_REG →NVCC_EMI_DRAM

• If SRTC is not used, VDDA and VDDAL1 can be powered ON anytime before POR_B, regardless

of any other power signal.

• When SRTC is used, VDDA and VDDAL1 must be powered on before VDD_REG.

• VDDGP can be powered ON anytime before POR_B, regardless of any other power signal.

• VP and VPH can be powered up together, or anytime after, the VCC. VP and VPH should come

before POR.

• TVDAC_DHVDD and TVDAC_AHVDDRGB should be powered from the same regulator. This

is due to ESD diode protection circuit, that may cause current leakage if one of the supplies is

powered ON before the other.

NOTE

The POR_B input must be immediately asserted at power-up and remain

asserted until after the last power rail reaches its working voltage.

NOTE

If NVCC_RESET power is removed or interrupted, a power-on reset is

generated.

Electrical Characteristics

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 25

Figure 2 shows the power-up sequence diagram.

Figure 2. Power-Up Detailed Sequence

1If fuse writing is required, VDD_FUSE should be powered ON after NVCC_CKIH is stable.

2When SRTC is used, VDD_REG must power on after VDDA and VDDAL1.

NOTE

Need to ensure that there is no back voltage (leakage) from any supply on

the board towards the 3.3 V supply (for example, from the parts that use

both 1.8 V and the 3.3 V supply).

NOTE

For further details on power-up sequence, see the “Setting up Power

Management” chapter of i.MX53 System Development User’s Guide

(MX53UG).

NVCC_CKIH

(in any order, after NVCC_CKIH

POR_B

Δt>0

VCC 90%

90%

(in any order, if needed)

Δt>0

90%

NVCC_SRTC_POW

(may remain ON) 90%

I/O Supplies below or equal to

I/O Supplies above 2.8 V nom./3.1 V max

2.8 V nom./3.1 V max.

90%

Δt>0

90%

Δt>0

VDD_REG2

NVCC_EMI_DRAM

Δt>0

(in any order)

VP, VPH

Δt>0

90%

ramp up start, if needed)

(in any order)

VDDA,VDDAL1,VDDGP

Δt>0

90%

i.MX53 Applications Processors for Industrial Products, Rev. 7

26 Freescale Semiconductor

Electrical Characteristics

4.2.2 Power-Down Sequence

Power-down sequence should follow one of the following two options:

• Option 1: Switch all supplies down simultaneously with further free discharge. A deviation of few

microseconds of actual power-down of the different power rails is acceptable.

• Option 2: Switch down supplies, in any order, keeping the following rules:

— NVCC_CKIH must be powered down at the same time or after the UHVIO I/O cell supplies

(for full supply list, see Table 6, Ultra High voltage I/O (UHVIO) supplies). A deviation of few

microseconds of actual power-down of the different power rails is acceptable.

— VDD_REG must be powered down at the same time or after NVCC_EMI_DRAM supply. A

deviation of few microseconds of actual power-down of the different power rails is acceptable.

— If all of the following conditions are met:

– VDD_REG is powered down to 0V (Not Hi-Z)

– VDD_DIG_PLL and VDD_ANA_PLL are provided externally,

– VDD_REG is powered down before VDD_DIG_PLL and VDD_ANA_PLL

Then the following rule should be kept: VDD_REG output impedance must be higher than 1

kW, when inactive.

4.2.3 Power Supplies Usage

• All I/O pins should not be externally driven while the I/O power supply for the pin (NVCC_xxx)

is off. This can cause internal latch-up and malfunctions due to reverse current flows. For

information about I/O power supply of each pin, see “Power Rail” columns in pin list tables of

Section 6, “Package Information and Contact Assignments.”

• If not using SATA interface and the embedded thermal sensor, the VP and VPH should be

grounded. In particular, keeping VPH turned OFF while the VP is powered ON is not

recommended and might lead to excessive power consumption.

• When internal clock source is used for SATA temperature monitor the USB_PHY supplies and

PLL need to be active because they are providing the clock.

• If not using the TVE module, the TVDAC_DHVDD and TVDAC_AHVDDRGB can be kept

floating or tied to GND—the recommendation is to float. If only the GPIO pads in

TVDAC_AHVDDRGB domain are in use, the supplies can be set to GPIO pad voltage range

(1.65 V to 3.1 V).

4.3 I/O DC Parameters

This section includes the DC parameters of the following I/O types:

• General Purpose I/O (GPIO)

• Double Data Rate 3 I/O (DDR3) for DDR2/LVDDR2, LPDDR2 and DDR3 modes

• Low Voltage I/O (LVIO)

• Ultra High Voltage I/O (UHVIO)

• LVDS I/O

Electrical Characteristics

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 27

NOTE

The term ‘OVDD’ in this section refers to the associated supply rail of an

input or output. The association is shown in Table 111.

Figure 3. Circuit for Parameters Voh and Vol for I/O Cells

4.3.1 General Purpose I/O (GPIO) DC Parameters

The parameters in Table 10 are guaranteed per the operating ranges in Table 6, unless otherwise noted.

Table 10 shows DC parameters for GPIO pads, operating at two supply ranges:

• 1.1 V to 1.3 V

• 1.65 V to 3.1 V

Table 10. GPIO I/O DC Electrical Characteristics

Parameter Symbol Test Conditions Min Typ Max Unit

High-level output voltage1Voh Iout = -0.8 mA OVDD - 0.15 — — V

Low-level output voltage1Vol Iout = 0.8 mA — — 0.15 V

High-Level DC input voltage1, 2VIH — 0.7 ×OVDD — OVDD V

Low-Level DC input voltage1, 2VIL — 0 — 0.3 ×OVDD V

Input Hysteresis VHYS OVDD = 1.875 V

OVDD = 2.775 V

0.25 0.34

0.45

—V

Schmitt trigger VT+2, 3 VT+ — 0.5 ×OVDD — — V

Schmitt trigger VT-2, 3 VT- — — — 0.5 ×OVDD V

Input current (no pull-up/down) Iin Vin = OVDD or 0 — — 10 μA

Input current (22 kΩ Pull-up) Iin Vin = 0 V

Vin = OVDD

——161

μA

Input current (47 kΩ Pull-up) Iin Vin = 0 V

Vin = OVDD

——76

μA

Input current (100 kΩ Pull-up) Iin Vin = 0 V

Vin= OVDD

——40

μA

i.MX53 Applications Processors for Industrial Products, Rev. 7

28 Freescale Semiconductor

Electrical Characteristics

4.3.2 LPDDR2 I/O DC Parameters

The LPDDR2 I/O pads support DDR2/LVDDR2, LPDDR2, and DDR3 operational modes.

4.3.2.1 DDR2 Mode I/O DC Parameters

The DDR2 interface fully complies with JESD79-2E DDR2 JEDEC standard release April, 2008. The

parameters in Table 11 are guaranteed per the operating ranges in Table 6, unless otherwise noted.

Input current (100 kΩ Pull-down) Iin Vin = 0 V

Vin = OVDD

——10

μA

Keeper Circuit Resistance — 1304—kΩ

1Overshoot and undershoot conditions (transitions above OVDD and below GND) on switching pads must be held below 0.6 V,

and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/ undershoot must

be controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other

methods. Non-compliance to this specification may affect device reliability or cause permanent damage to the device.

2To maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current DC

level through to the target DC level, VIL or VIH. Monotonic input transition time is from 0.1 ns to 1 s.

3Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled.

4Use an off-chip pull resistor of less than 60 kΩ to override this keeper.

Table 11. DDR2 I/O DC Electrical Parameters1

1Note that the JEDEC SSTL_18 specification (JESD8-15a) for a SSTL interface for class II operation supersedes any

specification in this document.

Parameters Symbol Test Conditions Min Typ Max Unit

High-level output voltage2

2OVDD is the I/O power supply (1.7 V–1.9 V for DDR2)

Voh Ioh = -0.1 mA 0.9 x OVDD — — V

Low-level output voltage Vol Iol = 0.1 mA — — 0.1 x OVDD V

Input Reference Voltage Vref 0.49 x

OVDD

0.5 x OVDD 0.51 x OVDD

DC input High Voltage (data pins) Vihd

(dc)

— Vref+0.125V — OVDD+0.3 V

DC input Low Voltage (data pins) Vild (dc) — -0.3 — Vref - 0.125V V

DC Input voltage range of each

differential input3

Vin (dc) — -0.3 — OVDD + 0.3 V

DC Differential input voltage required for

switching 4

Vid (dc) — 0.25 — OVDD + 0.6 V

Termination Voltage Vtt Vtt Vref - 0.04 Vref Vref + 0.04 V

Input current (no pull-up/down) Iin Vin = 0 V

Vin = OVDD

—

μA

Keeper Circuit Resistance — — — 1305—kΩ

Table 10. GPIO I/O DC Electrical Characteristics (continued)

Parameter Symbol Test Conditions Min Typ Max Unit

Electrical Characteristics

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 29

4.3.2.2 LPDDR2 Mode I/O DC Parameters

The LPDDR2 interface fully complies with JESD209-2B LPDDR2 JEDEC standard release June, 2009.

The parameters in Table 12 are guaranteed per the operating ranges in Table 6, unless otherwise noted.

4.3.2.3 DDR3 Mode I/O DC Parameters

The DDR3 interface fully complies with JESD79-3D DDR3 JEDEC standard release April, 2008. The

parameters in Table 13 are guaranteed per the operating ranges in Table 6, unless otherwise noted.

3Vin(dc) specifies the allowable DC voltage exertion of each differential input.

4Vid(dc) specifies the input differential voltage |Vtr-Vcp| required for switching, where Vtr is the “true” input level and Vcp is the

“complementary” input level. The minimum value is equal to Vih(dc) -Vil(dc).

5Use an off-chip pull resistor of less than 60 kΩ to override this keeper.

Table 12. LPDDR2 I/O DC Electrical Parameters1

1Note that the JEDEC LPDDR2 specification (JESD209_2B) supersedes any specification in this document.

Parameters Symbol Test Conditions Min Typ Max Unit

High-level output voltage Voh Ioh = -0.1 mA 0.9 x OVDD — — V

Low-level output voltage Vol Iol = 0.1 mA — — 0.1 x OVDD V

Input Reference Voltage Vref 0.49 x

OVDD

0.5 x OVDD 0.51 x OVDD

DC input High Voltage Vih(dc) — Vref+0.13V — OVDD V

DC input Low Voltage Vil(dc) — OVSS — Vref - 0.13V V

Differential Input Logic High Vih(diff) 0.26 See Note2

2The single-ended signals need to be within the respective limits (Vih(dc) max, Vil(dc) min) for single-ended signals as well as

the limitations for overshoot and undershoot.

Differential Input Logic Low Vil(diff) See Note2-0.26

Input current (no pull-up/down) Iin Vin = 0 V

Vin = OVDD

—

μA

Pull-up/Pull-down impedance Mismatch -15 +15 %

240 Ω unit calibration resolution 10 Ω

Keeper Circuit Resistance — — — 1403

3Use an off-chip pull resistor of less than 60 kΩ to override this keeper.

—kΩ

Table 13. DDR3 I/O DC Electrical Parameters

Parameters Symbol Test Conditions Min Typ Max Unit

High-level output voltage Voh Ioh = -0.1 mA 0.8 x OVDD1——V

Low-level output voltage Vol Iol = 0.1 mA — — 0.2 x OVDD V

DC input Logic High VIH(dc) — Vref2+0.1 — OVDD V

DC input Logic Low VIL(dc) — OVSS — Vref-0.1 V

Differential input Logic High VIH(diff) — 0.2 — See Note3V

i.MX53 Applications Processors for Industrial Products, Rev. 7

30 Freescale Semiconductor

Electrical Characteristics

4.3.3 Low Voltage I/O (LVIO) DC Parameters

The parameters in Table 14 are guaranteed per the operating ranges in Table 6, unless otherwise noted.

The LVIO pads operate only as inputs.

Differential input Logic Low VIL(diff) — See Note3—-0.2V

Over/undershoot peak Vpeak — — — 0.4 V

Over/undershoot area

(above OVDD or below OVSS)

Varea — — — 0.67 V-ns

Termination Voltage Vtt Vtt tracking OVDD/2 0.49 x OVDD Vref 0.51 x OVDD V

Input current (no pull-up/down) Iin VI = 0 V

VI=OVDD

—

μA

Pull-up/Pull-down impedance mismatch — Minimum impedance

configuration

—— 3Ω

240 Ω unit calibration resolution — — — — 10 Ω

Keeper Circuit Resistance — — — 1304—kΩ

1OVDD— I/O power supply (1.425 V–1.575 V for DDR3)

2Vref— DDR3 external reference voltage

3The single-ended signals need to be within the respective limits (Vih(dc) max, Vil(dc) min) for single-ended signals as well as

the limitations for overshoot and undershoot.

4Use an off-chip pull resistor of less than 60 kΩ to override this keeper.

Table 14. LVIO DC Electrical Characteristics

DC Electrical Characteristics Symbol Test Conditions Min Typ Max Unit

High-Level DC input voltage1, 2 Vih Ioh = -0.8 mA 0.7 ×OVDD — OVDD V

Low-Level DC input voltage1, 2 Vil Iol = 0.8 mA 0 — 0.3 ×OVDD V

Input Hysteresis Vhys OVDD = 1.875 V

OVDD = 2.775 V

0.35 0.62

1.27

—V

Schmitt trigger VT+2, 3 VT+ — 0.5 ×OVDD — — V

Schmitt trigger VT-2, 3 VT- — — — 0.5 ×OVDD V

Input current (no pull-up/down) Iin Vin = OVDD or 0 V — — 1 μA

Input current (22 kΩ Pull-up) Iin Vin = 0 V

Vin = OVDD

— — 161

μA

Input current (47 kΩ Pull-up) Iin Vin = 0 V

Vin = OVDD

——76

μA

Input current (100 kΩ Pull-up) Iin Vin = 0 V

Vin = OVDD

——36

μA

Input current (100 kΩ Pull-down) Iin Vin = 0 V

Vin = OVDD

—— 1

μA

Keeper Circuit Resistance — — 1304—kΩ

Table 13. DDR3 I/O DC Electrical Parameters (continued)

Electrical Characteristics

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 31

4.3.4 Ultra-High Voltage I/O (UHVIO) DC Parameters

The parameters in Table 15 are guaranteed per the operating ranges in Table 6, unless otherwise noted.

1Overshoot and undershoot conditions (transitions above OVDD and below GND) on switching pads must be held below 0.6 V,

and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/undershoot must be

controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other

methods. Non-compliance to this specification may affect device reliability or cause permanent damage to the device.

2To maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current DC

level through to the target DC level, VIL or VIH. Monotonic input transition time is from 0.1 ns to 1 s. VIL and VIH do not apply

when hysteresis is enabled.

3Hysteresis of 350 mV is guaranteed over all operating conditions when hysteresis is enabled.

4Use an off-chip pull resistor of less than 60 kΩ to override this keeper.

Table 15. UHVIO DC Electrical Characteristics

DC Electrical Characteristics Symbol Test Conditions Min Typ Max Unit

High-level output voltage1

1Overshoot and undershoot conditions (transitions above OVDD and below GND) on switching pads must be held below 0.6 V,

and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/undershoot must

be controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other

methods. Non-compliance to this specification may affect device reliability or cause permanent damage to the device.

Voh Iout = -0.8 mA OVDD-0.15 — — V

Low-level output voltage1Vol Iout = 0.8 mA — — 0.15 V

High-Level DC input voltage1, 2

2 To maintain a valid level, the transitioning edge of the input must sustain a constant slew rate (monotonic) from the current

DC level to the target DC level, VIL or VIH. Monotonic input transition time is from 0.1 ns to 1 s. VIL and VIH do not apply

when hysteresis is enabled.

VIH — 0.7 ×OVDD — OVDD V

Low-Level DC input voltage1, 2VIL — 0 — 0.3 ×OVDD V

Input Hysteresis VHYS low voltage mode

high voltage mode

0.38

0.95

—0.43

1.33

Schmitt trigger VT+2, 3

3Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled.

VT+ — 0.5 ×OVDD — — V

Schmitt trigger VT-2, 3 VT- — — — 0.5 ×OVDD V

Input current (no pull-up/down) Iin Vin = OVDD or 0 V — — 1 μA

Input current (22 kΩ Pull-up) Iin Vin = 0

Vin = OVDD

— — 202

μA

Input current (75 kΩ Pull-up) Iin Vin = 0

Vin = OVDD

——61

μA

Input current (100 kΩ Pull-up) Iin Vin = 0

Vin = OVDD

——47

μA

Input current (360 kΩ Pull-down) Iin Vin = 0

Vin = OVDD

—— 1

5.7

μA

Keeper Circuit Resistance — — — 1304

4Use an off-chip pull resistor of less than 60 kΩ to override this keeper.

—kΩ

i.MX53 Applications Processors for Industrial Products, Rev. 7

32 Freescale Semiconductor

Electrical Characteristics

4.3.5 LVDS I/O DC Parameters

The LVDS interface complies with TIA/EIA 644-A standard. See TIA/EIA STANDARD 644-A,

“Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits” for details.

Table 16 shows the Low Voltage Differential Signaling (LVDS) DC electrical characteristics. The

parameters in Table 16 are guaranteed per the operating ranges in Table 6, unless otherwise noted.

4.4 Output Buffer Impedance Characteristics

This section defines the I/O Impedance parameters of the i.MX53 processor for the following I/O types:

• General Purpose I/O (GPIO)

• Double Data Rate 3 I/O (DDR3) for DDR2/LVDDR2, LPDDR2, and DDR3 modes

• Ultra High Voltage I/O (UHVIO)

• LVDS I/O

NOTE

Output driver impedance is measured with “long” transmission line of

impedance Ztl attached to I/O pad and incident wave launched into

transmission lime. Rpu/Rpd and Ztl form a voltage divider that defines

specific voltage of incident wave relative to OVDD. Output driver

impedance is calculated from this voltage divider (see Figure 4).

Table 16. LVDS DC Electrical Characteristics

DC Electrical Characteristics Symbol Test Conditions Min Typ Max Unit

Output Differential Voltage VOD Rload = 100Ω between

padP and padN

250 350 450 mV

Output High Voltage VOH 1.25 1.375 1.6 V

Output Low Voltage VOL 0.9 1.025 1.25

Offset Voltage VOS 1.125 1.2 1.375

Electrical Characteristics

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 33

Figure 4. Impedance Matching Load for Measurement

ipp_do

Cload = 1p

Ztl Ω, L = 20 inches

predriver

PMOS (Rpu)

NMOS (Rpd)

pad

OVDD

OVSS

t,(ns)

U,(V)

OVDD

t,(ns)

VDD

Vin (do)

Vout (pad)

U,(V)

Vref

Rpu = Vovdd - Vref1

Vref1

× Ztl

Rpd = × Ztl

Vref2

Vovdd - Vref2

Vref1 Vref2

i.MX53 Applications Processors for Industrial Products, Rev. 7

34 Freescale Semiconductor

Electrical Characteristics

4.4.1 GPIO Output Buffer Impedance

Table 17 shows the GPIO output buffer impedance.

4.4.2 DDR Output Driver Average Impedance

The DDR2/LVDDR2 interface fully complies with JESD79-2E DDR2 JEDEC standard release April,

2008. The DDR3 interface fully complies with JESD79-3D DDR3 JEDEC standard release April, 2008.

Table 17. GPIO Output Buffer Impedance

Parameter Symbol Test Conditions Min

Typ

Max Unit

OVDD 2.775 V OVDD 1.875 V

Output Driver

Impedance

Rpu Low Drive Strength, Ztl = 150 Ω

Medium Drive Strength, Ztl = 75 Ω

High Drive Strength, Ztl = 50 Ω

Max Drive Strength, Ztl = 37.5 Ω

104

150

250

125

Output Driver

Impedance

Rpd Low Drive Strength, Ztl = 150 Ω

Medium Drive Strength, Ztl = 75 Ω

High Drive Strength, Ztl = 50 Ω

Max Drive Strength, Ztl = 37.5 Ω

134

243

122

Electrical Characteristics

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 35

Table 18 shows DDR output driver average impedance of the i.MX53 processor.

Table 18. DDR Output Driver Average Impedance1

1Output driver impedance is controlled across PVTs (process, voltages, and temperatures) using calibration procedure and

pu_*cal, pd_*cal input pins.

Parameter Symbol Test Conditions

Drive strength (DSE)

Unit

000 001 010 011 100 101 110 111

Output

Driver

Impedance

Rdrv2

2Output driver impedance deviation (calibration accuracy) is ±5% (max/min impedance) across PVTs.

LPDDR1/DDR2 mode

NVCC_DRAM = 1.8 V

DDR_SEL = 00

Calibration resistance = 300 Ω3

3Calibration is done against external reference resistor. Value of the resistor should be varied depending on DDR mode and

DDR_SEL setting.

Hi-Z 300 150 100 75 60 50 43 Ω

DDR2 mode

NVCC_DRAM = 1.8 V

DDR_SEL = 01

Calibration resistance = 180 Ω3

Hi-Z 180 90 60 45 36 30 26

DDR2 mode

NVCC_DRAM = 1.8 V

DDR_SEL = 10

Calibration resistance = 200 Ω3

Hi-Z 200 100 66 50 40 33 28

DDR2 mode

NVCC_DRAM= 1.8 V

DDR_SEL = 11

Calibration resistance = 140 Ω3

Hi-Z 140 70 46 35 28 23 20

LPDDR2 mode

NVCC_DRAM= 1.2 V

DDR_SEL = 014

Calibration resistance = 160 Ω3

4If DDR_SEL = ‘01’ or DDR_SEL = ‘11’ are selected with NVCC_DRAM = 1.2 V for LPDDR2 operation, the external reference

resistor value must be 160 Ω for a correct ZQ calibration. In any case, reference resistors attached to the DDR memory

devices should be kept to 240 Ω per the JEDEC standard.

Hi-Z 160 80 53 40 32 27 23

LPDDR2 mode

NVCC_DRAM = 1.2 V

DDR_SEL = 10

Calibration resistance = 240 Ω3

Hi-Z 240 120 80 60 48 40 34

LPDDR2 mode

NVCC_DRAM = 1.2 V

DDR_SEL = 114

Calibration resistance = 160 Ω3

Hi-Z 160 80 53 40 32 27 23

DDR3 mode

NVCC_DRAM = 1.5 V

DDR_SEL = 00

Calibration resistance = 200 Ω3

Hi-Z 240 120 80 60 48 48 34

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Electrical Characteristics

4.4.3 UHVIO Output Buffer Impedance

Table 19 shows the UHVIO output buffer impedance.

4.4.4 LVDS I/O Output Buffer Impedance

The LVDS interface complies with TIA/EIA 644-A standard. See, TIA/EIA STANDARD 644-A,

“Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits” for details.

4.5 I/O AC Parameters

This section includes the AC parameters of the following I/O types:

• General Purpose I/O (GPIO)

• Double Data Rate 3 I/O (DDR3) for DDR2/LVDDR2, LPDDR2 and DDR3 modes

• Low Voltage I/O (LVIO)

• Ultra High Voltage I/O (UHVIO)

• LVDS I/O

The load circuit and output transition time waveforms are shown in Figure 5 and Figure 6.

Figure 5. Load Circuit for Output

Figure 6. Output Transition Time Waveform

Table 19. UHVIO Output Buffer Impedance

Parameter Symbol Test Conditions

Min Typ Max

Unit

OVDD

1.95 V

OVDD

3.0 V

OVDD

1.875 V

OVDD

3.3 V

OVDD

1.65 V

OVDD

3.6 V

Output Driver

Impedance

Rpu Low Drive Strength, Ztl = 150 Ω

Medium Drive Strength, Ztl = 75 Ω

High Drive Strength, Ztl = 50 Ω

114

124

135

198

206

103

Output Driver

Impedance

Rpd Low Drive Strength, Ztl = 150 Ω

Medium Drive Strength, Ztl = 75 Ω

High Drive Strength, Ztl = 50 Ω

118

126

154

179

217

109

Tes t P o in t

From Output

Under Test

CL includes package, probe and fixture capacitance

OVDD

20%

80% 80%

20%

tr tf

Output (at pad)

Electrical Characteristics

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 37

4.5.1 GPIO I/O AC Electrical Characteristics

AC electrical characteristics for GPIO I/O in slow and fast modes are presented in the Table 20 and

Table 21, respectively. Note that the fast or slow I/O behavior is determined by the appropriate control bit

in the IOMUXC control registers.

Table 20. GPIO I/O AC Parameters Slow Mode

Parameter Symbol Test Condition Min Typ Max Unit

Output Pad Transition Times (Max Drive) tr, tf 15 pF

35 pF

— — 1.91/1.52

3.07/2.65

Output Pad Transition Times (High Drive) tr, tf 15 pF

35 pF

— — 2.22/1.81

3.81/3.42

Output Pad Transition Times (Medium Drive) tr, tf 15 pF

35 pF

— — 2.88/2.42

5.43/5.02

Output Pad Transition Times (Low Drive) tr, tf 15 pF

35 pF

— — 4.94/4.50

10.55/9.70

Output Pad Slew Rate (Max Drive)1

1tps is measured between VIL to VIH for rising edge and between VIH to VIL for falling edge.

tps 15 pF

35 pF

0.5/0.65

0.32/0.37

—— V/ns

Output Pad Slew Rate (High Drive)1tps 15 pF

35 pF

0.43/0.54

0.26/0.41

——

Output Pad Slew Rate (Medium Drive)1tps 15 pF

35 pF

0.34/0.41

0.18/0.2

——

Output Pad Slew Rate (Low Drive)1tps 15 pF

35 pF

0.20/0.22

0.09/0.1

——

Output Pad di/dt (Max Drive) tdit — — — 30 mA/ns

Output Pad di/dt (High Drive) tdit — — — 23

Output Pad di/dt (Medium drive) tdit — — — 15

Output Pad di/dt (Low drive) tdit — — — 7

Input Transition Times2

2Hysteresis mode is recommended for inputs with transition times greater than 25 ns.

trm — — — 25 ns

Table 21. GPIO I/O AC Parameters Fast Mode

Parameter Symbol Test

Condition Min Typ Max Unit

Output Pad Transition Times (Max Drive) tr, tf 15 pF

35 pF

— — 1.45/1.24

2.76/2.54

Output Pad Transition Times (High Drive) tr, tf 15 pF

35 pF

— — 1.81/1.59

3.57/3.33

Output Pad Transition Times (Medium

Drive)

tr, tf 15 pF

35 pF

— — 2.54/2.29

5.25/5.01

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Electrical Characteristics

4.5.2 LPDDR2 I/O AC Electrical Characteristics

The DDR2/LVDDR2 interface mode fully complies with JESD79-2E DDR2 JEDEC standard release

April, 2008. The DDR3 interface mode fully complies with JESD79-3D DDR3 JEDEC standard release

April, 2008.

Table 22 shows the AC parameters for LPDDR2 I/O operating in DDR2 mode.

Output Pad Transition Times (Low Drive) tr, tf 15 pF

35 pF

— — 4.82/4.5

10.54/9.95

Output Pad Slew Rate (Max Drive)1tps 15 pF

35 pF

0.69/0.78

0.36/0.39

—— V/ns

Output Pad Slew Rate (High Drive)1tps 15 pF

35 pF

0.55/0.62

0.28/0.30

—— V/ns

Output Pad Slew Rate (Medium Drive)1tps 15 pF

35 pF

0.39/0.44

0.19/0.20

—— V/ns

Output Pad Slew Rate (Low Drive)1tps 15 pF

35 pF

0.21/0.22

0.09/0.1

—— V/ns

Output Pad di/dt (Max Drive) tdit — — — 70 mA/ns

Output Pad di/dt (High Drive) tdit — — — 53 mA/ns

Output Pad di/dt (Medium drive) tdit — — — 35 mA/ns

Output Pad di/dt (Low drive) tdit — — — 18 mA/ns

Input Transition Times2trm — — — 25 ns

1tps is measured between VIL to VIH for rising edge and between VIH to VIL for falling edge.

2Hysteresis mode is recommended for inputs with transition time greater than 25 ns.

Table 22. LPDDR2 I/O DDR2 mode AC Characteristics1

1Note that the JEDEC SSTL_18 specification (JESD8-15a) for class II operation supersedes any specification in this

document.

Parameter Symbol Test Condition Min Typ Max Unit

AC input logic high Vih(ac) — Vref+0.25 — — V

AC input logic low Vil(ac) — — — Vref-0.25 V

AC differential input voltage2Vid(ac) — 0.5 — OVDD V

Input AC differential cross point voltage3Vix(ac) — Vref - 0.175 — Vref + 0.175 V

Output AC differential cross point voltage4Vox(ac) — Vref - 0.125 — Vref + 0.125 V

Single output slew rate tsr At 25 W to Vref 0.4 — 2 V/ns

Skew between pad rise/fall asymmetry +

skew caused by SSN

tSKD clk = 266 MHz

clk = 400 MHz

——0.2

0.1

Table 21. GPIO I/O AC Parameters Fast Mode (continued)

Parameter Symbol Test

Condition Min Typ Max Unit

Electrical Characteristics

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 39

Table 23 shows the AC parameters for LPDDR2 I/O operating in LPDDR2 mode.

Table 24 shows the AC parameters for LPDDR2 I/O operating in DDR3 mode.

2Vid(ac) specifies the input differential voltage | Vtr - Vcp | required for switching, where Vtr is the “true” input signal and Vcp

is the “complementary” input signal. The Minimum value is equal to Vih(ac) - Vil(ac).

3The typical value of Vix(ac) is expected to be about 0.5 x OVDD. and Vix(ac) is expected to track variation of OVDD. Vix(ac)

indicates the voltage at which differential input signal must cross.

4The typical value of Vox(ac) is expected to be about 0.5 x OVDD and Vox(ac) is expected to track variation in OVDD. Vox(ac)

indicates the voltage at which differential output signal must cross.

Table 23. LPDDR2 I/O LPDDR2 mode AC Characteristics1

1Note that the JEDEC LPDDR2 specification (JESD209_2B) supersedes any specification in this document.

Parameter Symbol Test Condition Min Typ Max Unit

AC input logic high Vih(ac) — Vref + 0.22 — OVDD V

AC input logic low Vil(ac) — 0 — Vref - 0.22 V

AC differential input high voltage2

2Vid(ac) specifies the input differential voltage | Vtr - Vcp | required for switching, where Vtr is the “true” input signal and Vcp

is the “complementary” input signal. The Minimum value is equal to Vih(ac) - Vil(ac).

Vidh(ac) — 0.44 — — V

AC differential input low voltage Vidl(ac) — — — 0.44 V

Input AC differential cross point voltage3

3The typical value of Vix(ac) is expected to be about 0.5 x OVDD. and Vix(ac) is expected to track variation of OVDD. Vix(ac)

indicates the voltage at which differential input signal must cross.

Vix(ac) Relative to OVDD/2 -0.12 — 0.12 V

Over/undershoot peak Vpeak — — — 0.35 V

Over/undershoot area (above OVDD

or below OVSS)

Varea 266 MHz — — 0.6 V-ns

Single output slew rate tsr 50 Ω to Vref. 5pF load.

Drive impedance= 40

Ω ± 30%

1.5 — 3.5 V/ns

50 Ω to Vref. 5 pF

load. Drive

impedance= 60 Ω ±

30%

1—2.5

Skew between pad rise/fall asymmetry +

skew caused by SSN

tSKD clk = 266 MHz

clk = 400 MHz

——0.2

0.1

Table 24. LPDDR2 I/O DDR3 mode AC Characteristics1

Parameter Symbol Test Condition Min Typ Max Unit

AC input logic high Vih(ac) — Vref + 0.175 — OVDD V

AC input logic low Vil(ac) — 0 — Vref - 0.175 V

AC differential input voltage2Vid(ac) — 0.35 — — V

Input AC differential cross point voltage3Vix(ac) — Vref - 0.15 — Vref + 0.15 V

Output AC differential cross point voltage4Vox(ac) — Vref - 0.15 — Vref + 0.15 V

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Electrical Characteristics

4.5.3 LVIO I/O AC Electrical Characteristics

AC electrical characteristics for LVIO I/O in slow and fast modes are presented in the Table 25 and

Table 26, respectively. Note that the fast or slow I/O behavior is determined by the appropriate control bit

in the IOMUXC control registers.

Single output slew rate tsr At 25 Ω to Vref 2.5 — 5 V/ns

Skew between pad rise/fall asymmetry +

skew caused by SSN

tSKD clk = 266 MHz

clk = 400 MHz

——0.2

0.1

1Note that the JEDEC JESD79_3C specification supersedes any specification in this document.

2Vid(ac) specifies the input differential voltage |Vtr-Vcp| required for switching, where Vtr is the “true” input signal and Vcp is

the “complementary” input signal. The Minimum value is equal to Vih(ac) - Vil(ac).

3The typical value of Vix(ac) is expected to be about 0.5 x OVDD. and Vix(ac) is expected to track variation of OVDD. Vix(ac)

indicates the voltage at which differential input signal must cross.

4The typical value of Vox(ac) is expected to be about 0.5 x OVDD and Vox(ac) is expected to track variation in OVDD. Vox(ac)

indicates the voltage at which differential output signal must cross.

Table 25. LVIO I/O AC Parameters in Slow Mode

Parameter Symbol Test Condition Min Typ Max Unit

Input Transition Times1

1Hysteresis mode is recommended for inputs with transition times greater than 25 ns.

trm — — — 25 ns

Table 24. LPDDR2 I/O DDR3 mode AC Characteristics1 (continued)

Parameter Symbol Test Condition Min Typ Max Unit

Electrical Characteristics

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 41

4.5.4 UHVIO I/O AC Electrical Characteristics

Table 27 shows the AC parameters for UHVIO I/O operating in low output voltage mode. Table 28

shows the AC parameters for UHVIO I/O operating in high output voltage mode.

Table 26. LVIO I/O AC Parameters in Fast Mode

Parameter Symbol Test

Condition Min Typ Max Unit

Input Transition Times1

1Hysteresis mode is recommended for inputs with transition time greater than 25 ns.

trm — — — 25 ns

Table 27. AC Electrical Characteristics of UHVIO Pad (Low Output Voltage Mode)

Parameter Symbol Test Condition Min Typ Max Unit

Output Pad Transition Times (High Drive) tr, tf 15 pF

35 pF

— — 1.59/1.69

3.05/3.30

Output Pad Transition Times (Medium Drive) tr, tf 15 pF

35 pF

— — 2.16/2.35

4.45/4.84

Output Pad Transition Times (Low Drive) tr, tf 15 pF

35 pF

— — 4.06/4.42

8.79/9.55

Output Pad Slew Rate (High Drive)1

1tps is measured between VIL to VIH for rising edge and between VIH to VIL for falling edge.

tps 15 pF

35 pF

0.63/0.59

0.33/0.30

—— V/ns

Output Pad Slew Rate (Medium Drive)1tps 15 pF

35 pF

0.46/0.42

0.22/0.21

——

Output Pad Slew Rate (Low Drive)1tps 15 pF

35 pF

0.25/0.23

0.11/0.11

——

Output Pad di/dt (High Drive) tdit — — — 43.6 mA/ns

Output Pad di/dt (Medium drive) tdit — — — 32.3

Output Pad di/dt (Low drive) tdit — — — 18.24

Input Transition Times2

2Hysteresis mode is recommended for inputs with transition times greater than 25 ns.

trm — — — 25 ns

Table 28. AC Electrical Characteristics of UHVIO Pad (High Output Voltage Mode)

Parameter Symbol Test Condition Min Typ Max Unit

Output Pad Transition Times (High Drive) tr, tf 15 pF

35 pF

— — 1.72/1.92

3.46/3.70

Output Pad Transition Times (Medium Drive) tr, tf 15 pF

35 pF

— — 2.38/2.56

5.07/5.25

Output Pad Transition Times (Low Drive) tr, tf 15 pF

35 pF

— — 4.55/4.58

10.04/9.94

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Electrical Characteristics

4.5.5 LVDS I/O AC Electrical Characteristics

The differential output transition time waveform is shown in Figure 7.

Figure 7. Differential LVDS Driver Transition Time Waveform

Table 29 shows the AC parameters for LVDS I/O.

Output Pad Slew Rate (High Drive)1tps 15 pF

35 pF

1.05/0.94

0.52/0.49

—— V/ns

Output Pad Slew Rate (Medium Drive)1tps 15 pF

35 pF

0.76/0.71

0.36/0.34

——

Output Pad Slew Rate (Low Drive)1tps 15 pF

35 pF

0.40/0.93

0.18/0.18

——

Output Pad di/dt (High Drive) tdit — — — 82.8 mA/ns

Output Pad di/dt (Medium drive) tdit — — — 65.6

Output Pad di/dt (Low drive) tdit — — — 43.1

Input Transition Times2trm — — — 25 ns

1tps is measured between VIL to VIH for rising edge and between VIH to VIL for falling edge.

2Hysteresis mode is recommended for inputs with transition times greater than 25 ns.

Table 29. AC Electrical Characteristics of LVDS Pad

Parameter Symbol Test Condition Min Typ Max Unit

Transition Low to High Time1

1Measurement levels are 20–80% from output voltage.

tTLH Rload = 100 Ω,

Cload = 2 pF

0.26 — 0.5 ns

Transition High to Low Time1tTHL 0.26 — 0.5

Operating Frequency f — — 300 — MHz

Offset voltage imbalance Vos — — — 150 mV

Table 28. AC Electrical Characteristics of UHVIO Pad (High Output Voltage Mode) (continued)

Parameter Symbol Test Condition Min Typ Max Unit

Electrical Characteristics

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 43

4.6 System Modules Timing

This section contains the timing and electrical parameters for the modules in the i.MX53 processor.

4.6.1 Reset Timings Parameters

Figure 8 shows the reset timing and Table 30 lists the timing parameters.

Figure 8. Reset Timing Diagram

4.6.2 WDOG Reset Timing Parameters

Figure 9 shows the WDOG reset timing and Table 31 lists the timing parameters.

Figure 9. WATCHDOG_RST Timing Diagram

NOTE

CKIL is approximately 32 kHz. TCKIL is one period or approximately 30 μs.

4.6.3 Clock Amplifier Parameters (CKIH1, CKIH2)

The input to Clock Amplifier (CAMP) is internally ac-coupled allowing direct interface to a square wave

or sinusoidal frequency source. No external series capacitors are required.

Table 30. Reset Timing Parameters

ID Parameter Min Max Unit

CC1 Duration of RESET_IN to be qualified as valid (input slope = 5 ns) 50 — ns

Table 31. WATCHDOG_RST Timing Parameters

ID Parameter Min Max Unit

CC5 Duration of WATCHDOG_RESET Assertion 1 — TCKIL

RESET_IN

CC1

(Input)

WATCHDOG_RST

CC5

(Input)

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Electrical Characteristics

Table 32 shows the electrical parameters of CAMP.

4.6.4 DPLL Electrical Parameters

Table 33 shows the electrical parameters of digital phase-locked loop (DPLL).

Table 32. CAMP Electrical Parameters (CKIH1, CKIH2)

Parameter Min Typ Max Unit

Input frequency 8.0 — 40.0 MHz

VIL (for square wave input) 0 — 0.3 V

VIH (for square wave input)1

1NVCC_CKIH is the supply voltage of CAMP.

NVCC_CKIH - 0.25 — NVCC_CKIH V

Sinusoidal input amplitude 0.4 — VDD Vp-p

Output duty cycle 45 50 55 %

Table 33. DPLL Electrical Parameters

Parameter Test Conditions/Remarks Min Typ Max Unit

Reference clock frequency range1

1Device input range cannot exceed the electrical specifications of the CAMP, see Table 32.

—10—100MHz

Reference clock frequency range after

pre-divider

—10—40MHz

Output clock frequency range (dpdck_2) — 300 — 1025 MHz

Pre-division factor2

2The values specified here are internal to DPLL. Inside the DPLL, a “1” is added to the value specified by the user. Therefore,

the user has to enter a value “1” less than the desired value at the inputs of DPLL for PDF and MFD.

—1—16—

Multiplication factor integer part — 5 — 15 —

Multiplication factor numerator3

3The maximum total multiplication factor (MFI + MFN/MFD) allowed is 15. Therefore, if the MFI value is 15, MFN value must

be zero.

Should be less than denominator -67108862 — 67108862 —

Multiplication factor denominator2— 1 — 67108863 —

Output Duty Cycle — 48.5 50 51.5 %

Frequency lock time4

(FOL mode or non-integer MF)

———398 Tdpdref

Phase lock time — — — 100 µs

Frequency jitter5 (peak value) — — 0.02 0.04 Tdck

Phase jitter (peak value) FPL mode, integer and fractional MF — 2.0 3.5 ns

Power dissipation fdck = 300 MHz at avdd = 1.8 V,

dvdd = 1.2 V

fdck = 650 MHz at avdd = 1.8 V,

dvdd = 1.2 V

— — 0.65 (avdd)

0.92 (dvdd)

1.98 (avdd)

1.8 (dvdd)

Electrical Characteristics

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 45

4.6.5 NAND Flash Controller (NFC) Parameters

This section provides the relative timing requirements among various signals of NFC at the module level,

in each operational mode.

Timing parameters in Figure 10, Figure 11, Figure 12, Figure 13, Figure 15, and Table 35 show the default

NFC mode (asymmetric mode) using two Flash clock cycles per one access of RE_B and WE_B.

Timing parameters in Figure 10, Figure 11, Figure 12, Figure 14, Figure 15, and Table 35 show symmetric

NFC mode using one Flash clock cycle per one access of RE_B and WE_B.

With reference to the timing diagrams, a high is defined as 80% of signal value and low is defined as 20%

of signal value. All parameters are given in nanoseconds. The BGA contact load used in calculations is

20 pF (except for NF16— 40 pF) and there is maximum drive strength on all contacts.

All timing parameters are a function of T, which is the period of the flash_clk clock (“enfc_clk” at system

level). This clock frequency can be controlled by the user, configuring CCM (SoC clock controller). The

clock is derived from emi_slow_clk after single divider.

Figure 34 demonstrates several examples of clock frequency settings.

NOTE

A potential limitation for minimum clock frequency may exist for some

devices. When the clock frequency is too low, the data bus capturing might

occur after the specified trhoh (RE_B high to output hold) period. Setting the

clock frequency above 25.6 MHz (that is, T = 39 ns) guaranties a proper

operation for devices having trhoh > 15 ns. It is also recommended that the

NFC_FREQ_SEL Fuse be set accordingly to initiate the boot with

33.33 MHz clock.

4Tdpdref is the time period of the reference clock after predivider. According to the specification, the maximum lock time in FOL

mode is 398 cycles of divided reference clock when DPLL starts after full reset.

5Tdck is the time period of the output clock, dpdck_2.

Table 34. NFC Clock Settings Examples

emi_slow_clk (MHz) nfc_podf (Division Factor) enfc_clk (MHz) T-Clock Period (ns)

100 (Boot mode) 71

1Boot value NFC_FREQ_SEL Fuse High (burned)

14.29 70

2Boot value NFC_FREQ_SEL Fuse Low

33.33 30

133 4 33.33 30

3 44.333

3For RBB_MODE=1, using NANDF_RB0 signal for ready/busy indication. This mode require setting the delay line. See the

Reference Manual for details.

22.5

266

315

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Electrical Characteristics

Lower frequency operation can be supported for most available devices in

the market, relying on data lines Bus-Keeper logic. This depends on device

behavior on the data bus in the time interval between data output valid to

data output high-Z state. In NAND device parameters this period is marked

between trhoh and trhz (RE_B high to output high-Z). In most devices, the

data transition from valid value to high-Z occurs without going through

other states. Setting the data bus pads to Bus-Keeper mode in the IOMUXC

registers, keeps the data bus valid internally after the specified hold time,

allowing proper capturing with slower clock.

Figure 10. Command Latch Cycle Timing

Figure 11. Address Latch Cycle Timing

NFCLE

NFCE_B

NFWE_B

NFIO[7:0] command

NF9

NF8

NF1 NF2

NF5

NF3 NF4

NFCE_B

NFWE_B

NFALE

NFIO[7:0] Address

NF9

NF8

NF5

NF3 NF4

NF6

NF11

NF10

NF7

Electrical Characteristics

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 47

Figure 12. Write Data Latch Timing

Figure 13. Read Data Latch Timing, Asymmetric Mode

Figure 14. Read Data Latch Timing, Symmetric Mode

NFCE_B

NFWE_B

NFIO[15:0] Data to NF

NF9

NF8

NF5

NF3

NF11

NF10

NFCE_B

NFRE_B

NFRB_B

NFIO[15:0] Data from NF

NF13

NF15

NF14

NF17

NF12

NF16

NFCE_B

NFRE_B

NFRB_B

NFIO[15:0] Data from NF

NF13

NF15

NF14

NF12

NF16 NF18

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Electrical Characteristics

Figure 15. Other Timing Parameters

NFCLE

NFCE_B

NFRE_B

NFRB_B

NFWE_B

NF20

NF19

NF21

NF22

Electrical Characteristics

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 49

Table 35. NFC—Timing Characteristics

ID Parameter Symbol Asymmetric Mode Min Symmetric Mode

Min Max

NF1 NFCLE setup Time tCLS 2T + 0.1 2T + 0.1 —

NF2 NFCLE Hold Time tCLH T - 4.45 T - 4.45 —

NF31

1In case of NUM_OF_DEVICES is greater than 0 (for example, interleaved mode), then only during the data phase of

symmetric mode the setup time will equal 1.5T + 0.95.

NFCE_B Setup Time tCS 3T + 0.95 3T+0.95 —

NF4 NFCE_B Hold Time tCH 2T-5.55 1.5T-5.55 —

NF5 NFWE_B Pulse Width tWP T-1.4 0.5T-1.4 —

NF6 NFALE Setup Time tALS 2T + 0.1 2T + 0.1 —

NF7 NFALE Hold Time tALH T - 4.45 T - 4.45 —

NF8 Data Setup Time tDS T-0.9 0.5T-0.9 —

NF9 Data Hold Time tDH T - 5.55 0.5T - 5.55 —

NF10 Write Cycle Time tWC 2T T-0.5 —

NF11 NFWE_B Hold Time tWH T - 1.15 0.5T - 1.15 —

NF12 Ready to NFRE_B Low tRR 9T + 8.9 9T + 8.9 —

NF13 NFRE_B Pulse Width tRP 1.5T 0.5T-1 —

NF14 READ Cycle Time tRC 2T T —

NF15 NFRE_B High Hold Time tREH 0.5T - 1.15 0.5T - 1.15 —

NF162

2tDSR is calculated by the following formula:

Asymmetric mode: tDSR = tREpd + tDpd + 1/2T - Tdl3

Symmetric mode: tDSR = tREpd + tDpd - Tdl3

tREpd + tDpd = 11.2 ns (including clock skew)

where tREpd is RE propogation delay in the chip including I/O pad delay, and tDpd is Data propogation delay from I/O pad to

EXTMC including I/O pad delay.

tDSR can be used to determine tREA max parameter with the following formula: tREA = 1.5T - tDSR.

Data Setup on READ tDSR 11.2 + 0.5T - Tdl3

3Tdl is composed of 4 delay-line units each generates an equal delay with min 1.25 ns and max 1 aclk period (Taclk). Default

is 1/4 aclk period for each delay-line unit, so all 4 delay lines together generates a total of 1 aclk period. Taclk is

“emi_slow_clk” of the system, which default value is 7.5 ns (133 MHz).

11.2 - Tdl3—

NF174Data Hold on READ tDHR 0—2Taclk +T

NF185Data Hold on READ tDHR —Tdl

3-11.2 2Taclk +T

NF19 CLE to RE delay tCLR 9T 9T —

NF20 CE to RE delay tCRE T - 3.45 T - 3.45 T + 0.3

NF21 WE high to RE low tWHR 10.5T 10.5T —

NF22 WE high to busy tWB ——6T

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Electrical Characteristics

4.6.6 External Interface Module (EIM)

The following subsections provide information on the EIM.

4.6.6.1 EIM Signal Cross Reference

Table 36 is a guide intended to help the user identify signals in the External Interface Module Chapter of

the Reference Manual which are identical to those mentioned in this data sheet.

4.6.6.2 EIM Interface Pads Allocation

EIM supports16-bit and 8-bit devices operating in address/data separate or multiplexed modes. In some

of the modes the EIM and the NAND FLASH have shared data bus. Table 37 provides EIM interface

pads allocation in different modes.

4NF17 is defined only in asymmetric operation mode.

NF17 max value is equivalent to max tRHZ value that can be used with NFC.

Taclk is “emi_slow_clk” of the system.

5NF18 is defined only in Symmetric operation mode.

tDHR (MIN) is calculated by the following formula: Tdl3 - (tREpd + tDpd)

where tREpd is RE propogation delay in the chip including I/O pad delay, and tDpd is Data propogation delay from I/O pad to

EXTMC including I/O pad delay.

NF18 max value is equivalent to max tRHZ value that can be used with NFC.

Taclk is “emi_slow_clk” of the system.

Table 36. EIM Signal Cross Reference

Reference Manual

EIM Chapter Nomenclature

Data Sheet Nomenclature,

Reference Manual External Signals and Pin Multiplexing Chapter,

and IOMUXC Controller Chapter Nomenclature

BCLK EIM_BCLK

CSx EIM_CSx

WE_B EIM_RW

OE_B EIM_OE

BEy_B EIM_EBx

ADV EIM_LBA

ADDR EIM_A[25:16], EIM_DA[15:0]

ADDR/M_DATA EIM_DAx (Addr/Data muxed mode)

DATA EIM_NFC_D (Data bus shared with NAND Flash)

EIM_Dx (dedicated data bus)

WAIT_B EIM_WAIT

Electrical Characteristics

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 51

Table 37. EIM Internal Module Multiplexing

Setup

Non Multiplexed Address/Data Mode Multiplexed

Address/Data mode

8 Bit 16 Bit 32 Bit 16 Bit 32 Bit

MUM = 0,

DSZ = 100

MUM = 0,

DSZ = 101

MUM = 0,

DSZ = 111

MUM = 0,

DSZ = 001

MUM = 0,

DSZ = 010

MUM = 0,

DSZ = 011

MUM = 1,

DSZ = 001

MUM = 1,

DSZ = 011

A[15:0] EIM_DA

[15:0]

EIM_DA

[15:0]

EIM_DA

[15:0]

EIM_DA

[15:0]

EIM_DA

[15:0]

EIM_DA

[15:0]

EIM_DA

[15:0]

EIM_DA

[15:0]

A[25:16] EIM_A

[25:16]

EIM_A

[25:16]

EIM_A

[25:16]

EIM_A

[25:16]

EIM_A

[25:16]

EIM_A

[24:16]1

1For 32-bit mode, the address range is A[24:0], due to address space allocation in memory map.

EIM_A

[25:16]

NANDF_D

[8:0]1

D[7:0],

EIM_EB0

NANDF_D

[7:0]2

— — NANDF_D

[7:0]2

2NANDF_D[7:0] multiplexed on ALT3 mode of PATA_DATA[7:0]

—NANDF_D

[7:0]

EIM_DA

[7:0]

EIM_DA

[7:0]

D[15:8],

EIM_EB1

—NANDF_D

[15:8]3

—NANDF_D

[15:8]3

3NANDF_D[15:8] multiplexed on ALT3 mode of PATA_DATA[15:8]

—NANDF_D

[15:8]

EIM_DA

[15:8]

EIM_DA

[15:8]

D[23:16],

EIM_EB2

————EIM_D

[23:16]

EIM_D

[23:16]

—NANDF_D

[7:0]

D[31:24],

EIM_EB3

——EIM_D

[31:24]

—EIM_D

[31:24]

EIM_D

[31:24]

—NANDF_D

[15:8]

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52 Freescale Semiconductor

Electrical Characteristics

4.6.6.3 General EIM Timing-Synchronous Mode

Figure 16, Figure 17, and Table 38 specify the timings related to the EIM module. All EIM output control

signals may be asserted and deasserted by an internal clock synchronized to the BCLK rising edge

according to corresponding assertion/negation control fields.

Figure 16. EIM Outputs Timing Diagram

Figure 17. EIM Inputs Timing Diagram

Table 38. EIM Bus Timing Parameters 1

ID Parameter

BCD = 0 BCD = 1 BCD = 2 BCD = 3

Min Max Min Max Min Max Min Max

WE1 BCLK Cycle time2t 2 x t 3 x t 4 x t

WE2 BCLK Low Level

Width

0.4 x t 0.8 x t 1.2 x t 1.6 x t

WE4

Address

CSx_B

WE_B

OE_B

BCLK

BEy_B

ADV_B

Output Data

...

WE5

WE6 WE7

WE8 WE9

WE10 WE11

WE12 WE13

WE14 WE15

WE16 WE17

WE3

WE2

WE1

Input Data

WAIT_B

BCLK

WE19

WE18

WE21

WE20

Electrical Characteristics

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 53

WE3 BCLK High Level

Width

0.4 x t 0.8 x t 1.2 x t 1.6 x t

WE4 Clock rise to address

valid3

-0.5 x t -

1.25

-0.5 x t +

1.75

-t - 1.25 -t + 1.75 -1.5 x t -

1.25

-1.5 x t

+1.75

-2 x t -

1.25

-2 x t +

1.75

WE5 Clock rise to address

invalid

0.5 x t -

1.25

0.5 x t + 1.75 t - 1.25 t + 1.75 1.5 x t -

1.25

1.5 x t +

1.75

2 x t -

1.25

2 x t + 1.75

WE6 Clock rise to CSx_B

valid

-0.5 x t -

1.25

-0.5 x t +

1.75

-t - 1.25 -t + 1.75 -1.5 x t -

1.25

-1.5 x t +

1.75

-2 x t -

1.25

-2 x t +

1.75

WE7 Clock rise to CSx_B

invalid

0.5 x t -

1.25

0.5 x t + 1.75 t - 1.25 t + 1.75 1.5 x t -

1.25

1.5 x t +

1.75

2 x t -

1.25

2 x t + 1.75

WE8 Clock rise to WE_B

Valid

-0.5 x t -

1.25

-0.5 x t +

1.75

-t - 1.25 -t + 1.75 -1.5 x t -

1.25

-1.5 x t +

1.75

-2 x t -

1.25

-2 x t +

1.75

WE9 Clock rise to WE_B

Invalid

0.5 x t -

1.25

0.5 x t + 1.75 t - 1.25 t + 1.75 1.5 x t -

1.25

1.5 x t +

1.75

2 x t -

1.25

2 x t + 1.75

WE10 Clock rise to OE_B

Valid

-0.5 x t -

1.25

-0.5 x t +

1.75

-t - 1.25 -t + 1.75 -1.5 x t -

1.25

-1.5 x t +

1.75

-2 x t -

1.25

-2 x t +

1.75

WE11 Clock rise to OE_B

Invalid

0.5 x t -

1.25

0.5 x t + 1.75 t - 1.25 t + 1.75 1.5 x t -

1.25

1.5 x t +

1.75

2 x t -

1.25

2 x t + 1.75

WE12 Clock rise to BEy_B

Valid

-0.5 x t -

1.25

-0.5 x t +

1.75

-t - 1.25 -t + 1.75 -1.5 x t -

1.25

-1.5 x t +

1.75

-2 x t -

1.25

-2 x t +

1.75

WE13 Clock rise to BEy_B

Invalid

0.5 x t -

1.25

0.5 x t + 1.75 t - 1.25 t + 1.75 1.5 x t -

1.25

1.5 x t +

1.75

2 x t -

1.25

2 x t + 1.75

WE14 Clock rise to ADV_B

Valid

-0.5 x t -

1.25

-0.5 x t +

1.75

-t - 1.25 -t + 1.75 -1.5 x t -

1.25

-1.5 x t +

1.75

-2 x t -

1.25

-2 x t +

1.75

WE15 Clock rise to ADV_B

Invalid

0.5 x t -

1.25

0.5 x t + 1.75 t - 1.25 t + 1.75 1.5 x t -

1.25

1.5 x t +

1.75

2 x t -

1.25

2 x t + 1.75

WE16 Clock rise to Output

Data Valid

-0.5 x t -

1.25

-0.5 x t +

1.75

-t - 1.25 -t + 1.75 -1.5 x t -

1.25

-1.5 x t +

1.75

-2 x t -

1.25

-2 x t +

1.75

WE17 Clock rise to Output

Data Invalid

0.5 x t -

1.25

0.5 x t + 1.75 t - 1.25 t + 1.75 1.5 x t -

1.25

1.5 x t +

1.75

2 x t -

1.25

2 x t + 1.75

WE18 Input Data setup time

to Clock rise

2 ns — 4 ns — — — — —

WE19 Input Data hold time

from Clock rise

2 ns — 2 ns — — — — —

WE20 WAIT_B setup time to

Clock rise

2 ns — 4 ns — — — — —

WE21 WAIT_B hold time

from Clock rise

2 ns — 2 ns — — — — —

Table 38. EIM Bus Timing Parameters (continued)1

ID Parameter

BCD = 0 BCD = 1 BCD = 2 BCD = 3

Min Max Min Max Min Max Min Max

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54 Freescale Semiconductor

Electrical Characteristics

4.6.6.4 Examples of EIM Synchronous Accesses

Figure 18 to Figure 21 provide few examples of basic EIM accesses to external memory devices with the

timing parameters mentioned previously for specific control parameters settings.

Figure 18. Synchronous Memory Read Access, WSC=1

1t is the maximal EIM logic (axi_clk) cycle time. The maximum allowed axi_clk frequency is 133 MHz, whereas the maximum

allowed BCLK frequency is 104 MHz. As a result, if BCD = 0, axi_clk must be ≤104 MHz. If BCD = 1, then 133 MHz is allowed

for axi_clk, resulting in a BCLK of 66.5 MHz. When the clock branch to EIM is decreased to 104 MHz, other busses are

impacted which are clocked from this source. See the CCM chapter of the i.MX53 Reference Manual for a detailed clock tree

description.

2BCLK parameters are being measured from the 50% point, that is, high is defined as 50% of signal value and low is defined

as 50% as signal value.

3For signal measurements “High” is defined as 80% of signal value and “Low” is defined as 20% of signal value.

Last Valid Address Address v1

D(v1)

BCLK

ADDR

DATA

WE_B

ADV_B

OE_B

BEy_B

CSx_B

WE4 WE5

WE6 WE7

WE10 WE11

WE13

WE12

WE14

WE15

WE18

WE19

Electrical Characteristics

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 55

Figure 19. Synchronous Memory, Write Access, WSC=1, WBEA=0, and WADVN=0

Figure 20. Muxed Address/Data (A/D) Mode, Synchronous Write Access, WSC=6, ADVA=0, ADVN=1, and

ADH=1

NOTE

In 32-bit muxed address/data (A/D) mode the 16 MSBs are driven on the

data bus.

Last Valid Address Address V1

D(V1)

BCLK

ADDR

DATA

WE_B

ADV_B

OE_B

BEy_B

CSx_B

WE4 WE5

WE6 WE7

WE8 WE9

WE12

WE13

WE14

WE15

WE16 WE17

Last

BCLK

ADDR/

WE_B

ADV_B

OE_B

BEy_B

CSx_B

Address V1 Write Data

Valid Addr

M_DATA

WE4

WE16

WE6

WE7

WE9

WE8

WE10

WE11

WE14 WE15

WE17

WE5

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56 Freescale Semiconductor

Electrical Characteristics

Figure 21. 16-Bit Muxed A/D Mode, Synchronous Read Access, WSC=7, RADVN=1, ADH=1, and OEA=0

4.6.6.5 General EIM Timing-Asynchronous Mode

Figure 22 through Figure 27, and Table 39 help to determine timing parameters relative to the chip select

(CS) state for asynchronous and DTACK EIM accesses with corresponding EIM bit fields and the timing

parameters mentioned above.

Asynchronous read and write access length in cycles may vary from what is shown in Figure 22 through

Figure 25 as RWSC, OEN, and CSN is configured differently. See i.MX53 reference manual for the EIM

programming model.

Last

BCLK

ADDR/

WE_B

ADV_B

OE_B

BEy_B

CSx_B

Address V1 Data

Valid Addr

M_DATA

WE5

WE6

WE7

WE14 WE15

WE10

WE11

WE12 WE13

WE18

WE19

WE4

Electrical Characteristics

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 57

Figure 22. Asynchronous Memory Read Access (RWSC = 5)

Figure 23. Asynchronous A/D Muxed Read Access (RWSC = 5)

Last Valid Address Address V1

D(V1)

ADDR/

DATA[7:0]

WE_B

ADV_B

OE_B

BEy_B

CSx_B

Next Address

WE39

WE35

WE37

WE32

WE36

WE38

WE43

WE40

WE31

WE44

INT_CLK

start of

access

end of

access

MAXDI

MAXCSO

MAXCO

M_DATA

Addr. V1 D(V1)

ADDR/

WE_B

ADV_B

OE_B

BEy_B

CSx_B

WE39

WE35A

WE37

WE36

WE38

WE40A

WE31

WE44

INT_CLK

start of

access

end of

access

MAXDI

MAXCSO

MAXCO

WE32A

M_DATA

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58 Freescale Semiconductor

Electrical Characteristics

Figure 24. Asynchronous Memory Write Access

Figure 25. Asynchronous A/D Muxed Write Access

Last Valid Address Address V1

D(V1)

ADDR

DATA

WE_B

ADV_B

OE_B

BEy_B

CSx_B

Next Address

WE31

WE39

WE33

WE45

WE32

WE40

WE34

WE46

WE42

WE41

WE_B

OE_B

BEy_B

CSx_B

WE33

WE45

WE34

WE46

WE42

Addr. V1 D(V1)

ADDR/

WE31

WE42

WE41A

WE32A

M_DATA

ADV_B

WE39

WE40A

Electrical Characteristics

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 59

Figure 26. DTACK Read Access (DAP=0)

Figure 27. DTACK Write Access (DAP=0)

Last Valid Address Address V1

D(V1)

ADDR

DATA[7:0]

WE_B

ADV_B

OE_B

BEy_B

CSx_B

Next Address

WE39

WE35

WE37

WE32

WE36

WE38

WE43

WE40

WE31

WE44

DTACK

WE47

WE48

Last Valid Address Address V1

D(V1)

ADDR

DATA

WE_B

ADV_B

OE_B

BEy_B

CSx_B

Next Address

WE31

WE39

WE33

WE45

WE32

WE40

WE34

WE46

WE42

WE41

DTACK

WE47

WE48

i.MX53 Applications Processors for Industrial Products, Rev. 7

60 Freescale Semiconductor

Electrical Characteristics

Table 39. EIM Asynchronous Timing Parameters Table Relative Chip Select

Ref No. Parameter

Determination by

Synchronous measured

parameters 12

Min

Max

(If 133 MHz is

supported by SOC)

Unit

WE31 CSx_B valid to Address Valid WE4 - WE6 - CSA3— 3 - CSA ns

WE32 Address Invalid to CSx_B

invalid

WE7 - WE5 - CSN4 —3 - CSNns

WE32A(

muxed

A/D

CSx_B valid to Address Invalid t5 + WE4 - WE7 + (ADVN +

ADVA + 1 - CSA3)

-3 + (ADVN +

ADVA + 1 - CSA)

—ns

WE33 CSx_B Valid to WE_B Valid WE8 - WE6 + (WEA - CSA) — 3 + (WEA - CSA) ns

WE34 WE_B Invalid to CSx_B Invalid WE7 - WE9 + (WEN - CSN) — 3 - (WEN_CSN) ns

WE35 CSx_B Valid to OE_B Valid WE10 - WE6 + (OEA - CSA) — 3 + (OEA - CSA) ns

WE35A

(muxed

A/D)

CSx_B Valid to OE_B Valid WE10 - WE6 + (OEA + RADVN

+ RADVA + ADH + 1 - CSA)

-3 + (OEA +

RADVN+RADVA

+ADH+1-CSA)

3 + (OEA +

RADVN+RADVA+AD

H+1-CSA)

WE36 OE_B Invalid to CSx_B Invalid WE7 - WE11 + (OEN - CSN) — 3 - (OEN - CSN) ns

WE37 CSx_B Valid to BEy_B Valid

(Read access)

WE12 - WE6 + (RBEA - CSA) — 3 + (RBEA6 - CSA) ns

WE38 BEy_B Invalid to CSx_B

Invalid (Read access)

WE7 - WE13 + (RBEN - CSN) — 3 - (RBEN7- CSN) ns

WE39 CSx_B Valid to ADV_B Valid WE14 - WE6 + (ADVA - CSA) — 3 + (ADVA - CSA) ns

WE40 ADV_B Invalid to CSx_B

Invalid (ADVL is asserted)

WE7 - WE15 - CSN — 3 - CSN ns

WE40A

(muxed

A/D)

CSx_B Valid to ADV_B Invalid WE14 - WE6 + (ADVN + ADVA

+ 1 - CSA)

-3 + (ADVN +

ADVA + 1 - CSA)

3 + (ADVN + ADVA +

1 - CSA)

WE41 CSx_B Valid to Output Data

Valid

WE16 - WE6 - WCSA — 3 - WCSA ns

WE41A

(muxed

A/D)

CSx_B Valid to Output Data

Valid

WE16 - WE6 + (WADVN +

WADVA + ADH + 1 - WCSA)

— 3 + (WADVN +

WADVA + ADH + 1 -

WCSA)

WE42 Output Data Invalid to CSx_B

Invalid

WE17 - WE7 - CSN — 3 - CSN ns

MAXCO Output max. delay from internal

driving ADDR/control FFs to

chip outputs.

10 — — ns

MAXCS

Output max. delay from CSx

internal driving FFs to CSx out.

10 — —

MAXDI DATA MAXIMUM delay from

chip input data to its internal FF

5——

Electrical Characteristics

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 61

4.6.7 DDR SDRAM Specific Parameters (DDR2/LVDDR2, LPDDR2, and

DDR3)

The DDR2/LVDDR2 interface fully complies with JESD79-2E – DDR2 JEDEC release April, 2008,

supporting DDR2-800 and LVDDR2-800.

The DDR3 interface fully complies with JESD79-3D – DDR3 JEDEC release April 2008 supporting

DDR3-800.

The LPDDR2 interface fully complies with JESD209-2B, supporting LPDDR2-800.

WE43 Input Data Valid to CSx_B

Invalid

MAXCO - MAXCSO + MAXDI MAXCO -

MAXCSO +

MAXDI

—ns

WE44 CSx_B Invalid to Input Data

invalid

00—ns

WE45 CSx_B Valid to BEy_B Valid

(Write access)

WE12 - WE6 + (WBEA - CSA) — 3 + (WBEA - CSA) ns

WE46 BEy_B Invalid to CSx_B Invalid

(Write access)

WE7 - WE13 + (WBEN - CSN) — -3 + (WBEN - CSN) ns

MAXDTI DTACK MAXIMUM delay from

chip dtack input to its internal

FF + 2 cycles for

synchronization

———

WE47 Dtack Active to CSx_B Invalid MAXCO - MAXCSO + MAXDTI MAXCO -

MAXCSO +

MAXDTI

—ns

WE48 CSx_B Invalid to Dtack invalid 0 0 — ns

1Parameters WE4... WE21 value see column BCD = 0 in Table 38.

2All config. parameters (CSA,CSN,WBEA,WBEN,ADVA,ADVN,OEN,OEA,RBEA & RBEN) are in cycle units.

3CS Assertion. This bit field determines when CS signal is asserted during read/write cycles.

4CS Negation. This bit field determines when CS signal is negated during read/write cycles.

5t is axi_clk cycle time.

6BE Assertion. This bit field determines when BE signal is asserted during read cycles.

7BE Negation. This bit field determines when BE signal is negated during read cycles.

Table 39. EIM Asynchronous Timing Parameters Table Relative Chip Select

Ref No. Parameter

Determination by

Synchronous measured

parameters 12

Min

Max

(If 133 MHz is

supported by SOC)

Unit

i.MX53 Applications Processors for Industrial Products, Rev. 7

62 Freescale Semiconductor

Electrical Characteristics

Figure 28 and Table 40 show the address and control timing parameters for DDR2 and DDR3.

Figure 28. DDR SDRAM Address and Control Parameters for DDR2 and DDR3

Table 40. DDR SDRAM Timing Parameter Table1 2

1All timings are refer to Vref level cross point.

2 Reference load model is 25 Ω resistor from each of the DDR outputs to VDD_REF.

ID Parameter Symbol

SDCLK = 400 MHz

Units

Min Max

DDR1 SDRAM clock high-level width tCH 0.48 0.52 tCK

DDR2 SDRAM clock low-level width tCL 0.48 0.52 tCK

DDR4 CS, RAS, CAS, CKE, WE, ODT setup time tIS 0.6 — ns

DDR5 CS, RAS, CAS, CKE, WE, ODT hold time tIH 0.6 — ns

DDR6 Address output setup time tIS 0.6 — ns

DDR7 Address output hold time tIH 0.6 — ns

SDCLK

ADDR ROW/BA COL/BA

CAS

RAS

DDR1

DDR2

DDR4

DDR5

DDR6

DDR7

SDCLK

ODT/CKE

DDR4

Electrical Characteristics

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 63

Figure 29 and Table 41 show the address and control timing parameters for LPDDR2.

Figure 29. DDR SDRAM Address and Control Timing Parameters for LPDDR2

Figure 30 and Table 42 show the data write timing parameters.

Figure 30. DDR SDRAM Data Write Cycle

Table 41. DDR SDRAM Timing Parameter Table for LPDDR21 2

1All timings are refer to Vref level cross point.

2 Reference load model is 25 Ω resistor from each of the DDR outputs to VDD_REF.

ID Parameter Symbol

SDCLK = 400 MHz

Units

Min Max

LP1 SDRAM clock high-level width tCH 0.45 0.55 tCK

LP2 SDRAM clock low-level width tCL 0.45 0.55 tCK

LP3 CS, CKE setup time tIS 0.3 — ns

LP4 CS, CKE hold time tIH 0.3 — ns

LP3 CA setup time tIS 0.3 — ns

LP4 CA hold time tIH 0.3 — ns

CKE

LP4

LP3

LP4

LP3

LP2

LP3

LP1

SDCLK

SDCLK_B

DQS (output)

DQ (output)

DQM (output)

Data Data Data Data Data Data Data Data

DM DM DM DM DM DM DM DM

DDR17

DDR18 DDR18

DDR21

DDR23

DDR22

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64 Freescale Semiconductor

Electrical Characteristics

Figure 31 and Table 43 show the data read timing parameters.

Figure 31. DDR SDRAM DQ vs. DQS and SDCLK Read Cycle

Table 42. DDR SDRAM Write Cycle 1 2 3

1All timings are refer to Vref level cross point.

2 Reference load model is 25 Ω resistor from each of the DDR outputs to VDD_REF.

3To receive the reported setup and hold values, write calibration should be performed in order to locate the DQS in the middle

of DQ window.

ID Parameter Symbol

SDCLK = 400 MHz

Unit

Min Max

DDR17 DQ and DQM setup time to DQS (differential strobe) tDS 0.285 — ns

DDR18 DQ and DQM hold time to DQS (differential strobe) tDH 0.285 — ns

DDR21 DQS latching rising transitions to associated clock edges tDQSS -0.25 +0.25 tCK

DDR22 DQS high level width tDQSH 0.45 0.55 tCK

DDR23 DQS low level width tDQSL 0.45 0.55 tCK

Table 43. DDR SDRAM Read Cycle 1

1To receive the reported setup and hold values, read calibration should be performed in order to locate the DQS in the middle

of DQ window.

ID Parameter Symbol

SDCLK = 400 MHz

Unit

Min Max

DDR26 Minimum required DQ valid window width

except from LPDDR2

—0.6 —ns

DDR26(LP

DDR2)

Minimum required DQ valid window width

for LPDDR2

—0.425 —ns

DDR27 DQS to DQ valid data — 0.275 0.475 ns

SDCLK

SDCLK_B

DQS (input)

DQ (input)

DATA

DATADATA

DATA

DATADATA

DDR26

DDR27

Electrical Characteristics

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 65

4.7 External Peripheral Interfaces Parameters

The following subsections provide information on external peripheral interfaces.

4.7.1 AUDMUX Timing Parameters

The AUDMUX provides a programmable interconnect logic for voice, audio and data routing between

internal serial interfaces (SSIs) and external serial interfaces (audio and voice codecs). The AC timing of

AUDMUX external pins is governed by the SSI module. For more information, see the respective SSI

electrical specifications found within this document.

4.7.2 CSPI and ECSPI Timing Parameters

This section describes the timing parameters of the CSPI and ECSPI blocks. The CSPI and ECSPI have

separate timing parameters for master and slave modes. The nomenclature used with the CSPI / ECSPI

modules and the respective routing of these signals is shown in Table 44.

4.7.2.1 CSPI Master Mode Timing

Figure 32 depicts the timing of CSPI in master mode. Table 45 lists the CSPI master mode timing

characteristics.

Figure 32. CSPI/ECSPI Master Mode Timing Diagram

Table 44. CSPI Nomenclature and Routing

Block Instance I/O Access

ECSPI-1 GPIO, KPP, DISP0_DAT, CSI0_DAT and EIM_D through IOMUXC

ECSPI-2 DISP0_DAT, CSI0_DAT and EIM through IOMUXC

CSPI DISP0_DAT, EIM_A/D, SD1 and SD2 through IOMUXC

CS1

CS7

CS2

CS4

CS6 CS5

CS8 CS9

SCLK

SSx

MOSI

MISO

RDY

CS10

CS3

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Electrical Characteristics

4.7.2.2 CSPI Slave Mode Timing

Figure 33 depicts the timing of CSPI in slave mode. Timing characteristics were not available at the time

of publication.

Figure 33. CSPI/ECSPI Slave Mode Timing Diagram

Table 45. CSPI Master Mode Timing Parameters

ID Parameter Symbol Min Max Unit

CS1 SCLK Cycle Time tclk 60 — ns

CS2 SCLK High or Low Time tSW 26 — ns

CS3 SCLK Rise or Fall1

1See specific I/O AC parameters Section 4.5, “I/O AC Parameters”

tRISE/FALL ——ns

CS4 SSx pulse width tCSLH 26 — ns

CS5 SSx Lead Time (Slave Select setup

time)

tSCS 26 — ns

CS6 SSx Lag Time (SS hold time) tHCS 26 — ns

CS7 MOSI Propagation Delay

(CLOAD =20pF)

tPDmosi -1 21 ns

CS8 MISO Setup Time tSmiso 5—ns

CS9 MISO Hold Time tHmiso 5—ns

CS10 RDY to SSx Time2

2SPI_RDY is sampled internally by ipg_clk and is asynchronous to all other CSPI signals.

tSDRY 5—ns

CS1

CS7 CS8

CS2

CS4

CS6 CS5

CS9

SCLK

SSx

MISO

MOSI

Electrical Characteristics

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 67

4.7.2.3 ECSPI Master Mode Timing

Figure 32 depicts the timing of ECSPI in master mode. Table 46 lists the ECSPI master mode timing

characteristics.

4.7.2.4 ECSPI Slave Mode Timing

Figure 33 depicts the timing of ECSPI in slave mode. Table 47 lists the ECSPI slave mode timing

characteristics.

Table 46. ECSPI Master Mode Timing Parameters

ID Parameter Symbol Min Max Unit

CS1 SCLK Cycle Time—Read

SCLK Cycle Time—Write

tclk 30

—ns

CS2 SCLK High or Low Time—Read

SCLK High or Low Time—Write

tSW 14

—ns

CS3 SCLK Rise or Fall1

1See specific I/O AC parameters Section 4.5, “I/O AC Parameters”

tRISE/FALL ——ns

CS4 SSx pulse width tCSLH Half SCLK period — ns

CS5 SSx Lead Time (CS setup time) tSCS 5—ns

CS6 SSx Lag Time (CS hold time) tHCS 5—ns

CS7 MOSI Propagation Delay (CLOAD =20pF) t

PDmosi -0.5 2.5 ns

CS8 MISO Setup Time tSmiso 8.5 — ns

CS9 MISO Hold Time tHmiso 0—ns

CS10 RDY to SSx Time2

2SPI_RDY is sampled internally by ipg_clk and is asynchronous to all other CSPI signals.

tSDRY 5—ns

Table 47. ECSPI Slave Mode Timing Parameters

ID Parameter Symbol Min Max Unit

CS1 SCLK Cycle Time–Read

SCLK Cycle Time–Write

tclk 15

—ns

CS2 SCLK High or Low Time–Read

SCLK High or Low Time–Write

tSW 7

—ns

CS4 SSx pulse width tCSLH Half SCLK period — ns

CS5 SSx Lead Time (CS setup time) tSCS 5—ns

CS6 SSx Lag Time (CS hold time) tHCS 5—ns

CS7 MOSI Setup Time tSmosi 4—ns

CS8 MOSI Hold Time tHmosi 4—ns

CS9 MISO Propagation Delay (CLOAD =20pF) t

PDmiso 417ns

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Electrical Characteristics

4.7.3 Enhanced Serial Audio Interface (ESAI) Timing Parameters

The ESAI consists of independent transmitter and receiver sections, each section with its own clock

generator. Table 48 shows the interface timing values. The number field in the table refers to timing signals

found in Figure 34 and Figure 35.

Table 48. Enhanced Serial Audio Interface (ESAI) Timing

No. Characteristics1’2,3

Symbol Expression3Min Max Condition4Unit

62 Clock cycle5tSSICC 4 × T

4 × T

30.0

—

i ck

63 Clock high period

• For internal clock —2 × Tc − 9.0 6 — —

• For external clock — 2 × T

c15 — —

64 Clock low period

• For internal clock —2 × Tc − 9.0 6 — —

• For external clock — 2 × T

c15 — —

65 SCKR rising edge to FSR out (bl) high —

—

17.0

7.0

x ck

i ck a

66 SCKR rising edge to FSR out (bl) low —

—

17.0

7.0

x ck

i ck a

67 SCKR rising edge to FSR out (wr) high6—

—

19.0

9.0

x ck

i ck a

68 SCKR rising edge to FSR out (wr) low6—

—

19.0

9.0

x ck

i ck a

69 SCKR rising edge to FSR out (wl) high —

—

16.0

6.0

x ck

i ck a

70 SCKR rising edge to FSR out (wl) low —

—

17.0

7.0

x ck

i ck a

71 Data in setup time before SCKR (SCK in synchronous

mode) falling edge

—

12.0

19.0

—

x ck

i ck

72 Data in hold time after SCKR falling edge —

—

3.5

9.0

—

x ck

i ck

73 FSR input (bl, wr) high before SCKR falling edge6—

—

2.0

12.0

—

x ck

i ck a

74 FSR input (wl) high before SCKR falling edge —

—

2.0

12.0

—

x ck

i ck a

75 FSR input hold time after SCKR falling edge —

—

2.5

8.5

—

x ck

i ck a

78 SCKT rising edge to FST out (bl) high —

—

18.0

8.0

x ck

i ck

79 SCKT rising edge to FST out (bl) low —

—

20.0

10.0

x ck

i ck

Electrical Characteristics

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 69

80 SCKT rising edge to FST out (wr) high6—

—

20.0

10.0

x ck

i ck

81 SCKT rising edge to FST out (wr) low6 —

—

22.0

12.0

x ck

i ck

82 SCKT rising edge to FST out (wl) high —

—

19.0

9.0

x ck

i ck

83 SCKT rising edge to FST out (wl) low —

—

20.0

10.0

x ck

i ck

84 SCKT rising edge to data out enable from high

impedance

—

22.0

17.0

x ck

i ck

86 SCKT rising edge to data out valid —

—

18.0

13.0

x ck

i ck

87 SCKT rising edge to data out high impedance 77 —

—

21.0

16.0

x ck

i ck

89 FST input (bl, wr) setup time before SCKT falling edge6—

—

2.0

18.0

—

x ck

i ck

90 FST input (wl) setup time before SCKT falling edge —

—

2.0

18.0

—

x ck

i ck

91 FST input hold time after SCKT falling edge —

—

4.0

5.0

—

x ck

i ck

95 HCKR/HCKT clock cycle — 2 x TC15 — — ns

96 HCKT input rising edge to SCKT output — — — 18.0 — ns

97 HCKR input rising edge to SCKR output — — — 18.0 — ns

1VCORE_VDD= 1.00 ± 0.10V

Tj = -40 °C to 125 °C

CL= 50 pF

2i ck = internal clock

x ck = external clock

i ck a = internal clock, asynchronous mode

(asynchronous implies that SCKT and SCKR are two different clocks)

i ck s = internal clock, synchronous mode

(synchronous implies that SCKT and SCKR are the same clock)

3bl = bit length

wl = word length

wr = word length relative

4SCKT(SCKT pin) = transmit clock

SCKR(SCKR pin) = receive clock

FST(FST pin) = transmit frame sync

FSR(FSR pin) = receive frame sync

HCKT(HCKT pin) = transmit high frequency clock

HCKR(HCKR pin) = receive high frequency clock

5For the internal clock, the external clock cycle is defined by Icyc and the ESAI control register.

Table 48. Enhanced Serial Audio Interface (ESAI) Timing (continued)

No. Characteristics1’2,3

Symbol Expression3Min Max Condition4Unit

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Electrical Characteristics

Figure 34. ESAI Transmitter Timing

6The word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame sync

signal waveform, but it spreads from one serial clock before the first bit clock (like the bit length frame sync signal), until the

second-to-last bit clock of the first word in the frame.

7Periodically sampled and not 100% tested.

SCKT

(Input/Output)

FST (Bit)

Out

FST (Word)

Out

Data Out

FST (Bit) In

FST (Word) In

78 79

82 83

8686

90 91

Last BitFirst Bit

Electrical Characteristics

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 71

Figure 35. ESAI Receiver Timing

SCKR

(Input/Output)

FSR (Bit)

Out

FSR (Word)

Out

Data In

FSR (Bit)

FSR (Word)

69 70

74 75

First Bit Last Bit

i.MX53 Applications Processors for Industrial Products, Rev. 7

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Electrical Characteristics

4.7.4 Enhanced Secured Digital Host Controller(eSDHCv2/v3) AC timing

This section describes the electrical information of the eSDHCv2/v3, which includes SD/eMMC4.3

(Single Data Rate) timing and eMMC4.4 (Dual Date Rate) timing.

4.7.4.1 SD/eMMC4.3 (Single Data Rate) AC Timing

Figure 36 depicts the timing of SD/eMMC4.3, and Table 49 lists the SD/eMMC4.3 timing characteristics.

Figure 36. SD/eMMC4.3 Timing

Table 49. SD/eMMC4.3 Interface Timing Specification

ID Parameter Symbols Min Max Unit

Card Input Clock

SD1 Clock Frequency (Low Speed) fPP10 400 kHz

Clock Frequency (SD/SDIO Full Speed/High Speed) fPP20 25/50 MHz

Clock Frequency (MMC Full Speed/High Speed) fPP30 20/52 MHz

Clock Frequency (Identification Mode) fOD 100 400 kHz

SD2 Clock Low Time tWL 7—ns

SD3 Clock High Time tWH 7—ns

SD4 Clock Rise Time tTLH —3ns

SD5 Clock Fall Time tTHL —3ns

eSDHC Output/Card Inputs CMD, DAT (Reference to CLK)

SD6 eSDHCv2 Output Delay (port 1, 2, and 4) tOD -3.5 3.5 ns

eSDHCv3 Output Delay (port 3) tOD -4.5 4.5 ns

SD1

SD3

SD5

SD4

SD7

CMD

output from eSDHCv2 to card DAT1

......

DAT7

DAT0

CMD

input from card to eSDHCv2 DAT1

......

DAT7

DAT0

SCK

SD2

SD8

SD6

Electrical Characteristics

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 73

4.7.4.2 eMMC4.4 (Dual Data Rate) eSDHCv3 AC Timing

Figure 37 depicts the timing of eMMC4.4. Table 50 lists the eMMC4.4 timing characteristics. Be aware

that only DATA is sampled on both edges of the clock (not applicable to CMD).

Figure 37. eMMC4.4 Timing

eSDHC Input/Card Outputs CMD, DAT (Reference to CLK)

SD7 eSDHC Input Setup Time tISU 2.5 — ns

SD8 eSDHC Input Hold Time4tIH 2.5 — ns

1In low speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V.

2In normal (full) speed mode for SD/SDIO card, clock frequency can be any value between 0–25 MHz. In high-speed mode,

clock frequency can be any value between 0–50 MHz.

3In normal (full) speed mode for MMC card, clock frequency can be any value between 0–20 MHz. In high-speed mode, clock

frequency can be any value between 0–52 MHz.

4To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns.

Table 50. eMMC4.4 Interface Timing Specification

ID Parameter Symbols Min Max Unit

Card Input Clock

SD1 Clock Frequency (MMC Full Speed/High Speed) fPP 052MHz

eSDHC Output / Card Inputs CMD, DAT (Reference to CLK)

SD2 eSDHC Output Delay tOD -4.5 4.5 ns

Table 49. SD/eMMC4.3 Interface Timing Specification (continued)

ID Parameter Symbols Min Max Unit

SD1

SD2

SD3

output from eSDHCv3 to card DAT1

......

DAT7

DAT0

input from card to eSDHCv3 DAT1

......

DAT7

DAT0

SCK

SD4

SD2

......

i.MX53 Applications Processors for Industrial Products, Rev. 7

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Electrical Characteristics

4.7.5 FEC AC Timing Parameters

This section describes the electrical information of the Fast Ethernet Controller (FEC) module. The FEC

is designed to support both 10 and 100 Mbps Ethernet/IEEE 802.3 networks. An external transceiver

interface and transceiver function are required to complete the interface to the media. The FEC supports

the 10/100 Mbps MII (18 pins in total) and the 10 Mbps (only 7-wire interface, which uses 7 of the MII

pins), for connection to an external Ethernet transceiver. For the pin list of MII and 7-wire, see the i.MX53

Reference Manual.

This section describes the AC timing specifications of the FEC. The MII signals are compatible with

transceivers operating at a voltage of 3.3 V.

4.7.5.1 MII Receive Signal Timing

The MII receive signal timing involves the FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER, and

FEC_RX_CLK signals. The receiver functions correctly up to a FEC_RX_CLK maximum frequency of

25 MHz + 1%. There is no minimum frequency requirement but the processor clock frequency must

exceed twice the FEC_RX_CLK frequency. Table 51 lists the MII receive channel signal timing

parameters and Figure 38 shows MII receive signal timings.

eSDHC Input / Card Outputs CMD, DAT (Reference to CLK)

SD3 eSDHC Input Setup Time tISU 2.5 — ns

SD4 eSDHC Input Hold Time tIH 2.5 — ns

Table 51. MII Receive Signal Timing

No. Characteristics1 2

1FEC_RX_DV, FEC_RX_CLK, and FEC_RXD0 have same timing in 10 Mbps 7-wire interface mode.

2Test conditions: 25pF on each output signal.

Min Max Unit

M1 FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER to FEC_RX_CLK setup 5 — ns

M2 FEC_RX_CLK to FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER hold 5 — ns

M3 FEC_RX_CLK pulse width high 35% 65% FEC_RX_CLK period

M4 FEC_RX_CLK pulse width low 35% 65% FEC_RX_CLK period

Table 50. eMMC4.4 Interface Timing Specification (continued)

ID Parameter Symbols Min Max Unit

Electrical Characteristics

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 75

Figure 38. MII Receive Signal Timing Diagram

4.7.5.2 MII Transmit Signal Timing

The MII transmit signal timing affects the FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER, and

FEC_TX_CLK signals. The transmitter functions correctly up to a FEC_TX_CLK maximum frequency

of 25 MHz + 1%. There is no minimum frequency requirement. In addition, the processor clock frequency

must exceed twice the FEC_TX_CLK frequency.

Table 52 lists MII transmit channel timing parameters. Figure 39 shows MII transmit signal timing

diagram for the values listed in Table 52.

Table 52. MII Transmit Signal Timing

Num Characteristic1 2

1FEC_TX_EN, FEC_TX_CLK, and FEC_TXD0 have the same timing in 10 Mbps 7-wire interface mode.

2Test conditions: 25pF on each output signal.

Min Max Unit

M5 FEC_TX_CLK to FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER invalid 5 — ns

M6 FEC_TX_CLK to FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER valid — 20 ns

M7 FEC_TX_CLK pulse width high 35% 65% FEC_TX_CLK period

M8 FEC_TX_CLK pulse width low 35% 65% FEC_TX_CLK period

FEC_RX_CLK (input)

FEC_RXD[3:0] (inputs)

FEC_RX_DV

FEC_RX_ER

M1 M2

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Electrical Characteristics

Figure 39. MII Transmit Signal Timing Diagram

4.7.5.3 MII Async Inputs Signal Timing (FEC_CRS and FEC_COL)

Table 53 lists MII asynchronous inputs signal timing information. Figure 40 shows MII asynchronous

input timings listed in Table 53.

Figure 40. MII Async Inputs Timing Diagram

4.7.5.4 MII Serial Management Channel Timing (FEC_MDIO and FEC_MDC)

Table 54 lists MII serial management channel timings. Figure 41 shows MII serial management channel

timings listed in Table 54. The MDC frequency should be equal to or less than 2.5 MHz to be compliant

with the IEEE 802.3 MII specification. However, the FEC can function correctly with a maximum MDC

frequency of 15 MHz.

Table 53. MII Async Inputs Signal Timing

Num Characteristic 1

1Test conditions: 25pF on each output signal.

Min Max Unit

M92

2FEC_COL has the same timing in 10 Mbit 7-wire interface mode.

FEC_CRS to FEC_COL minimum pulse width 1.5 — FEC_TX_CLK period

Table 54. MII Transmit Signal Timing

ID Characteristics1Min Max Unit

M10 FEC_MDC falling edge to FEC_MDIO output invalid (minimum propagation delay) 0 — ns

M11 FEC_MDC falling edge to FEC_MDIO output valid (max propagation delay) — 5 ns

M12 FEC_MDIO (input) to FEC_MDC rising edge setup 18 — ns

FEC_TX_CLK (input)

FEC_TXD[3:0] (outputs)

FEC_TX_EN

FEC_TX_ER

FEC_CRS, FEC_COL

Electrical Characteristics

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 77

Figure 41. MII Serial Management Channel Timing Diagram

4.7.5.5 RMII Mode Timing

In RMII mode, FEC_TX_CLK is used as the REF_CLK which is a 50 MHz ±50 ppm continuous reference

clock. FEC_RX_DV is used as the CRS_DV in RMII, and other signals under RMII mode include

FEC_TX_EN, FEC_TXD[1:0], FEC_RXD[1:0] and optional FEC_RX_ER.

The RMII mode timings are shown in Table 55 and Figure 42.

M13 FEC_MDIO (input) to FEC_MDC rising edge hold 0 — ns

M14 FEC_MDC pulse width high 40

60% FEC_MDC period

M15 FEC_MDC pulse width low 40

60% FEC_MDC period

1Test conditions: 25pF on each output signal.

Table 55. RMII Signal Timing

No. Characteristics1Min Max Unit

M16 REF_CLK(FEC_TX_CLK) pulse width high 35% 65% REF_CLK period

M17 REF_CLK(FEC_TX_CLK) pulse width low 35% 65% REF_CLK period

M18 REF_CLK to FEC_TXD[1:0], FEC_TX_EN invalid 2 — ns

M19 REF_CLK to FEC_TXD[1:0], FEC_TX_EN valid — 16 ns

Table 54. MII Transmit Signal Timing (continued)

ID Characteristics1Min Max Unit

FEC_MDC (output)

FEC_MDIO (output)

M14

M15

M10

M11

M12 M13

FEC_MDIO (input)

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78 Freescale Semiconductor

Electrical Characteristics

Figure 42. RMII Mode Signal Timing Diagram

4.7.6 Flexible Controller Area Network (FLEXCAN) AC Electrical

Specifications

The electrical characteristics are related to the CAN transceiver external to i.MX53 such as MC33902 from

Freescale. The i.MX53 has two CAN modules available for systems design. Tx and Rx ports for both

modules are multiplexed with other I/O pins. See the IOMUXC chapter of the i.MX53 Reference Manual

to see which pins expose Tx and Rx pins; these ports are named TXCAN and RXCAN, respectively.

M20 FEC_RXD[1:0], CRS_DV(FEC_RX_DV), FEC_RX_ER to

REF_CLK setup

4—ns

M21 REF_CLK to FEC_RXD[1:0], FEC_RX_DV, FEC_RX_ER

hold

2—ns

1Test conditions: 25pF on each output signal.

Table 55. RMII Signal Timing (continued)

No. Characteristics1Min Max Unit

REF_CLK (input)

FEC_TX_EN

M16

M17

M18

M19

M20 M21

FEC_RXD[1:0]

FEC_TXD[1:0] (output)

FEC_RX_ER

CRS_DV (input)

Electrical Characteristics

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 79

4.7.7 I2C Module Timing Parameters

This section describes the timing parameters of the I2C module. Figure 43 depicts the timing of I2C

module, and Table 56 lists the I2C module timing characteristics.

Figure 43. I2C Bus Timing

Table 56. I2C Module Timing Parameters

ID Parameter

Standard Mode

Supply Voltage =

1.65 V–1.95 V, 2.7 V–3.3 V

Fast Mode

Supply Voltage =

2.7 V–3.3 V Unit

Min Max Min Max

IC1 I2CLK cycle time 10 — 2.5 — µs

IC2 Hold time (repeated) START condition 4.0 — 0.6 — µs

IC3 Set-up time for STOP condition 4.0 — 0.6 — µs

IC4 Data hold time 01

1A device must internally provide a hold time of at least 300 ns for I2DAT signal in order to bridge the undefined region of the

falling edge of I2CLK.

3.452

2The maximum hold time has only to be met if the device does not stretch the LOW period (ID no IC5) of the I2CLK signal.

010.92µs

IC5 HIGH Period of I2CLK Clock 4.0 — 0.6 — µs

IC6 LOW Period of the I2CLK Clock 4.7 — 1.3 — µs

IC7 Set-up time for a repeated START condition 4.7 — 0.6 — µs

IC8 Data set-up time 250 — 1003

3A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement of Set-up time (ID No IC7)

of 250 ns must be met. This automatically is the case if the device does not stretch the LOW period of the I2CLK signal.

If such a device does stretch the LOW period of the I2CLK signal, it must output the next data bit to the I2DAT line

max_rise_time (IC9) + data_setup_time (IC7) = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification)

before the I2CLK line is released.

—ns

IC9 Bus free time between a STOP and START condition 4.7 — 1.3 — µs

IC10 Rise time of both I2DAT and I2CLK signals — 1000 20 + 0.1Cb4

4Cb = total capacitance of one bus line in pF.

300 ns

IC11 Fall time of both I2DAT and I2CLK signals — 300 20 + 0.1Cb4300 ns

IC12 Capacitive load for each bus line (Cb) — 400 — 400 pF

IC10 IC11 IC9

IC2 IC8 IC4 IC7 IC3

IC6

IC10

IC5

IC11 START STOP START

START

I2DAT

I2CLK

IC1

i.MX53 Applications Processors for Industrial Products, Rev. 7

80 Freescale Semiconductor

Electrical Characteristics

4.7.8 Image Processing Unit (IPU) Module Parameters

The purpose of the IPU is to provide comprehensive support for the flow of data from an image sensor

and/or to a display device. This support covers all aspects of these activities:

• Connectivity to relevant devices—cameras, displays, graphics accelerators, and TV encoders.

• Related image processing and manipulation: sensor image signal processing, display processing,

image conversions, and other related functions.

• Synchronization and control capabilities, such as avoidance of tearing artifacts.

4.7.8.1 IPU Sensor Interface Signal Mapping

The IPU supports a number of sensor input formats. Table 57 defines the mapping of the Sensor Interface

Pins used for various supported interface formats.

Table 57. Camera Input Signal Cross Reference, Format and Bits Per Cycle

Signal

Name1

1CSIx stands for CSI1 or CSI2.

RGB565

8 bits

2 cycles

RGB5652

8 bits

3 cycles

RGB6663

8 bits

3 cycles

RGB888

8 bits

3 cycles

YCbCr4

8 bits

2 cycles

RGB5655

16 bits

2 cycles

YCbCr6

16 bits

1 cycle

YCbCr7

16 bits

1 cycle

YCbCr8

20 bits

1 cycle

CSIx_DAT0 — — — — — — — 0 C[0]

CSIx_DAT1 — — — — — — — 0 C[1]

CSIx_DAT2 — — — — — — — C[0] C[2]

CSIx_DAT3 — — — — — — — C[1] C[3]

CSIx_DAT4 — — — — — B[0] C[0] C[2] C[4]

CSIx_DAT5 — — — — — B[1] C[1] C[3] C[5]

CSIx_DAT6 — — — — — B[2] C[2] C[4] C[6]

CSIx_DAT7 — — — — — B[3] C[3] C[5] C[7]

CSIx_DAT8 — — — — — B[4] C[4] C[6] C[8]

CSIx_DAT9 — — — — — G[0] C[5] C[7] C[9]

CSIx_DAT10 — — — — — G[1] C[6] 0 Y[0]

CSIx_DAT11 — — — — — G[2] C[7] 0 Y[1]

CSIx_DAT12 B[0], G[3] R[2],G[4],B[2] R/G/B[4] R/G/B[0] Y/C[0] G[3] Y[0] Y[0] Y[2]

CSIx_DAT13 B[1], G[4] R[3],G[5],B[3] R/G/B[5] R/G/B[1] Y/C[1] G[4] Y[1] Y[1] Y[3]

CSIx_DAT14 B[2], G[5] R[4],G[0],B[4] R/G/B[0] R/G/B[2] Y/C[2] G[5] Y[2] Y[2] Y[4]

CSIx_DAT15 B[3], R[0] R[0],G[1],B[0] R/G/B[1] R/G/B[3] Y/C[3] R[0] Y[3] Y[3] Y[5]

CSIx_DAT16 B[4], R[1] R[1],G[2],B[1] R/G/B[2] R/G/B[4] Y/C[4] R[1] Y[4] Y[4] Y[6]

CSIx_DAT17 G[0], R[2] R[2],G[3],B[2] R/G/B[3] R/G/B[5] Y/C[5] R[2] Y[5] Y[5] Y[7]

CSIx_DAT18 G[1], R[3] R[3],G[4],B[3] R/G/B[4] R/G/B[6] Y/C[6] R[3] Y[6] Y[6] Y[8]

CSIx_DAT19 G[2], R[4] R[4],G[5],B[4] R/G/B[5] R/G/B[7] Y/C[7] R[4] Y[7] Y[7] Y[9]

Electrical Characteristics

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 81

4.7.8.2 Sensor Interface Timings

There are three camera timing modes supported by the IPU.

4.7.8.2.1 BT.656 and BT.1120 Video Mode

Smart camera sensors, which include imaging processing, usually support video mode transfer. They use

an embedded timing syntax to replace the SENSB_VSYNC and SENSB_HSYNC signals. The timing

syntax is defined by the BT.656/BT.1120 standards.

This operation mode follows the recommendations of ITU BT.656/ ITU BT.1120 specifications. The only

control signal used is SENSB_PIX_CLK. Start-of-frame and active-line signals are embedded in the data

stream. An active line starts with a SAV code and ends with a EAV code. In some cases, digital blanking

is inserted in between EAV and SAV code. The CSI decodes and filters out the timing-coding from the data

stream, thus recovering SENSB_VSYNC and SENSB_HSYNC signals for internal use. On BT.656 one

component per cycle is received over the SENSB_DATA bus. On BT.1120 two components per cycle are

received over the SENSB_DATA bus.

4.7.8.2.2 Gated Clock Mode

The SENSB_VSYNC, SENSB_HSYNC, and SENSB_PIX_CLK signals are used in this mode. See

Figure 44.

Figure 44. Gated Clock Mode Timing Diagram

A frame starts with a rising edge on SENSB_VSYNC (all the timings correspond to straight polarity of the

corresponding signals). Then SENSB_HSYNC goes to high and hold for the entire line. Pixel clock is

2The MSB bits are duplicated on LSB bits implementing color extension.

3The two MSB bits are duplicated on LSB bits implementing color extension.

4YCbCr 8 bits—Supported within the BT.656 protocol (sync embedded within the data stream).

5RGB 16 bits—Supported in two ways: (1) As a “generic data” input, with no on-the-fly processing; (2) With on-the-fly

processing, but only under some restrictions on the control protocol.

6YCbCr 16 bits—Supported as a “generic data” input, with no on-the-fly processing.

7YCbCr 16 bits—Supported as a sub-case of the YCbCr, 20 bits, under the same conditions (BT.1120 protocol).

8YCbCr 20 bits—Supported only within the BT.1120 protocol (syncs embedded within the data stream).

SENSB_VSYNC

SENSB_HSYNC

SENSB_PIX_CLK

SENSB_DATA[19:0] invalid

1st byte

n+1th frame

invalid

1st byte

nth frame

Active Line

Start of Frame

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82 Freescale Semiconductor

Electrical Characteristics

valid as long as SENSB_HSYNC is high. Data is latched at the rising edge of the valid pixel clocks.

SENSB_HSYNC goes to low at the end of line. Pixel clocks then become invalid and the CSI stops

receiving data from the stream. For next line the SENSB_HSYNC timing repeats. For next frame the

SENSB_VSYNC timing repeats.

4.7.8.2.3 Non-Gated Clock Mode

The timing is the same as the gated-clock mode (described in Section 4.7.8.2.2, “Gated Clock Mode,”)

except for the SENSB_HSYNC signal, which is not used (see Figure 45). All incoming pixel clocks are

valid and cause data to be latched into the input FIFO. The SENSB_PIX_CLK signal is inactive (states

low) until valid data is going to be transmitted over the bus.

Figure 45. Non-Gated Clock Mode Timing Diagram

The timing described in Figure 45 is that of a typical sensor. Some other sensors may have a slightly

different timing. The CSI can be programmed to support rising/falling-edge triggered SENSB_VSYNC;

active-high/low SENSB_HSYNC; and rising/falling-edge triggered SENSB_PIX_CLK.

4.7.8.3 Electrical Characteristics

Figure 46 depicts the sensor interface timing. SENSB_MCLK signal described here is not generated by

the IPU. Table 58 lists the sensor interface timing characteristics.

Figure 46. Sensor Interface Timing Diagram

SENSB_VSYNC

SENSB_PIX_CLK

SENSB_DATA[19:0] invalid

1st byte

n+1th frame

invalid

1st byte

nth frame

Start of Frame

IP3

SENSB_DATA,

SENSB_VSYNC,

IP2 1/IP1

SENSB_PIX_CLK

(Sensor Output)

SENSB_HSYNC

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Freescale Semiconductor 83

4.7.8.4 IPU Display Interface Signal Mapping

The IPU supports a number of display output video formats. Table 59 defines the mapping of the Display

Interface Pins used during various supported video interface formats.

Table 58. Sensor Interface Timing Characteristics

ID Parameter Symbol Min Max Unit

IP1 Sensor output (pixel) clock frequency Fpck 0.01 180 MHz

IP2 Data and control setup time Tsu 2 — ns

IP3 Data and control holdup time Thd 1 — ns

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Electrical Characteristics

Table 59. Video Signal Cross-Reference

i.MX53 LCD

Comment1

Port Name

(x=0, 1)

RGB,

Signal

Name

(General)

RGB/TV Signal Allocation (Example) Smart

16-bit

RGB

18-bit

RGB

24 Bit

RGB

8-bit

YCrCb2

16-bit

YCrCb

20-bit

YCrCb

Signal

Name

DISPx_DAT0 DAT[0] B[0] B[0] B[0] Y/C[0] C[0] C[0] DAT[0] The restrictions are as follows:

a) There are maximal three

continuous groups of bits that

could be independently mapped to

the external bus.

Groups should not be overlapped.

b) The bit order is expressed in

each of the bit groups, for example

B[0] = least significant blue pixel

bit

DISPx_DAT1 DAT[1] B[1] B[1] B[1] Y/C[1] C[1] C[1] DAT[1]

DISPx_DAT2 DAT[2] B[2] B[2] B[2] Y/C[2] C[2] C[2] DAT[2]

DISPx_DAT3 DAT[3] B[3] B[3] B[3] Y/C[3] C[3] C[3] DAT[3]

DISPx_DAT4 DAT[4] B[4] B[4] B[4] Y/C[4] C[4] C[4] DAT[4]

DISPx_DAT5 DAT[5] G[0] B[5] B[5] Y/C[5] C[5] C[5] DAT[5]

DISPx_DAT6 DAT[6] G[1] G[0] B[6] Y/C[6] C[6] C[6] DAT[6]

DISPx_DAT7 DAT[7] G[2] G[1] B[7] Y/C[7] C[7] C[7] DAT[7]

DISPx_DAT8 DAT[8] G[3] G[2] G[0] — Y[0] C[8] DAT[8]

DISPx_DAT9 DAT[9] G[4] G[3] G[1] — Y[1] C[9] DAT[9]

DISPx_DAT10 DAT[10] G[5] G[4] G[2] — Y[2] Y[0] DAT[10]

DISPx_DAT11 DAT[11] R[0] G[5] G[3] — Y[3] Y[1] DAT[11]

DISPx_DAT12 DAT[12] R[1] R[0] G[4] — Y[4] Y[2] DAT[12]

DISPx_DAT13 DAT[13] R[2] R[1] G[5] — Y[5] Y[3] DAT[13]

DISPx_DAT14 DAT[14] R[3] R[2] G[6] — Y[6] Y[4] DAT[14]

DISPx_DAT15 DAT[15] R[4] R[3] G[7] — Y[7] Y[5] DAT[15]

DISPx_DAT16 DAT[16] — R[4] R[0] — — Y[6] —

DISPx_DAT17 DAT[17] — R[5] R[1] — — Y[7] —

DISPx_DAT18 DAT[18] — — R[2] — — Y[8] —

DISPx_DAT19 DAT[19] — — R[3] — — Y[9] —

DISPx_DAT20 DAT[20] — — R[4] — — — —

DISPx_DAT21 DAT[21] — — R[5] — — — —

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Freescale Semiconductor 85

DISPx_DAT22 DAT[22] — — R[6] — — — — —

DISPx_DAT23 DAT[23] — — R[7] — — — — —

DIx_DISP_CLK PixCLK — —

DIx_PIN1 — VSYNC_IN May be required for anti-tearing

DIx_PIN2 HSYNC — —

DIx_PIN3 VSYNC — VSYNC out

DIx_PIN4 — — Additional frame/row synchronous

signals with programmable timing

DIx_PIN5 — —

DIx_PIN6 — —

DIx_PIN7 — —

DIx_PIN8 — —

DIx_D0_CS — CS0 —

DIx_D1_CS — CS1 Alternate mode of PWM output for

contrast or brightness control

DIx_PIN11 — WR —

DIx_PIN12 — RD —

DIx_PIN13 — RS1 Register select signal

DIx_PIN14 — RS2 Optional RS2

DIx_PIN15 DRDY/DV DRDY Data validation/blank, data enable

DIx_PIN16 — — Additional data synchronous

signals with programmable

features/timing

DIx_PIN17 Q —

1 Signal mapping (both data and control/synchronization) is flexible. The table provides examples.

2This mode works in compliance with recommendation ITU-R BT.656. The timing reference signals (frame start, frame end, line

start, and line end) are embedded in the 8-bit data bus. Only video data is supported, transmission of non-video related data

during blanking intervals is not supported.

Table 59. Video Signal Cross-Reference (continued)

i.MX53 LCD

Comment1

Port Name

(x=0, 1)

RGB,

Signal

Name

(General)

RGB/TV Signal Allocation (Example) Smart

16-bit

RGB

18-bit

RGB

24 Bit

RGB

8-bit

YCrCb2

16-bit

YCrCb

20-bit

YCrCb

Signal

Name

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86 Freescale Semiconductor

Electrical Characteristics

NOTE

Table 59 provides information for both the Disp0 and Disp1 ports. However,

Disp1 port has reduced pinout depending on IOMUXC configuration and

therefore may not support all the above configurations. See the IOMUXC

table for details.

4.7.8.5 IPU Display Interface Timing

The IPU Display Interface supports two kinds of display accesses: synchronous and asynchronous. There

are two groups of external interface pins to provide synchronous and asynchronous controls accordantly.

4.7.8.5.1 Synchronous Controls

The synchronous control changes its value as a function of a system or of an external clock. This control

has a permanent period and a permanent wave form.

There are special physical outputs to provide synchronous controls:

• The ipp_disp_clk is a dedicated base synchronous signal that is used to generate a base display

(component, pixel) clock for a display.

• The ipp_pin_1– ipp_pin_7 are general purpose synchronous pins, that can be used to provide

HSYNC, VSYNC, DRDY or any else independent signal to a display.

The IPU has a system of internal binding counters for internal events (such as HSYNC/VSYCN and so on)

calculation. The internal event (local start point) is synchronized with internal DI_CLK. A suitable control

starts from the local start point with predefined UP and DOWN values to calculate control’s changing

points with half DI_CLK resolution. A full description of the counters system can be found in the IPU

chapter of the i.MX53 Reference Manual.

4.7.8.5.2 Asynchronous Controls

The asynchronous control is a data-oriented signal that changes its value with an output data according to

additional internal flags coming with the data.

There are special physical outputs to provide asynchronous controls, as follows:

• The ipp_d0_cs and ipp_d1_cs pins are dedicated to provide chip select signals to two displays.

• The ipp_pin_11– ipp_pin_17 are general purpose asynchronous pins, that can be used to provide

WR. RD, RS or any other data oriented signal to display.

NOTE

The IPU has independent signal generators for asynchronous signals

toggling. When a DI decides to put a new asynchronous data in the bus, a

new internal start (local start point) is generated. The signals generators

calculate predefined UP and DOWN values to change pins states with half

DI_CLK resolution.

Electrical Characteristics

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 87

4.7.8.6 Synchronous Interfaces to Standard Active Matrix TFT LCD Panels

4.7.8.6.1 IPU Display Operating Signals

The IPU uses four control signals and data to operate a standard synchronous interface:

• IPP_DISP_CLK—Clock to display

• HSYNC—Horizontal synchronization

• VSYNC—Vertical synchronization

• DRDY—Active data

All synchronous display controls are generated on the base of an internally generated “local start point”.

The synchronous display controls can be placed on time axis with DI’s offset, up and down parameters.

The display access can be whole number of DI clock (Tdiclk) only. The IPP_DATA can not be moved

relative to the local start point. The data bus of the synchronous interface is output direction only.

4.7.8.6.2 LCD Interface Functional Description

Figure 47 depicts the LCD interface timing for a generic active matrix color TFT panel. In this figure

signals are shown with negative polarity. The sequence of events for active matrix interface timing is:

• DI_CLK internal DI clock, used for calculation of other controls.

• IPP_DISP_CLK latches data into the panel on its negative edge (when positive polarity is

selected). In active mode, IPP_DISP_CLK runs continuously.

• HSYNC causes the panel to start a new line. (Usually IPP_PIN_2 is used as HSYNC.)

• VSYNC causes the panel to start a new frame. It always encompasses at least one HSYNC pulse.

(Usually IPP_PIN_3 is used as VSYNC.)

• DRDY acts like an output enable signal to the CRT display. This output enables the data to be

shifted onto the display. When disabled, the data is invalid and the trace is off.

(DRDY can be used either synchronous or asynchronous generic purpose pin as well.)

Figure 47. Interface Timing Diagram for TFT (Active Matrix) Panels

123 mm-1

HSYNC

VSYNC

HSYNC

LINE 1 LINE 2 LINE 3 LINE 4 LINE n-1 LINE n

DRDY

IPP_DISP_CLK

IPP_DATA

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Electrical Characteristics

4.7.8.6.3 TFT Panel Sync Pulse Timing Diagrams

Figure 48 depicts the horizontal timing (timing of one line), including both the horizontal sync pulse and

the data. All the parameters shown in the figure are programmable. All controls are started by

corresponding internal events—local start points. The timing diagrams correspond to inverse polarity of

the IPP_DISP_CLK signal and active-low polarity of the HSYNC, VSYNC, and DRDY signals.

Figure 48. TFT Panels Timing Diagram—Horizontal Sync Pulse

Figure 49 depicts the vertical timing (timing of one frame). All parameters shown in the figure are

programmable.

Figure 49. TFT Panels Timing Diagram—Vertical Sync Pulse

DI clock

VSYNC

HSYNC

DRDY

D0 D1

IP5o

IP13o

IP9o

IP8o IP8

IP9

IP10

IP7

IP5

IP6

local start point

IPP_DISP_CLK

IPP_DATA

IP14

VSYNC

HSYNC

DRDY

Start of frame End of frame

IP12

IP15

IP13

IP11

Electrical Characteristics

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 89

Table 60 shows timing characteristics of signals presented in Figure 48 and Figure 49.

Table 60. Synchronous Display Interface Timing Characteristics (Pixel Level)

ID Parameter Symbol Value Description Unit

IP5 Display interface clock period Tdicp (1) Display interface clock. IPP_DISP_CLK ns

IP6 Display pixel clock period Tdpcp DISP_CLK_PER_PIXEL

× Tdicp

Time of translation of one pixel to display,

DISP_CLK_PER_PIXEL—number of pixel

components in one pixel (1.n). The

DISP_CLK_PER_PIXEL is virtual

parameter to define Display pixel clock

period.

The DISP_CLK_PER_PIXEL is received

by DC/DI one access division to n

components.

IP7 Screen width time Tsw (SCREEN_WIDTH)

× Tdicp

SCREEN_WIDTH—screen width in,

interface clocks. horizontal blanking

included.

The SCREEN_WIDTH should be built by

suitable DI’s counter2.

IP8 HSYNC width time Thsw (HSYNC_WIDTH) HSYNC_WIDTH—Hsync width in DI_CLK

with 0.5 DI_CLK resolution. Defined by DI’s

counter.

IP9 Horizontal blank interval 1 Thbi1 BGXP × Tdicp BGXP—width of a horizontal blanking

before a first active data in a line (in

interface clocks). The BGXP should be built

by suitable DI’s counter.

IP10 Horizontal blank interval 2 Thbi2 (SCREEN_WIDTH -

BGXP - FW) × Tdicp

Width a horizontal blanking after a last

active data in a line (in interface clocks)

FW—with of active line in interface clocks.

The FW should be built by suitable DI’s

counter.

IP12 Screen height Tsh (SCREEN_HEIGHT)

× Ts w

SCREEN_HEIGHT— screen height in lines

with blanking.

The SCREEN_HEIGHT is a distance

between 2 VSYNCs.

The SCREEN_HEIGHT should be built by

suitable DI’s counter.

IP13 VSYNC width Tvsw VSYNC_WIDTH VSYNC_WIDTH—Vsync width in DI_CLK

with 0.5 DI_CLK resolution. Defined by DI’s

counter

IP14 Vertical blank interval 1 Tvbi1 BGYP × Tsw BGYP—width of first Vertical

blanking interval in line.The BGYP should

be built by suitable DI’s counter.

IP15 Vertical blank interval 2 Tvbi2 (SCREEN_HEIGHT -

BGYP - FH) × Tsw

Width of second Vertical

blanking interval in line.The FH should be

built by suitable DI’s counter.

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90 Freescale Semiconductor

Electrical Characteristics

The maximal accuracy of UP/DOWN edge of controls is:

IP5o Offset of IPP_DISP_CLK Todicp DISP_CLK_OFFSET

× Tdiclk

DISP_CLK_OFFSET—offset of

IPP_DISP_CLK edges from local start

point, in DI_CLK×2

(0.5 DI_CLK Resolution)

Defined by DISP_CLK counter

IP13o Offset of VSYNC Tovs VSYNC_OFFSET

× Tdiclk

VSYNC_OFFSET—offset of Vsync edges

from a local start point, when a Vsync

should be active, in DI_CLK×2

(0.5 DI_CLK Resolution).The

VSYNC_OFFSET should be built by

suitable DI’s counter.

IP8o Offset of HSYNC Tohs HSYNC_OFFSET

× Tdiclk

HSYNC_OFFSET—offset of Hsync edges

from a local start point, when a Hsync

should be active, in DI_CLK×2

(0.5 DI_CLK Resolution).The

HSYNC_OFFSET should be built by

suitable DI’s counter.

IP9o Offset of DRDY Todrdy DRDY_OFFSET

× Tdiclk

DRDY_OFFSET—offset of DRDY edges

from a suitable local start point, when a

corresponding data has been set on the

bus, in DI_CLK×2

(0.5 DI_CLK Resolution)

The DRDY_OFFSET should be built by

suitable DI’s counter.

1Display interface clock period immediate value.

DISP_CLK_PERIOD—number of DI_CLK per one Tdicp. Resolution 1/16 of DI_CLK.

DI_CLK_PERIOD—relation of between programing clock frequency and current system clock frequency

Display interface clock period average value.

2DI’s counter can define offset, period and UP/DOWN characteristic of output signal according to programed parameters of the

counter. Same of parameters in the table are not defined by DI’s registers directly (by name), but can be generated by

corresponding DI’s counter. The SCREEN_WIDTH is an input value for DI’s HSYNC generation counter. The distance

between HSYNCs is a SCREEN_WIDTH.

Table 60. Synchronous Display Interface Timing Characteristics (Pixel Level) (continued)

ID Parameter Symbol Value Description Unit

Tdicp

Tdiclk

DISP_CLK_PERIOD

DI_CLK_PERIOD

----------------------------------------------------

× for integer DISP_CLK_PERIOD

DI_CLK_PERIOD

----------------------------------------------------,

Tdiclk floor DISP_CLK_PERIOD

DI_CLK_PERIOD

---------------------------------------------------- 0.5 0.5±+





for fractional DISP_CLK_PERIOD

DI_CLK_PERIOD

----------------------------------------------------,











Tdicp Tdiclk

DISP_CLK_PERIOD

DI_CLK_PERIOD

----------------------------------------------------

×=

Accuracy 0.5 Tdiclk

×()0.62ns±=

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i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 91

The maximal accuracy of UP/DOWN edge of IPP_DATA is:

The DISP_CLK_PERIOD, DI_CLK_PERIOD parameters are programmed through the registers.

Figure 50 depicts the synchronous display interface timing for access level. The DISP_CLK_DOWN and

DISP_CLK_UP parameters are set through the Register. Table 61 lists the synchronous display interface

timing characteristics.

Figure 50. Synchronous Display Interface Timing Diagram—Access Level

Table 61. Synchronous Display Interface Timing Characteristics (Access Level)

ID Parameter Symbol Min Typ1

1The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display.

These conditions may be chip specific.

Max Unit

IP16 Display interface clock

low time

Tckl Tdicd-Tdicu-1.24 Tdicd2-Tdicu3Tdicd-Tdicu+1.24 ns

IP17 Display interface clock

high time

Tckh Tdicp-Tdicd+Tdicu-1.24 Tdicp-Tdicd+Tdicu Tdicp-Tdicd+Tdicu+1.2 ns

IP18 Data setup time Tdsu Tdicd-1.24 Tdicu — ns

IP19 Data holdup time Tdhd Tdicp-Tdicd-1.24 Tdicp-Tdicu — ns

IP20o Control signals offset

times (defines for each

pin)

Tocsu Tocsu-1.24 Tocsu Tocsu+1.24 ns

IP20 Control signals setup

time to display

interface clock

(defines for each pin)

Tcsu Tdicd-1.24-Tocsu%Tdicp Tdicu — ns

Accuracy Tdiclk 0.62ns±=

IP19 IP18

IP20

VSYNC

IP17IP16

DRDY

HSYNC

other controls

IP20o

local start point

Tdicd

Tdicu

IPP_DISP_CLK

IPP_DATA

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Electrical Characteristics

4.7.8.7 Interface to a TV Encoder (TVDAC)

The interface has an 8-bit data bus, transferring a single 8-bit value (Y/U/V) in each cycle. The timing of

the interface is described in Figure 51.

NOTE

• The frequency of the clock DISP_CLK is 27 MHz (within 10%)

• The HSYNC, VSYNC signals are active low.

• The DRDY signal is shown as active high.

• The transition to the next row is marked by the negative edge of the

HSYNC signal. It remains low for a single clock cycle.

• The transition to the next field/frame is marked by the negative edge of

the VSYNC signal. It remains low for at least one clock cycles.

— At a transition to an odd field (of the next frame), the negative edges

of VSYNC and HSYNC coincide.

— At a transition is to an even field (of the same frame), they do not

coincide.

• The active intervals—during which data is transferred—are marked by

the HSYNC signal being high.

2Display interface clock down time

3Display interface clock up time where CEIL(X) rounds the elements of X to the nearest integers towards infinity.

Tdicd 1

---T

diclk ceil×2 DISP_CLK_DOWN×

DI_CLK_PERIOD

-----------------------------------------------------------





Tdicu 1

---T

diclk ceil×2 DISP_CLK_UP×

DI_CLK_PERIOD

------------------------------------------------





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i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 93

Figure 51. TV Encoder Interface Timing Diagram

HSYNC

VSYNC

Cb Y CrCb Y Cr Y

Pixel Data Timing

Line and Field Timing - NTSC

Even Field Odd Field

Odd Field Even Field

624621

311308

Line and Field Timing - PAL

HSYNC

DRDY

VSYNC

HSYNC

DRDY

VSYNC

Even Field Odd Field

Odd Field Even Field

1523

262261

DRDY

HSYNC

DRDY

VSYNC

HSYNC

VSYNC

524 525 2 3 4 10

263 264 265 266 267 268 269 273

622 623 625 1 2 23

309 310 312 313 314 336

316315

DRDY

DISP_CLK

IPP_DATA

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94 Freescale Semiconductor

Electrical Characteristics

4.7.8.7.1 TVEv2 TV Encoder Performance Specifications

The TV encoder output specifications are shown in Table 62. All the parameters in the table are defined

under the following conditions:

•R

set = 1.05 kΩ±1%, resistor on TVDAC_VREF pin to GND

•R

load = 37.5 Ω±1%, output load to the GND

Table 62. TV Encoder Video Performance Specifications

Parameter Conditions Min Typ Max Unit

DAC STATIC PERFORMANCE

Resolution1——10—Bits

Integral Nonlinearity (INL)2— — 1 2 LSBs

Differential Nonlinearity (DNL) 2— — 0.6 1 LSBs

Channel-to-channel gain matching2——2—%

Full scale output voltage2Rset = 1.05 kΩ±1%

Rload = 37.5 Ω±1%

1.24 1.306 1.37 V

DAC DYNAMIC PERFORMANCE

Spurious Free Dynamic Range (SFDR) Fout = 3.38 MHz

Fsamp = 216 MHz

—59— dBc

Spurious Free Dynamic Range (SFDR) Fout = 8.3 MHz

Fsamp = 297 MHz

—54— dBc

VIDEO PERFORMANCE IN SD MODE2

Short Term Jitter (Line to Line) — — 2.5 — ±ns

Long Term Jitter (Field to Field) — — 3.5 — ±ns

Frequency Response 0–4.0 MHz -0.1 — 0.1 dB

5.75 MHz -0.7 — 0 dB

Luminance Nonlinearity — — 0.5 — ±%

Differential Gain — — 0.35 — %

Differential Phase — — 0.6 — Degrees

Signal-to-Noise Ratio (SNR) Flat field full bandwidth — 75 — dB

Hue Accuracy — — 0.8 — ±Degrees

Color Saturation Accuracy — — 1.5 — ±%

Chroma AM Noise — — -70 — dB

Chroma PM Noise — — -47 — dB

Chroma Nonlinear Phase — — 0.5 — ±Degrees

Chroma Nonlinear Gain — — 2.5 — ±%

Chroma/Luma Intermodulation — — 0.1 — ±%

Chroma/Luma Gain Inequality — — 1.0 — ±%

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4.7.8.8 Asynchronous Interfaces

The following sections describes the types of asynchronous interfaces.

4.7.8.8.1 Standard Parallel Interfaces

The IPU has four signal generator machines for asynchronous signal. Each machine generates IPU’s

internal control levels (0 or 1) by UP and DOWN that are defined in registers. Each asynchronous pin has

a dynamic connection with one of the signal generators. This connection is redefined again with a new

display access (pixel/component). The IPU can generate control signals according to system 80/68

requirements. The burst length is received as a result from predefined behavior of the internal signal

generator machines.

The access to a display is realized by the following:

• CS (IPP_CS) chip select

• WR (IPP_PIN_11) write strobe

• RD (IPP_PIN_12) read strobe

• RS (IPP_PIN_13) Register select (A0)

Both system 80 and system 68k interfaces are supported for all described modes as depicted in Figure 52,

Figure 53, Figure 54, and Figure 55. The timing images correspond to active-low IPP_CS, WR and RD

signals.

Each asynchronous access is defined by an access size parameter. This parameter can be different between

different kinds of accesses. This parameter defines a length of windows, when suitable controls of the

current access are valid. A pause between two different display accesses can be guaranteed by programing

suitable access sizes. There are no minimal/maximal hold/setup times hard defined by DI. Each control

signal can be switched at any time during access size.

Chroma/Luma Delay Inequality — — 1.0 — ±ns

VIDEO PERFORMANCE IN HD MODE2

Luma Frequency Response 0–30 MHz -0.2 — 0.2 dB

Chroma Frequency Response 0–15 MHz, YCbCr 422 mode -0.2 — 0.2 dB

Luma Nonlinearity — — 3.2 — %

Chroma Nonlinearity — — 3.4 — %

Luma Signal-to-Noise Ratio 0–30 MHz — 62 — dB

Chroma Signal-to-Noise Ratio 0–15 MHz — 72 — dB

1Guaranteed by design.

2Guaranteed by characterization.

Table 62. TV Encoder Video Performance Specifications (continued)

Parameter Conditions Min Typ Max Unit

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Figure 52. Asynchronous Parallel System 80 Interface (Type 1) Timing Diagram

Burst access mode with sampling by CS signal

Single access mode (all control signals are not active for one display interface clock after each display access)

IPP_CS

IPP_DATA

IPP_CS

IPP_DATA

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Freescale Semiconductor 97

Figure 53. Asynchronous Parallel System 80 Interface (Type 2) Timing Diagram

Burst access mode with sampling by WR/RD signals

Single access mode (all control signals are not active for one display interface clock after each display access)

IPP_CS

IPP_DATA

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Figure 54. Asynchronous Parallel System 68k Interface (Type 1) Timing Diagram

(READ/WRITE)

(ENABLE)

(READ/WRITE)

(ENABLE)

Burst access mode with sampling by CS signal

Single access mode (all control signals are not active for one display interface clock after each display access)

IPP_CS

IPP_DATA

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Freescale Semiconductor 99

Figure 55. Asynchronous Parallel System 68k Interface (Type 2) Timing Diagram

Display operation can be performed with IPP_WAIT signal. The DI reacts to the incoming IPP_WAIT

signal with 2 DI_CLK delay. The DI finishes a current access and a next access is postponed until

IPP_WAIT release. Figure 56 shows timing of the parallel interface with IPP_WAIT control.

(READ/WRITE)

(ENABLE)

(READ/WRITE)

(ENABLE)

Burst access mode with sampling by ENABLE signal

Single access mode (all control signals are not active for one display interface clock after each display access)

IPP_CS

IPP_DATA

IPP_CS

IPP_DATA

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Electrical Characteristics

Figure 56. Parallel Interface Timing Diagram—Read Wait States

4.7.8.8.2 Asynchronous Parallel Interface Timing Parameters

Figure 57 depicts timing of asynchronous parallel interfaces based on the system 80 and system 68k

interfaces. Table 64 shows timing characteristics at display access level. All timing diagrams are based

on active low control signals (signals polarity is controlled through the DI_DISP_SIG_POL register).

DI clock

IPP_DATA

IPP_WAIT

IPP_DATA_IN

waiting

IP39

IPP_CS

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Freescale Semiconductor 101

Figure 57. Asynchronous Parallel Interface Timing Diagram

Table 63. Asynchronous Display Interface Timing Parameters (Pixel Level)

ID Parameter Symbol Value Description Unit

IP28a Address Write system cycle time Tcycwa ACCESS_SIZE_# predefined value in DI REGISTER ns

IP28d Data Write system cycle time Tcycwd ACCESS_SIZE_# predefined value in DI REGISTER ns

IP29 RS start Tdcsrr UP# RS strobe switch, predefined value

in DI REGISTER

IP30 CS start Tdcsc UP# CS strobe switch, predefined value

in DI REGISTER

IP31 CS hold Tdchc DOWN# CS strobe release, predefined

value in DI REGISTER

—

IP32 RS hold Tdchrr DOWN# RS strobe release, predefined

value in DI REGISTER

—

IP35 Write start Tdcsw UP# write strobe switch, predefined

value in DI REGISTER

IP36 Controls hold time for write Tdchw DOWN# write strobe release, predefined

value in DI REGISTER

DI clock

A0 D0 D1

PP_DATA_IN D2 D3

local start point

IP27

IP28d

IP28a

local start point

IP37

IP33

IP35

IP38

IP34

IP36

IP29

IP31

IP32

IP47 IP30

IPP_CS

IPP_DATA

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Table 64. Asynchronous Parallel Interface Timing Parameters (Access Level)

ID Parameter Symbol Min Typ1

1The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display.

These conditions may be chip specific.

Max Unit

IP28 Write system cycle time Tcycw Tdicpw - 1.24 Tdicpw2

2Display period value for write

ACCESS_SIZE is predefined in REGISTER.

Tdicpw+1.24 ns

IP29 RS start Tdcsrr Tdicurs - 1.24 Tdicurs Tdicurs+1.24 ns

IP30 CS start Tdcsc Tdicucs - 1.24 Tdicur Tdicucs+1.24 ns

IP31 CS hold Tdchc Tdicdcs - Tdicucs - 1.24 Tdicdcs3-Tdicucs4

3Display control down for CS

DISP_DOWN is predefined in REGISTER.

4Display control up for CS

DISP_UP is predefined in REGISTER.

Tdicdcs - Tdicucs+1.24 ns

IP32 RS hold Tdchrr Tdicdrs - Tdicurs - 1.24 Tdicdrs5-Tdicurs6

5Display control down for RS

DISP_DOWN is predefined in REGISTER.

6Display control up for RS

DISP_UP is predefined in REGISTER.

Tdicdrs - Tdicurs+1.24 ns

IP35 Controls setup time for

write

Tdcsw Tdicuw - 1.24 Tdicuw Tdicuw+1.24 ns

IP36 Controls hold time for

write

Tdchw Tdicdw - Tdicuw - 1.24 Tdicpw7-Tdicuw8Tdicdw-Tdicuw+1.24 ns

IP38 Slave device data hold

time8

Troh Tdrp - Tlbd - Tdicdr+1.2

— Tdicpr-Tdicdr-1.24 ns

Tdicpw TDI_CLK ceil×

DI_ACCESS_SIZE_#

DI_CLK_PERIOD

-----------------------------------------------------

Tdicdcs 1

---T

DI_CLK ceil×2 DISP_DOWN_#×

DI_CLK_PERIOD

--------------------------------------------------





Tdicucs 1

---T

DI_CLK ceil×2 DISP_UP_#×

DI_CLK_PERIOD

----------------------------------------------





Tdicdrs 1

---T

DI_CLK ceil×2 DISP_DOWN_#×

DI_CLK_PERIOD

--------------------------------------------------





Tdicurs 1

---T

DI_CLK ceil×2DISP_UP_#×

DI_CLK_PERIOD

----------------------------------------------





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4.7.9 LVDS Display Bridge (LDB) Module Parameters

The LVDS interface complies with TIA/EIA 644-A standard. For more details, see TIA/EIA STANDARD

644-A, “Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits”.

4.7.10 One-Wire (OWIRE) Timing Parameters

Figure 58 depicts the RPP timing, and Table 65 lists the RPP timing parameters.

Figure 58. Reset and Presence Pulses (RPP) Timing Diagram

7Display control down for read

DISP_DOWN is predefined in REGISTER.

8Display control up for write

DISP_UP is predefined in REGISTER.

Table 65. RPP Sequence Delay Comparisons Timing Parameters

ID Parameters Symbol Min Typ Max Unit

OW1 Reset Time Low tRSTL 480 511 —1

1In order not to mask signaling by other devices on the 1-Wire bus, tRSTL + tR should always be less than 960 µs.

µs

OW2 Presence Detect High tPDH 15 — 60 µs

OW3 Presence Detect Low tPDL 60 — 240 µs

OW4 Reset Time High

(includes recovery time)

tRSTH 480 512 — µs

Tdicdrw 1

---T

DI_CLK ceil×2 DISP_DOWN_#×

DI_CLK_PERIOD

--------------------------------------------------





Tdicuw 1

---T

DI_CLK ceil×2DISP_UP_#×

DI_CLK_PERIOD

----------------------------------------------





One-Wire bus

One Wire Device Tx

“Presence Pulse”

(BATT_LINE)

One-WIRE Tx

“Reset Pulse”

OW1

OW2

OW3

OW4

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Electrical Characteristics

Figure 59 depicts Write 0 Sequence timing, and Table 66 lists the timing parameters.

Figure 59. Write 0 Sequence Timing Diagram

Figure 60 depicts Write 1 Sequence timing, Figure 61 depicts the Read Sequence timing, and Table 67

lists the timing parameters.

Figure 60. Write 1 Sequence Timing Diagram

Figure 61. Read Sequence Timing Diagram

Table 66. WR0 Sequence Timing Parameters

ID Parameter Symbol Min Typ Max Unit

OW5 Write 0 Low Time tLOW0 60 100 120 µs

OW6 Transmission Time Slot tSLOT OW5 117 120 µs

Recovery time tREC 1——µs

OW5

OW6

One-Wire bus

(BATT_LINE)

tREC

OW7

OW8

One-Wire bus

(BATT_LINE)

tSU

OW8

OW10

One-Wire bus

(BATT_LINE)

OW9 OW11

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4.7.11 Pulse Width Modulator (PWM) Timing Parameters

This section describes the electrical information of the PWM. The PWM can be programmed to select one

of three clock signals as its source frequency. The selected clock signal is passed through a prescaler before

being input to the counter. The output is available at the pulse-width modulator output (PWMO) external

pin.

Figure 62 depicts the timing of the PWM, and Table 68 lists the PWM timing parameters.

Figure 62. PWM Timing

Table 67. WR1 /RD Timing Parameters

ID Parameter Symbol Min Typ Max Unit

OW7 Write 1 Low Time tLOW1 1 5 15 µs

OW8 Transmission Time Slot tSLOT 60 117 120 µs

Read Data Setup tSU ——1µs

OW9 Read Low Time tLOWR 1 5 15 µs

OW10 Read Data Valid tRDV —15—µs

OW11 Release Time tRELEASE 0 — 45 µs

Table 68. PWM Output Timing Parameter

Ref. No. Parameter Min Max Unit

1 System CLK frequency1

1CL of PWMO = 30 pF

0 ipg_clk MHz

2a Clock high time 12.29 — ns

2b Clock low time 9.91 — ns

3a Clock fall time — 0.5 ns

3b Clock rise time — 0.5 ns

4a Output delay time — 9.37 ns

4b Output setup time 8.71 — ns

System Clock

2a 1

PWM Output

3a 4b

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Electrical Characteristics

4.7.12 PATA Timing Parameters

This section describes the timing parameters of the Parallel ATA module which are compliant with

ATA/ATAPI-6 specification.

Parallel ATA module can work on PIO/Multi-Word DMA/Ultra DMA transfer modes. Each transfer mode

has different data transfer rate, Ultra DMA mode 4 data transfer rate is up to 100MB/s. Parallel ATA

module interface consist of a total of 29 pins. Some pins act on different function in different transfer

mode. There are different requirements of timing relationships among the function pins conform with

ATA/ATAPI-6 specification and these requirements are configurable by the ATA module registers.

Table 69 and Figure 63 define the AC characteristics of all the PATA interface signals in all data transfer

modes.

Figure 63. PATA Interface Signals Timing Diagram

The user must use level shifters for 5.0 V compatibility on the ATA interface. The i.MX53 PATA interface

is 3.3 V compatible.

The use of bus buffers introduces delay on the bus and skew between signal lines. These factors make it

difficult to operate the bus at the highest speed (UDMA-5) when bus buffers are used. If fast UDMA mode

operation is needed, this may not be compatible with bus buffers.

Another area of attention is the slew rate limit imposed by the ATA specification on the ATA bus.

According to this limit, any signal driven on the bus should have a slew rate between 0.4 and 1.2 V/ns with

a 40 pF load. Not many vendors of bus buffers specify slew rate of the outgoing signals.

When bus buffers are used, the ata_data bus buffer is special. This is a bidirectional bus buffer, so a

direction control signal is needed. This direction control signal is ata_buffer_en. When its high, the bus

should drive from host to device. When its low, the bus should drive from device to host. Steering of the

signal is such that contention on the host and device tri-state busses is always avoided.

Table 69. AC Characteristics of All Interface Signals

ID Parameter Symbol Min Max Unit

SI1 Rising edge slew rate for any signal on ATA interface1

1SRISE and SFALL shall meet this requirement when measured at the sender’s connector from 10–90% of full signal

amplitude with all capacitive loads from 15–40 pF where all signals have the same capacitive load value.

Srise —1.25V/ns

SI2 Falling edge slew rate for any signal on ATA interface1Sfall —1.25V/ns

SI3 Host interface signal capacitance at the host connector Chost —20pF

ATA Interface Signals

SI1SI2

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In the timing equations, some timing parameters are used. These parameters depend on the

implementation of the i.MX53 PATA interface on silicon, the bus buffer used, the cable delay and cable

skew. Table 70 shows ATA timing parameters.

Table 70. PATA Timing Parameters

Name Description Value/

Contributing Factor1

1Values provided where applicable.

T Bus clock period (AHB_CLK_ROOT) Peripheral clock frequency

(7.5 ns for 133 MHz clock)

ti_ds Set-up time ata_data to ata_iordy edge (UDMA-in only)

UDMA0

UDMA1

UDMA2, UDMA3

UDMA4

UDMA5

15 ns

10 ns

7 ns

5 ns

4 ns

ti_dh Hold time ata_iordy edge to ata_data (UDMA-in only)

UDMA0, UDMA1, UDMA2, UDMA3, UDMA4

UDMA5

5.0 ns

4.6 ns

tco Propagation delay bus clock L-to-H to

ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack,

ata_data, ata_buffer_en

12.0 ns

tsu Set-up time ata_data to bus clock L-to-H 8.5 ns

tsui Set-up time ata_iordy to bus clock H-to-L 8.5 ns

thi Hold time ata_iordy to bus clock H to L 2.5 ns

tskew1 Max difference in propagation delay bus clock L-to-H to any of following signals

ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack,

ata_data (write), ata_buffer_en

7ns

tskew2 Max difference in buffer propagation delay for any of following signals:

ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack,

ata_data (write), ata_buffer_en

Transceiver

tskew3 Max difference in buffer propagation delay for any of following signals ata_iordy,

ata_data (read)

Transceiver

tbuf Max buffer propagation delay Transceiver

tcable1 Cable propagation delay for ata_data Cable

tcable2 Cable propagation delay for control signals ata_dior, ata_diow, ata_iordy,

ata_dmack

Cable

tskew4 Max difference in cable propagation delay between ata_iordy and ata_data (read) Cable

tskew5 Max difference in cable propagation delay between (ata_dior, ata_diow,

ata_dmack) and ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_data(write)

Cable

tskew6 Max difference in cable propagation delay without accounting for ground bounce Cable

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Electrical Characteristics

4.7.12.1 PIO Mode Read Timing

Figure 64 shows timing for PIO read. Table 71 lists the timing parameters for PIO read.

Figure 64. PIO Read Timing Diagram

Table 71. PIO Read Timing Parameters

ATA

Parameter

from Figure 64 Value Controlling

Variable

t1 t1 t1(min) = time_1 x T - (tskew1 + tskew2 + tskew5) time_1

t2 (read) t2r t2(min) = time_2r x T - (tskew1 + tskew2 + tskew5) time_2r

t9 t9 t9(min) = time_9 x T - (tskew1 + tskew2 + tskew6) time_9

t5 t5 t5(min) = tco + tsu + tbuf + tbuf+ tcable1 + tcable2 time_2 (affects tsu and

tco)

t6 t6 0 —

tA tA tA(min) = (1.5 + time_ax) x T - (tco + tsui + tcable2 + tcable2 + 2 x tbuf) time_ax

trd trd1 trd1(max) = (-trd)+ (tskew3 + tskew4)

trd1(min) = (time_pio_rdx - 0.5) x T - (tsu + thi)

(time_pio_rdx - 0.5) x T > tsu + thi + tskew3 + tskew4

time_pio_rdx

t0 — t0(min) = (time_1 + time_2r+ time_9) x T time_1, time_2r, time_9

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Figure 65 shows timing for PIO write. Table 72 lists the timing parameters for PIO write.

Figure 65. Multi-word DMA (MDMA) Timing

Table 72. PIO Write Timing Parameters

ATA

Paramete

Parameter

from Figure 65 Value Controlling

Variable

t1 t1 t1(min) = time_1 x T - (tskew1 + tskew2 + tskew5) time_1

t2 (write) t2w t2(min) = time_2w x T - (tskew1 + tskew2 + tskew5) time_2w

t9 t9 t9(min) = time_9 x T - (tskew1 + tskew2 + tskew6) time_9

t3 — t3(min) = (time_2w - time_on) x T - (tskew1 + tskew2 +tskew5) If not met, increase

time_2w

t4 t4 t4(min) = time_4 x T - tskew1 time_4

tA tA tA = (1.5 + time_ax) x T - (tco + tsui + tcable2 + tcable2 + 2 x tbuf) time_ax

t0 — t0(min) = (time_1 + time_2 + time_9) x T time_1, time_2r,

time_9

— — Avoid bus contention when switching buffer on by making ton long enough —

— — Avoid bus contention when switching buffer off by making toff long enough —

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Electrical Characteristics

Figure 66 shows timing for MDMA read, Figure 67 shows timing for MDMA write, and Table 73 lists

the timing parameters for MDMA read and write.

Figure 66. MDMA Read Timing Diagram

Figure 67. MDMA Write Timing Diagram

Table 73. MDMA Read and Write Timing Parameters

ATA

Parameter

Parameter from

Figure 66 (Read),

Figure 67 (Write)

Value Controlling

Variable

tm, ti tm tm(min) = ti(min) = time_m x T - (tskew1 + tskew2 + tskew5) time_m

td td, td1 td1(min) = td(min) = time_d x T - (tskew1 + tskew2 + tskew6) time_d

tk tk1tk(min) = time_k x T - (tskew1 + tskew2 + tskew6) time_k

t0 — t0(min) = (time_d + time_k) x T time_d, time_k

tg(read) tgr tgr(min-read) = tco + tsu + tbuf + tbuf + tcable1 + tcable2

tgr(min-drive) = td - te(drive)

time_d

tf(read) tfr tfr(min) = 5 ns —

tg(write) — tg(min-write) = time_d x T - (tskew1 + tskew2 + tskew5) time_d

tf(write) — tf(min-write) = time_k x T - (tskew1 + tskew2 + tskew6) time_k

tL — tL (max) = (time_d + time_k - 2)×T - (tsu + tco + 2×tbuf + 2×tcable2) time_d,

time_k2

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4.7.12.2 Ultra DMA (UDMA) Input Timing

Figure 68 shows timing when the UDMA in transfer starts, Figure 69 shows timing when the UDMA in

host terminates transfer, Figure 70 shows timing when the UDMA in device terminates transfer, and

Table 74 lists the timing parameters for UDMA in burst.

Figure 68. UDMA in Transfer Starts Timing Diagram

tn, tj tkjn tn= tj= tkjn = time_jn x T - (tskew1 + tskew2 + tskew6) time_jn

—ton

toff

ton = time_on × T - tskew1

toff = time_off × T - tskew1

—

1tk1 in the MDMA figures (Figure 66 and Figure 67) equals (tk - 2 x T).

2tk1 in the MDMA figures equals (tk – 2 x T).

Table 73. MDMA Read and Write Timing Parameters (continued)

ATA

Parameter

Parameter from

Figure 66 (Read),

Figure 67 (Write)

Value Controlling

Variable

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Electrical Characteristics

Figure 69. UDMA in Host Terminates Transfer Timing Diagram

Figure 70. UDMA in Device Terminates Transfer Timing Diagram

Table 74. UDMA in Burst Timing Parameters

ATA

Parameter

from

Figure 68,

Figure 69, and

Figure 70

Description Controlling Variable

tack tack tack (min) = (time_ack × T) - (tskew1 + tskew2) time_ack

tenv tenv tenv (min) = (time_env × T) - (tskew1 + tskew2)

tenv (max) = (time_env × T) + (tskew1 + tskew2)

time_env

tds tds1 tds - (tskew3) - ti_ds > 0 tskew3, ti_ds, ti_dh

should be low enough

tdh tdh1 tdh - (tskew3) - ti_dh > 0

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4.7.12.3 UDMA Output Timing

Figure 71 shows timing when the UDMA out transfer starts, Figure 72 shows timing when the UDMA out

host terminates transfer, Figure 73 shows timing when the UDMA out device terminates transfer, and

Table 75 lists the timing parameters for UDMA out burst.

Figure 71. UDMA Out Transfer Starts Timing Diagram

tcyc tc1 (tcyc - tskew) > T T big enough

trp trp trp (min) = time_rp × T - (tskew1 + tskew2 + tskew6) time_rp

—tx1

1(time_rp × T) - (tco + tsu + 3T + 2 ×tbuf + 2×tcable2) > trfs (drive) time_rp

tmli tmli1 tmli1 (min) = (time_mlix + 0.4) × T time_mlix

tzah tzah tzah (min) = (time_zah + 0.4) × T time_zah

tdzfs tdzfs tdzfs = (time_dzfs × T) - (tskew1 + tskew2) time_dzfs

tcvh tcvh tcvh = (time_cvh ×T) - (tskew1 + tskew2) time_cvh

—ton

toff2

ton = time_on × T - tskew1

toff = time_off × T - tskew1

—

1There is a special timing requirement in the ATA host that requires the internal DIOW to go only high 3 clocks after the last

active edge on the DSTROBE signal. The equation given on this line tries to capture this constraint.

2Make ton and toff big enough to avoid bus contention.

Table 74. UDMA in Burst Timing Parameters (continued)

ATA

Parameter

from

Figure 68,

Figure 69, and

Figure 70

Description Controlling Variable

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Electrical Characteristics

Figure 72. UDMA Out Host Terminates Transfer Timing Diagram

Figure 73. UDMA Out Device Terminates Transfer Timing Diagram

Table 75. UDMA Out Burst Timing Parameters

ATA

Parameter

from

Figure 71,

Figure 72,

Figure 73

Value Controlling

Variable

tack tack tack (min) = (time_ack × T) - (tskew1 + tskew2) time_ack

tenv tenv tenv (min) = (time_env × T) - (tskew1 + tskew2)

tenv (max) = (time_env × T) + (tskew1 + tskew2)

time_env

tdvs tdvs tdvs = (time_dvs × T) - (tskew1 + tskew2) time_dvs

tdvh tdvh tdvs = (time_dvh × T) - (tskew1 + tskew2) time_dvh

tcyc tcyc tcyc = time_cyc × T - (tskew1 + tskew2) time_cyc

t2cyc — t2cyc = time_cyc × 2 × T time_cyc

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4.7.13 SATA PHY Parameters

This section describes SATA PHY electrical specifications.

4.7.13.1 Reference Clock Electrical and Jitter Specifications

The refclk signal is differential and supports frequencies of 25 MHz or 50-156.25 MHz (100 MHz and

125 MHz are common frequencies). The frequency is pin-selectable (for more information about the

signal, see “Per-Transceiver Control and Status Signals” in the SATA PHY chapter in the Reference

Manual).

Table 76 provides the SATA PHY reference clock specifications.

trfs1 trfs trfs = 1.6 × T + tsui + tco + tbuf + tbuf —

— tdzfs tdzfs = time_dzfs × T - (tskew1) time_dzfs

tss tss tss = time_ss × T - (tskew1 + tskew2) time_ss

tmli tdzfs_mli tdzfs_mli =max (time_dzfs, time_mli) × T - (tskew1 + tskew2) —

tli tli1 tli1 > 0 —

tli tli2 tli2 > 0 —

tli tli3 tli3 > 0 —

tcvh tcvh tcvh = (time_cvh ×T) - (tskew1 + tskew2) time_cvh

—ton

toff

ton = time_on × T - tskew1

toff = time_off × T - tskew1

—

Table 76. Reference Clock Specifications

Parameters Test Conditions Min Max Unit

Differential peak voltage (typically 0.71 V) — 350 850 mV

Common mode voltage

(refclk_p + refclk_m) / 2

— 175 2,000 mV

Total phase jitter For information about total

phase jitter, see following

section

—3ps RMS

Minimum/maximum duty cycle — 40 60 % UI

Frequency range — 25 156.25 MHz

Table 75. UDMA Out Burst Timing Parameters (continued)

ATA

Parameter

from

Figure 71,

Figure 72,

Figure 73

Value Controlling

Variable

i.MX53 Applications Processors for Industrial Products, Rev. 7

116 Freescale Semiconductor

Electrical Characteristics

4.7.13.1.1 Reference Clock Jitter Measurement

The total phase jitter on the reference clock is specified at 3 ps RMS. There are numerous ways to measure

the reference clock jitter, one of which is as follows.

Using a high-speed sampling scope (20 GSamples/s), 1 million samples of the differential reference clock

are taken, and the zero-crossing times of each rising edge are calculated. From the zero-crossing data, an

average reference clock period is calculated. This average reference clock period is subtracted from each

sequential, instantaneous period to find the difference between each reference clock rising edge and the

ideal placement to produce the phase jitter sequence. The power spectral density (PSD) of the phase jitter

is calculated and integrated after being weighted with the transfer function shown in Figure 74. The square

root of the resultant integral is the RMS total phase jitter.

Figure 74. Weighting Function for RMS Phase Jitter Calculation

4.7.13.2 Transmitter and Receiver Characteristics

The SATA PHY meets or exceeds the electrical compliance requirements defined in the SATA

specification. The following subsections provide values obtained from a combination of simulations and

silicon characterization.

NOTE

The tables in the following sections indicate any exceptions to the SATA

specification or aspects of the SATA PHY that exceed the standard, as well

as provide information about parameters not defined in the standard.

4.7.13.2.1 SATA PHY Transmitter Characteristics

Table 77 provides specifications for SATA PHY transmitter characteristics.

Table 77. SATA2 PHY Transmitter Characteristics

Parameters Symbol Min Typ Max Unit

Transmit common mode voltage VCTM 0.4 — 0.6 V

Transmitter pre-emphasis accuracy (measured

change in de-emphasized bit)

— -0.5 — 0.5 dB

Electrical Characteristics

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 117

4.7.13.2.2 SATA PHY Receiver Characteristics

Table 78 provides specifications for SATA PHY receiver characteristics.

4.7.13.3 SATA_REXT Reference Resistor Connection

The impedance calibration process requires connection of reference resistor 191 Ω.1% precision resistor

on SATA_REXT pad to ground.

Resistor calibration consists of learning which state of the internal Resistor Calibration register causes an

internal, digitally trimmed calibration resistor to best match the impedance applied to the SATA_REXT

pin. The calibration register value is then supplied to all Tx and Rx termination resistors.

During the calibration process (for a few tens of microseconds), up to 0.3 mW can be dissipated in the

external SATA_REXT resistor. At other times, no power is dissipated by the SATA_REXT resistor.

4.7.13.4 SATA Connectivity When Not in Use

NOTE

The Temperature Sensor is part of the SATA module. If SATA IP is disabled,

the Temperature Sensor will not work as well. Temperature Sensor

functionality is important in supporting high performance applications

without overheating the device (at high ambient temp).

When both SATA and thermal sensor are not required, connect VP and VPH supplies to ground. The rest

of the ports, both inputs and outputs (SATA_REFCLKM, SATA_REFCLKP, SATA_REXT, SATA_RXM,

SATA_RXP, SATA_TXM) can be left floating. It is not recommended to turn off the VPH while the VP is

active.

When SATA is not in use but thermal sensor is still required, both VP and VPH supplies must be powered

on according to their nominal voltage levels. The reference clock input frequency must fall within the

specified range of 25 MHz to 156.25 MHz. SATA_REXT does not need to be connected, as the

termination impedance is not of consequence.

Table 78. SATA PHY Receiver Characteristics

Parameters Symbol Min Typ Max Unit

Minimum Rx eye height (differential

peak-to-peak)

VMIN_RX_EYE_HEIGHT — — 175 mV

Tolerance PPM -400 — 400 ppm

i.MX53 Applications Processors for Industrial Products, Rev. 7

118 Freescale Semiconductor

Electrical Characteristics

4.7.14 SCAN JTAG Controller (SJC) Timing Parameters

Figure 75 depicts the SJC test clock input timing. Figure 76 depicts the SJC boundary scan timing.

Figure 77 depicts the SJC test access port. Signal parameters are listed in Table 79.

Figure 75. Test Clock Input Timing Diagram

Figure 76. Boundary Scan (JTAG) Timing Diagram

TCK

(Input) VM VM

VIH

VIL

SJ1

SJ2 SJ2

SJ3

TCK

(Input)

Data

Inputs

Data

Outputs

Data

Outputs

Data

Outputs

VIH

VIL

Input Data Valid

Output Data Valid

SJ4 SJ5

SJ6

SJ7

SJ6

Electrical Characteristics

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 119

Figure 77. Test Access Port Timing Diagram

Figure 78. TRST Timing Diagram

Table 79. JTAG Timing

ID Parameter1,2

All Frequencies

Unit

Min Max

SJ0 TCK frequency of operation 1/(3•TDC)10.001 22 MHz

SJ1 TCK cycle time in crystal mode 45 — ns

SJ2 TCK clock pulse width measured at VM222.5 — ns

SJ3 TCK rise and fall times — 3 ns

SJ4 Boundary scan input data set-up time 5 — ns

SJ5 Boundary scan input data hold time 24 — ns

SJ6 TCK low to output data valid — 40 ns

SJ7 TCK low to output high impedance — 40 ns

SJ8 TMS, TDI data set-up time 5 — ns

TCK

(Input)

TDI

(Input)

TDO

(Output)

TDO

(Output)

TDO

(Output)

VIH

VIL

Input Data Valid

Output Data Valid

TMS

SJ8 SJ9

SJ10

SJ11

SJ10

TCK

(Input)

TRST

(Input)

SJ13

SJ12

i.MX53 Applications Processors for Industrial Products, Rev. 7

120 Freescale Semiconductor

Electrical Characteristics

4.7.15 SPDIF Timing Parameters

The Sony/Philips Digital Interconnect Format (SPDIF) data is sent using the bi-phase marking code. When

encoding, the SPDIF data signal is modulated by a clock that is twice the bit rate of the data signal.

Table 80 and Figures , show SPDIF timing parameters for the Sony/Philips Digital Interconnect Format

(SPDIF), including the timing of the modulating Rx clock (SRCK) for SPDIF in Rx mode and the timing

of the modulating Tx clock (STCLK) for SPDIF in Tx mode.

SJ9 TMS, TDI data hold time 25 — ns

SJ10 TCK low to TDO data valid — 44 ns

SJ11 TCK low to TDO high impedance — 44 ns

SJ12 TRST assert time 100 — ns

SJ13 TRST set-up time to TCK low 40 — ns

1TDC = target frequency of SJC

2VM = mid-point voltage

Table 80. SPDIF Timing Parameters

Characteristics Symbol

Timing Parameter Range

Units

Min Max

SPDIFIN Skew: asynchronous inputs, no specs apply — — 0.7 ns

SPDIFOUT output (Load = 50pf)

• Skew

• Transition rising

• Transition falling

—

1.5

24.2

31.3

SPDIFOUT1 output (Load = 30pf)

• Skew

• Transition rising

• Transition falling

—

1.5

13.6

18.0

Modulating Rx clock (SRCK) period srckp 40.0 — ns

SRCK high period srckph 16.0 — ns

SRCK low period srckpl 16.0 — ns

Modulating Tx clock (STCLK) period stclkp 40.0 — ns

STCLK high period stclkph 16.0 — ns

STCLK low period stclkpl 16.0 — ns

Table 79. JTAG Timing (continued)

ID Parameter1,2

All Frequencies

Unit

Min Max

Electrical Characteristics

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 121

Figure 79. SPDIF Timing Diagram

Figure 80. STCLK Timing

4.7.16 SSI Timing Parameters

This section describes the timing parameters of the SSI module. The connectivity of the serial

synchronous interfaces are summarized in Table 81.

NOTE

• The terms WL and BL used in the timing diagrams and tables refer to

Word Length (WL) and Bit Length (BL).

• The SSI timing diagrams use generic signal names wherein the names

used in the i.MX53 Reference Manual are channel specific signal

names. For example, a channel clock referenced in the IOMUXC

chapter as AUD3_TXC appears in the timing diagram as TXC.

Table 81. AUDMUX Port Allocation

Port Signal Nomenclature Type and Access

AUDMUX port 1 SSI 1 Internal

AUDMUX port 2 SSI 2 Internal

AUDMUX port 3 AUD3 External— AUD3 I/O

AUDMUX port 4 AUD4 External— EIM or CSPI1 I/O through IOMUXC

AUDMUX port 5 AUD5 External— EIM or SD1 I/O through IOMUXC

AUDMUX port 6 AUD6 External— EIM or DISP2 through IOMUXC

AUDMUX port 7 SSI 3 Internal

SRCK

(Output)

VMVM

srckp

srckph

srckpl

STCLK

(Input)

VMVM

stclkp

stclkph

stclkpl

i.MX53 Applications Processors for Industrial Products, Rev. 7

122 Freescale Semiconductor

Electrical Characteristics

4.7.16.1 SSI Transmitter Timing with Internal Clock

Figure 81 depicts the SSI transmitter internal clock timing and Table 82 lists the timing parameters for the

SSI transmitter internal clock.

Figure 81. SSI Transmitter Internal Clock Timing Diagram

Table 82. SSI Transmitter Timing with Internal Clock

ID Parameter Min Max Unit

Internal Clock Operation

SS1 (Tx/Rx) CK clock period 81.4 — ns

SS2 (Tx/Rx) CK clock high period 36.0 — ns

SS3 (Tx/Rx) CK clock rise time — 6.0 ns

SS4 (Tx/Rx) CK clock low period 36.0 — ns

SS5 (Tx/Rx) CK clock fall time — 6.0 ns

SS6 (Tx) CK high to FS (bl) high — 15.0 ns

SS8 (Tx) CK high to FS (bl) low — 15.0 ns

SS10 (Tx) CK high to FS (wl) high — 15.0 ns

SS12 (Tx) CK high to FS (wl) low — 15.0 ns

SS14 (Tx/Rx) Internal FS rise time — 6.0 ns

SS15 (Tx/Rx) Internal FS fall time — 6.0 ns

SS16 (Tx) CK high to STXD valid from high impedance — 15.0 ns

SS19

SS1

SS2 SS4

SS3

SS5

SS6 SS8

SS10 SS12

SS14

SS18

SS15

SS17

SS16

SS43

SS42

Note: SRXD input in synchronous mode only

TXC

TXFS (wl)

(Output)

TXFS (bl)

(Output)

RXD

(Input)

TXD

(Output)

: SRXD input in synchronous mode only

Electrical Characteristics

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 123

NOTE

• All the timings for the SSI are given for a non-inverted serial clock

polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync

(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have

been inverted, all the timing remains valid by inverting the clock signal

STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables

and in the figures.

• All timings are on Audiomux Pads when SSI is being used for data

transfer.

• The terms WL and BL refer to Word Length (WL) and Bit Length (BL).

• “Tx” and “Rx” refer to the Transmit and Receive sections of the SSI.

• For internal Frame Sync operation using external clock, the FS timing is

same as that of Tx Data (for example, during AC97 mode of operation).

SS17 (Tx) CK high to STXD high/low — 15.0 ns

SS18 (Tx) CK high to STXD high impedance — 15.0 ns

SS19 STXD rise/fall time — 6.0 ns

Synchronous Internal Clock Operation

SS42 SRXD setup before (Tx) CK falling 10.0 — ns

SS43 SRXD hold after (Tx) CK falling 0.0 — ns

SS52 Loading — 25.0 pF

Table 82. SSI Transmitter Timing with Internal Clock (continued)

ID Parameter Min Max Unit

i.MX53 Applications Processors for Industrial Products, Rev. 7

124 Freescale Semiconductor

Electrical Characteristics

4.7.16.2 SSI Receiver Timing with Internal Clock

Figure 82 depicts the SSI receiver internal clock timing and Table 83 lists the timing parameters for the

receiver timing with the internal clock

Figure 82. SSI Receiver Internal Clock Timing Diagram

Table 83. SSI Receiver Timing with Internal Clock

ID Parameter Min Max Unit

Internal Clock Operation

SS1 (Tx/Rx) CK clock period 81.4 — ns

SS2 (Tx/Rx) CK clock high period 36.0 — ns

SS3 (Tx/Rx) CK clock rise time — 6.0 ns

SS4 (Tx/Rx) CK clock low period 36.0 — ns

SS5 (Tx/Rx) CK clock fall time — 6.0 ns

SS7 (Rx) CK high to FS (bl) high — 15.0 ns

SS9 (Rx) CK high to FS (bl) low — 15.0 ns

SS11 (Rx) CK high to FS (wl) high — 15.0 ns

SS13 (Rx) CK high to FS (wl) low — 15.0 ns

SS20 SRXD setup time before (Rx) CK low 10.0 — ns

SS21 SRXD hold time after (Rx) CK low 0.0 — ns

SS50

SS48

SS1

SS4SS2

SS51

SS20

SS21

SS49

SS7 SS9

SS11 SS13

SS47

SS3

SS5

TXC

(Output)

TXFS (bl)

(Output)

TXFS (wl)

(Output)

RXD

(Input)

RXC

(Output)

Electrical Characteristics

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 125

NOTE

• All the timings for the SSI are given for a non-inverted serial clock

polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync

(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have

been inverted, all the timing remains valid by inverting the clock signal

STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables

and in the figures.

• All timings are on Audiomux Pads when SSI is being used for data

transfer.

• “Tx” and “Rx” refer to the Transmit and Receive sections of the SSI.

• The terms WL and BL refer to Word Length (WL) and Bit Length (BL).

• For internal Frame Sync operation using external clock, the FS timing is

same as that of Tx Data (for example, during AC97 mode of operation).

Oversampling Clock Operation

SS47 Oversampling clock period 15.04 — ns

SS48 Oversampling clock high period 6.0 — ns

SS49 Oversampling clock rise time — 3.0 ns

SS50 Oversampling clock low period 6.0 — ns

SS51 Oversampling clock fall time — 3.0 ns

Table 83. SSI Receiver Timing with Internal Clock (continued)

ID Parameter Min Max Unit

i.MX53 Applications Processors for Industrial Products, Rev. 7

126 Freescale Semiconductor

Electrical Characteristics

4.7.16.3 SSI Transmitter Timing with External Clock

Figure 83 depicts the SSI transmitter external clock timing and Table 84 lists the timing parameters for

the transmitter timing with the external clock

Figure 83. SSI Transmitter External Clock Timing Diagram

Table 84. SSI Transmitter Timing with External Clock

ID Parameter Min Max Unit

External Clock Operation

SS22 (Tx/Rx) CK clock period 81.4 — ns

SS23 (Tx/Rx) CK clock high period 36.0 — ns

SS24 (Tx/Rx) CK clock rise time — 6.0 ns

SS25 (Tx/Rx) CK clock low period 36.0 — ns

SS26 (Tx/Rx) CK clock fall time — 6.0 ns

SS27 (Tx) CK high to FS (bl) high -10.0 15.0 ns

SS29 (Tx) CK high to FS (bl) low 10.0 — ns

SS31 (Tx) CK high to FS (wl) high -10.0 15.0 ns

SS33 (Tx) CK high to FS (wl) low 10.0 — ns

SS37 (Tx) CK high to STXD valid from high impedance — 15.0 ns

SS38 (Tx) CK high to STXD high/low — 15.0 ns

SS45

SS33

SS24

SS26

SS25

SS23

Note: SRXD Input in Synchronous mode only

SS31

SS29

SS27

SS22

SS44

SS39

SS38

SS37

SS46

TXC

(Input)

TXFS (bl)

(Input)

TXFS (wl)

(Input)

TXD

(Output)

RXD

(Input)

Electrical Characteristics

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 127

NOTE

• All the timings for the SSI are given for a non-inverted serial clock

polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync

(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have

been inverted, all the timing remains valid by inverting the clock signal

STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables

and in the figures.

• All timings are on Audiomux Pads when SSI is being used for data

transfer.

• “Tx” and “Rx” refer to the Transmit and Receive sections of the SSI.

• The terms WL and BL refer to Word Length (WL) and Bit Length (BL).

• For internal Frame Sync operation using external clock, the FS timing is

same as that of Tx Data (for example, during AC97 mode of operation).

SS39 (Tx) CK high to STXD high impedance — 15.0 ns

Synchronous External Clock Operation

SS44 SRXD setup before (Tx) CK falling 10.0 — ns

SS45 SRXD hold after (Tx) CK falling 2.0 — ns

SS46 SRXD rise/fall time — 6.0 ns

Table 84. SSI Transmitter Timing with External Clock (continued)

ID Parameter Min Max Unit

i.MX53 Applications Processors for Industrial Products, Rev. 7

128 Freescale Semiconductor

Electrical Characteristics

4.7.16.4 SSI Receiver Timing with External Clock

Figure 84 depicts the SSI receiver external clock timing and Table 85 lists the timing parameters for the

receiver timing with the external clock.

Figure 84. SSI Receiver External Clock Timing Diagram

Table 85. SSI Receiver Timing with External Clock

ID Parameter Min Max Unit

External Clock Operation

SS22 (Tx/Rx) CK clock period 81.4 — ns

SS23 (Tx/Rx) CK clock high period 36 — ns

SS24 (Tx/Rx) CK clock rise time — 6.0 ns

SS25 (Tx/Rx) CK clock low period 36 — ns

SS26 (Tx/Rx) CK clock fall time — 6.0 ns

SS28 (Rx) CK high to FS (bl) high -10 15.0 ns

SS30 (Rx) CK high to FS (bl) low 10 — ns

SS32 (Rx) CK high to FS (wl) high -10 15.0 ns

SS34 (Rx) CK high to FS (wl) low 10 — ns

SS35 (Tx/Rx) External FS rise time — 6.0 ns

SS36 (Tx/Rx) External FS fall time — 6.0 ns

SS40 SRXD setup time before (Rx) CK low 10 — ns

SS41 SRXD hold time after (Rx) CK low 2 — ns

SS24

SS34

SS35

SS30

SS28

SS26

SS25

SS23

SS40

SS22

SS32

SS36

SS41

TXC

TXFS (bl)

TXFS (wl)

RXD

(Input)

Electrical Characteristics

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 129

NOTE

• All the timings for the SSI are given for a non-inverted serial clock

polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync

(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have

been inverted, all the timing remains valid by inverting the clock signal

STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables

and in the figures.

• All timings are on Audiomux Pads when SSI is being used for data

transfer.

• “Tx” and “Rx” refer to the Transmit and Receive sections of the SSI.

• The terms WL and BL refer to Word Length (WL) and Bit Length (BL).

• For internal Frame Sync operation using external clock, the FS timing is

same as that of Tx Data (for example, during AC97 mode of operation).

4.7.17 UART I/O Configuration and Timing Parameters

4.7.17.1 UART RS-232 I/O Configuration in Different Modes

The i.MX53 UART interfaces can serve both as DTE or DCE device. This can be configured by the

DCEDTE control bit (default 0 — DCE mode). Table 86 shows the UART I/O configuration based on

the enabled mode.

4.7.17.2 UART RS-232 Serial Mode Timing

The following sections describe the electrical information of the UART module in the RS-232 mode.

4.7.17.2.1 UART Transmitter

Figure 85 depicts the transmit timing of UART in the RS-232 serial mode, with 8 data bit/1 stop bit format.

Table 87 lists the UART RS-232 serial mode transmit timing characteristics.

Table 86. UART I/O Configuration vs. Mode

Port

DTE Mode DCE Mode

Direction Description Direction Description

RTS Output RTS from DTE to DCE Input RTS from DTE to DCE

CTS Input CTS from DCE to DTE Output CTS from DCE to DTE

DTR Output DTR from DTE to DCE Input DTR from DTE to DCE

DSR Input DSR from DCE to DTE Output DSR from DCE to DTE

DCD Input DCD from DCE to DTE Output DCD from DCE to DTE

RI Input RING from DCE to DTE Output RING from DCE to DTE

TXD_MUX Input Serial data from DCE to DTE Output Serial data from DCE to DTE

RXD_MUX Output Serial data from DTE to DCE Input Serial data from DTE to DCE

i.MX53 Applications Processors for Industrial Products, Rev. 7

130 Freescale Semiconductor

Electrical Characteristics

Figure 85. UART RS-232 Serial Mode Transmit Timing Diagram

4.7.17.2.2 UART Receiver

Figure 86 depicts the RS-232 serial mode receive timing with 8 data bit/1 stop bit format. Table 88 lists

serial mode receive timing characteristics.

Figure 86. UART RS-232 Serial Mode Receive Timing Diagram

4.7.17.3 UART IrDA Mode Timing

The following subsections give the UART transmit and receive timings in IrDA mode.

4.7.17.3.3 UART IrDA Mode Transmitter

Figure 87 depicts the UART IrDA mode transmit timing, with 8 data bit/1 stop bit format. Table 89 lists

the transmit timing characteristics.

Table 87. RS-232 Serial Mode Transmit Timing Parameters

ID Parameter Symbol Min Max Units

UA1 Transmit Bit Time tTbit 1/Fbaud_rate1 -

Tref_clk2

1Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.

2Tref_clk: The period of UART reference clock ref_clk (ipg_perclk after RFDIV divider).

1/Fbaud_rate +

Tref_clk

—

Table 88. RS-232 Serial Mode Receive Timing Parameters

ID Parameter Symbol Min Max Units

UA2 Receive Bit Time1

1The UART receiver can tolerate 1/(16 x Fbaud_rate) tolerance in each bit. But accumulation tolerance in one frame must not

exceed 3/(16 x Fbaud_rate).

tRbit 1/Fbaud_rate2 - 1/(16

x Fbaud_rate)

2Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.

1/Fbaud_rate +

1/(16 x Fbaud_rate)

—

Bit 1 Bit 2Bit 0 Bit 4 Bit 5 Bit 6 Bit 7

TXD

(output) Bit 3

Start

Bit STOP

BIT

Start

Bit

Possible

Parity

Bit

Par Bit

UA1

UA1 UA1

UA1

Bit 1 Bit 2Bit 0 Bit 4 Bit 5 Bit 6 Bit 7

RXD

(input) Bit 3

Start

Bit STOP

BIT

Start

Bit

Possible

Parity

Bit

Par Bit

UA2 UA2

Electrical Characteristics

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 131

Figure 87. UART IrDA Mode Transmit Timing Diagram

4.7.17.3.4 UART IrDA Mode Receiver

Figure 88 depicts the UART IrDA mode receive timing, with 8 data bit/1 stop bit format. Table 90 lists the

receive timing characteristics.

Figure 88. UART IrDA Mode Receive Timing Diagram

Table 89. IrDA Mode Transmit Timing Parameters

ID Parameter Symbol Min Max Units

UA3 Transmit Bit Time in IrDA mode tTIRbit 1/Fbaud_rate1 -

Tref_clk2

1Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.

2Tref_clk: The period of UART reference clock ref_clk (ipg_perclk after RFDIV divider).

1/Fbaud_rate + Tref_clk —

UA4 Transmit IR Pulse Duration tTIRpulse (3/16) x (1/Fbaud_rate)

- Tref_clk

(3/16) x (1/Fbaud_rate)

+ Tref_clk

—

Table 90. IrDA Mode Receive Timing Parameters

ID Parameter Symbol Min Max Units

UA5 Receive Bit Time1 in IrDA mode

1 The UART receiver can tolerate 1/(16 x Fbaud_rate) tolerance in each bit. But accumulation tolerance in one frame must not

exceed 3/(16 x Fbaud_rate).

tRIRbit 1/Fbaud_rate2 - 1/(16

x Fbaud_rate)

2Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.

1/Fbaud_rate + 1/(16 x

Fbaud_rate)

—

UA6 Receive IR Pulse Duration tRIRpulse 1.41 us (5/16) x (1/Fbaud_rate)—

Bit 1 Bit 2

Bit 0 Bit 4 Bit 5 Bit 6 Bit 7

TXD

(output)

Bit 3

Start

Bit

STOP

BIT

Possible

Parity

Bit

UA3 UA3 UA3 UA3

UA4

Bit 1 Bit 2

Bit 0 Bit 4 Bit 5 Bit 6 Bit 7

RXD

(input)

Bit 3

Start

Bit

STOP

BIT

Possible

Parity

Bit

UA5 UA5 UA5 UA5

UA6

i.MX53 Applications Processors for Industrial Products, Rev. 7

132 Freescale Semiconductor

Electrical Characteristics

4.7.18 USB-OH-3 Parameters

This section describes the electrical parameters of the USB OTG port and USB HOST ports. For on-chip

USB PHY parameters see Section 4.7.19, “USB PHY Parameters.”

4.7.18.1 Serial Interface

In order to support four serial different interfaces, the USB serial transceiver can be configured to operate

in one of four modes:

• DAT_SE0 bidirectional, 3-wire mode

• DAT_SE0 unidirectional, 6-wire mode

• VP_VM bidirectional, 4-wire mode

• VP_VM unidirectional, 6-wire mode

4.7.18.1.1 DAT_SE0 Bidirectional Mode

Figure 89. USB Transmit Waveform in DAT_SE0 Bidirectional Mode

Table 91. Signal Definitions — DAT_SE0 Bidirectional Mode

Name Direction Signal Description

USB_TXOE_B Out Transmit enable, active low

USB_DAT_VP Out

TX data when USB_TXOE_B is low

Differential RX data when USB_TXOE_B is high

USB_SE0_VM Out

SE0 drive when USB_TXOE_B is low

SE0 RX indicator when USB_TXOE_B is high

USB_DAT_VP

USB_SE0_VM US1

US2

Transmit

US4

USB_TXOE_B US3

Electrical Characteristics

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Freescale Semiconductor 133

Figure 90. USB Receive Waveform in DAT_SE0 Bidirectional Mode

Table 92. Definitions of USB Waveform in DAT_SE0 Bi — Directional Mode

No. Parameter Signal Name Direction Min Max Unit Conditions /

Reference Signal

US1 TX Rise/Fall Time USB_DAT_VP Out — 5.0 ns 50 pF

US2 TX Rise/Fall Time USB_SE0_VM Out — 5.0 ns 50 pF

US3 TX Rise/Fall Time USB_TXOE_B Out — 5.0 ns 50 pF

US4 TX Duty Cycle USB_DAT_VP Out 49.0 51.0 % —

US7 RX Rise/Fall Time USB_DAT_VP In — 3.0 ns 35 pF

US8 RX Rise/Fall Time USB_SE0_VM In — 3.0 ns 35 pF

US8

US7

USB_DAT_VP

USB_SE0_VM

USB_TXOE_B

Receive

USB_SE0_VM

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Electrical Characteristics

4.7.18.1.2 DAT_SE0 Unidirectional Mode

Figure 91. USB Transmit Waveform in DAT_SE0 Unidirectional Mode

Table 93. Signal Definitions — DAT_SE0 Unidirectional Mode

Name Direction Signal Description

USB_TXOE_B Out Transmit enable, active low

USB_DAT_VP Out TX data when USB_TXOE_B is low

USB_SE0_VM Out SE0 drive when USB_TXOE_B is low

USB_VP1 In Buffered data on DP when USB_TXOE_B is high

USB_VM1 In Buffered data on DM when USB_TXOE_B is high

USB_DAT_VP

USB_SE0_VM

US9

US10

Transmit

US12

USB_TXOE_B

US11

Electrical Characteristics

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Figure 92. USB Receive Waveform in DAT_SE0 Unidirectional Mode

Table 94. USB Port Timing Specification in DAT_SE0 Unidirectional Mode

No. Parameter Signal Name Signal

Source Min Max Unit Condition /

Reference Signal

US9 TX Rise/Fall Time USB_DAT_VP Out — 5.0 ns 50 pF

US10 TX Rise/Fall Time USB_SE0_VM Out — 5.0 ns 50 pF

US11 TX Rise/Fall Time USB_TXOE_B Out — 5.0 ns 50 pF

US12 TX Duty Cycle USB_DAT_VP Out 49.0 51.0 % —

US15 RX Rise/Fall Time USB_VP1 In — 3.0 ns 35 pF

US16 RX Rise/Fall Time USB_VM1 In — 3.0 ns 35 pF

US16US15

USB_DAT_VP

USB_TXOE_B

Receive

USB_SE0_VM

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Electrical Characteristics

4.7.18.1.3 VP_VM Bidirectional Mode

Figure 93. USB Transmit Waveform in VP_VM Bidirectional Mode

Figure 94. USB Receive Waveform in VP_VM Bidirectional Mode

Table 95. Signal Definitions — VP_VM Bidirectional Mode

Name Direction Signal Description

USB_TXOE_B Out Transmit enable, active low

USB_DAT_VP Out (Tx)

In (Rx)

TX VP data when USB_TXOE_B is low

RX VP data when USB_TXOE_B is high

USB_SE0_VM Out (Tx)

In (Rx)

TX VM data when USB_TXOE_B low

RX VM data when USB_TXOE_B high

USB_DAT_VP

USB_SE0_VM

US18

US19

Transmit

USB_TXOE_B

US20

US22

US21

US22

USB_DAT_VP

USB_SE0_VM

US26

US28 US27

Receive

Electrical Characteristics

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Freescale Semiconductor 137

4.7.18.1.4 VP_VM Unidirectional Mode

Figure 95. USB Transmit Waveform in VP_VM Unidirectional Mode

Table 96. USB Port Timing Specification in VP_VM Bidirectional Mode

No. Parameter Signal Name Direction Min Max Unit Condition /

Reference Signal

US18 TX Rise/Fall Time USB_DAT_VP Out —5.0 ns 50 pF

US19 TX Rise/Fall Time USB_SE0_VM Out —5.0 ns 50 pF

US20 TX Rise/Fall Time USB_TXOE_B Out —5.0 ns 50 pF

US21 TX Duty Cycle USB_DAT_VP Out 49.0 51.0 % —

US22 TX Overlap USB_SE0_VM Out -3.0 +3.0 ns USB_DAT_VP

US26 RX Rise/Fall Time USB_DAT_VP In —3.0 ns 35 pF

US27 RX Rise/Fall Time USB_SE0_VM In —3.0 ns 35 pF

US28 RX Skew USB_DAT_VP In -4.0 +4.0 ns USB_SE0_VM

Table 97. Signal Definitions — VP_VM Unidirectional Mode

Name Direction Signal Description

USB_TXOE_B Out Transmit enable, active low

USB_DAT_VP Out TX VP data when USB_TXOE_B is low

USB_SE0_VM Out TX VM data when USB_TXOE_B is low

USB_VP1 In RX VP data when USB_TXOE_B is high

USB_VM1 In RX VM data when USB_TXOE_B is high

USB_DAT_VP

USB_SE0_VM

US30

US31

Transmit

USB_TXOE_B

US32

US34

US33

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Electrical Characteristics

Figure 96. USB Receive Waveform in VP_VM Unidirectional Mode

Table 98. USB Timing Specification in VP_VM Unidirectional Mode

No. Parameter Signal Direction Min Max Unit

Conditions /

Reference

Signal

US30 TX Rise/Fall Time USB_DAT_VP Out — 5.0 ns 50 pF

US31 TX Rise/Fall Time USB_SE0_V

Out — 5.0 ns 50 pF

US32 TX Rise/Fall Time USB_TXOE_

Out — 5.0 ns 50 pF

US33 TX Duty Cycle USB_DAT_VP Out 49.0 51.0 % —

US34 TX Overlap USB_SE0_V

Out -3.0 3.0 ns USB_DAT_VP

US38 RX Rise/Fall Time USB_VP1 In — 3.0 ns 35 pF

US39 RX Rise/Fall Time USB_VM1 In — 3.0 ns 35 pF

US40 RX Skew USB_VP1 In -4.0 +4.0 ns USB_VM1

US38

USB_VM1

Receive

USB_TXOE_B

US40

US39

USB_VP1

Electrical Characteristics

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Freescale Semiconductor 139

4.7.18.2 Parallel Interface (Normal ULPI) Timing

Electrical and timing specifications of Parallel Interface (Normal ULPI) for Host Port2 and Port3 are

presented in the subsequent sections.

Figure 97. USB Transmit/Receive Waveform in Parallel Mode

4.7.19 USB PHY Parameters

This section describes the USB-OTG PHY and the USB Host port PHY parameters.

4.7.19.1 USB PHY AC Parameters

Table 101 lists the AC timing parameters for USB PHY.

Table 99. Signal Definitions — Parallel Interface (Normal ULPI)

Name Direction Signal Description

USB_Clk In Interface clock. All interface signals are synchronous to Clock.

USB_Data[7:0] I/O Bi-directional data bus, driven low by the link during idle. Bus

ownership is determined by Dir.

USB_Dir In Direction. Control the direction of the Data bus.

USB_Stp Out Stop. The link asserts this signal for 1 clock cycle to stop the

data stream currently on the bus.

USB_Nxt In Next. The PHY asserts this signal to throttle the data.

Table 100. USB Timing Specification for Normal ULPI Mode

ID Parameter Min Max Unit Conditions /

Reference Signal

US15 Setup Time (Dir&Nxt in, Data in) 6.0 — ns 10 pF

US16 Hold Time (Dir&Nxt in, Data in) 0.0 — ns 10 pF

US17 Output Delay Time (Stp out, Data out — 9.0 ns 10 pF

USB_Stp

USB_Dir/Nxt

US17

US16

USB_Data

US15

US16

US15

US17

USB_Clk

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Electrical Characteristics

4.7.19.2 USB PHY Additional Electrical Parameters

Table 102 lists the parameters for additional electrical characteristics for USB PHY.

4.7.19.3 USB PHY System Clocking (SYSCLK)

Table 103 lists the USB PHY system clocking parameters.

Table 101. USB PHY AC Timing Parameters

Parameter Conditions Min Typ Max Unit

trise 1.5 Mbps

12 Mbps

480 Mbps

0.5

—300

tfall 1.5 Mbps

12 Mbps

480 Mbps

0.5

—300

Jitter 1.5 Mbps

12 Mbps

480 Mbps

——10

0.2

Table 102. Additional Electrical Characteristics for USB PHY

Parameter Conditions Min Typ Max Unit

Vcm DC

(dc level measured at receiver connector)

HS Mode

LS/FS Mode

-0.05

0.8

—0.5

2.5

Crossover Voltage LS Mode

FS Mode

1.3

—2

Power supply ripple noise

(analog 3.3 V)

< 160 MHz -50 0 50 mV

Power supply ripple noise

(analog 2.5 V)

<1.2MHz

>1.2MHz

-10

-50

Power supply ripple noise

(Digital 1.2 V)

All conditions -50 0 50 mV

Table 103. USB PHY System Clocking Parameters

Parameter Conditions Min Typ Max Unit

Clock deviation Reference Clock

frequency 24 MHz

-150 — 150 ppm

Rise/fall time — — — 200 ps

Jitter (peak-peak) < 1.2 MHz 0 — 50 ps

Jitter (peak-peak) > 1.2 MHz 0 — 100 ps

Duty-cycle Reference Clock

frequency 24 MHz

40 — 60 %

Electrical Characteristics

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Freescale Semiconductor 141

4.7.19.4 USB PHY Voltage Thresholds

Table 104 lists the USB PHY voltage thresholds.

4.7.19.5 USB PHY Termination

USB driver impedance in FS and HS modes is 45 Ω±10% (steady state). No external resistors required.

4.8 XTAL Electrical Specifications

Table 105 shows the XTALOSC electrical specifications.

Table 106 shows the XTALOSC_32K electrical specifications.

4.9 Integrated LDO Voltage Regulators Parameters

The PLL supplies VDD_DIG_PLL and VDD_ANA_PLL can be powered ON from internal LDO voltage

regulator (default case). In this case VDD_REG is used as internal regulator’s power source. The

regulator’s output can be used as a supply for other domains such as VDDA and VDDAL1.

Table 107 shows the VDD_DIG_PLL and VDD_ANA_PLL Integrated Voltage Regulators Parameters.

Table 104. VBUS Comparators Thresholds

Parameter Conditions Min Typ Max Unit

A-Device Session Valid — 0.8 1.4 2.0 V

B-Device Session Valid — 0.8 1.4 4.0 V

B-Device Session End — 0.2 0.45 0.8 V

VBUS Valid Comparator Threshold1

1For VBUS maximum rating, see Table 4 on page 16

—4.44.64.75V

Table 105. XTALOSC Electrical Specifications

Parameter Min Typ Max Units

Frequency 22 24 27 MHz

Table 106. XTALOSC_32K Electrical Specifications

Parameter Min Typ Max Units

Frequency — 32.768/32.01

1Recommended nominal frequency 32.768 kHz.

—kHz

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Boot Mode Configuration

5 Boot Mode Configuration

This section provides information on boot mode configuration pins allocation and boot devices interfaces

allocation.

5.1 Boot Mode Configuration Pins

Table 108 provides boot options, functionality, fuse values, and associated pins. Several input pins are also

sampled at reset and can be used to override fuse values, depending on the value of BT_FUSE_SEL fuse.

The boot option pins are in effect when BT_FUSE_SEL fuse is ‘0’ (cleared, which is the case for an

unblown fuse). For detailed boot mode options configured by the boot mode pins, see i.MX53 Fuse Map

document and Boot chapter in i.MX53 reference manual.

Table 107. LDO Voltage Regulators Electrical Specifications

Parameter Symbol Min Typ Max Units

VDD_DIG_PLL functional Voltage

Range1

1 VDD_DIG_PLL and VDD_ANA_PLL voltages are programmable, but should not be set outside the target functional range

for proper PLL operation.

VVID_DIG_PLL 1.15 1.2 1.3 V

VDD_ANA_PLL functional Voltage

Range1

VVDD_ANA_PLL 1.7 1.8 1.95 V

VDD_DIG_PLL and VDD_ANA_PLL

accuracy

———±3%

VDD_DIG_PLL power-supply rejection

ratio2

2The gain or attenuation from the input supply variation to the output of the LDO (by design).

——-18—dB

VDD_ANA_PLL power-supply rejection

ratio2

——-15—dB

Output current3

3The limitation is for sum of the VDD_DIG_PLL and VDD_ANA_PLL current.

IVID_DIG_PLL+

IVDD_ANA_PLL

— — 125 mA

Table 108. Fuses and Associated Pins Used for Boot

Pin Direction at

Reset eFUSE Name Details

BOOT_MODE[1] Input N/A Boot Mode selection

BOOT_MODE[0] Input

Boot Mode Configuration

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Freescale Semiconductor 143

5.2 Boot Devices Interfaces Allocation

Table 109 lists the interfaces that can be used by the boot process in accordance with the specific boot

mode configuration. The table also describes the interface’s specific modes and IOMUXC allocation,

which are configured during boot when appropriate.

EIM_A22 Input BOOT_CFG1[7]/Test Mode Selection Boot Options, Pin value overrides fuse

settings for BT_FUSE_SEL = ‘0’.

Signal Configuration as Fuse Override

Input at Power Up. These are special I/O

lines that control the boot up configuration

during product development. In production,

the boot configuration can be controlled by

fuses.

EIM_A21 Input BOOT_CFG1[6]/Test Mode Selection

EIM_A20 Input BOOT_CFG1[5]/Test Mode Selection

EIM_A19 Input BOOT_CFG1[4]

EIM_A18 Input BOOT_CFG1[3]

EIM_A17 Input BOOT_CFG1[2]

EIM_A16 Input BOOT_CFG1[1]

EIM_LBA Input BOOT_CFG1[0]

EIM_EB0 Input BOOT_CFG2[7]

EIM_EB1 Input BOOT_CFG2[6]

EIM_DA0 Input BOOT_CFG2[5]

EIM_DA1 Input BOOT_CFG2[4]

EIM_DA2 Input BOOT_CFG2[3]

EIM_DA3 Input BOOT_CFG2[2]

EIM_DA4 Input BOOT_CFG3[7]

EIM_DA5 Input BOOT_CFG3[6]

EIM_DA6 Input BOOT_CFG3[5]

EIM_DA7 Input BOOT_CFG3[4]

EIM_DA8 Input BOOT_CFG3[3]

EIM_DA9 Input BOOT_CFG3[2]

EIM_DA10 Input BOOT_CFG3[1]

Table 109. Interfaces Allocation During Boot

Interface IP Instance Allocated Pads During Boot Comment

SPI CSPI EIM_A25, EIM_D21, EIM_D22, EIM_D28 Only SS1 is supported

SPI ECSPI-1 EIM_D[19:16] Only SS1 is supported

SPI ECSPI-2 CSI_DAT[10:8], EIM_LBA Only SS1 is supported

Table 108. Fuses and Associated Pins Used for Boot (continued)

Pin Direction at

Reset eFUSE Name Details

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Boot Mode Configuration

5.3 Power Setup During Boot

By default, VDD_DIG_PLL is driven from internal on-die 1.2 V linear regulator (LDO). In order to

achieve the standard operating mode (see VDD_DIG_PLL on Table 6), LDO output to VDD_DIG_PLL

should be configured by software by boot code after power-up to 1.3 V output. This is done by

programming the PLL1P2_VREG bits.

EIM EIM EIM • Lower 16-bit data bus A/D

multiplexed or upper 16 bit data bus

non multiplexed

• Only CS0 is supported.

NAND Flash EXTMC NAND • 8/16-bit

• NAND data can be muxed either over

EIM data or PATA data

• Only CS0 is supported

SD/MMC eSDHCv2-1 PATA_DATA[11:8], SD1_DATA[3:0], SD1_CMD,

SD1_CLK

1, 4, or 8 bit

SD/MMC eSDHCv2-2 PATA_DATA[15:12], SD2_CLK, SD2_CMD,

SD2_DATA[3:0]

1, 4, or 8 bit

SD/MMC eSDHCv3-3 PATA_RESET_B, PATA_IORDY, PATA_DA_0,

PATA_DATA[3:0], PATA_DATA[11:8]

1, 4, or 8 bit

SD/MMC eSDHCv2-4 PATA_DA1, PATA_DA_2, PATA_DATA[7:4],

PATA_DATA[15:12]

1, 4, or 8 bit

I2C I2C-1 EIM_D21, EIM_D28 —

I2C I2C-2 EIM_D16, EIM_EB2 —

I2C I2C-3 EIM_D[18:17] —

PATA PATA PATA_DIOW, PATA_DMACK, PATA_DMARQ,

PATA_BUFFER_EN, PATA_INTRQ, PATA_DIOR,

PATA_RESET_B, PATA_IORDY, PATA_DA_[2:0],

PATA_CS_[1:0], PATA_DATA[15:0]

—

SATA SATA_PHY SATA_TXM, SATA_TXP, SATA_RXP, SATA_RXM,

SATA_REXT, SATA_REFCLKM, SATA_REFCLKP

—

UART UARTv2-1 CSI0_DAT[11:10] RXD/TXD only

UART UARTv2-2 PATA_DMARQ, PATA_BUFFER_EN RXD/TXD only

UART UARTv2-3 EIM_D24, EIM_D25 RXD/TXD only

UART UARTv2-4 CSI0_DAT[13:12] RXD/TXD only

UART UARTv2-5 CSI0_DAT[15:14] RXD/TXD only

USB USB-OTG

PHY

USB_H1_GPANAIO

USB_H1_RREFEXT

USB_H1_DP

USB_H1_DN

USB_H1_VBUS

—

Table 109. Interfaces Allocation During Boot (continued)

Interface IP Instance Allocated Pads During Boot Comment

Package Information and Contact Assignments

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Freescale Semiconductor 145

6 Package Information and Contact Assignments

This section includes the contact assignment information and mechanical package drawing.

6.1 19x19 mm Package Information

This section contains the outline drawing, signal assignment map, ground/power reference ID (by ball grid

location) for the 19 ×19 mm, 0.8 mm pitch package.

6.1.1 Case TEPBGA-2, 19 x 19 mm, 0.8 mm Pitch, 23 x 23 Ball Matrix

Figure 98 shows the top view of the 19×19 mm package, Figure 99 shows the bottom view and the ball

location (529 solder balls) of the 19×19 mm package, and Figure 100 shows the side view of the 19×19

mm package.

Figure 98. 19 x 19 mm Package Top View

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146 Freescale Semiconductor

Package Information and Contact Assignments

Figure 99. 19 x 19 mm Package, 529 Solder Balls, Bottom View

Figure 100. 19 x 19 mm Package Side View

Package Information and Contact Assignments

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Freescale Semiconductor 147

The following notes apply to Figure 98, Figure 99, and Figure 100.

1. All dimensions are in millimeters.

2. Dimensions and tolerancing per ASME Y14.5M1–994.

6.1.2 19 x 19 mm Ground, Power, Sense, and Reference Contact

Assignments

Table 110 shows the device connection list for ground, power, sense, and reference contact signals

alpha-sorted by name.

Table 110. 19 x 19 mm Ground, Power, Sense, and Reference Contact Assignments

Contact Name Package Contact Assignment(s)

DDR_VREF L17

GND A1, A11, A13, A18, A2, A22, A23, AA11, AA15, AA20, AA21, AB1, AB18, AB2, AB22, AB23,

AC1, AC18, AC2, AC22, AC23, B1, B11, B13, B18, B23, C12, C20, C21, D19, E19, F19, F20,

F21, F22, G19, G7, H10, H12, H8, J11, J13, J15, J17, J20, J9, K10, K12, K14, K16, K21, K8,

L11, L13, L15, L7, L9, M10, M12, M14, M16, M8, N11, N13, N15, N9, P10, P12, P14, P16,

P21, P7, P8, R11, R13, R15, R17, R20, R9, T10, T14, T16, T8, U15, U19, V15, V18, V19,

V20, V21, V22, W19, Y14, Y15, Y19

NVCC_CKIH G17

NVCC_CSI R7

NVCC_EIM_MAIN U10, U9

NVCC_EIM_SEC U7

NVCC_EMI_DRAM H18, K17, N17, P17, T18

NVCC_FEC F11

NVCC_GPIO F8

NVCC_JTAG G9

NVCC_KEYPAD F7

NVCC_LCD J6, J7

NVCC_LVDS U13

NVCC_LVDS_BG U14

NVCC_NANDF T12

NVCC_PATA N7

NVCC_RESET H16

NVCC_SD1 H15

NVCC_SD2 H14

NVCC_SRTC_POW V11

NVCC_XTAL V12

SVCC B22

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Package Information and Contact Assignments

6.1.3 19 x 19 mm Signal Assignments, Power Rails, and I/O

Table 111 displays an alpha-sorted list of the signal assignments including power rails. The table also

includes out of reset pad state.

SVDDGP B2

TVDAC_AHVDDRGB U17, V16

TVDAC_DHVDD U16

USB_H1_VDDA25 F13

USB_H1_VDDA33 G13

USB_OTG_VDDA25 F14

USB_OTG_VDDA33 G14

VCC H13, J14, J16, K13, K15, L14, L16, M11, M13, M15, M9, N10, N12, N14, N16, N8, P11, P13,

P15, P9, R10, R12, R14, R16, R8, T11, T13, T15, T17, T7, T9, U18, U8

VDDA G12, M17, M7, U12

VDDAL1 F9

VDD_ANA_PLL G16

VDD_DIG_PLL H17

VDD_FUSE G15

VDDGP G10, G11, G8, H11, H7, H9, J10, J12, J8, K11, K7, K9, L10, L12, L8

VDD_REG G18

VP A15, B15

VPH A9, B9

Table 111. 19 x 19 mm Signal Assignments, Power Rails, and I/O

Contact Name Contact

Assignment Power Rail I/O Buffer

Type

Out of Reset Condition1

Alt.

Mode

Block

Instance Block I/O Direction Config.

Value

BOOT_MODE0 C18 NVCC_RESET LVIO ALT0 SRC src_BOOT_MO

DE[0]

Input 100 KΩ

BOOT_MODE1 B20 NVCC_RESET LVIO ALT0 SRC src_BOOT_MO

DE[1]

Input 100 KΩ

CKIH1 B21 NVCC_CKIH ANALOG ALT0 CAMP-1 camp1_CKIH Input Analog

CKIH2 D18 NVCC_CKIH ANALOG ALT0 CAMP-2 camp2_CKIH Input Analog

CKIL AB10 NVCC_SRTC_POW ANALOG — SRCT CKIL — —

Table 110. 19 x 19 mm Ground, Power, Sense, and Reference Contact Assignments (continued)

Contact Name Package Contact Assignment(s)

Package Information and Contact Assignments

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Freescale Semiconductor 149

CSI0_DAT10 R5 NVCC_CSI UHVIO ALT1 GPIO-5 gpio5_GPIO[28] Input 100 KΩ

CSI0_DAT11 T2 NVCC_CSI UHVIO ALT1 GPIO-5 gpio5_GPIO[29] Input 100 KΩ

CSI0_DAT12 T3 NVCC_CSI UHVIO ALT1 GPIO-5 gpio5_GPIO[30] Input 360 KΩ

CSI0_DAT13 T6 NVCC_CSI UHVIO ALT1 GPIO-5 gpio5_GPIO[31] Input 360 KΩ

CSI0_DAT14 U1 NVCC_CSI UHVIO ALT1 GPIO-6 gpio6_GPIO[0] Input 360 KΩ

CSI0_DAT15 U2 NVCC_CSI UHVIO ALT1 GPIO-6 gpio6_GPIO[1] Input 360 KΩ

CSI0_DAT16 T4 NVCC_CSI UHVIO ALT1 GPIO-6 gpio6_GPIO[2] Input 360 KΩ

CSI0_DAT17 T5 NVCC_CSI UHVIO ALT1 GPIO-6 gpio6_GPIO[3] Input 360 KΩ

CSI0_DAT18 U3 NVCC_CSI UHVIO ALT1 GPIO-6 gpio6_GPIO[4] Input 360 KΩ

CSI0_DAT19 U4 NVCC_CSI UHVIO ALT1 GPIO-6 gpio6_GPIO[5] Input 360 KΩ

CSI0_DAT4 R1 NVCC_CSI UHVIO ALT1 GPIO-5 gpio5_GPIO[22] Input 100 KΩ

CSI0_DAT5 R2 NVCC_CSI UHVIO ALT1 GPIO-5 gpio5_GPIO[23] Input 360 KΩ

CSI0_DAT6 R6 NVCC_CSI UHVIO ALT1 GPIO-5 gpio5_GPIO[24] Input 100 KΩ

CSI0_DAT7 R3 NVCC_CSI UHVIO ALT1 GPIO-5 gpio5_GPIO[25] Input 100 KΩ

CSI0_DAT8 T1 NVCC_CSI UHVIO ALT1 GPIO-5 gpio5_GPIO[26] Input 100 KΩ

CSI0_DAT9 R4 NVCC_CSI UHVIO ALT1 GPIO-5 gpio5_GPIO[27] Input 360 KΩ

CSI0_DATA_EN P3 NVCC_CSI UHVIO ALT1 GPIO-5 gpio5_GPIO[20] Input 100 KΩ

CSI0_MCLK P2 NVCC_CSI UHVIO ALT1 GPIO-5 gpio5_GPIO[19] Input 100 KΩ

CSI0_PIXCLK P1 NVCC_CSI UHVIO ALT1 GPIO-5 gpio5_GPIO[18] Input 100 KΩ

Table 111. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)

Contact Name Contact

Assignment Power Rail I/O Buffer

Type

Out of Reset Condition1

Alt.

Mode

Block

Instance Block I/O Direction Config.

Value

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Package Information and Contact Assignments

CSI0_VSYNC P4 NVCC_CSI UHVIO ALT1 GPIO-5 gpio5_GPIO[21] Input 100 KΩ

DI0_DISP_CLK H4 NVCC_LCD GPIO ALT1 GPIO-4 gpio4_GPIO[16] Input 100 KΩ

DI0_PIN15 E4 NVCC_LCD GPIO ALT1 GPIO-4 gpio4_GPIO[17] Input 100 KΩ

DI0_PIN2 D3 NVCC_LCD GPIO ALT1 GPIO-4 gpio4_GPIO[18] Input 100 KΩ

DI0_PIN3 C2 NVCC_LCD GPIO ALT1 GPIO-4 gpio4_GPIO[19] Input 100 KΩ

DI0_PIN4 D2 NVCC_LCD GPIO ALT1 GPIO-4 gpio4_GPIO[20] Input 100 KΩ

DISP0_DAT0 J5 NVCC_LCD GPIO ALT1 GPIO-4 gpio4_GPIO[21] Input 100 KΩ

DISP0_DAT1 J4 NVCC_LCD GPIO ALT1 GPIO-4 gpio4_GPIO[22] Input 100 KΩ

DISP0_DAT10 G3 NVCC_LCD GPIO ALT1 GPIO-4 gpio4_GPIO[31] Input 100 KΩ

DISP0_DAT11 H5 NVCC_LCD GPIO ALT1 GPIO-5 gpio5_GPIO[5] Input 100 KΩ

DISP0_DAT12 H1 NVCC_LCD GPIO ALT1 GPIO-5 gpio5_GPIO[6] Input 100 KΩ

DISP0_DAT13 E1 NVCC_LCD GPIO ALT1 GPIO-5 gpio5_GPIO[7] Input 100 KΩ

DISP0_DAT14 F2 NVCC_LCD GPIO ALT1 GPIO-5 gpio5_GPIO[8] Input 100 KΩ

DISP0_DAT15 F3 NVCC_LCD GPIO ALT1 GPIO-5 gpio5_GPIO[9] Input 100 KΩ

DISP0_DAT16 D1 NVCC_LCD GPIO ALT1 GPIO-5 gpio5_GPIO[10] Input 100 KΩ

DISP0_DAT17 F5 NVCC_LCD GPIO ALT1 GPIO-5 gpio5_GPIO[11] Input 100 KΩ

DISP0_DAT18 G4 NVCC_LCD GPIO ALT1 GPIO-5 gpio5_GPIO[12] Input 100 KΩ

DISP0_DAT19 G5 NVCC_LCD GPIO ALT1 GPIO-5 gpio5_GPIO[13] Input 100 KΩ

DISP0_DAT2 H2 NVCC_LCD GPIO ALT1 GPIO-4 gpio4_GPIO[23] Input 100 KΩ

Table 111. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)

Contact Name Contact

Assignment Power Rail I/O Buffer

Type

Out of Reset Condition1

Alt.

Mode

Block

Instance Block I/O Direction Config.

Value

Package Information and Contact Assignments

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 151

DISP0_DAT20 F4 NVCC_LCD GPIO ALT1 GPIO-5 gpio5_GPIO[14] Input 100 KΩ

DISP0_DAT21 C1 NVCC_LCD GPIO ALT1 GPIO-5 gpio5_GPIO[15] Input 100 KΩ

DISP0_DAT22 E3 NVCC_LCD GPIO ALT1 GPIO-5 gpio5_GPIO[16] Input 100 KΩ

DISP0_DAT23 C3 NVCC_LCD GPIO ALT1 GPIO-5 gpio5_GPIO[17] Input 100 KΩ

DISP0_DAT3 F1 NVCC_LCD GPIO ALT1 GPIO-4 gpio4_GPIO[24] Input 100 KΩ

DISP0_DAT4 G2 NVCC_LCD GPIO ALT1 GPIO-4 gpio4_GPIO[25] Input 100 KΩ

DISP0_DAT5 H3 NVCC_LCD GPIO ALT1 GPIO-4 gpio4_GPIO[26] Input 100 KΩ

DISP0_DAT6 G1 NVCC_LCD GPIO ALT1 GPIO-4 gpio4_GPIO[27] Input 100 KΩ

DISP0_DAT7 H6 NVCC_LCD GPIO ALT1 GPIO-4 gpio4_GPIO[28] Input 100 KΩ

DISP0_DAT8 G6 NVCC_LCD GPIO ALT1 GPIO-4 gpio4_GPIO[29] Input 100 KΩ

DISP0_DAT9 E2 NVCC_LCD GPIO ALT1 GPIO-4 gpio4_GPIO[30] Input 100 KΩ

DRAM_A0 M19 NVCC_EMI_DRAM DDR3 ALT0 EXTMC emi_DRAM_A[0] Output Low

DRAM_A1 L21 NVCC_EMI_DRAM DDR3 ALT0 EXTMC emi_DRAM_A[1] Output Low

DRAM_A10 K19 NVCC_EMI_DRAM DDR3 ALT0 EXTMC emi_DRAM_A[1

Output Low

DRAM_A11 L22 NVCC_EMI_DRAM DDR3 ALT0 EXTMC emi_DRAM_A[1

Output Low

DRAM_A12 L20 NVCC_EMI_DRAM DDR3 ALT0 EXTMC emi_DRAM_A[1

Output Low

DRAM_A13 L23 NVCC_EMI_DRAM DDR3 ALT0 EXTMC emi_DRAM_A[1

Output Low

DRAM_A14 N18 NVCC_EMI_DRAM DDR3 ALT0 EXTMC emi_DRAM_A[1

Output Low

DRAM_A15 M18 NVCC_EMI_DRAM DDR3 ALT0 EXTMC emi_DRAM_A[1

Output Low

DRAM_A2 M20 NVCC_EMI_DRAM DDR3 ALT0 EXTMC emi_DRAM_A[2] Output Low

Table 111. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)

Contact Name Contact

Assignment Power Rail I/O Buffer

Type

Out of Reset Condition1

Alt.

Mode

Block

Instance Block I/O Direction Config.

Value

i.MX53 Applications Processors for Industrial Products, Rev. 7

152 Freescale Semiconductor

Package Information and Contact Assignments

DRAM_A3 N20 NVCC_EMI_DRAM DDR3 ALT0 EXTMC emi_DRAM_A[3] Output Low

DRAM_A4 K20 NVCC_EMI_DRAM DDR3 ALT0 EXTMC emi_DRAM_A[4] Output Low

DRAM_A5 N21 NVCC_EMI_DRAM DDR3 ALT0 EXTMC emi_DRAM_A[5] Output Low

DRAM_A6 M22 NVCC_EMI_DRAM DDR3 ALT0 EXTMC emi_DRAM_A[6] Output Low

DRAM_A7 N22 NVCC_EMI_DRAM DDR3 ALT0 EXTMC emi_DRAM_A[7] Output Low

DRAM_A8 N23 NVCC_EMI_DRAM DDR3 ALT0 EXTMC emi_DRAM_A[8] Output Low

DRAM_A9 M21 NVCC_EMI_DRAM DDR3 ALT0 EXTMC emi_DRAM_A[9] Output Low

DRAM_CALIBRA

TION

M23 NVCC_EMI_DRAM special — — (used in DRAM

driver

calibration. See

Section 3.1,

“Special Signal

Considerations”)

Input —

DRAM_CAS L18 NVCC_EMI_DRAM DDR3 ALT0 EXTMC emi_DRAM_CA

Output High

DRAM_CS0 K18 NVCC_EMI_DRAM DDR3 ALT0 EXTMC emi_DRAM_CS[

Output High

DRAM_CS1 P19 NVCC_EMI_DRAM DDR3 ALT0 EXTMC emi_DRAM_CS[

Output High

DRAM_D0 H20 NVCC_EMI_DRAM DDR3 ALT0 EXTMC emi_DRAM_D[0

]

Output High

DRAM_D1 G21 NVCC_EMI_DRAM DDR3 ALT0 EXTMC emi_DRAM_D[1

]

Output High

DRAM_D10 E22 NVCC_EMI_DRAM DDR3 ALT0 EXTMC emi_DRAM_D[1

Output High

DRAM_D11 D20 NVCC_EMI_DRAM DDR3 ALT0 EXTMC emi_DRAM_D[1

Output High

DRAM_D12 E23 NVCC_EMI_DRAM DDR3 ALT0 EXTMC emi_DRAM_D[1

Output High

DRAM_D13 C23 NVCC_EMI_DRAM DDR3 ALT0 EXTMC emi_DRAM_D[1

Output High

DRAM_D14 F23 NVCC_EMI_DRAM DDR3 ALT0 EXTMC emi_DRAM_D[1

Output High

DRAM_D15 C22 NVCC_EMI_DRAM DDR3 ALT0 EXTMC emi_DRAM_D[1

Output High

DRAM_D16 U20 NVCC_EMI_DRAM DDR3 ALT0 EXTMC emi_DRAM_D[1

Output High

Table 111. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)

Contact Name Contact

Assignment Power Rail I/O Buffer

Type

Out of Reset Condition1

Alt.

Mode

Block

Instance Block I/O Direction Config.

Value

Package Information and Contact Assignments

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 153

DRAM_D17 T21 NVCC_EMI_DRAM DDR3 ALT0 EXTMC emi_DRAM_D[1

Output High

DRAM_D18 U21 NVCC_EMI_DRAM DDR3 ALT0 EXTMC emi_DRAM_D[1

Output High

DRAM_D19 R21 NVCC_EMI_DRAM DDR3 ALT0 EXTMC emi_DRAM_D[1

Output High

DRAM_D2 J21 NVCC_EMI_DRAM DDR3 ALT0 EXTMC emi_DRAM_D[2

]

Output High

DRAM_D20 U23 NVCC_EMI_DRAM DDR3 ALT0 EXTMC emi_DRAM_D[2

Output High

DRAM_D21 R22 NVCC_EMI_DRAM DDR3 ALT0 EXTMC emi_DRAM_D[2

Output High

DRAM_D22 U22 NVCC_EMI_DRAM DDR3 ALT0 EXTMC emi_DRAM_D[2

Output High

DRAM_D23 R23 NVCC_EMI_DRAM DDR3 ALT0 EXTMC emi_DRAM_D[2

Output High

DRAM_D24 Y20 NVCC_EMI_DRAM DDR3 ALT0 EXTMC emi_DRAM_D[2

Output High

DRAM_D25 W21 NVCC_EMI_DRAM DDR3 ALT0 EXTMC emi_DRAM_D[2

Output High

DRAM_D26 Y21 NVCC_EMI_DRAM DDR3 ALT0 EXTMC emi_DRAM_D[2

Output High

DRAM_D27 W22 NVCC_EMI_DRAM DDR3 ALT0 EXTMC emi_DRAM_D[2

Output High

DRAM_D28 AA23 NVCC_EMI_DRAM DDR3 ALT0 EXTMC emi_DRAM_D[2

Output High

DRAM_D29 V23 NVCC_EMI_DRAM DDR3 ALT0 EXTMC emi_DRAM_D[2

Output High

DRAM_D3 G20 NVCC_EMI_DRAM DDR3 ALT0 EXTMC emi_DRAM_D[3

]

Output High

DRAM_D30 AA22 NVCC_EMI_DRAM DDR3 ALT0 EXTMC emi_DRAM_D[3

Output High

DRAM_D31 W23 NVCC_EMI_DRAM DDR3 ALT0 EXTMC emi_DRAM_D[3

Output High

DRAM_D4 J23 NVCC_EMI_DRAM DDR3 ALT0 EXTMC emi_DRAM_D[4

]

Output High

DRAM_D5 G23 NVCC_EMI_DRAM DDR3 ALT0 EXTMC emi_DRAM_D[5

]

Output High

Table 111. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)

Contact Name Contact

Assignment Power Rail I/O Buffer

Type

Out of Reset Condition1

Alt.

Mode

Block

Instance Block I/O Direction Config.

Value

i.MX53 Applications Processors for Industrial Products, Rev. 7

154 Freescale Semiconductor

Package Information and Contact Assignments

DRAM_D6 J22 NVCC_EMI_DRAM DDR3 ALT0 EXTMC emi_DRAM_D[6

]

Output High

DRAM_D7 G22 NVCC_EMI_DRAM DDR3 ALT0 EXTMC emi_DRAM_D[7

]

Output High

DRAM_D8 E21 NVCC_EMI_DRAM DDR3 ALT0 EXTMC emi_DRAM_D[8

]

Output High

DRAM_D9 D21 NVCC_EMI_DRAM DDR3 ALT0 EXTMC emi_DRAM_D[9

]

Output High

DRAM_DQM0 H21 NVCC_EMI_DRAM DDR3 ALT0 EXTMC emi_DRAM_DQ

M[0]

Output Low

DRAM_DQM1 E20 NVCC_EMI_DRAM DDR3 ALT0 EXTMC emi_DRAM_DQ

M[1]

Output Low

DRAM_DQM2 T20 NVCC_EMI_DRAM DDR3 ALT0 EXTMC emi_DRAM_DQ

M[2]

Output Low

DRAM_DQM3 W20 NVCC_EMI_DRAM DDR3 ALT0 EXTMC emi_DRAM_DQ

M[3]

Output Low

DRAM_RAS J19 NVCC_EMI_DRAM DDR3 ALT0 EXTMC emi_DRAM_RA

Output High

DRAM_RESET P18 NVCC_EMI_DRAM DDR3 ALT0 EXTMC emi_DRAM_RE

SET

Output Low

DRAM_SDBA0 R19 NVCC_EMI_DRAM DDR3 ALT0 EXTMC emi_DRAM_SD

BA[0]

Output Low

DRAM_SDBA1 P20 NVCC_EMI_DRAM DDR3 ALT0 EXTMC emi_DRAM_SD

BA[1]

Output Low

DRAM_SDBA2 N19 NVCC_EMI_DRAM DDR3 ALT0 EXTMC emi_DRAM_SD

BA[2]

Output Low

DRAM_SDCKE0 H19 NVCC_EMI_DRAM DDR3 ALT0 EXTMC emi_DRAM_SD

CKE[0]

Output Low

DRAM_SDCKE1 T19 NVCC_EMI_DRAM DDR3 ALT0 EXTMC emi_DRAM_SD

CKE[1]

Output Low

DRAM_SDCLK_

K23 NVCC_EMI_DRAM DDR3CLK ALT0 EXTMC emi_DRAM_SD

CLK0

Output Floating

DRAM_SDCLK_

0_B

K22 NVCC_EMI_DRAM DDR3CLK ALT0 EXTMC emi_DRAM_SD

CLK0_B

Output Floating

DRAM_SDCLK_

P22 NVCC_EMI_DRAM DDR3CLK ALT0 EXTMC emi_DRAM_SD

CLK1

Output Floating

DRAM_SDCLK_

1_B

P23 NVCC_EMI_DRAM DDR3CLK ALT0 EXTMC emi_DRAM_SD

CLK1_B

Output Floating

Table 111. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)

Contact Name Contact

Assignment Power Rail I/O Buffer

Type

Out of Reset Condition1

Alt.

Mode

Block

Instance Block I/O Direction Config.

Value

Package Information and Contact Assignments

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 155

DRAM_SDODT0 J18 NVCC_EMI_DRAM DDR3 ALT0 EXTMC emi_DRAM_OD

T[0]

Output Low

DRAM_SDODT1 R18 NVCC_EMI_DRAM DDR3 ALT0 EXTMC emi_DRAM_OD

T[1]

Output Low

DRAM_SDQS0 H23 NVCC_EMI_DRAM DDR3CLK ALT0 EXTMC emi_DRAM_SD

QS[0]

Input Low

DRAM_SDQS0_

H22 NVCC_EMI_DRAM DDR3CLK ALT0 EXTMC emi_DRAM_SD

QS_B[0]

Input High

DRAM_SDQS1 D23 NVCC_EMI_DRAM DDR3CLK ALT0 EXTMC emi_DRAM_SD

QS[1]

Input Low

DRAM_SDQS1_

D22 NVCC_EMI_DRAM DDR3CLK ALT0 EXTMC emi_DRAM_SD

QS_B[1]

Input High

DRAM_SDQS2 T22 NVCC_EMI_DRAM DDR3CLK ALT0 EXTMC emi_DRAM_SD

QS[2]

Input Low

DRAM_SDQS2_

T23 NVCC_EMI_DRAM DDR3CLK ALT0 EXTMC emi_DRAM_SD

QS_B[2]

Input High

DRAM_SDQS3 Y22 NVCC_EMI_DRAM DDR3CLK ALT0 EXTMC emi_DRAM_SD

QS[3]

Input Low

DRAM_SDQS3_

Y23 NVCC_EMI_DRAM DDR3CLK ALT0 EXTMC emi_DRAM_SD

QS_B[3]

Input High

DRAM_SDWE L19 NVCC_EMI_DRAM DDR3 ALT0 EXTMC emi_DRAM_SD

Output High

ECKIL AC10 NVCC_SRTC_POW ANALOG — SRTC ECKIL {no block

I/O by this name

in RM}

——

EIM_A16 AA5 NVCC_EIM_MAIN UHVIO ALT0 EXTMC emi_EIM_A[16] Output2—

EIM_A17 V7 NVCC_EIM_MAIN UHVIO ALT0 EXTMC emi_EIM_A[17] Output2—

EIM_A18 AB3 NVCC_EIM_MAIN UHVIO ALT0 EXTMC emi_EIM_A[18] Output2—

EIM_A19 W7 NVCC_EIM_MAIN UHVIO ALT0 EXTMC emi_EIM_A[19] Output2—

EIM_A20 Y6 NVCC_EIM_MAIN UHVIO ALT0 EXTMC emi_EIM_A[20] Output2—

EIM_A21 AA4 NVCC_EIM_MAIN UHVIO ALT0 EXTMC emi_EIM_A[21] Output2—

EIM_A22 AA3 NVCC_EIM_MAIN UHVIO ALT0 EXTMC emi_EIM_A[22] Output2—

EIM_A23 V6 NVCC_EIM_MAIN UHVIO ALT0 EXTMC emi_EIM_A[23] Output —

EIM_A24 Y5 NVCC_EIM_MAIN UHVIO ALT0 EXTMC emi_EIM_A[24] Output —

EIM_A25 W6 NVCC_EIM_MAIN UHVIO ALT0 EXTMC emi_EIM_A[25] Output —

EIM_BCLK W11 NVCC_EIM_MAIN UHVIO ALT0 EXTMC emi_EIM_BCLK Output —

Table 111. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)

Contact Name Contact

Assignment Power Rail I/O Buffer

Type

Out of Reset Condition1

Alt.

Mode

Block

Instance Block I/O Direction Config.

Value

i.MX53 Applications Processors for Industrial Products, Rev. 7

156 Freescale Semiconductor

Package Information and Contact Assignments

EIM_CS0 W8 NVCC_EIM_MAIN UHVIO ALT0 EXTMC emi_EIM_CS[0] Output —

EIM_CS1 Y7 NVCC_EIM_MAIN UHVIO ALT0 EXTMC emi_EIM_CS[1] Output —

EIM_D16 U6 NVCC_EIM_SEC UHVIO ALT1 GPIO-3 gpio3_GPIO[16] Input 100 KΩ

EIM_D17 U5 NVCC_EIM_SEC UHVIO ALT1 GPIO-3 gpio3_GPIO[17] Input 100 KΩ

EIM_D18 V1 NVCC_EIM_SEC UHVIO ALT1 GPIO-3 gpio3_GPIO[18] Input 100 KΩ

EIM_D19 V2 NVCC_EIM_SEC UHVIO ALT1 GPIO-3 gpio3_GPIO[19] Input 100 KΩ

EIM_D20 W1 NVCC_EIM_SEC UHVIO ALT1 GPIO-3 gpio3_GPIO[20] Input 100 KΩ

EIM_D21 V3 NVCC_EIM_SEC UHVIO ALT1 GPIO-3 gpio3_GPIO[21] Input 100 KΩ

EIM_D22 W2 NVCC_EIM_SEC UHVIO ALT1 GPIO-3 gpio3_GPIO[22] Input 360 KΩ

EIM_D23 Y1 NVCC_EIM_SEC UHVIO ALT1 GPIO-3 gpio3_GPIO[23] Input 100 KΩ

EIM_D24 Y2 NVCC_EIM_SEC UHVIO ALT1 GPIO-3 gpio3_GPIO[24] Input 100 KΩ

EIM_D25 W3 NVCC_EIM_SEC UHVIO ALT1 GPIO-3 gpio3_GPIO[25] Input 100 KΩ

EIM_D26 V5 NVCC_EIM_SEC UHVIO ALT1 GPIO-3 gpio3_GPIO[26] Input 100 KΩ

EIM_D27 V4 NVCC_EIM_SEC UHVIO ALT1 GPIO-3 gpio3_GPIO[27] Input 100 KΩ

EIM_D28 AA1 NVCC_EIM_SEC UHVIO ALT1 GPIO-3 gpio3_GPIO[28] Input 100 KΩ

EIM_D29 AA2 NVCC_EIM_SEC UHVIO ALT1 GPIO-3 gpio3_GPIO[29] Input 100 KΩ

EIM_D30 W4 NVCC_EIM_SEC UHVIO ALT1 GPIO-3 gpio3_GPIO[30] Input 100 KΩ

EIM_D31 W5 NVCC_EIM_SEC UHVIO ALT1 GPIO-3 gpio3_GPIO[31] Input 360 KΩ

EIM_DA0 Y8 NVCC_EIM_MAIN UHVIO ALT0 EXTMC emi_NAND_EIM

_DA[0]

Input2100 KΩ

EIM_DA1 AC4 NVCC_EIM_MAIN UHVIO ALT0 EXTMC emi_NAND_EIM

_DA[1]

Input2100 KΩ

Table 111. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)

Contact Name Contact

Assignment Power Rail I/O Buffer

Type

Out of Reset Condition1

Alt.

Mode

Block

Instance Block I/O Direction Config.

Value

Package Information and Contact Assignments

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 157

EIM_DA10 AB7 NVCC_EIM_MAIN UHVIO ALT0 EXTMC emi_NAND_EIM

_DA[10]

Input2100 KΩ

EIM_DA11 AC6 NVCC_EIM_MAIN UHVIO ALT0 EXTMC emi_NAND_EIM

_DA[11]

Input 100 KΩ

EIM_DA12 V10 NVCC_EIM_MAIN UHVIO ALT0 EXTMC emi_NAND_EIM

_DA[12]

Input 100 KΩ

EIM_DA13 AC7 NVCC_EIM_MAIN UHVIO ALT0 EXTMC emi_NAND_EIM

_DA[13]

Input 100 KΩ

EIM_DA14 Y10 NVCC_EIM_MAIN UHVIO ALT0 EXTMC emi_NAND_EIM

_DA[14]

Input 100 KΩ

EIM_DA15 AA9 NVCC_EIM_MAIN UHVIO ALT0 EXTMC emi_NAND_EIM

_DA[15]

Input 100 KΩ

EIM_DA2 AA7 NVCC_EIM_MAIN UHVIO ALT0 EXTMC emi_NAND_EIM

_DA[2]

Input2100 KΩ

EIM_DA3 W9 NVCC_EIM_MAIN UHVIO ALT0 EXTMC emi_NAND_EIM

_DA[3]

Input2100 KΩ

EIM_DA4 AB6 NVCC_EIM_MAIN UHVIO ALT0 EXTMC emi_NAND_EIM

_DA[4]

Input2100 KΩ

EIM_DA5 V9 NVCC_EIM_MAIN UHVIO ALT0 EXTMC emi_NAND_EIM

_DA[5]

Input2100 KΩ

EIM_DA6 Y9 NVCC_EIM_MAIN UHVIO ALT0 EXTMC emi_NAND_EIM

_DA[6]

Input2100 KΩ

EIM_DA7 AC5 NVCC_EIM_MAIN UHVIO ALT0 EXTMC emi_NAND_EIM

_DA[7]

Input2100 KΩ

EIM_DA8 AA8 NVCC_EIM_MAIN UHVIO ALT0 EXTMC emi_NAND_EIM

_DA[8]

Input2100 KΩ

EIM_DA9 W10 NVCC_EIM_MAIN UHVIO ALT0 EXTMC emi_NAND_EIM

_DA[9]

Input2100 KΩ

EIM_EB0 AC3 NVCC_EIM_MAIN UHVIO ALT0 EXTMC emi_EIM_EB[0] Output2—

EIM_EB1 AB5 NVCC_EIM_MAIN UHVIO ALT0 EXTMC emi_EIM_EB[1] Output2—

EIM_EB2 Y3 NVCC_EIM_MAIN UHVIO ALT1 GPIO-2 gpio2_GPIO[30] Input 100 KΩ

EIM_EB3 Y4 NVCC_EIM_MAIN UHVIO ALT1 GPIO-2 gpio2_GPIO[31] Input 100 KΩ

EIM_LBA AA6 NVCC_EIM_MAIN UHVIO ALT0 EXTMC emi_EIM_LBA Output2—

EIM_OE V8 NVCC_EIM_MAIN UHVIO ALT0 EXTMC emi_EIM_OE Output —

EIM_RW AB4 NVCC_EIM_MAIN UHVIO ALT0 EXTMC emi_EIM_RW Output —

Table 111. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)

Contact Name Contact

Assignment Power Rail I/O Buffer

Type

Out of Reset Condition1

Alt.

Mode

Block

Instance Block I/O Direction Config.

Value

i.MX53 Applications Processors for Industrial Products, Rev. 7

158 Freescale Semiconductor

Package Information and Contact Assignments

EIM_WAIT AB9 NVCC_EIM_MAIN UHVIO ALT0 EXTMC emi_EIM_WAIT Output —

EXTAL AB11 NVCC_XTAL ANALOG — EXTALO

EXTAL — —

FASTR_ANA E18 NVCC_CKIH ANALOG — — (reserved, tie to

ground)

——

FASTR_DIG E17 NVCC_CKIH ANALOG — — (reserved, tie to

ground)

——

FEC_CRS_DV D11 NVCC_FEC UHVIO ALT1 GPIO-1 gpio1_GPIO[25] Input 100 KΩ

FEC_MDC E10 NVCC_FEC UHVIO ALT1 GPIO-1 gpio1_GPIO[31] Input 100 KΩ

FEC_MDIO D12 NVCC_FEC UHVIO ALT1 GPIO-1 gpio1_GPIO[22] Input 100 KΩ

FEC_REF_CLK E12 NVCC_FEC UHVIO ALT1 GPIO-1 gpio1_GPIO[23] Input 100 KΩ

FEC_RX_ER F12 NVCC_FEC UHVIO ALT1 GPIO-1 gpio1_GPIO[24] Input 100 KΩ

FEC_RXD0 C11 NVCC_FEC UHVIO ALT1 GPIO-1 gpio1_GPIO[27] Input 100 KΩ

FEC_RXD1 E11 NVCC_FEC UHVIO ALT1 GPIO-1 gpio1_GPIO[26] Input 100 KΩ

FEC_TX_EN C10 NVCC_FEC UHVIO ALT1 GPIO-1 gpio1_GPIO[28] Input 360 KΩ

FEC_TXD0 F10 NVCC_FEC UHVIO ALT1 GPIO-1 gpio1_GPIO[30] Input 100 KΩ

FEC_TXD1 D10 NVCC_FEC UHVIO ALT1 GPIO-1 gpio1_GPIO[29] Input 100 KΩ

GPIO_0 C8 NVCC_GPIO UHVIO ALT1 GPIO-1 gpio1_GPIO[0] Input 360 KΩ

GPIO_1 B7 NVCC_GPIO UHVIO ALT1 GPIO-1 gpio1_GPIO[1] Input 360 KΩ

GPIO_10 W16 TVDAC_AHVDDRG

GPIO ALT0 GPIO-4 gpio4_GPIO[0] Input 100 KΩ

GPIO_11 V17 TVDAC_AHVDDRG

GPIO ALT0 GPIO-4 gpio4_GPIO[1] Input 100 KΩ

GPIO_12 W17 TVDAC_AHVDDRG

GPIO ALT0 GPIO-4 gpio4_GPIO[2] Input 100 KΩ

Table 111. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)

Contact Name Contact

Assignment Power Rail I/O Buffer

Type

Out of Reset Condition1

Alt.

Mode

Block

Instance Block I/O Direction Config.

Value

Package Information and Contact Assignments

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 159

GPIO_13 AA18 TVDAC_AHVDDRG

GPIO ALT0 GPIO-4 gpio4_GPIO[3] Input 100 KΩ

GPIO_14 W18 TVDAC_AHVDDRG

GPIO ALT0 GPIO-4 gpio4_GPIO[4] Input 100 KΩ

GPIO_16 C6 NVCC_GPIO UHVIO ALT1 GPIO-7 gpio7_GPIO[11] Input 360 KΩ

GPIO_17 A3 NVCC_GPIO UHVIO ALT1 GPIO-7 gpio7_GPIO[12] Input 360 KΩ

GPIO_18 D7 NVCC_GPIO UHVIO ALT1 GPIO-7 gpio7_GPIO[13] Input 360 KΩ

GPIO_19 B4 NVCC_KEYPAD UHVIO ALT1 GPIO-4 gpio4_GPIO[5] Input3100 KΩ

GPIO_2 C7 NVCC_GPIO UHVIO ALT1 GPIO-1 gpio1_GPIO[2] Input 360 KΩ

GPIO_3 A6 NVCC_GPIO UHVIO ALT1 GPIO-1 gpio1_GPIO[3] Input 360 KΩ

GPIO_4 D8 NVCC_GPIO UHVIO ALT1 GPIO-1 gpio1_GPIO[4] Input 100 KΩ

GPIO_5 A5 NVCC_GPIO UHVIO ALT1 GPIO-1 gpio1_GPIO[5] Input 360 KΩ

GPIO_6 B6 NVCC_GPIO UHVIO ALT1 GPIO-1 gpio1_GPIO[6] Input 360 KΩ

GPIO_7 A4 NVCC_GPIO UHVIO ALT1 GPIO-1 gpio1_GPIO[7] Input 360 KΩ

GPIO_8 B5 NVCC_GPIO UHVIO ALT1 GPIO-1 gpio1_GPIO[8] Input 360 KΩ

GPIO_9 E8 NVCC_GPIO UHVIO ALT1 GPIO-1 gpio1_GPIO[9] Input 100 KΩ

JTAG_MOD C9 NVCC_JTAG GPIO ALT0 SJC sjc_MOD Input 100 KΩ

JTAG_TCK D9 NVCC_JTAG GPIO ALT0 SJC sjc_TCK Input 100 KΩ

JTAG_TDI B8 NVCC_JTAG GPIO ALT0 SJC sjc_TDI Input 47 KΩ

JTAG_TDO A7 NVCC_JTAG GPIO ALT0 SJC sjc_TDO Input Keeper

JTAG_TMS A8 NVCC_JTAG GPIO ALT0 SJC sjc_TMS Input 47 KΩ

Table 111. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)

Contact Name Contact

Assignment Power Rail I/O Buffer

Type

Out of Reset Condition1

Alt.

Mode

Block

Instance Block I/O Direction Config.

Value

i.MX53 Applications Processors for Industrial Products, Rev. 7

160 Freescale Semiconductor

Package Information and Contact Assignments

JTAG_TRSTB E9 NVCC_JTAG GPIO ALT0 SJC sjc_TRSTB Input 47 KΩ

KEY_COL0 C5 NVCC_KEYPAD UHVIO ALT1 GPIO-4 gpio4_GPIO[6] Input4100 KΩ

KEY_COL1 E7 NVCC_KEYPAD UHVIO ALT1 GPIO-4 gpio4_GPIO[8] Input 100 KΩ

KEY_COL2 C4 NVCC_KEYPAD UHVIO ALT1 GPIO-4 gpio4_GPIO[10] Input 100 KΩ

KEY_COL3 F6 NVCC_KEYPAD UHVIO ALT1 GPIO-4 gpio4_GPIO[12] Input 100 KΩ

KEY_COL4 E5 NVCC_KEYPAD UHVIO ALT1 GPIO-4 gpio4_GPIO[14] Input 100 KΩ

KEY_ROW0 B3 NVCC_KEYPAD UHVIO ALT1 GPIO-4 gpio4_GPIO[7] Input 360 KΩ

KEY_ROW1 D6 NVCC_KEYPAD UHVIO ALT1 GPIO-4 gpio4_GPIO[9] Input 100 KΩ

KEY_ROW2 D5 NVCC_KEYPAD UHVIO ALT1 GPIO-4 gpio4_GPIO[11] Input 100 KΩ

KEY_ROW3 D4 NVCC_KEYPAD UHVIO ALT1 GPIO-4 gpio4_GPIO[13] Input 100 KΩ

KEY_ROW4 E6 NVCC_KEYPAD UHVIO ALT1 GPIO-4 gpio4_GPIO[15] Input 360 KΩ

LVDS_BG_RES AA14 NVCC_LVDS_BG ANALOG — LDB LVDS_BG_RES — —

LVDS0_CLK_N AB16 NVCC_LVDS LVDS ALT0 GPIO-7 gpio7_GPI[25] Input Floating

LVDS0_CLK_P AC16 NVCC_LVDS LVDS ALT0 GPIO-7 gpio7_GPI[24] Input Floating

LVDS0_TX0_N Y17 NVCC_LVDS LVDS ALT0 GPIO-7 gpio7_GPI[31] Input Floating

LVDS0_TX0_P AA17 NVCC_LVDS LVDS ALT0 GPIO-7 gpio7_GPI[30] Input Floating

LVDS0_TX1_N AB17 NVCC_LVDS LVDS ALT0 GPIO-7 gpio7_GPI[29] Input Floating

LVDS0_TX1_P AC17 NVCC_LVDS LVDS ALT0 GPIO-7 gpio7_GPI[28] Input Floating

LVDS0_TX2_N Y16 NVCC_LVDS LVDS ALT0 GPIO-7 gpio7_GPI[27] Input Floating

LVDS0_TX2_P AA16 NVCC_LVDS LVDS ALT0 GPIO-7 gpio7_GPI[26] Input Floating

LVDS0_TX3_N AB15 NVCC_LVDS LVDS ALT0 GPIO-7 gpio7_GPI[23] Input Floating

LVDS0_TX3_P AC15 NVCC_LVDS LVDS ALT0 GPIO-7 gpio7_GPI[22] Input Floating

LVDS1_CLK_N AA13 NVCC_LVDS LVDS ALT0 GPIO-6 gpio6_GPI[27] Input Floating

LVDS1_CLK_P Y13 NVCC_LVDS LVDS ALT0 GPIO-6 gpio6_GPI[26] Input Floating

Table 111. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)

Contact Name Contact

Assignment Power Rail I/O Buffer

Type

Out of Reset Condition1

Alt.

Mode

Block

Instance Block I/O Direction Config.

Value

Package Information and Contact Assignments

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 161

LVDS1_TX0_N AC14 NVCC_LVDS LVDS ALT0 GPIO-6 gpio6_GPI[31] Input Floating

LVDS1_TX0_P AB14 NVCC_LVDS LVDS ALT0 GPIO-6 gpio6_GPI[30] Input Floating

LVDS1_TX1_N AC13 NVCC_LVDS LVDS ALT0 GPIO-6 gpio6_GPI[29] Input Floating

LVDS1_TX1_P AB13 NVCC_LVDS LVDS ALT0 GPIO-6 gpio6_GPI[28] Input Floating

LVDS1_TX2_N AC12 NVCC_LVDS LVDS ALT0 GPIO-6 gpio6_GPI[25] Input Floating

LVDS1_TX2_P AB12 NVCC_LVDS LVDS ALT0 GPIO-6 gpio6_GPI[24] Input Floating

LVDS1_TX3_N AA12 NVCC_LVDS LVDS ALT0 GPIO-6 gpio6_GPI[23] Input Floating

LVDS1_TX3_P Y12 NVCC_LVDS LVDS ALT0 GPIO-6 gpio6_GPI[22] Input Floating

NANDF_ALE Y11 NVCC_NANDF UHVIO ALT1 GPIO-6 gpio6_GPIO[8] Input 100 KΩ

NANDF_CLE AA10 NVCC_NANDF UHVIO ALT1 GPIO-6 gpio6_GPIO[7] Input 100 KΩ

NANDF_CS0 W12 NVCC_NANDF UHVIO ALT1 GPIO-6 gpio6_GPIO[11] Input 100 KΩ

NANDF_CS1 V13 NVCC_NANDF UHVIO ALT1 GPIO-6 gpio6_GPIO[14] Input 100 KΩ

NANDF_CS2 V14 NVCC_NANDF UHVIO ALT1 GPIO-6 gpio6_GPIO[15] Input 100 KΩ

NANDF_CS3 W13 NVCC_NANDF UHVIO ALT1 GPIO-6 gpio6_GPIO[16] Input 100 KΩ

NANDF_RB0 U11 NVCC_NANDF UHVIO ALT1 GPIO-6 gpio6_GPIO[10] Input 100 KΩ

NANDF_RE_B AC8 NVCC_EIM_MAIN UHVIO ALT1 GPIO-6 gpio6_GPIO[13] Input 100 KΩ

NANDF_WE_B AB8 NVCC_EIM_MAIN UHVIO ALT1 GPIO-6 gpio6_GPIO[12] Input 100 KΩ

NANDF_WP_B AC9 NVCC_NANDF UHVIO ALT1 GPIO-6 gpio6_GPIO[9] Input 100 KΩ

PATA_BUFFER_

K4 NVCC_PATA UHVIO ALT1 GPIO-7 gpio7_GPIO[1] Input 100 KΩ

PATA_CS_0 L5 NVCC_PATA UHVIO ALT1 GPIO-7 gpio7_GPIO[9] Input 100 KΩ

PATA_CS_1 L2 NVCC_PATA UHVIO ALT1 GPIO-7 gpio7_GPIO[10] Input 100 KΩ

PATA_DA_0 K6 NVCC_PATA UHVIO ALT1 GPIO-7 gpio7_GPIO[6] Input 100 KΩ

Table 111. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)

Contact Name Contact

Assignment Power Rail I/O Buffer

Type

Out of Reset Condition1

Alt.

Mode

Block

Instance Block I/O Direction Config.

Value

i.MX53 Applications Processors for Industrial Products, Rev. 7

162 Freescale Semiconductor

Package Information and Contact Assignments

PATA_DA_1 L3 NVCC_PATA UHVIO ALT1 GPIO-7 gpio7_GPIO[7] Input 100 KΩ

PATA_DA_2 L4 NVCC_PATA UHVIO ALT1 GPIO-7 gpio7_GPIO[8] Input 100 KΩ

PATA_DATA0 L1 NVCC_PATA UHVIO ALT1 GPIO-2 gpio2_GPIO[0] Input 100 KΩ

PATA_DATA1 M1 NVCC_PATA UHVIO ALT1 GPIO-2 gpio2_GPIO[1] Input 100 KΩ

PATA_DATA10 N4 NVCC_PATA UHVIO ALT1 GPIO-2 gpio2_GPIO[10] Input 100 KΩ

PATA_DATA11 M6 NVCC_PATA UHVIO ALT1 GPIO-2 gpio2_GPIO[11] Input 100 KΩ

PATA_DATA12 N5 NVCC_PATA UHVIO ALT1 GPIO-2 gpio2_GPIO[12] Input 100 KΩ

PATA_DATA13 N6 NVCC_PATA UHVIO ALT1 GPIO-2 gpio2_GPIO[13] Input 100 KΩ

PATA_DATA14 P6 NVCC_PATA UHVIO ALT1 GPIO-2 gpio2_GPIO[14] Input 100 KΩ

PATA_DATA15 P5 NVCC_PATA UHVIO ALT1 GPIO-2 gpio2_GPIO[15] Input 100 KΩ

PATA_DATA2 L6 NVCC_PATA UHVIO ALT1 GPIO-2 gpio2_GPIO[2] Input 100 KΩ

PATA_DATA3 M2 NVCC_PATA UHVIO ALT1 GPIO-2 gpio2_GPIO[3] Input 100 KΩ

PATA_DATA4 M3 NVCC_PATA UHVIO ALT1 GPIO-2 gpio2_GPIO[4] Input 100 KΩ

PATA_DATA5 M4 NVCC_PATA UHVIO ALT1 GPIO-2 gpio2_GPIO[5] Input 100 KΩ

PATA_DATA6 N1 NVCC_PATA UHVIO ALT1 GPIO-2 gpio2_GPIO[6] Input 100 KΩ

PATA_DATA7 M5 NVCC_PATA UHVIO ALT1 GPIO-2 gpio2_GPIO[7] Input 100 KΩ

PATA_DATA8 N2 NVCC_PATA UHVIO ALT1 GPIO-2 gpio2_GPIO[8] Input 100 KΩ

PATA_DATA9 N3 NVCC_PATA UHVIO ALT1 GPIO-2 gpio2_GPIO[9] Input 100 KΩ

PATA_DIOR K3 NVCC_PATA UHVIO ALT1 GPIO-7 gpio7_GPIO[3] Input 100 KΩ

Table 111. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)

Contact Name Contact

Assignment Power Rail I/O Buffer

Type

Out of Reset Condition1

Alt.

Mode

Block

Instance Block I/O Direction Config.

Value

Package Information and Contact Assignments

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 163

PATA_DIOW J3 NVCC_PATA UHVIO ALT1 GPIO-6 gpio6_GPIO[17] Input 100 KΩ

PATA_DMACK J2 NVCC_PATA UHVIO ALT1 GPIO-6 gpio6_GPIO[18] Input 100 KΩ

PATA_DMARQ J1 NVCC_PATA UHVIO ALT1 GPIO-7 gpio7_GPIO[0] Input 100 KΩ

PATA_INTRQ K5 NVCC_PATA UHVIO ALT1 GPIO-7 gpio7_GPIO[2] Input 100 KΩ

PATA_IORDY K1 NVCC_PATA UHVIO ALT1 GPIO-7 gpio7_GPIO[5] Input 100 KΩ

PATA_RESET_B K2 NVCC_PATA UHVIO ALT1 GPIO-7 gpio7_GPIO[4] Input 100 KΩ

PMIC_ON_REQ W14 NVCC_SRTC_POW GPIO ALT0 SRTC srtc_SRTCALAR

Output —

PMIC_STBY_RE

W15 NVCC_SRTC_POW GPIO ALT0 CCM ccm_PMIC_VST

BY_REQ

Output —

POR_B C19 NVCC_RESET LVIO ALT0 SRC src_POR_B Input 100 KΩ

RESET_IN_B A21 NVCC_RESET LVIO ALT0 SRC src_RESET_B Input 100 KΩ

SATA_REFCLKM A14 VPH ANALOG — SATA SATA_REFCLK

——

SATA_REFCLKP B14 VPH ANALOG — SATA SATA_REFCLK

——

SATA_REXT C13 VPH ANALOG — SATA SATA_REXT — —

SATA_RXM A12 VPH ANALOG — SATA SATA_RXM — —

SATA_RXP B12 VPH ANALOG — SATA SATA_RXP — —

SATA_TXM B10 VPH ANALOG — SATA SATA_TXM — —

SATA_TXP A10 VPH ANALOG — SATA SATA_TXP — —

SD1_CLK E16 NVCC_SD1 UHVIO ALT1 GPIO-1 gpio1_GPIO[20] Input 100 KΩ

SD1_CMD F18 NVCC_SD1 UHVIO ALT1 GPIO-1 gpio1_GPIO[18] Input 100 KΩ

SD1_DATA0 A20 NVCC_SD1 UHVIO ALT1 GPIO-1 gpio1_GPIO[16] Input 100 KΩ

SD1_DATA1 C17 NVCC_SD1 UHVIO ALT1 GPIO-1 gpio1_GPIO[17] Input 100 KΩ

Table 111. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)

Contact Name Contact

Assignment Power Rail I/O Buffer

Type

Out of Reset Condition1

Alt.

Mode

Block

Instance Block I/O Direction Config.

Value

i.MX53 Applications Processors for Industrial Products, Rev. 7

164 Freescale Semiconductor

Package Information and Contact Assignments

SD1_DATA2 F17 NVCC_SD1 UHVIO ALT1 GPIO-1 gpio1_GPIO[19] Input 100 KΩ

SD1_DATA3 F16 NVCC_SD1 UHVIO ALT1 GPIO-1 gpio1_GPIO[21] Input 100 KΩ

SD2_CLK E14 NVCC_SD2 UHVIO ALT1 GPIO-1 gpio1_GPIO[10] Input 100 KΩ

SD2_CMD C15 NVCC_SD2 UHVIO ALT1 GPIO-1 gpio1_GPIO[11] Input 100 KΩ

SD2_DATA0 D13 NVCC_SD2 UHVIO ALT1 GPIO-1 gpio1_GPIO[15] Input 100 KΩ

SD2_DATA1 C14 NVCC_SD2 UHVIO ALT1 GPIO-1 gpio1_GPIO[14] Input 100 KΩ

SD2_DATA2 D14 NVCC_SD2 UHVIO ALT1 GPIO-1 gpio1_GPIO[13] Input 100 KΩ

SD2_DATA3 E13 NVCC_SD2 UHVIO ALT1 GPIO-1 gpio1_GPIO[12] Input 100 KΩ

TEST_MODE D17 NVCC_RESET LVIO ALT0 tcu_TEST_MOD

Input 100 KΩ

TVCDC_IOB_BA

AB19 TVDAC_AHVDDRG

ANALOG — TVE TVCDC_IOB_B

ACK

——

TVCDC_IOG_BA

AC20 TVDAC_AHVDDRG

ANALOG — TVE TVCDC_IOG_B

ACK

——

TVCDC_IOR_BA

AB21 TVDAC_AHVDDRG

ANALOG — TVE TVCDC_IOR_B

ACK

——

TVDAC_COMP AA19 TVDAC_AHVDDRG

ANALOG — TVE TVDAC_COMP — —

TVDAC_IOB AC19 TVDAC_AHVDDRG

ANALOG — TVE TVDAC_IOB — —

TVDAC_IOG AB20 TVDAC_AHVDDRG

ANALOG — TVE TVDAC_IOG — —

TVDAC_IOR AC21 TVDAC_AHVDDRG

ANALOG — TVE TVDAC_IOR — —

TVDAC_VREF Y18 TVDAC_AHVDDRG

ANALOG — TVE TVDAC_VREF — —

USB_H1_DN B17 USB_H1_VDDA25,

USB_H1_VDDA33

ANALOG5

— USB USB_H1_DN — —

USB_H1_DP A17 USB_H1_VDDA25,

USB_H1_VDDA33

ANALOG5

— USB USB_H1_DP — —

Table 111. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)

Contact Name Contact

Assignment Power Rail I/O Buffer

Type

Out of Reset Condition1

Alt.

Mode

Block

Instance Block I/O Direction Config.

Value

Package Information and Contact Assignments

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 165

NOTE

KEY_COL0 and GPIO_19 act as output for diagnostic signals during

power-on reset.

USB_H1_GPANA

A16 USB_H1_VDDA25,

USB_H1_VDDA33

ANALOG2

— USB USB_H1_GPAN

AIO

——

USB_H1_RREFE

B16 USB_H1_VDDA25,

USB_H1_VDDA33

ANALOG2

— USB USB_H1_RREF

EXT

——

USB_H1_VBUS D15 USB_H1_VDDA25,

USB_H1_VDDA33

ANALOG5

— USB USB_H1_VBUS — —

USB_OTG_DN A19 USB_OTG_VDDA25

USB_OTG_VDDA33

ANALOG5

— USB USB_OTG_DN — —

USB_OTG_DP B19 USB_OTG_VDDA25

USB_OTG_VDDA33

ANALOG5

— USB USB_OTG_DP — —

USB_OTG_GPA

NAIO

F15 USB_OTG_VDDA25

USB_OTG_VDDA33

ANALOG2

— USB USB_OTG_GPA

NAIO

——

USB_OTG_ID C16 USB_OTG_VDDA25

USB_OTG_VDDA33

ANALOG2

— USB USB_OTG_ID — —

USB_OTG_RRE

FEXT

D16 USB_OTG_VDDA25

USB_OTG_VDDA33

ANALOG2

— USB USB_OTG_RRE

FEXT

——

USB_OTG_VBU

E15 USB_OTG_VDDA25

USB_OTG_VDDA33

ANALOG5

— USB USB_OTG_VBU

——

XTAL AC11 NVCC_XTAL ANALOG — XTALOS

XTAL — —

1The state immediately after reset and before ROM firmware or software has executed.

2During power-on reset, this port acts as input for fuse override. See Section 5.1, “Boot Mode Configuration Pins” for details.

For appropriate resistor values, see Chapter 1 of i.MX53 System Development User's Guide (MX53UG).

3During power-on reset, this port acts as output for diagnostic signal INT_BOOT

4During power-on reset, this port acts as output for diagnostic signal ANY_PU_RST

Table 111. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)

Contact Name Contact

Assignment Power Rail I/O Buffer

Type

Out of Reset Condition1

Alt.

Mode

Block

Instance Block I/O Direction Config.

Value

i.MX53 Applications Processors for Industrial Products, Rev. 7

166 Freescale Semiconductor

Package Information and Contact Assignments

6.1.4 19 x 19 mm, 0.8 mm Pitch Ball Map

Table 112 shows the 19 × 19 mm, 0.8 mm pitch ball map.

Table 112. 19 x 19 mm, 0.8 mm Pitch Ball Map

GND

GPIO_17

GPIO_7

GPIO_5

GPIO_3

JTAG_TDO

JTAG_TMS

VPH

SATA_TXP

GND

SATA_RXM

GND

SATA_REFCLKM

USB_H1_GPANAIO

USB_H1_DP

GND

USB_OTG_DN

SD1_DATA0

RESET_IN_B

GND

SVDDGP

KEY_ROW0

GPIO_19

GPIO_8

GPIO_6

GPIO_1

JTAG_TDI

VPH

SATA_TXM

GND

SATA_RXP

GND

SATA_REFCLKP

USB_H1_RREFEXT

USB_H1_DN

GND

USB_OTG_DP

BOOT_MODE1

CKIH1

SVCC

GND

DISP0_DAT21

DI0_PIN3

DISP0_DAT23

KEY_COL2

KEY_COL0

GPIO_16

GPIO_2

GPIO_0

JTAG_MOD

FEC_TX_EN

FEC_RXD0

GND

SATA_REXT

SD2_DATA1

SD2_CMD

USB_OTG_ID

SD1_DATA1

BOOT_MODE0

POR_B

GND

DRAM_D15

DRAM_D13

DISP0_DAT16

DI0_PIN4

DI0_PIN2

KEY_ROW3

KEY_ROW2

KEY_ROW1

GPIO_18

GPIO_4

JTAG_TCK

FEC_TXD1

FEC_CRS_DV

FEC_MDIO

SD2_DATA0

SD2_DATA2

USB_H1_VBUS

USB_OTG_RREFEXT

TEST_MODE

CKIH2

GND

DRAM_D11

DRAM_D9

DRAM_SDQS1_B

DRAM_SDQS1

DISP0_DAT13

DISP0_DAT9

DISP0_DAT22

DI0_PIN15

KEY_COL4

KEY_ROW4

KEY_COL1

GPIO_9

JTAG_TRSTB

FEC_MDC

FEC_RXD1

FEC_REF_CLK

SD2_DATA3

SD2_CLK

USB_OTG_VBUS

SD1_CLK

FASTR_DIG

FASTR_ANA

GND

DRAM_DQM1

DRAM_D8

DRAM_D10

DRAM_D12

DISP0_DAT3

DISP0_DAT14

DISP0_DAT15

DISP0_DAT20

DISP0_DAT17

KEY_COL3

NVCC_KEYPAD

NVCC_GPIO

VDDAL1

FEC_TXD0

NVCC_FEC

FEC_RX_ER

USB_H1_VDDA25

USB_OTG_VDDA25

USB_OTG_GPANAIO

SD1_DATA3

SD1_DATA2

SD1_CMD

GND

DRAM_D14

Package Information and Contact Assignments

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 167

DISP0_DAT6

DISP0_DAT4

DISP0_DAT10

DISP0_DAT18

DISP0_DAT19

DISP0_DAT8

GND

VDDGP

NVCC_JTAG

VDDGP

VDDA

USB_H1_VDDA33

USB_OTG_VDDA33

VDD_FUSE

VDD_ANA_PLL

NVCC_CKIH

VDD_REG

GND

DRAM_D3

DRAM_D1

DRAM_D7

DRAM_D5

DISP0_DAT12

DISP0_DAT2

DISP0_DAT5

DI0_DISP_CLK

DISP0_DAT11

DISP0_DAT7

VDDGP

GND

VDDGP

GND

VDDGP

GND

VCC

NVCC_SD2

NVCC_SD1

NVCC_RESET

VDD_DIG_PLL

NVCC_EMI_DRAM

DRAM_SDCKE0

DRAM_D0

DRAM_DQM0

DRAM_SDQS0_B

DRAM_SDQS0

PATA_DMARQ

PATA_DMACK

PATA_DIOW

DISP0_DAT1

DISP0_DAT0

NVCC_LCD

VDDGP

GND

VDDGP

GND

VDDGP

GND

VCC

GND

VCC

GND

DRAM_SDODT0

DRAM_RAS

GND

DRAM_D2

DRAM_D6

DRAM_D4

PATA_IORDY

PATA_RESET_B

PATA_DIOR

PATA_BUFFER_EN

PATA_INTRQ

PATA_DA_0

VDDGP

GND

VDDGP

GND

VDDGP

GND

VCC

GND

VCC

GND

NVCC_EMI_DRAM

DRAM_CS0

DRAM_A10

DRAM_A4

GND

DRAM_SDCLK_0_B

DRAM_SDCLK_0

PATA_DATA0

PATA_CS_1

PATA_DA_1

PATA_DA_2

PATA_CS_0

PATA_DATA2

GND

VDDGP

GND

VDDGP

GND

VDDGP

GND

VCC

GND

VCC

DDR_VREF

DRAM_CAS

DRAM_SDWE

DRAM_A12

DRAM_A1

DRAM_A11

DRAM_A13

PATA_DATA1

PATA_DATA3

PATA_DATA4

PATA_DATA5

PATA_DATA7

PATA_DATA11

VDDA

GND

VCC

GND

VCC

GND

VCC

GND

VCC

GND

VDDA

DRAM_A15

DRAM_A0

DRAM_A2

DRAM_A9

DRAM_A6

DRAM_CALIBRATION

PATA_DATA6

PATA_DATA8

PATA_DATA9

PATA_DATA10

PATA_DATA12

PATA_DATA13

NVCC_PATA

VCC

GND

VCC

GND

VCC

GND

VCC

GND

VCC

NVCC_EMI_DRAM

DRAM_A14

DRAM_SDBA2

DRAM_A3

DRAM_A5

DRAM_A7

DRAM_A8

Table 112. 19 x 19 mm, 0.8 mm Pitch Ball Map (continued)

i.MX53 Applications Processors for Industrial Products, Rev. 7

168 Freescale Semiconductor

Package Information and Contact Assignments

CSI0_PIXCLK

CSI0_MCLK

CSI0_DATA_EN

CSI0_VSYNC

PATA_DATA15

PATA_DATA14

GND

VCC

GND

VCC

GND

VCC

GND

VCC

GND

NVCC_EMI_DRAM

DRAM_RESET

DRAM_CS1

DRAM_SDBA1

GND

DRAM_SDCLK_1

DRAM_SDCLK_1_B

CSI0_DAT4

CSI0_DAT5

CSI0_DAT7

CSI0_DAT9

CSI0_DAT10

CSI0_DAT6

NVCC_CSI

VCC

GND

VCC

GND

VCC

GND

VCC

GND

VCC

GND

DRAM_SDODT1

DRAM_SDBA0

GND

DRAM_D19

DRAM_D21

DRAM_D23

CSI0_DAT8

CSI0_DAT11

CSI0_DAT12

CSI0_DAT16

CSI0_DAT17

CSI0_DAT13

VCC

GND

VCC

GND

VCC

NVCC_NANDF

VCC

GND

VCC

GND

VCC

NVCC_EMI_DRAM

DRAM_SDCKE1

DRAM_DQM2

DRAM_D17

DRAM_SDQS2

DRAM_SDQS2_B

CSI0_DAT14

CSI0_DAT15

CSI0_DAT18

CSI0_DAT19

EIM_D17

EIM_D16

NVCC_EIM_SEC

VCC

NVCC_EIM_MAIN

NANDF_RB0

VDDA

NVCC_LVDS

NVCC_LVDS_BG

GND

TVDAC_DHVDD

TVDAC_AHVDDRGB

VCC

GND

DRAM_D16

DRAM_D18

DRAM_D22

DRAM_D20

EIM_D18

EIM_D19

EIM_D21

EIM_D27

EIM_D26

EIM_A23

EIM_A17

EIM_OE

EIM_DA5

EIM_DA12

NVCC_SRTC_POW

NVCC_XTAL

NANDF_CS1

NANDF_CS2

GND

TVDAC_AHVDDRGB

GPIO_11

GND

DRAM_D29

EIM_D20

EIM_D22

EIM_D25

EIM_D30

EIM_D31

EIM_A25

EIM_A19

EIM_CS0

EIM_DA3

EIM_DA9

EIM_BCLK

NANDF_CS0

NANDF_CS3

PMIC_ON_REQ

PMIC_STBY_REQ

GPIO_10

GPIO_12

GPIO_14

GND

DRAM_DQM3

DRAM_D25

DRAM_D27

DRAM_D31

EIM_D23

EIM_D24

EIM_EB2

EIM_EB3

EIM_A24

EIM_A20

EIM_CS1

EIM_DA0

EIM_DA6

EIM_DA14

NANDF_ALE

LVDS1_TX3_P

LVDS1_CLK_P

GND

LVDS0_TX2_N

LVDS0_TX0_N

TVDAC_VREF

GND

DRAM_D24

DRAM_D26

DRAM_SDQS3

DRAM_SDQS3_B

Table 112. 19 x 19 mm, 0.8 mm Pitch Ball Map (continued)

Package Information and Contact Assignments

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 169

EIM_D28

EIM_D29

EIM_A22

EIM_A21

EIM_A16

EIM_LBA

EIM_DA2

EIM_DA8

EIM_DA15

NANDF_CLE

GND

LVDS1_TX3_N

LVDS1_CLK_N

LVDS_BG_RES

GND

LVDS0_TX2_P

LVDS0_TX0_P

GPIO_13

TVDAC_COMP

GND

DRAM_D30

DRAM_D28

GND

EIM_A18

EIM_RW

EIM_EB1

EIM_DA4

EIM_DA10

NANDF_WE_B

EIM_WAIT

CKIL

EXTAL

LVDS1_TX2_P

LVDS1_TX1_P

LVDS1_TX0_P

LVDS0_TX3_N

LVDS0_CLK_N

LVDS0_TX1_N

GND

TVCDC_IOB_BACK

TVDAC_IOG

TVCDC_IOR_BACK

GND

EIM_EB0

EIM_DA1

EIM_DA7

EIM_DA11

EIM_DA13

NANDF_RE_B

NANDF_WP_B

ECKIL

XTAL

LVDS1_TX2_N

LVDS1_TX1_N

LVDS1_TX0_N

LVDS0_TX3_P

LVDS0_CLK_P

LVDS0_TX1_P

GND

TVDAC_IOB

TVCDC_IOG_BACK

TVDAC_IOR

GND

Table 112. 19 x 19 mm, 0.8 mm Pitch Ball Map (continued)

i.MX53 Applications Processors for Industrial Products, Rev. 7

170 Freescale Semiconductor

Revision History

7 Revision History

Table 113 provides a revision history for this data sheet.

Table 113. i.MX53 Data Sheet Document Revision History

Rev.

Number Date Substantive Change(s)

Rev. 7 05/2015 • Updated mask set in Table 1.

• Added SRTC information and note on NVCC_RESET power in Section 4.2.1, “Power-Up Sequence”.

• Added SRTC footnote to Figure 2.

Rev. 6 03/2013 In Table 1, “Ordering Information” removed MCIMX535DVV2C, as it no longer exists.

In Table 6, “i.MX53 Operating Ranges,” updated minimum values of LVDS interface supply

(NVCC_LVDS) and LVDS band gap supply (NVCC_LVDS_BG) to 2.375 volts.

Rev. 5 09/2012 • In Table 1, "Ordering Information," on page 2,” renamed “Features” column as “CPU Frequency.”

•In Section 1.2, “Features:”

—Changed “SATA I” to “SATA II” under Hard disk drives bullet

—Added a new bullet item to mention support for tamper detection mechanism

•In Section 1.2, “Features,” added a new bullet item to mention support for FlexCAN feature.

• Removed the note shown at the end of Section 1.2, “Features.”

•In Table 2, "i.MX53 Digital and Analog Blocks," on page 7, removed details of MPEG2 encoder, as

this is not supported on i.MX53.

•In Table 6, "i.MX53 Operating Ranges," on page 18:

—Changed VDDGP max voltage, for all frequency ranges and for STOP mode, to 1.15 V

—Updated footnote on TVDAC_DHVDD and TVDAC_AHVDDRGB

•In Table 8, "Maximal Supply Currents," on page 20:

—Corrected power line name, MVCC_XTAL, to NVCC_XTAL

—Added a footnote on NVCC_EMI_DRAM

—Updated max current value and added a footnote for power line, NVCC_SRTC_POW

—Removed duplicate entries for NVCC_EMI_DRAM and NVCC_XTAL

•In Section 4.2.3, “Power Supplies Usage,” updated the fourth bullet item.

•In Figure 25, "Asynchronous A/D Muxed Write Access," on page 58, renamed “WE41” as “WE41A”

and shifted its position to left.

•In Table 57, "Camera Input Signal Cross Reference, Format and Bits Per Cycle," on page 80, added

a footnote on “YCbCr 8 bits 2 cycles” column header.

Rev. 4 11/2011 • In Section 1, “Introduction,” changed 1 GHz to 1.2 GHz in the second paragraph and updated the

bulleted list after the second paragraph.

•In Table 1, "Ordering Information," on page 2:

—Removed part numbers “PCIMX535DVV1C” and “MCIMX538DZK1C”

—Added a new part number “MCIMX535DVV2C”

—Updated package information for part number “PCIMX538DZK1C”

—Updated the second footnote

•In Section 1.2, “Features,” changed “Target frequency” to “Maximum frequency” and 1 GHz to 1–1.2

GHz in the third bullet item of the first bulleted list.

•In Table 2, "i.MX53 Digital and Analog Blocks," on page 7, removed “Sorenson H.263 decode, 4CIF

resolution, 8 Mbps bit rate” from VPU brief description.

•In Table 4, "Absolute Maximum Ratings," on page 16, changed the maximum voltage for VDDGP

from 1.35V to 1.4V.

•In Table 6, "i.MX53 Operating Ranges," on page 18:

—Added a row and a footnote for “ARM core supply voltage fARM ≤ 1200 MHz” parameter of VDDGP

—Added a new footnote for “Peripheral supply voltage” parameter of VCC

—Updated the footnote for “Junction temperature” parameter

(continued on next page)

Revision History

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 171

Rev. 4 11/2011 • In Section 1, “Introduction,” added a new bullet item, Applications processor, to the bulleted list that

contains features of the i.MX53 processor.

•In Section 1.2, “Features,” changed “Target frequency” to “Maximum frequency” and added a new

bullet item to mention support for the DVFS feature.

•In Section 2.1, “Block Diagram,” added Figure 1, "i.MX53 System Block Diagram," on page 6.

•In Table 2, "i.MX53 Digital and Analog Blocks," on page 7, removed “Sorenson H.263 decode, 4CIF

resolution, 8 Mbps bit rate” from VPU brief description.

• Added a note after Section 4.2.1, “Power-Up Sequence,” cross-referencing i.MX53 System

Development User’s Guide.

•In Table 10, "GPIO I/O DC Electrical Characteristics," on page 27:

—Changed test condition “Iout = -1 mA” to “Iout = -0.8 mA” in the first row

—Removed test condition “Iout= specified Ioh Drive” from the first row

—Removed “0.8 x OVDD” from the Min column of the first row

—Changed test condition “Iout = 1 mA” to “Iout = 0.8 mA” in the second row

—Removed test condition “Iout= specified Iol Drive” from the second row

—Removed “0.2 x OVDD” from the Max column of the second row

—Removed rows 3–6

—Changed the max value for Iin at condition “Vin = OVDD or 0” in row 12 from 2 μA to 10 μA

—Changed the max value for Iin at condition “Vin = OVDD” in rows 13–15 from 2 μA to 10 μA

—Changed the max value for Iin at condition “Vin = 0 V” in row 15 from 36 μA to 40 μA

—Changed the max value for Iin at condition “Vin = 0 V” in row 16 from 2 μA to 10 μA

—Changed the max value for Iin at condition “Vin = OVDD” in row 16 from 36 μA to 40 μA

•In Table 11, "DDR2 I/O DC Electrical Parameters," on page 28:

—Added test condition “Ioh = -0.1 mA” in the first row

—Added test condition “Iol = 0.1 mA” in the second row

—Removed rows 3–4

•In Section 4, “Electrical Characteristics,” removed the note appearing after the first paragraph.

•In Section 4.2.1, “Power-Up Sequence,” updated the fifth bullet item to specify that VDD_ANA_PLL

can be used to power NVCC_CKIH and NVCC_RESET.

•In Section 4.3.2.2, “LPDDR2 Mode I/O DC Parameters,” added the sentence “The parameters in

Table 12 are guaranteed per the operating ranges in Tab le 6 , unless otherwise noted.” before

Table 12.

•In Table 12, "LPDDR2 I/O DC Electrical Parameters," on page 29:

—Added test condition “Ioh = -0.1 mA” in the first row

—Added test condition “Iol = 0.1 mA” in the second row

•In Table 13, "DDR3 I/O DC Electrical Parameters," on page 29:

—Added test condition “Ioh = -0.1 mA” in the first row

—Added test condition “Iol = 0.1 mA” in the second row

•In Table 14, "LVIO DC Electrical Characteristics," on page 30:

—Added test condition “Ioh = -0.8 mA” in the first row

—Added test condition “Iol = 0.8 mA” in the second row

•In Table 15, "UHVIO DC Electrical Characteristics," on page 31:

—Changed test condition “Iout = -1 mA” to “Iout = -0.8 mA” in the first row

—Removed test condition “Iout= specified Ioh Drive” from the first row

—Removed “0.8 x OVDD” from the Min column of the first row

—Changed test condition “Iout = 1 mA” to “Iout = 0.8 mA” in the second row

—Removed test condition “Iout= specified Iol Drive” from the second row

—Removed “0.2 x OVDD” from the Max column of the second row

—Removed rows 3–6

Table 113. i.MX53 Data Sheet Document Revision History (continued)

Rev.

Number Date Substantive Change(s)

i.MX53 Applications Processors for Industrial Products, Rev. 7

172 Freescale Semiconductor

Revision History

Rev. 4

(continued)

11/2011 • In Section 4.3.5, “LVDS I/O DC Parameters,” added the sentence “The parameters in Table 16 are

guaranteed per the operating ranges in Ta b l e 6, unless otherwise noted.” before Table 16.

•In Table 16, "LVDS DC Electrical Characteristics," on page 32, changed test condition “Rload=100Ω

padP, –padN” to “Rload = 100Ω between padP and padN”.

•In Table 35, " NFC—Timing Characteristics," on page 49, corrected footnote number for Tdl.

•In Table 49, "SD/eMMC4.3 Interface Timing Specification," on page 72, updated eSDHC output delay.

•In Table 50, "eMMC4.4 Interface Timing Specification," on page 73, updated eSDHC output delay.

•In Table 62, "TV Encoder Video Performance Specifications," on page 94, changed test condition

“Fout = 9.28 MHz” for SFDR to “Fout = 8.3 MHz”.

Rev. 3 06/2011 • In Table 6, "i.MX53 Operating Ranges," on page 18, updated operating ranges of VDDGP and VCC.

•In Section 4.1.1, “Absolute Maximum Ratings,” updated the caution note on page 16.

Rev. 2 05/2011 Initial release.

Table 113. i.MX53 Data Sheet Document Revision History (continued)

Rev.

Number Date Substantive Change(s)

Document Number: IMX53IEC

Rev. 7

05/2015

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