PIC16(L)F720/721 20-Pin Flash Microcontrollers Devices Included In This Data Sheet: * PIC16F720 * PIC16LF720 * PIC16F721 * PIC16LF721 High-Performance RISC CPU: * Only 35 Instructions to Learn: - All single-cycle instructions except branches * Operating Speed: - DC - 16 MHz oscillator/clock input - DC - 250 ns instruction cycle * Up to 4K x 14 Words of Flash Program Memory * Up to 256 bytes of Data Memory (RAM) * Interrupt Capability * 8-Level Deep Hardware Stack * Direct, Indirect and Relative Addressing modes * Processor Self-Write/Read access to Program Memory Special Microcontroller Features: * Precision Internal Oscillator: - 16 MHz or 500 kHz operation - Factory calibrated to 1%, typical - Software tunable - Software selectable /1, /2, /4 or /8 divider * Power-Saving Sleep mode * Industrial and Extended Temperature Range * Power-on Reset (POR) * Power-up Timer (PWRT) * Brown-out Reset (BOR) * Multiplexed Master Clear with Pull-up/Input Pin * Programmable Code Protection * In-Circuit Serial ProgrammingTM (ICSPTM) via Two Pins * 128 Bytes High-Endurance Flash: - 100,000 write Flash endurance (minimum) * Wide Operating Voltage Range: - 1.8V to 5.5V (PIC16F720/721) - 1.8V to 3.6V (PIC16LF720/721) 2010-2013 Microchip Technology Inc. Low-Power Features: * Standby Current: - 40 nA @ 1.8V, typical * Low-Power Watchdog Timer Current: - 500 nA @ 1.8V, typical Peripheral Features: * Up to 17 I/O Pins and 1 Input-only Pin: - High-current source/sink for direct LED drive - Interrupt-on-change pins - Individually programmable weak pull-ups * A/D Converter: - 8-bit resolution - 12 channels - Selectable Voltage reference * Timer0: 8-Bit Timer/Counter with 8-Bit Programmable Prescaler * Enhanced Timer1 - 16-bit timer/counter with prescaler - External Gate Input mode with toggle and single shot modes - Interrupt-on-gate completion * Timer2: 8-Bit Timer/Counter with 8-Bit Period Register, Prescaler and Postscaler * Capture, Compare, PWM module (CCP) - 16-bit Capture, max resolution 12.5 ns - 16-bit Compare, max resolution 250 ns - 10-bit PWM, max frequency 15 kHz * Addressable Universal Synchronous Asynchronous Receiver Transmitter (AUSART) * Synchronous Serial Port (SSP) - SPI (Master/Slave) - I2CTM (Slave) with Address Mask DS40001430E-page 1 PIC16(L)F720/721 DS40001430E-page 2 Debug(1) XLP PIC16(L)F707 (1) 8192 363 36 14 32 4/2 1 1 PIC16(L)F720 (2) 2048 128 18 12 -- 2/1 1 1 PIC16(L)F721 (2) 4096 256 18 12 -- 2/1 1 1 PIC16(L)F722 (4) 2048 128 25 11 8 2/1 1 1 PIC16(L)F722A (3) 2048 128 25 11 8 2/1 1 1 PIC16(L)F723 (4) 4096 192 25 11 8 2/1 1 1 PIC16(L)F723A (3) 4096 192 25 11 8 2/1 1 1 PIC16(L)F724 (4) 4096 192 36 14 16 2/1 1 1 PIC16(L)F726 (4) 8192 368 25 11 8 2/1 1 1 PIC16(L)F727 (4) 8192 368 36 14 16 2/1 1 1 Note 1: I - Debugging, Integrated on Chip; H - Debugging, Requires Debug Header. 2: One pin is input-only. Data Sheet Index: (Unshaded devices are described in this document.) 1: DS41418 PIC16(L)F707 Data Sheet, 40/44-Pin Flash, 8-bit Microcontrollers. 2: DS41430 PIC16(L)F720/721 Data Sheet, 20-Pin Flash, 8-bit Microcontrollers. 3: DS41417 PIC16(L)F722A/723A Data Sheet, 28-Pin Flash, 8-bit Microcontrollers. 4: DS41341 PIC16(L)F72X Data Sheet, 28/40/44-Pin Flash, 8-bit Microcontrollers. CCP SSP (I2CTM/SPI) AUSART Timers (8/16-bit) CapSense (ch) 8-bit ADC (ch) I/O's(2) Data SRAM (bytes) Program Memory Flash (words) Device Data Sheet Index PIC16(L)F72X Family Types 2 1 1 2 2 2 2 2 2 2 I I I I I I I I I I Y -- -- Y Y Y Y Y Y Y 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 Pin Diagrams - 20-PIN DIAGRAM FOR PIC16F720/721 AND PIC16LF720/721 PDIP, SOIC, SSOP VDD 1 20 VSS 2 19 RA0/AN0/ICSPDAT 3 18 RA1/AN1/ICSPCLK RA3/MCLR/VPP 4 17 RA2/AN2/T0CKI/INT 16 RC0/AN4 15 RC1/AN5 14 RC2/AN6 13 RB4/AN10/SDI/SDA RC5/CCP1 5 PIC16F720/721 PIC16LF720/721 RA5/T1CKI/CLKIN RA4/AN3/T1G/CLKOUT RC4 6 RC3/AN7 7 RC6/AN8/SS 8 RC7/AN9/SDO 9 12 RB5/AN11/RX/DT 10 11 RB6/SCK/SCL RB7/TX/CK Pin Diagrams - 20-PIN DIAGRAM FOR PIC16F720/721 AND PIC16LF720/721 RA0/AN0/ICSPDAT VSS VDD RA5/T1CKI/CLKIN RA4/AN3/T1G/CLKOUT QFN (4x4) 20 19 18 17 16 RA3/MCLR/VPP 1 RC5/CCP1 2 RC4 3 RC3/AN7 4 2010-2013 Microchip Technology Inc. 14 RA2/AN2/T0CKI/INT PIC16F720/721 13 RC0/AN4 PIC16LF720/721 12 RC1/AN5 5 8 RB6/SCK/SCL 9 10 RB5/AN11/RX/DT 7 RB4/AN10/SDI/SDA 6 RB7/TX/CK 11 RC2/AN6 RC7/AN9/SDO RC6/AN8/SS 15 RA1/AN1/ICSPCLK DS40001430E-page 3 PIC16(L)F720/721 CCP AUSART SSP Interrupt Pull-up 19 16 AN0 -- -- -- -- IOC Y ICSPDAT RA1 18 15 AN1 -- -- -- -- IOC Y ICSPCLK RA2 17 14 AN2 T0CKI -- -- -- INT/IOC -- -- RA3 4 1 -- -- -- -- -- IOC Y MCLR/VPP Basic Timers RA0 I/O A/D 20-Pin QFN 20-PIN ALLOCATION TABLE (PIC16F720/721 AND PIC16LF720/721) 20-Pin PDIP/SOIC/ SSOP TABLE 1: RA4 3 20 AN3 T1G -- -- -- IOC Y CLKOUT RA5 2 19 -- T1CKI -- -- -- IOC Y CLKIN RB4 13 10 AN10 -- -- -- SDI/SDA IOC Y -- RB5 12 9 AN11 -- -- RX/DT -- IOC Y -- RB6 11 8 -- -- -- -- SCK/SCL IOC Y -- RB7 10 7 -- -- -- TX/CK -- IOC Y -- RC0 16 13 AN4 -- -- -- -- -- -- -- RC1 15 12 AN5 -- -- -- -- -- -- -- RC2 14 11 AN6 -- -- -- -- -- -- -- RC3 7 4 AN7 -- -- -- -- -- -- -- RC4 6 3 -- -- -- -- -- -- -- -- RC5 5 2 -- -- CCP1 -- -- -- -- -- RC6 8 5 AN8 -- -- -- SS -- -- -- RC7 9 6 AN9 -- -- -- SDO -- -- -- VDD 1 18 -- -- -- -- -- -- -- VDD Vss 20 17 -- -- -- -- -- -- -- VSS DS40001430E-page 4 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 Table of Contents 1.0 Device Overview ......................................................................................................................................................................... 7 2.0 Memory Organization ................................................................................................................................................................ 11 3.0 Resets ....................................................................................................................................................................................... 25 4.0 Interrupts ................................................................................................................................................................................... 35 5.0 Low Dropout (LDO) Voltage Regulator ..................................................................................................................................... 43 6.0 I/O Ports .................................................................................................................................................................................... 45 7.0 Oscillator Module....................................................................................................................................................................... 65 8.0 Device Configuration ................................................................................................................................................................. 71 9.0 Analog-to-Digital Converter (ADC) Module ............................................................................................................................... 75 10.0 Fixed Voltage Reference........................................................................................................................................................... 85 11.0 Temperature Indicator Module ................................................................................................................................................... 87 12.0 Timer0 Module .......................................................................................................................................................................... 89 13.0 Timer1 Module with Gate Control.............................................................................................................................................. 93 14.0 Timer2 Module ........................................................................................................................................................................ 105 15.0 Capture/Compare/PWM (CCP) Module .................................................................................................................................. 107 16.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (AUSART) .......................................................... 117 17.0 SSP Module Overview ............................................................................................................................................................ 137 18.0 Flash Program Memory Self Read/Self Write Control............................................................................................................. 159 19.0 Power-Down Mode (Sleep) ..................................................................................................................................................... 167 20.0 In-Circuit Serial ProgrammingTM (ICSPTM) .............................................................................................................................. 169 21.0 Instruction Set Summary ......................................................................................................................................................... 171 22.0 Development Support.............................................................................................................................................................. 181 23.0 Electrical Specifications........................................................................................................................................................... 185 24.0 DC and AC Characteristics Graphs and Charts ...................................................................................................................... 211 25.0 Packaging Information............................................................................................................................................................. 231 Appendix A: Data Sheet Revision History......................................................................................................................................... 241 Appendix B: Migrating From Other PIC(R) Devices............................................................................................................................. 241 The Microchip Web Site .................................................................................................................................................................... 249 Customer Change Notification Service ............................................................................................................................................. 249 Customer Support ............................................................................................................................................................................. 249 Reader Response ............................................................................................................................................................................. 250 Product Identification System ............................................................................................................................................................ 251 2010-2013 Microchip Technology Inc. DS40001430E-page 5 PIC16(L)F720/721 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: * Microchip's Worldwide Web site; http://www.microchip.com * Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS40001430E-page 6 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 1.0 DEVICE OVERVIEW The PIC16(L)F720/721 devices are covered by this data sheet. They are available in 20-pin packages. Figure 1-1 shows a block diagram of the PIC16(L)F720/721 devices. Table 1-1 shows the pinout descriptions. 2010-2013 Microchip Technology Inc. DS40001430E-page 7 PIC16(L)F720/721 FIGURE 1-1: 20-PIN DEVICE BLOCK DIAGRAM FOR PIC16F720/721 PORTA Configuration 13 Program Counter Flash Program 8K x 14 (1) Memory Program Program Bus RAM File Registers Registers(1) 368 x 8 8 Level Stack (13-bit) Memory 14 RA0 RA1 RA2 RA3 RA4 RA5 8 Data Bus RAM Addr PORTB 9 Addr MUX Instruction Instruction Reg reg 7 Direct Addr 8 RB4 RB5 RB6 RB7 Indirect Addr FSR FSR Reg reg STATUS STATUS Reg reg 8 3 CLKIN CLKOUT Instruction Decode & Control Timing Generation MUX Power-up Timer Power-on Reset PORTC ALU Watchdog Timer Brown-out Reset LDO Regulator RC0 RC1 RC2 RC3 RC4 RC5 RC6 RC7 8 W W Reg reg PMDATL Internal Oscillator Block MCLR VDD Self read/ write Flash memory VSS PMADRL CCP1 CCP1 T0CKI Timer0 T1G TX/CK RX/DT ICSPDAT ICSPCLK AUSART AUSART ICSPTM SDI/ SCK/ SDO SDA SCL SS T1CKI Timer1 Timer2 Synchronous Serial Port Analog-To-Digital Converter AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 Note: PIC16(L)F720 - 2k x 14 Flash, 128 x 8 RAM PIC16(L)F721 - 4k x 14 Flash, 256 x 8 RAM. DS40001430E-page 8 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 TABLE 1-1: PINOUT DESCRIPTION Name RA0/AN0/ICSPDAT/ICDDAT RA1/AN1/ICSPCLK/ICDCLK RA2/AN2/T0CKI/INT RA3/MCLR/VPP RA4/AN3/T1G/CLKOUT Function OUT RA0 TTL CMOS AN0 AN -- ICSPDAT ST CMOS ICSPTM Data I/O. General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. RA1 TTL CMOS AN1 AN -- ICSPCLK ST -- RB4/AN10/SDI/SDA RB5/AN11/RX/DT RB6/SCK/SCL RB7/TX/CK RC0/AN4 RC1/AN5 RC2/AN6 RC3/AN7 Legend: General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. A/D Channel 0 Input. A/D Channel 1 Input. ICSPTM Clock. General purpose I/O with IOC and WPU. RA2 TTL CMOS AN2 AN -- A/D Channel 2 Input. T0CKI ST -- Timer0 Clock Input. INT ST -- External interrupt. RA3 TTL -- General purpose input-only with IOC and WPU. MCLR ST -- Master Clear with internal pull-up. VPP HV -- Programming Voltage. RA4 TTL CMOS AN3 AN -- A/D Channel 3 Input. T1G ST -- Timer1 Gate Input. CLKOUT RA5/T1CKI/CLKIN Description IN General purpose I/O with IOC and WPU. -- CMOS RA5 TTL CMOS FOSC/4 output. T1CKI ST -- Timer1 Clock input. CLKIN ST -- External Clock Input (EC mode). RB4 TTL CMOS AN10 AN -- General purpose I/O with IOC and WPU. General purpose I/O with IOC and WPU. A/D Channel 10 Input. SDI ST -- SPI Data Input. SDA I2C OD I2CTM Data. RB5 TTL CMOS AN11 AN -- RX ST -- DT ST CMOS General purpose I/O with IOC and WPU. A/D Channel 11 Input. USART asynchronous input. USART synchronous data. RB6 TTL CMOS General purpose I/O with IOC and WPU. SCK ST CMOS SPI Clock. SCL I2C OD RB7 TTL CMOS TX -- CMOS USART asynchronous transmit. CK ST CMOS USART synchronous clock. RC0 ST CMOS General purpose I/O. AN4 AN -- A/D Channel 4 Input. RC1 ST CMOS General purpose I/O. AN5 AN -- A/D Channel 5 Input. RC2 ST CMOS General purpose I/O. AN6 AN -- A/D Channel 6 Input. RC3 ST CMOS General purpose I/O. AN7 AN -- A/D Channel 7 Input. I2CTM Clock. General purpose I/O with IOC and WPU. AN = Analog input or output, CMOS = CMOS compatible input or output, OD = Open Drain, TTL = TTL compatible input, ST = Schmitt Trigger input with CMOS levels, I2CTM = Schmitt Trigger input with I2C, HV = High Voltage, XTAL = Crystal levels 2010-2013 Microchip Technology Inc. DS40001430E-page 9 PIC16(L)F720/721 TABLE 1-1: PINOUT DESCRIPTION (CONTINUED) Name Function IN OUT RC4 RC4 ST CMOS General purpose I/O. RC5/CCP1 RC5 ST CMOS General purpose I/O. CCP1 ST CMOS Capture/Compare/PWM 1. RC6 ST CMOS General purpose I/O. AN8 AN -- A/D Channel 8 Input. RC6/AN8/SS RC7/AN9/SDO VDD Vss Legend: Description SS ST -- RC7 ST CMOS General purpose I/O. AN9 AN -- A/D Channel 9 Input. Slave Select input. SDO -- CMOS VDD Power -- Positive supply. SPI Data Output. Vss Power -- Ground supply. AN = Analog input or output, CMOS = CMOS compatible input or output, OD = Open Drain, TTL = TTL compatible input, ST = Schmitt Trigger input with CMOS levels, I2CTM = Schmitt Trigger input with I2C, HV = High Voltage, XTAL = Crystal levels DS40001430E-page 10 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 2.0 MEMORY ORGANIZATION 2.1 Program Memory Organization The PIC16(L)F720/721 has a 13-bit program counter capable of addressing a 8K x 14 program memory space. Table 2-1 shows the memory sizes implemented. Accessing a location above these boundaries will cause a wrap-around within the implemented memory space. The Reset vector is at 0000h and the interrupt vector is at 0004h. TABLE 2-1: DEVICE SIZE AND ADDRESSES Program Memory Size (Words) Last Program Memory Address High-Endurance Flash Memory Address Range(1) PIC16F720 PIC16LF720 2048 07FFh 0780h-07FFh PIC16F721 PIC16LF721 4096 0FFFh 0F80h-0FFFh Device Note 1: High-Endurance Flash applies to the low byte of each address in the range. FIGURE 2-1: PROGRAM MEMORY MAP AND STACK FOR THE PIC16(L)F720 FIGURE 2-2: PC<12:0> CALL, RETURN RETFIE, RETLW On-chip Program Memory PROGRAM MEMORY MAP AND STACK FOR THE PIC16(L)F721 PC<12:0> CALL, RETURN RETFIE, RETLW 13 13 Stack Level 1 Stack Level 2 Stack Level 1 Stack Level 2 Stack Level 8 Stack Level 8 Reset Vector 0000h Reset Vector 0000h Interrupt Vector 0004H 0005h Interrupt Vector 0004H 0005h Page 0 07FFh 0800h Wraps to Page 0 0FFFh 1000h Wraps to Page 0 17FFh 1800h Wraps to Page 0 1FFFh 2010-2013 Microchip Technology Inc. On-chip Program Memory Page 0 07FFh 0800h Page 1 0FFFh 1000h Wraps to Page 0 17FFh 1800h Wraps to Page 1 1FFFh DS40001430E-page 11 PIC16(L)F720/721 2.2 Data Memory Organization The data memory is partitioned into multiple banks which contain the General Purpose Registers (GPRs) and the Special Function Registers (SFRs). Bits RP0 and RP1 are bank select bits. RP1 RP0 0 0 Bank 0 is selected 0 1 Bank 1 is selected 1 0 Bank 2 is selected 1 1 Bank 3 is selected Each bank extends up to 7Fh (128 bytes). The lower locations of each bank are reserved for the Special Function Registers. Above the Special Function Registers are the General Purpose Registers, implemented as static RAM. All implemented banks contain Special Function Registers. Some frequently used Special Function Registers from one bank are mirrored in another bank for code reduction and quicker access. DS40001430E-page 12 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 2.2.1 GENERAL PURPOSE REGISTER FILE The register file is organized as 128 x 8 bits in the PIC16(L)F720, 256 x 8 bits in the PIC16(L)F721. Each register is accessed either directly or indirectly through the File Select Register (FSR), (Refer to Section 2.5 "Indirect Addressing, INDF and FSR Registers"). 2.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers are registers used by the CPU and peripheral functions for controlling the desired operation of the device (refer to Table 2-2). These registers are static RAM. The Special Function Registers can be classified into two sets: core and peripheral. The Special Function Registers associated with the "core" are described in this section. Those related to the operation of the peripheral features are described in the section of that peripheral feature. 2010-2013 Microchip Technology Inc. DS40001430E-page 13 PIC16(L)F720/721 FIGURE 2-3: PIC16(L)F720 SPECIAL FUNCTION REGISTERS File Address INDF(*) 00h INDF(*) 80h INDF(*) 100h INDF(*) 180h TMR0 01h OPTION_REG 81h TMR0 101h OPTION_REG 181h PCL 02h PCL 82h PCL 102h PCL 182h STATUS 03h STATUS 83h STATUS 103h STATUS 183h FSR 104h FSR 04h FSR 84h 05h TRISA 85h 105h FSR ANSELA 184h PORTA PORTB 06h TRISB 86h 106h ANSELB 186h PORTC 07h TRISC 87h 107h ANSELC 187h 08h 88h 108h 09h 89h 109h 185h 188h 189h PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh 0Ch PIE1 8Ch PMDATL 10Ch PMCON1 18Ch 8Dh PMADRL 10Dh PMCON2 18Dh PIR1 0Dh TMR1L 0Eh PCON 8Eh PMDATH 10Eh 18Eh TMR1H 0Fh T1GCON 8Fh PMADRH 10Fh 18Fh T1CON 10h OSCCON 90h 110h 190h TMR2 11h OSCTUNE 91h 111h 191h T2CON 12h PR2 92h 112h 192h SSPBUF 13h SSPADD/SSPMSK 93h 113h 193h SSPCON 14h SSPSTAT 94h 114h 194h CCPR1L 15h WPUA 95h WPUB 115h 195h CCPR1H 16h IOCA 96h IOCB 116h 196h CCP1CON 17h 97h 117h 197h RCSTA 18h TXSTA 98h 118h 198h TXREG 19h SPBRG 99h 119h 199h RCREG 1Ah 9Ah 11Ah 19Ah 1Bh 9Bh 11Bh 19Bh 1Ch 9Ch 11Ch 19Ch 9Dh 11Dh 19Dh 9Eh 11Eh 19Eh 9Fh 11Fh 19Fh A0h 120h 1A0h 1Dh ADRES 1Eh ADCON0 1Fh FVRCON ADCON1 20h General Purpose Register 32 Bytes General Purpose Register 80 Bytes BFh C0h 06Fh EFh 16Fh 1EFh 070h F0h 170h 1F0h Accesses 70h - 7Fh Access RAM 7Fh BANK 0 Legend: * Accesses 70h - 7Fh FFh BANK 1 Accesses 70h - 7Fh 17Fh BANK 2 1FFh BANK 3 = Unimplemented data memory locations, read as `0'. = Not a physical register. DS40001430E-page 14 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 FIGURE 2-4: PIC16(L)F721 SPECIAL FUNCTION REGISTERS File Address INDF(*) 00h INDF(*) 80h INDF(*) 100h INDF(*) 180h TMR0 01h OPTION_REG 81h TMR0 101h OPTION_REG 181h PCL 02h PCL 82h PCL 102h PCL 182h STATUS 03h STATUS 83h STATUS 103h STATUS 183h FSR 104h FSR 04h FSR 84h 05h TRISA 85h 105h FSR ANSELA 184h PORTA PORTB 06h TRISB 86h 106h ANSELB 186h PORTC 07h TRISC 87h 107h ANSELC 187h 88h 108h 08h 09h PCLATH 89h 188h 109h 10Ah 189h 0Ah PCLATH 8Ah INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh PIR1 0Ch PIE1 8Ch PMDATL 10Ch PMCON1 18Ch 8Dh PMADRL 10Dh PMCON2 18Dh TMR1L 0Eh PCON 8Eh PMDATH 10Eh 18Eh TMR1H 0Fh T1GCON 8Fh PMADRH 10Fh 18Fh T1CON 10h OSCCON 90h 110h 190h TMR2 11h OSCTUNE 91h 111h 191h T2CON 12h PR2 92h 112h 192h SSPBUF 13h SSPADD/SSPMSK 93h 113h 193h SSPCON 14h SSPSTAT 94h 114h 194h 0Dh PCLATH 185h PCLATH 18Ah CCPR1L 15h WPUA 95h WPUB 115h 195h CCPR1H 16h IOCA 96h IOCB 116h 196h CCP1CON 17h 97h 117h 197h RCSTA 18h TXSTA 98h 118h 198h TXREG 19h SPBRG 99h 119h 199h RCREG 1Ah 9Ah 11Ah 19Ah 1Bh 9Bh 11Bh 19Bh 1Ch 9Ch 11Ch 19Ch 9Dh 11Dh 19Dh 9Eh 11Eh 19Eh 9Fh 11Fh 19Fh A0h 120h 1A0h 16Fh 1EFh 1Dh ADRES 1Eh ADCON0 1Fh General Purpose Register 80 Bytes 20h 06Fh 070h Access RAM FVRCON ADCON1 General Purpose Register 80 Bytes Accesses 70h - 7Fh Legend: * F0h Accesses 70h - 7Fh FFh 7Fh BANK 0 EFh General Purpose Register 80 Bytes BANK 1 170h Accesses 70h - 7Fh 17Fh BANK 2 1F0h 1FFh BANK 3 = Unimplemented data memory locations, read as `0'. = Not a physical register. 2010-2013 Microchip Technology Inc. DS40001430E-page 15 PIC16(L)F720/721 TABLE 2-2: Address SPECIAL FUNCTION REGISTER SUMMARY Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 0 00h( 2) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx 01h TMR0 Timer0 module Register xxxx xxxx uuuu uuuu 02h( 2) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000 03h( 2) STATUS 000q quuu 04h( 2) FSR 05h PORTA IRP RP1 RP0 -- -- RA5 TO PD Z DC C 0001 1xxx xxxx xxxx uuuu uuuu RA2 RA1 RA0 --xx xxxx --xx xxxx Indirect Data Memory Address Pointer RA4 RA3 06h PORTB RB7 RB6 RB5 RB4 -- -- -- -- xxxx ---- uuuu ---- 07h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu -- 08h -- Unimplemented -- 09h -- Unimplemented -- -- Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000 0Ah( 1),( 2) PCLATH 0Bh( 2) INTCON 0Ch PIR1 0Dh -- 0Eh TMR1L 0Fh TMR1H 10h T1CON 11h TMR2 12h T2CON 13h SSPBUF 14h SSPCON 15h CCPR1L 16h CCPR1H 17h CCP1CON 18h RCSTA 19h TXREG 1Ah RCREG -- -- -- GIE PEIE TMR0IE INTE RABIE TMR0IF INTF RABIF 0000 000x 0000 000x TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 Unimplemented -- -- Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu 0000 -0-0 uuuu -u-u Holding Register for the Most Significant Byte of the 16-bit TMR1 Register TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 -- T1SYNC -- TMR1ON Timer2 module Register -- TOUTPS3 WCOL SSPOV 0000 0000 0000 0000 -000 0000 -000 0000 xxxx xxxx uuuu uuuu 0000 0000 0000 0000 Capture/Compare/PWM Register Low Byte xxxx xxxx uuuu uuuu Capture/Compare/PWM Register High Byte xxxx xxxx uuuu uuuu TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 Synchronous Serial Port Receive Buffer/Transmit Register SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 -- -- DC1 B1 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x AUSART Transmit Data Register 0000 0000 0000 0000 AUSART Receive Data Register 0000 0000 0000 0000 1Bh -- Unimplemented -- -- 1Ch -- Unimplemented -- -- 1Dh -- Unimplemented -- -- ADC Result Register xxxx xxxx uuuu uuuu --00 0000 --00 0000 1Eh ADRES 1Fh ADCON0 Legend: Note 1: 2: 3: 4: 5: -- -- CHS3 CHS2 CHS1 CHS0 GO/ DONE ADON x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as `0', r = reserved. Shaded locations are unimplemented, read as `0'. The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are transferred to the upper byte of the program counter. These registers can be addressed from any bank. Accessible only when SSPM<3:0> = 1001. This bit is unimplemented and reads as `1'. See Register 6-2. DS40001430E-page 16 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 TABLE 2-2: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 1 80h( 2) INDF 81h OPTION_ REG 82h( 2) PCL 83h( 2) STATUS 84h( 2) FSR 85h(5) TRISA 86h TRISB TRISB7 TRISB6 TRISB5 TRISB4 -- -- -- -- 1111 ---- 1111 ---- 87h TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111 88h -- Unimplemented -- -- 89h -- Unimplemented -- -- Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000 8Ah( 1),( 2) Addressing this location uses contents of FSR to address data memory (not a physical register) RABPU INTEDG IRP RP1 RP0 -- -- TRISA5 T0CS T0SE xxxx xxxx xxxx xxxx PS1 PS0 1111 1111 1111 1111 0000 0000 0000 0000 Z DC C 0001 1xxx 000q quuu xxxx xxxx uuuu uuuu TRISA2 TRISA1 TRISA0 --11 -111 --11 -111 PSA PS2 Program Counter (PC) Least Significant Byte TO PD Indirect Data Memory Address Pointer PCLATH 8Bh( 2) INTCON 8Ch PIE1 8Dh -- 8Eh PCON 8Fh -- TRISA4 --(4) -- -- GIE PEIE TMR0IE INTE RABIE TMR0IF INTF RABIF 0000 000x 0000 000x TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 Unimplemented -- -- -- -- -- -- -- -- POR BOR ---- --qq ---- --uu T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ DONE T1GVAL T1GSS1 T1GSS0 0000 0x00 uuuu uxuu 90h OSCCON -- -- IRCF1 IRCF0 ICSL ICSS -- -- --10 qq-- --10 qq-- 91h OSCTUNE -- -- TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 --00 0000 --uu uuuu 92h PR2 Timer2 module Period Register 1111 1111 1111 1111 93h SSPADD ADD<7:0> 0000 0000 0000 0000 93h( 3) SSPMSK MSK<7:0> 1111 1111 1111 1111 94h SSPSTAT 95h 96h SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000 WPUA -- -- WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 --11 1111 --11 1111 IOCA -- -- IOCA5 IOCA4 IOCA3 IOCA2 IOCA1 IOCA0 --00 0000 --00 0000 97h -- 98h TXSTA CSRC TX9 TXEN 99h SPBRG BRG7 BRG6 BRG5 Unimplemented -- -- SYNC -- BRGH TRMT TX9D 0000 -010 0000 -010 BRG4 BRG3 BRG2 BRG1 BRG0 0000 0000 0000 0000 9Ah -- Unimplemented -- -- 9Bh -- Unimplemented -- -- 9Ch -- Unimplemented -- -- q000 --00 9Dh FVRCON 9Eh FVRRDY FVREN TSEN TSRNG -- ADCS2 ADCS1 ADCS0 -- 9Fh ADCON1 Legend: Note 1: 2: 3: 4: 5: -- -- ADFVR1 ADFVR0 q000 --00 -- -- -- -- -- -- -000 ---- -000 ---- Unimplemented x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as `0', r = reserved. Shaded locations are unimplemented, read as `0'. The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are transferred to the upper byte of the program counter. These registers can be addressed from any bank. Accessible only when SSPM<3:0> = 1001. This bit is unimplemented and reads as `1'. See Register 6-2. 2010-2013 Microchip Technology Inc. DS40001430E-page 17 PIC16(L)F720/721 TABLE 2-2: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 2 100h( 2) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx 101h TMR0 Timer0 module Register xxxx xxxx uuuu uuuu 102h( 2) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000 103h( 2) STATUS 0001 1xxx 000q quuu 104h( 2) FSR IRP RP1 RP0 TO PD Z DC C Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu 105h -- Unimplemented -- -- 106h -- Unimplemented -- -- 107h -- Unimplemented -- -- 108h -- Unimplemented -- -- 109h -- Unimplemented -- -- ---0 0000 ---0 0000 10Ah( 1),( 2) PCLATH -- -- GIE PEIE -- Write Buffer for the upper 5 bits of the Program Counter 10Bh( 2) INTCON 0000 000x 0000 000x 10Ch PMDATL Program Memory Read Data Register Low Byte xxxx xxxx xxxx xxxx 10Dh PMADRL Program Memory Read Address Register Low Byte 0000 0000 0000 0000 10Eh PMDATH -- -- --xx xxxx --xx xxxx 10Fh PMADRH -- -- TMR0IE INTE RABIE TMR0IF INTF RABIF Program Memory Read Data Register High Byte -- Program Memory Read Address Register High Byte ---0 0000 ---0 0000 110h -- Unimplemented -- -- 111h -- Unimplemented -- -- 112h -- Unimplemented -- -- 113h -- Unimplemented -- -- 114h -- Unimplemented -- -- 115h WPUB WPUB7 WPUB6 WPUB5 WPUB4 -- -- -- -- 1111 ---- 1111 ---- 116h IOCB IOCB7 IOCB6 IOCB5 IOCB4 -- -- -- -- 0000 ---- 0000 ---- 117h -- Unimplemented -- -- 118h -- Unimplemented -- -- 119h -- Unimplemented -- -- 11Ah -- Unimplemented -- -- 11Bh -- Unimplemented -- -- 11Ch -- Unimplemented -- -- 11Dh -- Unimplemented -- -- 11Eh -- Unimplemented -- -- 11Fh -- Unimplemented -- -- Legend: Note 1: 2: 3: 4: 5: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as `0', r = reserved. Shaded locations are unimplemented, read as `0'. The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are transferred to the upper byte of the program counter. These registers can be addressed from any bank. Accessible only when SSPM<3:0> = 1001. This bit is unimplemented and reads as `1'. See Register 6-2. DS40001430E-page 18 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 TABLE 2-2: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 3 180h( 2) INDF 181h OPTION_ REG 182h( 2) PCL 183h( 2) STATUS Addressing this location uses contents of FSR to address data memory (not a physical register) RABPU INTEDG IRP RP1 RP0 -- -- -- ANSA4 T0CS T0SE PSA xxxx xxxx xxxx xxxx PS1 PS0 1111 1111 1111 1111 0000 0000 0000 0000 Z DC C 0001 1xxx 000q quuu xxxx xxxx uuuu uuuu ANSA2 ANSA1 ANSA0 ---1 -111 ---1 -111 PS2 Program Counter (PC) Least Significant Byte TO PD 184h( 2) FSR 185h ANSELA 186h ANSELB -- -- ANSB5 ANSB4 -- -- -- -- --11 ---- --11 ---- 187h ANSELC ANSC7 ANSC6 -- -- ANSC3 ANSC2 ANSC1 ANSC0 11-- 1111 11-- 1111 -- -- -- 188h Indirect Data Memory Address Pointer -- 18Ah( 1),( 2) PCLATH -- Unimplemented Write Buffer for the upper 5 bits of the Program Counter -- -- ---0 0000 ---0 0000 18Bh( 2) INTCON GIE PEIE TMR0IE INTE RABIE TMR0IF INTF RABIF 0000 000x 0000 000x 18Ch PMCON1 --(4) CFGS LWLO FREE -- WREN WR RD 1000 -000 1000 -000 18Dh PMCON2 Program Memory Control Register 2 (not a physical register) ---- ---- ---- ---- 190h -- Unimplemented -- -- 191h -- Unimplemented -- -- 192h -- Unimplemented -- -- 193h -- Unimplemented -- -- 194h -- Unimplemented -- -- 195h -- Unimplemented -- -- 196h -- Unimplemented -- -- 197h -- Unimplemented -- -- 198h -- Unimplemented -- -- 199h -- Unimplemented -- -- 19Ah -- Unimplemented -- -- 19Bh -- Unimplemented -- -- 19Ch -- Unimplemented -- -- 19Dh -- Unimplemented -- -- 19Eh -- Unimplemented -- -- 19Fh -- Unimplemented -- -- Legend: Note 1: 2: 3: 4: 5: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as `0', r = reserved. Shaded locations are unimplemented, read as `0'. The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are transferred to the upper byte of the program counter. These registers can be addressed from any bank. Accessible only when SSPM<3:0> = 1001. This bit is unimplemented and reads as `1'. See Register 6-2. 2010-2013 Microchip Technology Inc. DS40001430E-page 19 PIC16(L)F720/721 2.2.2.1 STATUS Register The STATUS register, shown in Register 2-1, contains: * the arithmetic status of the ALU * the Reset status * the bank select bits for data memory (SRAM) The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. REGISTER 2-1: R/W-0 It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect any Status bits. For other instructions not affecting any Status bits (Refer to Section 21.0 "Instruction Set Summary"). Note 1: The C and DC bits operate as Borrow and Digit Borrow out bits, respectively, in subtraction. STATUS: STATUS REGISTER R/W-0 IRP For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as `000u u1uu' (where u = unchanged). RP1 R/W-0 RP0 R-1 TO R-1 PD R/W-x R/W-x R/W-x Z DC(1) C(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 IRP: Register Bank Select bit (used for indirect addressing) 1 = Bank 2, 3 (100h-1FFh) 0 = Bank 0, 1 (00h-FFh) bit 6-5 RP<1:0>: Register Bank Select bits (used for direct addressing) 00 = Bank 0 (00h-7Fh) 01 = Bank 1 (80h-FFh) 10 = Bank 2 (100h-17Fh) 11 = Bank 3 (180h-1FFh) bit 4 TO: Time-out bit 1 = After power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred bit 3 PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit Carry/Digit Borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)(1) 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result bit 0 C: Carry/Borrow bit(1) (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two's complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register. DS40001430E-page 20 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 2.2.2.2 OPTION_REG Register Note: The OPTION_REG register, shown in Register 2-2, is a readable and writable register, which contains various control bits to configure: * Software programmable prescaler for the Timer0/ WDT * External RA2/INT interrupt * Timer0 * Weak pull-ups on PORTA or PORTB REGISTER 2-2: To achieve a 1:1 prescaler assignment for Timer0, assign the prescaler to the WDT by setting the PSA bit of the OPTION_REG register to `1'. Refer to Section 12.1.3 "Software Programmable Prescaler". OPTION_REG: OPTION REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RABPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 RABPU: PORTA or PORTB Pull-up Enable bit 1 = PORTA or PORTB pull-ups are disabled 0 = PORTA or PORTB pull-ups are enabled by individual bits in the WPUB register bit 6 INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of INT pin 0 = Interrupt on falling edge of INT pin bit 5 T0CS: Timer0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (FOSC/4) bit 4 T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin bit 3 PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module bit 2-0 PS<2:0>: Prescaler Rate Select bits Bit Value 000 001 010 011 100 101 110 111 2010-2013 Microchip Technology Inc. Timer0 Rate 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 WDT Rate 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 DS40001430E-page 21 PIC16(L)F720/721 2.2.2.3 PCON Register The Power Control (PCON) register contains flag bits (refer to Table 3-4) to differentiate between a: * * * * Power-on Reset (POR) Brown-out Reset (BOR) Watchdog Timer Reset (WDT) External MCLR Reset The PCON register also controls the software enable of the BOR. The PCON register bits are shown in Register 2-3. REGISTER 2-3: PCON: POWER CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 R/W-q R/W-q -- -- -- -- -- -- POR BOR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown q = Value depends on condition bit 7-2 Unimplemented: Read as `0' bit 1 POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset occurs) DS40001430E-page 22 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 2.3 PCL and PCLATH The Program Counter (PC) is 13 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<12:8>) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. Figure 2-5 shows the two situations for the loading of the PC. The upper example in Figure 2-5 shows how the PC is loaded on a write to PCL (PCLATH<4:0> PCH). The lower example in Figure 2-5 shows how the PC is loaded during a CALL or GOTO instruction (PCLATH<4:3> PCH). FIGURE 2-5: LOADING OF PC IN DIFFERENT SITUATIONS PCH 12 PCL 8 7 0 PC 8 PCLATH<4:0> 5 Instruction with PCL as Destination ALU Result PCLATH PCH 12 11 10 PCL 8 7 0 PC GOTO, CALL 2 PCLATH<4:3> 11 Note 1: There are no Status bits to indicate stack overflow or stack underflow conditions. 2: There are no instructions/mnemonics called PUSH or POP. These are actions that occur from the execution of the CALL, RETURN, RETLW and RETFIE instructions or the vectoring to an interrupt address. 2.4 Program Memory Paging All devices are capable of addressing a continuous 8K word block of program memory. The CALL and GOTO instructions provide only 11 bits of address to allow branching within any 2K program memory page. When doing a CALL or GOTO instruction, the upper two bits of the address are provided by PCLATH<4:3>. When doing a CALL or GOTO instruction, the user must ensure that the page select bits are programmed so that the desired program memory page is addressed. If a return from a CALL instruction (or interrupt) is executed, the entire 13-bit PC is POPed off the stack. Therefore, manipulation of the PCLATH<4:3> bits is not required for the RETURN instructions (which POPs the address from the stack). Note: The contents of the PCLATH register are unchanged after a RETURN or RETFIE instruction is executed. The user must rewrite the contents of the PCLATH register for any subsequent subroutine calls or GOTO instructions. Opcode<10:0> PCLATH 2.3.1 COMPUTED GOTO A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When performing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block). Refer to the Application Note AN556, "Implementing a Table Read" (DS00556). 2.3.2 Example 2-1 shows the calling of a subroutine in page 1 of the program memory. This example assumes that PCLATH is saved and restored by the Interrupt Service Routine (if interrupts are used). EXAMPLE 2-1: ORG 500h PAGESEL SUB_P1 ;Select page 1 ;(800h-FFFh) CALL SUB1_P1 ;Call subroutine in : ;page 1 (800h-FFFh) : ORG 900h ;page 1 (800h-FFFh) STACK All devices have an 8-level x 13-bit wide hardware stack (refer to Figures 2-1 and 2-2). The stack space is not part of either program or data space and the Stack Pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation. The stack operates as a circular buffer. This means that after the stack has been PUSHed eight times, the ninth PUSH overwrites the value that was stored from the first PUSH. The tenth PUSH overwrites the second PUSH (and so on). 2010-2013 Microchip Technology Inc. CALL OF A SUBROUTINE IN PAGE 1 FROM PAGE 0 SUB1_P1 : : RETURN ;called subroutine ;page 1 (800h-FFFh) ;return to ;Call subroutine ;in page 0 ;(000h-7FFh) DS40001430E-page 23 PIC16(L)F720/721 2.5 Indirect Addressing, INDF and FSR Registers EXAMPLE 2-2: INDIRECT ADDRESSING MOVLW 020h ;initialize pointer MOVWF FSR ;to RAM BANKISEL 020h NEXT CLRF INDF ;clear INDF register INCF FSR ;inc pointer BTFSS FSR,4 ;all done? GOTO NEXT ;no clear next CONTINUE ;yes continue The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing. Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually accesses data pointed to by the File Select Register (FSR). Reading INDF itself indirectly will produce 00h. Writing to the INDF register indirectly results in a no operation (although Status bits may be affected). An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit of the STATUS register, as shown in Figure 2-6. A simple program to clear RAM location 020h-02Fh using indirect addressing is shown in Example 2-2. FIGURE 2-6: DIRECT/INDIRECT ADDRESSING Direct Addressing RP1 From Opcode RP0 6 Bank Select Indirect Addressing 0 Bank Select Location Select 00h 7 IRP 00 01 10 11 File Select Register0 Location Select 180h Data Memory 7Fh 1FFh Bank 0 Note: Bank 1 Bank 2 Bank 3 For memory map detail, refer to Figures 2-3 and 2-4. DS40001430E-page 24 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 3.0 RESETS The PIC16(L)F720/721 differentiates between various kinds of Reset: a) b) c) d) e) f) Power-on Reset (POR) WDT Reset during normal operation WDT Reset during Sleep MCLR Reset during normal operation MCLR Reset during Sleep Brown-out Reset (BOR) A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 3-1. Some registers are not affected in any Reset condition; their status is unknown on POR and unchanged in any other Reset. Most other registers are reset to a "Reset state" on: * * * * * Most registers are not affected by a WDT wake-up since this is viewed as the resumption of normal operation. TO and PD bits are set or cleared differently in different Reset situations, as indicated in Table 3-5. These bits are used in software to determine the nature of the Reset. The MCLR Reset path has a noise filter to detect and ignore small pulses. See Section 23.0 "Electrical Specifications" for pulse width specifications. Power-on Reset (POR) MCLR Reset MCLR Reset during Sleep WDT Reset Brown-out Reset (BOR) FIGURE 3-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT MCLRE MCLR/VPP Sleep WDT Module WDT Time-out Reset POR Power-on Reset VDD Brown-out(1) Reset BOREN Chip_Reset CLKIN PWRT WDTOSC 11-bit Ripple Counter Enable PWRT Note 1: Refer to the Configuration Word Register 1 (Register 8-1). 2010-2013 Microchip Technology Inc. DS40001430E-page 25 PIC16(L)F720/721 TABLE 3-1: STATUS BITS AND THEIR SIGNIFICANCE POR BOR TO PD 0 x 1 1 Power-on Reset or LDO Reset 0 x 0 x Illegal, TO is set on POR 0 x x 0 Illegal, PD is set on POR 1 0 1 1 Brown-out Reset 1 1 0 1 WDT Reset 1 1 0 0 WDT Wake-up 1 1 u u MCLR Reset during normal operation 1 1 1 0 MCLR Reset during Sleep or interrupt wake-up from Sleep TABLE 3-2: Condition RESET CONDITION FOR SPECIAL REGISTERS(2) Program Counter STATUS Register PCON Register Power-on Reset 0000h 0001 1xxx ---- --0x MCLR Reset during normal operation 0000h 000u uuuu ---- --uu MCLR Reset during Sleep 0000h 0001 0uuu ---- --uu WDT Reset 0000h 0000 1uuu ---- --uu WDT Wake-up PC + 1 uuu0 0uuu ---- --uu 0000h 0001 1uuu ---- --u0 PC + 1(1) uuu1 0uuu ---- --uu Condition Brown-out Reset Interrupt Wake-up from Sleep Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as `0'. Note 1: When the wake-up is due to an interrupt and Global Interrupt Enable bit (GIE) is set, the return address is pushed on the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1. 2: If a Status bit is not implemented, that bit will be read as `0'. DS40001430E-page 26 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 3.1 MCLR 3.3 The PIC16(L)F720/721 has a noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. It should be noted that a Reset does not drive the MCLR pin low. Voltages applied to the pin that exceed its specification can result in both MCLR Resets and excessive current beyond the device specification during the ESD event. For this reason, Microchip recommends that the MCLR pin no longer be tied directly to VDD. The use of an RC network, as shown in Figure 3-2, is suggested. An internal MCLR option is enabled by clearing the MCLRE bit in the Configuration Word register. When MCLRE = 0, the Reset signal to the chip is generated internally. When the MCLRE = 1, the RA3/MCLR pin becomes an external Reset input. In this mode, the RA3/MCLR pin has a weak pull-up to VDD. In-Circuit Serial ProgrammingTM is not affected by selecting the internal MCLR option. The Power-up Timer provides a fixed 72 ms (nominal) time out on power-up only, from POR or Brown-out Reset. The Power-up Timer operates from the WDT oscillator. For more information, see Section 7.3 "Internal Clock Modes". The chip is kept in Reset as long as PWRT is active. The PWRT delay allows the VDD to rise to an acceptable level. A Configuration bit, PWRTE, can disable (if set) or enable (if cleared or programmed) the Power-up Timer. The Power-up Timer should be enabled when Brown-out Reset is enabled, although it is not required. The Power-up Timer delay will vary from chip-to-chip and vary due to: * VDD variation * Temperature variation * Process variation See DC parameters for details "Electrical Specifications"). Note: FIGURE 3-2: RECOMMENDED MCLR CIRCUIT VDD (R) PIC MCU R1 10 k MCLR C1 0.1 F 3.4 Power-on Reset (POR) (Section 23.0 The Power-up Timer is enabled by the PWRTE bit in the Configuration Word. Watchdog Timer (WDT) The WDT has the following features: * Shares an 8-bit prescaler with Timer0 * Time-out period is from 17 ms to 2.2 seconds, nominal * Enabled by a Configuration bit WDT is cleared under certain conditions described in Table 3-3. 3.4.1 3.2 Power-up Timer (PWRT) WDT OSCILLATOR The WDT derives its time base from 31 kHz internal oscillator. The on-chip POR circuit holds the chip in Reset until VDD has reached a high enough level for proper operation. A maximum rise time for VDD is required. See Section 23.0 "Electrical Specifications" for details. If the BOR is enabled, the maximum rise time specification does not apply. The BOR circuitry will keep the device in Reset until VDD reaches VBOR (see Section 3.5 "Brown-out Reset (BOR)"). When the device starts normal operation (exits the Reset condition), device operating parameters (i.e., voltage, frequency, temperature, etc.) must be met to ensure operation. If these conditions are not met, the device must be held in Reset until the operating conditions are met. For additional information, refer to Application Note AN607, "Power-up Trouble Shooting" (DS00607). 2010-2013 Microchip Technology Inc. DS40001430E-page 27 PIC16(L)F720/721 3.4.2 WDT CONTROL The WDTEN bit is located in the Configuration Word Register 1. When set, the WDT runs continuously. The PSA and PS<2:0> bits of the OPTION_REG register control the WDT period. See Section 12.0 "Timer0 Module" for more information. FIGURE 3-3: WATCHDOG TIMER BLOCK DIAGRAM T1GSS = 11 TMR1GE From TMR0 Clock Source WDTEN Low-Power WDT OSC 0 Divide by 512 Postscaler 1 8 PS<2:0> TO TMR0 PSA 0 1 WDT Reset To T1G WDTEN TABLE 3-3: WDT STATUS Conditions WDTEN = 0 WDT Cleared CLRWDT Command Exit Sleep + System Clock = INTOSC, EXTCLK DS40001430E-page 28 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 3.5 Brown-out Reset (BOR) Brown-out Reset is enabled by programming the BOREN<1:0> bits in the Configuration register. Between the POR and BOR, complete voltage range coverage for execution protection can be implemented. Two bits are used to enable the BOR. When BOREN = 11, the BOR is always enabled. When BOREN = 10, the BOR is enabled, but disabled during Sleep. When BOREN = 0X, the BOR is disabled. If VDD falls below VBOR for greater than parameter (TBOR) (see Section 23.0 "Electrical Specifications"), the Brown-out situation will reset the device. This will occur regardless of VDD slew rate. A Reset is not ensured to occur if VDD falls below VBOR for more than parameter (TBOR). If VDD drops below VBOR while the Power-up Timer is running, the chip will go back into a Brown-out Reset and the Power-up Timer will be re-initialized. Once VDD rises above VBOR, the Power-up Timer will execute a 64 ms Reset. FIGURE 3-4: BROWN-OUT SITUATIONS VDD Internal Reset VBOR 64 ms(1) VDD Internal Reset VBOR < 64 ms 64 ms(1) VDD Internal Reset Note 1: VBOR 64 ms(1) 64 ms delay only if PWRTE bit is programmed to `0'. 2010-2013 Microchip Technology Inc. DS40001430E-page 29 PIC16(L)F720/721 3.6 Time-out Sequence 3.7 PWRT time-out is invoked after POR has expired. The total time-out will vary based on oscillator configuration and PWRTE bit status. For example, in EC mode with PWRTE bit = 1 (PWRT disabled), there will be no timeout at all. Figure 3-5, Figure 3-6 and Figure 3-7 depict time-out sequences. Power Control (PCON) Register The Power Control (PCON) register has two Status bits to indicate what type of Reset that last occurred. Bit 0 is BOR (Brown-out Reset). BOR is unknown on Power-on Reset. It must then be set by the user and checked on subsequent Resets to see if BOR = 0, indicating that a Brown-out has occurred. The BOR Status bit is a "don't care" and is not necessarily predictable if the brown-out circuit is disabled (BOREN<1:0> = 00 in the Configuration Word register). Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, the time-outs will expire. Then, bringing MCLR high will begin execution immediately (see Figure 3-6). This is useful for testing purposes or to synchronize more than one PIC16(L)F720/721 device operating in parallel. Bit 1 is POR (Power-on Reset). It is a `0' on Power-on Reset and unaffected otherwise. The user must write a `1' to this bit following a Power-on Reset. On a subsequent Reset, if POR is `0', it will indicate that a Power-on Reset has occurred (i.e., VDD may have gone too low). Table 3-5 shows the Reset conditions for some special registers. For more information, see Section 3.5 "Brown-out Reset (BOR)". TABLE 3-4: TIME-OUT IN VARIOUS SITUATIONS Oscillator Configuration EC, INTOSC TABLE 3-5: Power-up Brown-out Reset PWRTE = 0 PWRTE = 1 PWRTE = 0 PWRTE = 1 Wake-up from Sleep TPWRT -- TPWRT -- -- RESET BITS AND THEIR SIGNIFICANCE POR BOR TO PD Condition 0 u 1 1 Power-on Reset 1 0 1 1 Brown-out Reset u u 0 u WDT Reset u u 0 0 WDT Wake-up u u u u MCLR Reset during normal operation u u 1 0 MCLR Reset during Sleep Legend: u = unchanged, x = unknown FIGURE 3-5: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 1 VDD MCLR Internal POR TPWRT PWRT Time-out Internal Reset DS40001430E-page 30 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 FIGURE 3-6: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 2 VDD MCLR Internal POR TPWRT PWRT Time-out Internal Reset FIGURE 3-7: TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH VDD): CASE 3 VDD MCLR Internal POR TPWRT PWRT Time-out Internal Reset 2010-2013 Microchip Technology Inc. DS40001430E-page 31 PIC16(L)F720/721 TABLE 3-6: Register INITIALIZATION CONDITION FOR REGISTERS Address Power-on Reset/ Brown-out Reset(1) MCLR Reset/ WDT Reset W Wake-up from Sleep through Interrupt/Time-out -- xxxx xxxx uuuu uuuu uuuu uuuu INDF 00h/80h/ 100h/180h xxxx xxxx xxxx xxxx uuuu uuuu TMR0 01h/101h xxxx xxxx uuuu uuuu uuuu uuuu PCL 02h/82h/ 102h/182h 0000 0000 0000 0000 PC + 1(3) STATUS 03h/83h/ 103h/183h 0001 1xxx 000q quuu(4) uuuq quuu(4) FSR 04h/84h/ 104h/184h xxxx xxxx uuuu uuuu uuuu uuuu PORTA 05h --xx xxxx --xx xxxx --uu uuuu PORTB 06h xxxx ---- xxxx ---- uuuu ---- PORTC 07h xxxx xxxx xxxx xxxx uuuu uuuu PCLATH 0Ah/8Ah/ 10Ah/18Ah ---0 0000 ---0 0000 ---u uuuu INTCON 0Bh/8Bh/ 10Bh/18Bh 0000 000x 0000 000x uuuu uuuu(2) PIR1 0Ch 0000 0000 0000 0000 uuuu uuuu(2) TMR1L 0Eh xxxx xxxx uuuu uuuu uuuu uuuu TMR1H 0Fh xxxx xxxx uuuu uuuu uuuu uuuu T1CON 10h 0000 -0-0 0000 -0-0 uuuu -u-u TMR2 11h 0000 0000 0000 0000 uuuu uuuu T2CON 12h -000 0000 -000 0000 -uuu uuuu SSPBUF 13h xxxx xxxx xxxx xxxx uuuu uuuu SSPCON 14h 0000 0000 0000 0000 uuuu uuuu CCPR1L 15h xxxx xxxx xxxx xxxx uuuu uuuu CCPR1H 16h xxxx xxxx xxxx xxxx uuuu uuuu CCP1CON 17h --00 0000 --00 0000 --uu uuuu RCSTA 18h 0000 000x 0000 000x uuuu uuuu TXREG 19h 0000 0000 0000 0000 uuuu uuuu RCREG 1Ah 0000 0000 0000 0000 uuuu uuuu ADRES 1Eh xxxx xxxx uuuu uuuu uuuu uuuu ADCON0 1Fh --00 0000 --00 0000 --uu uuuu 81h/181h 1111 1111 1111 1111 uuuu uuuu 85h --11 -111 --11 -111 --uu -uuu TRISB 86h 1111 ---- 1111 ---- uuuu ---- TRISC 87h 1111 1111 1111 1111 uuuu uuuu 8Ch 0000 0000 0000 0000 uuuu uuuu OPTION_REG TRISA PIE1 Legend: Note 1: 2: 3: 4: 5: u = unchanged, x = unknown, - = unimplemented bit, reads as `0', q = value depends on condition. If VDD goes too low, Power-on Reset will be activated and registers will be affected differently. One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up). When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). See Table 3-8 for Reset value for specific condition. If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u. DS40001430E-page 32 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 TABLE 3-6: INITIALIZATION CONDITION FOR REGISTERS (CONTINUED) Address Power-on Reset/ Brown-out Reset(1) PCON 8Eh ---- --qq ---- --uu(1,5) ---- --uu T1GCON 8Fh 0000 0x00 uuuu uxuu uuuu uxuu OSCCON 90h --10 qq-- --10 qq-- --uu qq-- OSCTUNE 91h --00 0000 --uu uuuu --uu uuuu PR2 92h 1111 1111 1111 1111 uuuu uuuu SSPADD 93h 0000 0000 0000 0000 uuuu uuuu SSPMSK 93h 1111 1111 1111 1111 uuuu uuuu SSPSTAT 94h 0000 0000 0000 0000 uuuu uuuu WPUB 115h 1111 ---- 1111 ---- uuuu ---- WPUA 95h --11 1111 --11 1111 --uu uuuu IOCB 116h 0000 ---- 0000 ---- uuuu ---- IOCA 96h --00 0000 --00 0000 --uu uuuu TXSTA 98h 0000 -010 0000 -010 uuuu -uuu SPBRG 99h 0000 0000 0000 0000 uuuu uuuu FVRCON 9Dh q000 --00 q000 --00 uuuu --uu ADCON1 9Fh -000 ---- -000 ---- -uuu ---- PMDATL 10Ch xxxx xxxx xxxx xxxx uuuu uuuu PMADRL 10Dh 0000 0000 0000 0000 uuuu uuuu PMDATH 10Eh --xx xxxx --xx xxxx --uu uuuu PMADRH 10Fh ---0 0000 ---0 0000 ---u uuuu ANSELA 185h ---1 -111 ---1 -111 ---u -uuu ANSELB 186h --11 ---- --11 ---- --uu ---- ANSELC 187h 11-- 1111 11-- 1111 uu-- uuuu 18Ch 1000 -000 1000 -000 1000 -000 Register PMCON1 Legend: Note 1: 2: 3: 4: 5: MCLR Reset/ WDT Reset Wake-up from Sleep through Interrupt/Time-out u = unchanged, x = unknown, - = unimplemented bit, reads as `0', q = value depends on condition. If VDD goes too low, Power-on Reset will be activated and registers will be affected differently. One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up). When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). See Table 3-8 for Reset value for specific condition. If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u. 2010-2013 Microchip Technology Inc. DS40001430E-page 33 PIC16(L)F720/721 TABLE 3-7: INITIALIZATION CONDITION FOR SPECIAL REGISTERS Program Counter STATUS Register PCON Register Power-on Reset 0000h 0001 1xxx ---- --0x MCLR Reset during normal operation 0000h 000u uuuu ---- --uu MCLR Reset during Sleep 0000h 0001 0uuu ---- --uu WDT Reset 0000h 0000 uuuu ---- --uu WDT Wake-up PC + 1 uuu0 0uuu ---- --uu Brown-out Reset 0000h 0001 1xxx ---- --10 uuu1 0uuu ---- --uu Condition Interrupt Wake-up from Sleep PC + 1 (1) Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as `0'. Note 1: When the wake-up is due to an interrupt and Global Interrupt Enable bit (GIE) is set, the PC is loaded with the interrupt vector (0004h) after execution of PC + 1. TABLE 3-8: SUMMARY OF REGISTERS ASSOCIATED WITH RESETS Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page STATUS IRP RP1 RP0 TO PD Z DC C 20 -- -- -- -- -- -- POR BOR 22 PCON Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as `0', q = value depends on condition. Shaded cells are not used by Resets. Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. DS40001430E-page 34 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 4.0 INTERRUPTS The PIC16(L)F720/721 device family features an interruptible core, allowing certain events to preempt normal program flow. An Interrupt Service Routine (ISR) is used to determine the source of the interrupt and act accordingly. Some interrupts can be configured to wake the MCU from Sleep mode. The PIC16(L)F720/721 device family has 11 interrupt sources, differentiated by corresponding interrupt enable and flag bits: * * * * * * * * * * * Timer0 Overflow Interrupt External Edge Detect on INT Pin Interrupt Interrupt-on-change, PORTA and PORTB pins Timer1 Gate Interrupt A/D Conversion Complete Interrupt AUSART Receive Interrupt AUSART Transmit Interrupt SSP Event Interrupt CCP1 Event Interrupt Timer2 Match with PR2 Interrupt Timer1 Overflow Interrupt A block diagram of the interrupt logic is shown in Figure 4-1. FIGURE 4-1: INTERRUPT LOGIC IOC-RB4 IOCB4 IOC-RB5 IOCB5 IOC-RB6 IOCB6 IOC-RB7 IOCB7 IOC-RA0 IOCA0 IOC-RA1 IOCA1 IOC-RA2 IOCA2 IOC-RA3 IOCA3 IOC-RA4 IOCA4 IOC-RA5 IOCA5 2010-2013 Microchip Technology Inc. SSPIF SSPIE TXIF TXIE RCIF RCIE TMR2IF TMR2IE TMR1IF TMR1IE ADIF ADIE TMR1GIF TMR1GIE Wake-up (if in Sleep mode)(1) TMR0IF TMR0IE INTF INTE RABIF RABIE Interrupt to CPU PEIE GIE CCP1IF CCP1IE Note 1: Some peripherals depend upon the system clock for operation. Since the system clock is suspended during Sleep, these peripherals will not wake the part from Sleep. See Section 19.1 "Wake-up from Sleep". DS40001430E-page 35 PIC16(L)F720/721 4.1 Operation interrupts. Because the GIE bit is cleared, any interrupt that occurs while executing the ISR will be recorded through its Interrupt Flag, but will not cause the processor to redirect to the interrupt vector. Interrupts are disabled upon any device Reset. They are enabled by setting the following bits: * GIE bit of the INTCON register * Interrupt Enable bit(s) for the specific interrupt event(s) * PEIE bit of the INTCON register (if the Interrupt Enable bit of the interrupt event is contained in the PIE1 register) The RETFIE instruction exits the ISR by popping the previous address from the stack and setting the GIE bit. For additional information on a specific interrupt's operation, refer to its peripheral chapter. Note 1: Individual interrupt flag bits are set, regardless of the state of any other enable bits. The INTCON and PIR1 registers record individual interrupts via interrupt flag bits. Interrupt flag bits will be set, regardless of the status of the GIE, PEIE and individual Interrupt Enable bits. 2: All interrupts will be ignored while the GIE bit is cleared. Any interrupt occurring while the GIE bit is clear will be serviced when the GIE bit is set again. The following events happen when an interrupt event occurs while the GIE bit is set: * Current prefetched instruction is flushed * GIE bit is cleared * Current Program Counter (PC) is pushed onto the stack * PC is loaded with the interrupt vector 0004h 4.2 Interrupt latency is defined as the time from when the interrupt event occurs to the time code execution at the interrupt vector begins. The latency for synchronous interrupts is three instruction cycles. For asynchronous interrupts, the latency is three to four instruction cycles, depending on when the interrupt occurs. See Figure 4-2 for timing details. The ISR determines the source of the interrupt by polling the interrupt flag bits. The interrupt flag bits must be cleared before exiting the ISR to avoid repeated FIGURE 4-2: Interrupt Latency INT PIN INTERRUPT TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CLKIN CLKOUT (3) (4) INT pin (1) (1) INTF flag (INTCON<1>) Interrupt Latency (2) (5) GIE bit (INTCON<7>) INSTRUCTION FLOW PC Instruction Fetched Instruction Executed Note 1: PC Inst (PC) Inst (PC - 1) PC + 1 Inst (PC + 1) Inst (PC) PC + 1 -- Dummy Cycle 0004h 0005h Inst (0004h) Inst (0005h) Dummy Cycle Inst (0004h) INTF flag is sampled here (every Q1). 2: Asynchronous interrupt latency = 3-4 TCY. Synchronous latency = 3 TCY, where TCY = instruction cycle time. Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction. 3: CLKOUT is available only in INTOSC and RC Oscillator modes. 4: For minimum width of INT pulse, refer to AC specifications in Section 23.0 "Electrical Specifications". 5: INTF is enabled to be set any time during the Q4-Q1 cycles. DS40001430E-page 36 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 4.3 Interrupts During Sleep Some interrupts can be used to wake from Sleep. To wake from Sleep, the peripheral must be able to operate without the system clock. The interrupt source must have the appropriate Interrupt Enable bit(s) set prior to entering Sleep. On waking from Sleep, if the GIE bit is also set, the processor will branch to the interrupt vector. Otherwise, the processor will continue executing instructions after the SLEEP instruction. The instruction directly after the SLEEP instruction will always be executed before branching to the ISR. Refer to the Section 19.0 "Power-Down Mode (Sleep)" for more details. 4.4 INT Pin The external interrupt, INT pin, causes an asynchronous, edge-triggered interrupt. The INTEDG bit of the OPTION_REG register determines on which edge the interrupt will occur. When the INTEDG bit is set, the rising edge will cause the interrupt. When the INTEDG bit is clear, the falling edge will cause the interrupt. The INTF bit of the INTCON register will be set when a valid edge appears on the INT pin. If the GIE and INTE bits are also set, the processor will redirect program execution to the interrupt vector. This interrupt is disabled by clearing the INTE bit of the INTCON register. 4.5 Context Saving When an interrupt occurs, only the return PC value is saved to the stack. If the ISR modifies or uses an instruction that modifies key registers, their values must be saved at the beginning of the ISR and restored when the ISR completes. This prevents instructions EXAMPLE 4-1: Note: The microcontroller does not normally require saving the PCLATH register. However, if computed GOTOs are used, the PCLATH register must be saved at the beginning of the ISR and restored when the ISR is complete to ensure correct program flow. The code shown in Example 4-1 can be used to do the following. * * * * * * * Save the W register Save the STATUS register Save the PCLATH register Execute the ISR program Restore the PCLATH register Restore the STATUS register Restore the W register Since most instructions modify the W register, it must be saved immediately upon entering the ISR. The SWAPF instruction is used when saving and restoring the W and STATUS registers because it will not affect any bits in the STATUS register. It is useful to place W_TEMP in shared memory because the ISR cannot predict which bank will be selected when the interrupt occurs. The processor will branch to the interrupt vector by loading the PC with 0004h. The PCLATH register will remain unchanged. This requires the ISR to ensure that the PCLATH register is set properly before using an instruction that causes PCLATH to be loaded into the PC. See Section 2.3 "PCL and PCLATH" for details on PC operation. SAVING W, STATUS AND PCLATH REGISTERS IN RAM MOVWFW_TEMP SWAPFSTATUS,W BANKSELSTATUS_TEMP MOVWFSTATUS_TEMP MOVF PCLATH,W MOVWF PCLATH_TEMP : :(ISR) : BANKSELSTATUS_TEMP MOVF PCLATH_TEMP,W MOVWF PCLATH SWAPFSTATUS_TEMP,W MOVWFSTATUS SWAPFW_TEMP,F SWAPFW_TEMP,W following the ISR from using invalid data. Examples of key registers include the W, STATUS, FSR and PCLATH registers. ;Copy W to W_TEMP register ;Swap status to be saved into W ;Swaps are used because they do not affect the status bits ;Select regardless of current bank ;Copy status to bank zero STATUS_TEMP register ;Copy PCLATH to W register ;Copy W register to PCLATH_TEMP ;Insert user code here ;Select regardless of current bank ; ;Restore PCLATH ;Swap STATUS_TEMP register into W ;(sets bank to original state) ;Move W into STATUS register ;Swap W_TEMP ;Swap W_TEMP into W 2010-2013 Microchip Technology Inc. DS40001430E-page 37 PIC16(L)F720/721 4.5.1 INTCON REGISTER Note: The INTCON register is a readable and writable register, which contains the various enable and flag bits for TMR0 register overflow, PORTB change and external RA2/INT pin interrupts. REGISTER 4-1: R/W-0 INTCON: INTERRUPT CONTROL REGISTER R/W-0 GIE Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. PEIE R/W-0 TMR0IE R/W-0 INTE R/W-0 (1) RABIE R/W-0 R/W-0 R/W-x TMR0IF(2) INTF RABIF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 GIE: Global Interrupt Enable bit 1 = Enables all unmasked interrupts 0 = Disables all interrupts bit 6 PEIE: Peripheral Interrupt Enable bit 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts bit 5 TMR0IE: Timer0 Overflow Interrupt Enable bit 1 = Enables the Timer0 interrupt 0 = Disables the Timer0 interrupt bit 4 INTE: INT External Interrupt Enable bit 1 = Enables the INT external interrupt 0 = Disables the INT external interrupt bit 3 RABIE: PORTA or PORTB Change Interrupt Enable bit(1) 1 = Enables the PORTA or PORTB change interrupt 0 = Disables the PORTA or PORTB change interrupt bit 2 TMR0IF: Timer0 Overflow Interrupt Flag bit(2) 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow bit 1 INTF: INT External Interrupt Flag bit 1 = The INT external interrupt occurred (must be cleared in software) 0 = The INT external interrupt did not occur bit 0 RABIF: PORTA or PORTB Change Interrupt Flag bit 1 = When at least one of the PORTA or PORTB general purpose I/O pins changed state (must be cleared in software) 0 = None of the PORTA or PORTB general purpose I/O pins have changed state Note 1: 2: The appropriate bits in the IOCB register must also be set. TMR0IF bit is set when Timer0 rolls over. Timer0 is unchanged on Reset and should be initialized before clearing TMR0IF bit. DS40001430E-page 38 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 4.5.2 PIE1 REGISTER The PIE1 register contains the interrupt enable bits, as shown in Register 4-2. REGISTER 4-2: Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7 TMR1GIE: Timer1 Gate Interrupt Enable bit 1 = Enable the Timer1 gate acquisition complete interrupt 0 = Disable the Timer1 gate acquisition complete interrupt bit 6 ADIE: A/D Converter (ADC) Interrupt Enable bit 1 = Enables the ADC interrupt 0 = Disables the ADC interrupt bit 5 RCIE: USART Receive Interrupt Enable bit 1 = Enables the USART receive interrupt 0 = Disables the USART receive interrupt bit 4 TXIE: USART Transmit Interrupt Enable bit 1 = Enables the USART transmit interrupt 0 = Disables the USART transmit interrupt bit 3 SSPIE: Synchronous Serial Port (SSP) Interrupt Enable bit 1 = Enables the SSP interrupt 0 = Disables the SSP interrupt bit 2 CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the Timer2 to PR2 match interrupt 0 = Disables the Timer2 to PR2 match interrupt bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit 1 = Enables the Timer1 overflow interrupt 0 = Disables the Timer1 overflow interrupt 2010-2013 Microchip Technology Inc. x = Bit is unknown DS40001430E-page 39 PIC16(L)F720/721 4.5.3 PIR1 REGISTER The PIR1 register contains the interrupt flag bits, as shown in Register 4-3. REGISTER 4-3: Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1 R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 TMR1GIF: Timer1 Gate Interrupt Flag bit 1 = Timer1 gate is inactive 0 = Timer1 gate is active bit 6 ADIF: A/D Converter Interrupt Flag bit 1 = A/D conversion complete (must be cleared in software) 0 = A/D conversion has not completed or has not been started bit 5 RCIF: USART Receive Interrupt Flag bit 1 = The USART receive buffer is full (cleared by reading RCREG) 0 = The USART receive buffer is not full bit 4 TXIF: USART Transmit Interrupt Flag bit 1 = The USART transmit buffer is empty (cleared by writing to TXREG) 0 = The USART transmit buffer is full bit 3 SSPIF: Synchronous Serial Port (SSP) Interrupt Flag bit 1 = The Transmission/Reception is complete (must be cleared in software) 0 = Waiting to Transmit/Receive bit 2 CCP1IF: CCP1 Interrupt Flag bit Capture mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unused in this mode bit 1 TMR2IF: Timer2 to PR2 Interrupt Flag bit 1 = A Timer2 to PR2 match occurred (must be cleared in software) 0 = No Timer2 to PR2 match occurred bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit 1 = The TMR1 register overflowed (must be cleared in software) 0 = The TMR1 register did not overflow DS40001430E-page 40 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 TABLE 4-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page GIE PEIE TMR0IE INTE RABIE TMR0IF INTF RABIF 38 RABPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 21 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 39 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 40 Name INTCON OPTION_REG Legend: - = Unimplemented locations, read as `0', u = unchanged, x = unknown. Shaded cells are not used by the capture, compare and PWM. 2010-2013 Microchip Technology Inc. DS40001430E-page 41 PIC16(L)F720/721 NOTES: DS40001430E-page 42 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 5.0 LOW DROPOUT (LDO) VOLTAGE REGULATOR The PIC16F720/721 devices differ from the PIC16LF720/721 devices due to an internal Low Dropout (LDO) voltage regulator. The PIC16F720/721 contain an internal LDO, while the PIC16LF720/721 do not. The lithography of the die allows a maximum operating voltage of 3.6V on the internal digital logic. In order to continue to support 5.0V designs, a LDO voltage regulator is integrated on the die. The LDO voltage regulator allows for the internal digital logic to operate at 3.2V, while I/O's operate at 5.0V (VDD). 2010-2013 Microchip Technology Inc. DS40001430E-page 43 PIC16(L)F720/721 NOTES: DS40001430E-page 44 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 6.0 I/O PORTS 6.1.1 WEAK PULL-UPS There are as many as eighteen general purpose I/O pins available. Depending on which peripherals are enabled, some or all of the pins may not be available as general purpose I/O. In general, when a peripheral is enabled, the associated pin may not be used as a general purpose I/O pin. Each of the PORTA pins has an individually configurable internal weak pull-up. Control bits WPUA<5:0> enable or disable each pull-up (see Register 6-5). Each weak pull-up is automatically turned off when the port pin is configured as an output. All pull-ups are disabled on a Power-on Reset by the RABPU bit of the OPTION_REG register. 6.1 6.1.2 PORTA and TRISA Registers PORTA is a 8-bit wide, bidirectional port. The corresponding data direction register is TRISA (Register 6-2). Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., disable the output driver). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., enables output driver and puts the contents of the output latch on the selected pin). Example 6-1 shows how to initialize PORTA. Reading the PORTA register (Register 6-1) reads the status of the pins, whereas writing to it will write to the PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch. The TRISA register (Register 6-2) controls the PORTA pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the TRISA register are maintained set when using them as analog inputs. I/O pins configured as analog input always read `0'. Note: The ANSELA register must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read `0'. EXAMPLE 6-1: BANKSEL CLRF BANKSEL CLRF BANKSEL MOVLW MOVWF PORTA PORTA ANSELA ANSELA TRISA 0Ch TRISA INITIALIZING PORTA ; ;Init PORTA ; ;digital I/O ; ;Set RA<3:2> as inputs ;and set RA<5:4,1:0> ;as outputs 2010-2013 Microchip Technology Inc. INTERRUPT-ON-CHANGE All of the PORTA pins are individually configurable as an interrupt-on-change pin. Control bits IOCA<5:0> enable or disable the interrupt function for each pin (see Register 6-6). The interrupt-on-change feature is disabled on a Power-on Reset. For enable interrupt-on-change pins, the present value is compared with the old value latched on the last read of PORTA to determine which bits have changed or mismatched the old value. The `mismatch' outputs of the last read are OR'd together to set the PORTA Change Interrupt Flag bit (RABIF) in the INTCON register. This interrupt can wake the device from Sleep. The user, in the Interrupt Service Routine, clears the interrupt by: 1. 2. Any read or write of PORTA. This will end the mismatch condition. Clear the flag bit RABIF. A mismatch condition will continue to set flag bit RABIF. Reading or writing PORTA will end the mismatch condition and allow flag bit RABIF to be cleared. The latch holding the last read value is not affected by a MCLR or Brown-out Reset. After these Resets, the RABIF flag will continue to be set if a mismatch is present. Note: When a pin change occurs at the same time as a read operation on PORTA, the RABIF flag will always be set. If multiple PORTA pins are configured for the interrupt-on-change, the user may not be able to identify which pin changed state. DS40001430E-page 45 PIC16(L)F720/721 REGISTER 6-1: PORTA: PORTA REGISTER U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u -- -- RA5 RA4 RA3(1) RA2 RA1 RA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-6 Unimplemented: Read as `0' bit 5-0 RA<5:0>: PORTA I/O Pin bit 1 = Port pin is > VIH 0 = Port pin is < VIL Note 1: x = Bit is unknown RA<3> is input only. REGISTER 6-2: TRISA: PORTA TRI-STATE REGISTER U-0 U-0 R/W-1 R/W-1 U-1 R/W-1 R/W-1 R/W-1 -- -- TRISA5 TRISA4 --(1) TRISA2 TRISA1 TRISA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-6 Unimplemented: Read as `0' bit 5-4 TRISA<5:4>: PORTA Tri-State Control bit 1 = PORTA pin configured as an input (tri-stated) 0 = PORTA pin configured as an output bit 3 Unimplemented: Read as `1' bit 2-0 TRISA<2:0>: PORTA Tri-State Control bit 1 = PORTA pin configured as an input (tri-stated) 0 = PORTA pin configured as an output Note 1: x = Bit is unknown TRISA<3> is unimplemented and read as 1. REGISTER 6-3: U-0 WPUA: WEAK PULL-UP PORTA REGISTER U-0 -- -- R/W-1 WPUA5 R/W-1 WPUA4 R/W-1 WPUA3 (2) R/W-1 R/W-1 R/W-1 WPUA2 WPUA1 WPUA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-6 Unimplemented: Read as `0' bit 5-0 WPUA<5:0>: Weak Pull-up PORTA Control bits 1 = Weak pull-up enabled(1) 0 = Weak pull-up disabled x = Bit is unknown Note 1: Enabling weak pull-ups also requires that the RABPU bit of the OPTION_REG register be cleared. 2: If MCLREN = 1, WPUA3 is always enabled. DS40001430E-page 46 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 REGISTER 6-4: IOCA: INTERRUPT-ON-CHANGE PORTA REGISTER U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- IOCA5 IOCA4 IOCA3 IOCA2 IOCA1 IOCA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-6 Unimplemented: Read as `0' bit 5-0 IOCA<5:0>: Interrupt-on-Change PORTA Control bits 1 = Interrupt-on-change enabled(1) 0 = Interrupt-on-change disabled x = Bit is unknown Note 1: Interrupt-on-change also requires that the RABIE bit of the INTCON register be set. 6.1.3 ANSELA REGISTER The ANSELA register (Register 6-5) is used to configure the Input mode of an I/O pin to analog. Setting the appropriate ANSELA bit high will cause all digital reads on the pin to be read as `0' and allow analog functions on the pin to operate correctly. The state of the ANSELA bits has no affect on digital output functions. A pin with TRIS clear and ANSEL set will still operate as a digital output, but the Input mode will be analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected port. REGISTER 6-5: ANSELA: PORTA ANALOG SELECT REGISTER U-0 U-0 U-0 R/W-1 U-0 R/W-1 R/W-1 R/W-1 -- -- -- ANSA4 -- ANSA2 ANSA1 ANSA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as `0' bit 4 ANSA4: Analog Select between Analog or Digital Function on Pin RA<4> 0 = Digital I/O. Pin is assigned to port or digital special function. 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer is disabled. bit 3 Unimplemented: Read as `0' bit 2-0 ANSA<2:0>: Analog Select between Analog or Digital Function on Pins RA<2:0>, respectively 0 = Digital I/O. Pin is assigned to port or digital special function. 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer is disabled. Note 1: Setting a pin to an analog input automatically disables the digital input circuitry. Weak pull-ups, if available, are unaffected. The corresponding TRIS bit must be set to Input mode by the user in order to allow external control of the voltage on the pin. 2010-2013 Microchip Technology Inc. DS40001430E-page 47 PIC16(L)F720/721 6.1.4 PIN DESCRIPTIONS AND DIAGRAMS Each PORTA pin is multiplexed with other functions. The pins and their combined functions are briefly described here. For specific information about individual functions such as the A/D Converter (ADC), refer to the appropriate section in this data sheet. 6.1.4.1 RA0/AN0/ICSPDAT Figure 6-1 shows the diagram for this pin. This pin is configurable to function as one of the following: * General purpose I/O * Analog input for the ADC * ICSP programming data (separate controls from TRISA) * ICD Debugging data (separate controls from TRISA) 6.1.4.2 RA1/AN1/ICSPCLK Figure 6-2 shows the diagram for this pin. This pin is configurable to function as one of the following: * General purpose I/O * Analog input for the ADC * ICSP programming clock (separate controls from TRISA) * ICD Debugging clock (separate controls from TRISA) 6.1.4.3 RA2/AN2/T0CKI/INT Figure 6-3 shows the diagram for this pin. This pin is configurable to function as one of the following: * * * * General purpose I/O Analog input for the ADC External interrupt Clock input for Timer0 The Timer0 clock input function works independently of any TRIS register setting. Effectively, if TRISA2 = 0, the PORTA2 register bit will output to the pad and Clock Timer0 at the same time. 6.1.4.4 RA3/MCLR/VPP Figure 6-4 shows the diagram for this pin. This pin is configurable to function as one of the following: * General purpose I/O * Master Clear Reset with weak pull-up 6.1.4.5 RA4/AN3/T1G/CLKOUT Figure 6-5 shows the diagram for this pin. This pin is configurable to function as one of the following: * * * * General purpose I/O Analog input for the ADC Timer1 gate input Clock output 6.1.4.6 RA5/T1CKI/CLKIN Figure 6-6 shows the diagram for this pin. This pin is configurable to function as one of the following: * General purpose I/O * Timer1 Clock input * Clock input DS40001430E-page 48 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 FIGURE 6-1: BLOCK DIAGRAM OF RA0 ICSPTM mode Analog(1) Input mode DEBUG VDD Data Bus D Weak Q CK Q WR WPUA RABPU RD WPUA VDD PORT_ICDDAT 0 1 D WR PORTA Q 1 0 CK Q I/O Pin VSS 0 1 D WR TRISA TRIS_ICDDAT Q CK Q RD TRISA Analog(1) Input mode RD PORTA D WR IOCA Q CK Q Q RD IOCA D EN Q Q3 D EN Interrupt-on-Change RD PORTA ICSPDAT To A/D Converter Note 1: ANSEL determines Analog Input mode. 2010-2013 Microchip Technology Inc. DS40001430E-page 49 PIC16(L)F720/721 FIGURE 6-2: BLOCK DIAGRAM OF RA1 Data Bus WR WPUA D Q DEBUG VDD CK Q Weak RABPU RD WPUA D WR PORTA ICSPTM mode Analog(1) Input mode Q PORT_ICDCLK CK Q VDD 0 1 1 0 D WR TRISA I/O Pin Q 0 CK Q VSS 1 RD TRISA Analog(1) Input mode TRIS_ICDCLK RD PORTA D WR IOCA Q Q CK Q D EN Q3 RD IOCA Q Interrupt-on-Change D EN RD PORTA To A/D Converter ICSPCLK Note DS40001430E-page 50 1: ANSEL determines Analog Input mode. 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 FIGURE 6-3: BLOCK DIAGRAM OF RA2 Data Bus WR WPUA D CK Q Analog(1) Input mode Q Weak To Voltage Regulator (for PIC16F720/721 only) RABPU RD WPUA D WR PORTA VDD CK VDD Q Q I/O Pin D WR TRISA CK Q Q VSS Analog(1) Input mode RD TRISA RD PORTA D WR IOCA CK Q Q Q D EN RD IOCA Q Interrupt-onChange Q3 D EN RD PORTA To Timer0 To INT To A/D Converter Note 1: ANSEL determines Analog Input mode. 2010-2013 Microchip Technology Inc. DS40001430E-page 51 PIC16(L)F720/721 FIGURE 6-4: BLOCK DIAGRAM OF RA3 FIGURE 6-5: BLOCK DIAGRAM OF RA4 VDD MCLRE Analog(2) Input mode Weak Data Bus Data Bus Reset RD TRISA Input Pin WR WPUA D CK Q VDD Q Weak VSS MCLRE RD PORTA D WR IOCA MCLRE CK VSS RABPU RD WPUA Q Q Q RD IOCA Interrupt-onChange Q D Q3 D WR PORTA CK FOSC/4 Q 0 I/O Pin CLKOUT Enable D WR TRISA 1 Q EN RD PORTA VDD CLKOUT Enable D EN CLK modes CK VSS Q INTOSC/ RC/EC(1) Q CLKOUT Enable RD TRISA Analog Input mode RD PORTA D WR IOCA CK Q Q Q D EN RD IOCA Q Q3 D EN Interrupt-onChange RD PORTA To T1G To A/D Converter Note DS40001430E-page 52 1: With CLKOUT option. 2: ANSEL determines Analog Input mode. 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 FIGURE 6-6: BLOCK DIAGRAM OF RA5 INTOSC mode Data Bus D WR WPUA CK VDD Q Weak Q RABPU RD WPUA D WR PORTA CK VDD Q Q I/O Pin D WR TRISA CK Q Q VSS INTOSC mode RD TRISA RD PORTA D WR IOCA CK Q Q Q D EN Q3 RD IOCA Q D EN Interrupt-onChange RD PORTA To TMR1 or CLKIN TABLE 6-1: Name ANSELA OPTION_REG SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page -- -- -- ANSA4 -- ANSA2 ANSA1 ANSA0 47 RABPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 21 RA4 RA3 RA2 RA1 RA0 46 TRISA4 -- TRISA2 TRISA1 TRISA0 46 PORTA -- -- RA5 TRISA -- -- TRISA5 Legend: x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by PORTA. 2010-2013 Microchip Technology Inc. DS40001430E-page 53 PIC16(L)F720/721 6.2 PORTB and TRISB Registers PORTB is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISB (Register 6-7). Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). Example 6-2 shows how to initialize PORTB. Reading the PORTB register (Register 6-6) reads the status of the pins, whereas writing to it will write to the PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch. The TRISB register (Register 6-7) controls the PORTB pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the TRISB register are maintained set when using them as analog inputs. I/O pins configured as analog input always read `0'. Example 6-2 shows how to initialize PORTB. EXAMPLE 6-2: BANKSEL CLRF BANKSEL CLRF BANKSEL MOVLW MOVWF Note: INITIALIZING PORTB PORTB ; PORTB ;Init PORTB ANSELB ANSELB ;Make RB<7:4> digital TRISB ; B'11110000';Set RB<7:4> as inputs TRISB ; The ANSELB register must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read `0'. 6.2.1 ANSELB REGISTER The ANSELB register (Register 6-10) is used to configure the Input mode of an I/O pin to analog. Setting the appropriate ANSELB bit high will cause all digital reads on the pin to be read as `0' and allow analog functions on the pin to operate correctly. The state of the ANSELB bits has no affect on digital output functions. A pin with TRIS clear and ANSELB set will still operate as a digital output, but the Input mode will be analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected port. 6.2.2 WEAK PULL-UPS Each of the PORTB pins has an individually configurable internal weak pull-up. Control bits WPUB<7:4> enable or disable each pull-up (see Register 6-8). Each weak pullup is automatically turned off when the port pin is configured as an output. All pull-ups are disabled on a Power-on Reset by the RABPU bit of the OPTION_REG register. 6.2.3 INTERRUPT-ON-CHANGE All of the PORTB pins are individually configurable as an interrupt-on-change pin. Control bits IOCB<7:4> enable or disable the interrupt function for each pin. Refer to Register 6-9. The interrupt-on-change feature is disabled on a Power-on Reset. For enabled interrupt-on-change pins, the present value is compared with the old value latched on the last read of PORTB to determine which bits have changed or mismatched the old value. The `mismatch' outputs of the last read are OR'd together to set the PORTB Change Interrupt Flag bit (RABIF) in the INTCON register. This interrupt can wake the device from Sleep. The user, in the Interrupt Service Routine, clears the interrupt by: a) b) Any read or write of PORTB. This will end the mismatch condition. Clear the flag bit RABIF. A mismatch condition will continue to set flag bit RABIF. Reading or writing PORTB will end the mismatch condition and allow flag bit RABIF to be cleared. The latch holding the last read value is not affected by a MCLR nor Brown-out Reset. After these Resets, the RABIF flag will continue to be set if a mismatch is present. Note: DS40001430E-page 54 When a pin change occurs at the same time as a read operation on PORTB, the RABIF flag will always be set. If multiple PORTB pins are configured for the interrupt-on-change, the user may not be able to identify which pin changed state. 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 REGISTER 6-6: PORTB: PORTB REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u U-0 U-0 U-0 U-0 RB7 RB6 RB5 RB4 -- -- -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-4 RB<7:4>: PORTB I/O Pin bit 1 = Port pin is > VIH 0 = Port pin is < VIL bit 3-0 Unimplemented: Read as `0' REGISTER 6-7: x = Bit is unknown TRISB: PORTB TRI-STATE REGISTER R/W-1 R/W-1 R/W-1 R/W-1 U-0 U-0 U-0 U-0 TRISB7 TRISB6 TRISB5 TRISB4 -- -- -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-4 TRISB<7:4>: PORTB Tri-State Control bit 1 = PORTB pin configured as an input (tri-stated) 0 = PORTB pin configured as an output bit 3-0 Unimplemented: Read as `0' REGISTER 6-8: x = Bit is unknown WPUB: WEAK PULL-UP PORTB REGISTER R/W-1 R/W-1 R/W-1 R/W-1 U-0 U-0 U-0 U-0 WPUB7 WPUB6 WPUB5 WPUB4 -- -- -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-4 WPUB<7:4>: Weak Pull-up PORTB Control bits 1 = Weak pull-up enabled (1,2) 0 = Weak pull-up disabled bit 3-0 Unimplemented: Read as `0' Note 1: 2: x = Bit is unknown Global RABPU bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled. The weak pull-up device is automatically disabled if the pin is in configured as an output. 2010-2013 Microchip Technology Inc. DS40001430E-page 55 PIC16(L)F720/721 REGISTER 6-9: R/W-0 IOCB: INTERRUPT-ON-CHANGE PORTB REGISTER R/W-0 IOCB7 IOCB6 R/W-0 IOCB5 R/W-0 U-0 U-0 U-0 U-0 IOCB4 -- -- -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-4 IOCB<7:4>: Interrupt-on-Change PORTB Control bits 1 = Interrupt-on-change enabled(1) 0 = Interrupt-on-change disabled bit 3-0 Unimplemented: Read as `0' x = Bit is unknown Note 1: Interrupt-on-change also requires that the RABIE bit of the INTCON register be set. REGISTER 6-10: ANSELB: PORTB ANALOG SELECT REGISTER U-0 U-0 R/W-1 R/W-1 U-0 U-0 U-0 U-0 -- -- ANSB5 ANSB4 -- -- -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as `0' bit 5-4 ANSB<5:4>: Analog Select between Analog or Digital Function on Pins RB<5:4>, respectively 0 = Digital I/O. Pin is assigned to port or digital special function. 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. bit 3-0 Unimplemented: Read as `0' Note 1: Setting a pin to an analog input automatically disables the digital input circuitry. Weak pull-ups, if available, are unaffected. The corresponding TRIS bit must be set to Input mode by the user, in order to allow external control of the voltage on the pin. DS40001430E-page 56 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 6.2.4 PIN DESCRIPTIONS AND DIAGRAMS Each PORTB pin is multiplexed with other functions. The pins and their combined functions are briefly described here. For specific information about individual functions such as the SSP, I2CTM or interrupts, refer to the appropriate section in this data sheet. 6.2.4.1 RB4/AN10/SDI/SDA Figure 6-7 shows the diagram for this pin. The RB4 pin is configurable to function as one of the following: FIGURE 6-7: Data Bus WR WPUB WR PORTB 6.2.4.2 WR TRISB Figure 6-8 shows the diagram for this pin. The RB5 pin is configurable to function as one of the following: * General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. * Analog input for the A/D * USART asynchronous receive * USART synchronous receive 6.2.4.3 RB6/SCK/SCL Figure 6-9 shows the diagram for this pin. The RB6 pin is configurable to function as one of the following: * General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. * Synchronous Serial Port clock for both SPI and I2C 6.2.4.4 VDD CK Q Weak RABPU D Q SSPEN VDD SSP 0 1 CK Q 1 0 D Q CK I/O Pin From 1 0 SSP Q VSS 0 1 Analog(1) Input mode RD TRISB RD PORTB D Q Q CK Q WR IOCB D EN RD IOCB Q D Q3 ST EN Interrupt-onChange RD PORTB To SSP To A/D Converter RB7/TX/CK Figure 6-10 shows the diagram for this pin. The RB7 pin is configurable to function as one of the following: Q Analog(1) Input mode RD WPUB * General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. * Analog input for the A/D * Synchronous Serial Port Input (SPI) * I2C data I/O RB5/AN11/RX/DT D BLOCK DIAGRAM OF RB4 Note 1: ANSEL determines Analog Input mode. * General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. * USART asynchronous transmit * USART synchronous clock 2010-2013 Microchip Technology Inc. DS40001430E-page 57 PIC16(L)F720/721 FIGURE 6-8: Data Bus WR WPUB D BLOCK DIAGRAM OF RB5 Q Analog(1) Input mode Data Bus VDD CK Q WR WPUB Weak D BLOCK DIAGRAM OF RB6 Q VDD CK Q Weak RABPU RD WPUB RABPU RD WPUB FIGURE 6-9: SYNC SPEN D WR PORTB Q CK Q D VDD AUSART DT 1 0 1 0 D WR TRISB Q WR TRISB VSS 0 1 Analog(1) Input mode RD TRISB CK Q Q CK Q RD IOCB Q WR IOCB D EN D 0 1 From SSP 1 0 I/O Pin VSS 1 0 Q Q CK Q D EN Q3 ST EN Interrupt-onChange Q VDD RD PORTB D D Q SSPEN SSP Clock 1 0 RD TRISB RD PORTB WR IOCB CK Q D I/O Pin From AUSART 1 0 CK Q WR PORTB Q RD IOCB Q D Q3 ST EN Interrupt-onChange RD PORTB RD PORTB To SSP To AUSART RX/DT To A/D Converter Note 1: ANSEL determines Analog Input mode. DS40001430E-page 58 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 FIGURE 6-10: Data Bus D WR WPUB BLOCK DIAGRAM OF RB7 Q VDD CK Q Weak RABPU RD WPUB SPEN TXEN SYNC D WR PORTB Q AUSART CK 0 1 AUSART TX 1 0 VDD CK Q 0 1 0 1 D WR TRISB I/O Pin Q `1' CK Q 0 1 VSS 1 0 RD TRISB RD PORTB D WR IOCB Q Q CK Q D EN RD IOCB Q Q3 D EN Interrupt-onChange RD PORTB TABLE 6-2: Name ANSELB SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page -- -- ANSB5 ANSB4 -- -- -- -- 56 GIE PEIE TMR0IE INTE RABIE TMR0IF INTF RABIF 38 IOCB IOCB7 IOCB6 IOCB5 IOCB4 -- -- -- -- 56 OPTION_REG RABPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 21 INTCON PORTB RB7 RB6 RB5 RB4 -- -- -- -- 55 TRISB TRISB7 TRISB6 TRISB5 TRISB4 -- -- -- -- 55 WPUB WPUB7 WPUB6 WPUB5 WPUB4 -- -- -- -- 55 Legend: x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by PORTB. 2010-2013 Microchip Technology Inc. DS40001430E-page 59 PIC16(L)F720/721 6.3 PORTC and TRISC Registers PORTC is a 8-bit wide, bidirectional port. The corresponding data direction register is TRISC (Register 6-12). Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). Example 6-3 shows how to initialize PORTC. Reading the PORTC register (Register 6-11) reads the status of the pins, whereas writing to it will write to the PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch. The TRISC register (Register 6-12) controls the PORTC pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the TRISC register are maintained set when using them as analog inputs. I/O pins configured as analog input always read `0'. EXAMPLE 6-3: BANKSEL CLRF BANKSEL MOVLW MOVWF 6.3.1 INITIALIZING PORTC PORTC PORTC TRISC B`00001100' TRISC ; ;Init PORTC ; ;Set RC<3:2> as inputs ;and set RC<7:4,1:0> ;as outputs ANSELC REGISTER The ANSELC register (Register 6-13) is used to configure the Input mode of an I/O pin to analog. Setting the appropriate ANSELC bit high will cause all digital reads on the pin to be read as `0' and allow analog functions on the pin to operate correctly. The state of the ANSELC bits has no effect on digital output functions. A pin with TRIS clear and ANSELC set will still operate as a digital output, but the Input mode will be analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected port. REGISTER 6-11: PORTC: PORTC REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-0 x = Bit is unknown RC<7:0>: PORTC General Purpose I/O Pin bits 1 = Port pin is > VIH 0 = Port pin is < VIL DS40001430E-page 60 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 REGISTER 6-12: TRISC: PORTC TRI-STATE REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-0 x = Bit is unknown TRISC<7:0>: PORTC Tri-State Control bits 1 = PORTC pin configured as an input (tri-stated) 0 = PORTC pin configured as an output REGISTER 6-13: ANSELC: ANALOG SELECT REGISTER FOR PORTC R/W-1 R/W-1 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 ANSC7 ANSC6 -- -- ANSC3 ANSC2 ANSC1 ANSC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7-6 ANSC<7:6>: Analog Select between Analog or Digital Function on Pins RB<7:6>, respectively 0 = Digital I/O. Pin is assigned to port or digital special function. 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. bit 5-4 Unimplemented: Read as `0' bit 3-0 ANSC<3:0>: Analog Select between Analog or Digital Function on Pins RC<3:0>, respectively 0 = Digital I/O. Pin is assigned to port or digital special function. 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. Note 1: Setting a pin to an analog input automatically disables the digital input circuitry. Weak pull-ups, if available, are unaffected. The corresponding TRIS bit must be set to Input mode by the user in order to allow external control of the voltage on the pin. 2010-2013 Microchip Technology Inc. DS40001430E-page 61 PIC16(L)F720/721 6.3.2 RC0/AN4 Figure 6-11 shows the diagram for this pin. The RC0 pin is configurable to function as one of the following: FIGURE 6-11: Data Bus * General purpose I/O * Analog input for the A/D 6.3.3 RC1/AN5 D WR PORTC Figure 6-11 shows the diagram for this pin. The RC1 pin is configurable to function as one of the following: * General purpose I/O * Analog input for the A/D 6.3.4 RC2/AN6 Figure 6-12 shows the diagram for this pin. The RC2 pin is configurable to function as one of the following: * General purpose I/O * Analog input for the A/D 6.3.5 * General purpose I/O * Analog input for the A/D RC4 Figure 6-13 shows the diagram for this pin. The RC4 pin functions as one of the following: RC5/CCP1 Figure 6-14 shows the diagram for this pin. The RC5 pin is configurable to function as one of the following: * General purpose I/O * Capture, Compare or PWM (1 output) 6.3.8 RC6/AN8/SS Figure 6-15 shows the diagram for this pin. The RC6 pin is configurable to function as one of the following: * General purpose I/O * Analog input for the A/D * SS input to SSP 6.3.9 CK Q I/O Pin D WR TRISC Q CK Q VSS Analog Input mode(1) RD TRISC RD PORTC To A/D Converter Note RC7/AN9/SDO Figure 6-16 shows the diagram for this pin. The RC7 pin is configurable to function as one of the following: 1: ANSEL determines Analog Input mode. FIGURE 6-12: BLOCK DIAGRAM OF RC2 AND RC3 Data Bus * General purpose I/O 6.3.7 VDD Q RC3/AN7 Figure 6-12 shows the diagram for this pin. The RC3 pin is configurable to function as one of the following: 6.3.6 BLOCK DIAGRAM OF RC0 AND RC1 D WR PORTC CK VDD Q Q I/O Pin D WR TRISC CK Q Q VSS Analog Input mode(1) RD TRISC RD PORTC To A/D Converter Note 1: ANSEL determines Analog Input mode. * General purpose I/O * Analog input for the A/D * SDO output of SSP DS40001430E-page 62 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 FIGURE 6-13: BLOCK DIAGRAM OF RC4 FIGURE 6-15: Data Bus VDD D I/O Pin Data Bus D WR PORTC Q CK Q D WR TRISC WR PORTC CK D WR TRISC Q CK Q CK Q Q Q VSS Analog Input mode(1) RD TRISC RD PORTC To SS Input RD PORTC To A/D Converter FIGURE 6-14: Data bus BLOCK DIAGRAM OF RC5 CCP1OUT Enable D CK CCP1OUT D CK 1: ANSEL determines Analog Input mode. FIGURE 6-16: Q Q Note BLOCK DIAGRAM OF RC7 VDD PORT/SDO Select 0 1 Data Bus 1 0 WR TRISC VDD Q I/O Pin VSS RD TRISC WR PORTC BLOCK DIAGRAM OF RC6 Q Q SDO 0 1 I/O Pin D VSS WR PORTC RD TRISC CK Q VDD 1 0 Q I/O Pin D RD PORTC WR TRISC To CCP1 input RD TRISC CK Q Q VSS Analog Input mode(1) RD PORTC To A/D Converter Note 2010-2013 Microchip Technology Inc. 1: ANSEL determines Analog Input mode. DS40001430E-page 63 PIC16(L)F720/721 TABLE 6-3: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSELC ANSC7 ANSC6 -- -- ANSC3 ANSC2 ANSC1 ANSC0 61 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 61 PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 60 Name Legend: x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by PORTC. DS40001430E-page 64 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 7.0 OSCILLATOR MODULE 7.1 Overview Clock source modes are configured by the FOSC bits in Configuration Word 1 (CONFIG1). The oscillator module can be configured for one of the following modes of operation. The oscillator module has a variety of clock sources and selection features that allow it to be used in a range of applications while maximizing performance and minimizing power consumption. Figure 7-1 illustrates a block diagram of the oscillator module. 1. 2. 3. The system can be configured to use an internal calibrated high-frequency oscillator as clock source, with a choice of selectable speeds via software. In addition, the system can also be configured to use an external clock source via the CLKIN pin. FIGURE 7-1: EC - CLKOUT function on RA4/CLKOUT pin, CLKIN on RA5/CLKIN. EC - I/O function on RA4/CLKOUT pin, CLKIN on RA5/CLKIN. INTOSC - CLKOUT function on RA4/CLKOUT pin, I/O function on RA5/CLKIN INTOSCIO - I/O function on RA4/CLKOUT pin, I/O function on RA5/CLKIN 4. SIMPLIFIED PIC(R) MCU CLOCK SOURCE BLOCK DIAGRAM FOSC<1:0> (Configuration Word 1) EC MUX CLKIN Internal Oscillator 0 16 MHz/500 kHz 1 8 MHz/250 kHz Postscaler HFINTOSC 32x PLL 4 MHz/125 kHz 2 MHz/62.5 kHz System Clock (CPU and Peripherals) INTOSC 11 10 MUX MFINTOSC MUX 500 kHz IRCF<1:0> (OSCCON Register) 01 00 PLLEN (Configuration Word 1) 2010-2013 Microchip Technology Inc. DS40001430E-page 65 PIC16(L)F720/721 7.2 Clock Source Modes Clock source modes can be classified as external or internal. * Internal clock source (INTOSC) is contained within the oscillator module and derived from a 500 kHz high precision oscillator. The oscillator module has eight selectable output frequencies, with a maximum internal frequency of 16 MHz. * The External Clock mode (EC) relies on an external signal for the clock source. The system clock can be selected between external or internal clock sources via the FOSC bits of the Configuration Word 1. 7.3 Internal Clock Modes The oscillator module has eight output frequencies derived from a 500 kHz high precision oscillator. The IRCF bits of the OSCCON register select the postscaler applied to the clock source dividing the frequency by 1, 2, 4 or 8. Setting the PLLEN bit of the Configuration Word 1 locks the internal clock source to 16 MHz before the postscaler is selected by the IRCF bits. The PLLEN bit must be set or cleared at the time of programming; therefore, only the upper or low four clock source frequencies are selectable in software. The internal oscillator block has one internal oscillator and a dedicated Phase-Locked Loop that are used to generate two internal system clock sources: the 16 MHz High-Frequency Internal Oscillator (HFINTOSC) and the 500 kHz (MFINTOSC). Both can be useradjusted via software using the OSCTUNE register (Register 7-2). 7.3.1 INTOSC AND INTOSCIO MODES The INTOSC and INTOSCIO modes configure the internal oscillators as the system clock source when the device is programmed using the oscillator selection or the FOSC<1:0> bits in the CONFIG1 register. See Section 8.0 "Device Configuration" for more information. 7.3.2 FREQUENCY SELECT BITS (IRCF) The output of the 500 kHz MFINTOSC and 16 MHz HFINTOSC, with Phase-Locked Loop enabled, connect to a postscaler and multiplexer (see Figure 7-1). The Internal Oscillator Frequency Select bits (IRCF) of the OSCCON register select the frequency output of the internal oscillator. Depending upon the PLLEN bit, one of four frequencies of two frequency sets can be selected via software: If PLLEN = 1, HFINTOSC frequency selection is as follows: * * * * 16 MHz 8 MHz (default after Reset) 4 MHz 2 MHz If PLLEN = 0, MFINTOSC frequency selection is as follows: * * * * 500 kHz 250 kHz (default after Reset) 125 kHz 62.5 kHz Note: Following any Reset, the IRCF<1:0> bits of the OSCCON register are set to `10' and the frequency selection is set to 8 MHz or 250 kHz. The user can modify the IRCF bits to select a different frequency. There is no start-up delay before a new frequency selected in the IRCF bits takes effect. This is because the old and new frequencies are derived from INTOSC via the postscaler and multiplexer. Start-up delay specifications are located in the Table 23-2 in Section 23.0 "Electrical Specifications". In INTOSC mode, CLKIN is available for general purpose I/O. CLKOUT outputs the selected internal oscillator frequency divided by 4. The CLKOUT signal may be used to provide a clock for external circuitry, synchronization, calibration, test or other application requirements. In INTOSCIO mode, CLKIN and CLKOUT are available for general purpose I/O. DS40001430E-page 66 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 7.4 Oscillator Control The Oscillator Control (OSCCON) register (Figure 7-1) displays the status and allows frequency selection of the internal oscillator (INTOSC) system clock. The OSCCON register contains the following bits: * Frequency selection bits (IRCF) * Status Locked bits (ICSL) * Status Stable bits (ICSS) REGISTER 7-1: OSCCON: OSCILLATOR CONTROL REGISTER U-0 U-0 R/W-1 R/W-0 R-q R-q U-0 U-0 -- -- IRCF1 IRCF0 ICSL ICSS -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown q = Value depends on condition bit 7-6 Unimplemented: Read as `0' bit 5-4 IRCF<1:0>: Internal Oscillator Frequency Select bits When PLLEN = 1 (16 MHz HFINTOSC) 11 = 16 MHz 10 = 8 MHz (default) 01 = 4 MHz 00 = 2 MHz When PLLEN = 0 (500 kHz MFINTOSC) 11 = 500 kHz 10 = 250 kHz (default) 01 = 125 kHz 00 = 62.5 kHz bit 3 ICSL: Internal Clock Oscillator Status Locked bit (2% Stable) 1 = 16 MHz/500 kHz internal oscillator is in lock 0 = 16 MHz/500 kHz internal oscillator has not yet locked bit 2 ICSS: Internal Clock Oscillator Status Stable bit (0.5% Stable) 1 = 16 MHz/500 kHz internal oscillator has stabilized to its maximum accuracy 0 = 16 MHz/500 kHz internal oscillator has not yet reached its maximum accuracy bit 1-0 Unimplemented: Read as `0' 2010-2013 Microchip Technology Inc. DS40001430E-page 67 PIC16(L)F720/721 7.5 Oscillator Tuning The INTOSC is factory calibrated but can be adjusted in software by writing to the OSCTUNE register (Register 7-2). The default value of the OSCTUNE register is `0'. The value is a 6-bit two's complement number. When the OSCTUNE register is modified, the INTOSC frequency will begin shifting to the new frequency. Code execution continues during this shift. There is no indication that the shift has occurred. REGISTER 7-2: OSCTUNE: OSCILLATOR TUNING REGISTER U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as `0' bit 5-0 TUN<5:0>: Frequency Tuning bits 01 1111 = Maximum frequency 01 1110 = * * * 00 0001 = 00 0000 = Oscillator module is running at the factory-calibrated frequency. 11 1111 = * * * 10 0000 = Minimum frequency DS40001430E-page 68 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 7.6 External Clock Modes 7.6.1 EC MODE The External Clock (EC) mode allows an externally generated logic level as the system clock source. When operating in this mode, an external clock source is connected to the CLKIN input and the CLKOUT is available for general purpose I/O. Figure 7-2 shows the pin connections for EC mode. FIGURE 7-2: EXTERNAL CLOCK (EC) MODE OPERATION CLKIN Clock from Ext. System PIC(R) MCU CLKOUT I/O TABLE 7-1: Name SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES Bit 3 Bit 2 Bit 1 Register on Page Bit 7 Bit 6 Bit 5 Bit 4 Bit 0 OSCCON -- -- IRCF1 IRCF0 ICSL ICSS -- -- 67 OSCTUNE -- -- TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 68 Legend: x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by oscillators. TABLE 7-2: Name CONFIG1 CONFIG2 SUMMARY OF CONFIGURATION WORD WITH CLOCK SOURCES Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0 13:8 -- -- -- PLLEN -- -- 7:0 -- CP MCLRE PWRTE WDTEN -- 13:8 -- -- -- -- -- -- -- -- 7:0 -- -- -- -- -- -- WRT1 WRT0 BOREN1 BOREN0 FOSC1 FOSC0 Register on Page 72 73 Legend: -- = unimplemented location, read as `0'. Shaded cells are not used by clock sources. 2010-2013 Microchip Technology Inc. DS40001430E-page 69 PIC16(L)F720/721 NOTES: DS40001430E-page 70 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 8.0 DEVICE CONFIGURATION Device configuration consists of Configuration Word 1 and Configuration Word 2 registers, code protection and Device ID. 8.1 Configuration Words There are several Configuration Word bits that allow different oscillator and memory protection options. These are implemented as Configuration Word 1 register at 2007h and Configuration Word 2 register at 2008h. These registers are only accessible during programming. 2010-2013 Microchip Technology Inc. DS40001430E-page 71 PIC16(L)F720/721 REGISTER 8-1: CONFIGURATION WORD 1 U-1 R/P-1 U-1 U-1 R/P-1 R/P-1 -- PLLEN -- -- BOREN1 BOREN0 bit 13 bit 8 U-1 R/P-1 R/P-1 R/P-1 R/P-1 U-1 R/P-1 R/P-1 -- CP MCLRE PWRTE WDTEN -- FOSC1 FOSC0 bit 7 bit 0 Legend: P = Programmable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 13 Unimplemented: Read as `1' bit 12 PLLEN: INTOSC PLL Enable bit 0 = INTOSC frequency is up to 500 kHz (Max. MFINTOSC) 1 = INTOSC frequency is up to 16 MHz (Max. HFINTOSC) bit 11-10 Unimplemented: Read as `1' bit 9-8 BOREN<1:0>: Brown-out Reset Enable bits(1) 0x = Brown-out Reset disabled 10 = Brown-out Reset enabled during operation and disabled in Sleep 11 = Brown-out Reset enabled bit 7 Unimplemented: Read as `1' bit 6 CP: Flash Program Memory Code Protection bit 0 = Program Memory code protection is enabled 1 = Program Memory code protection is disabled bit 5 MCLRE: MCLR/VPP Pin Function Select bit 1 = MCLR/VPP pin function is MCLR; Weak pull-up enabled. 0 = MCLR/VPP pin function is digital input; MCLR internally disabled; Weak pull-up disabled bit 4 PWRTE: Power-up Timer Enable bit 0 = PWRT enabled 1 = PWRT disabled bit 3 WDTEN: Watchdog Timer Enable bit 0 = WDT disabled 1 = WDT enabled bit 2 Unimplemented: Read as `1' bit 1-0 FOSC<1:0>: Oscillator Selection bits 11 = EC oscillator: CLKOUT function on CLKOUT pin, and CLKIN function on CLKIN pin 10 = EC oscillator: I/O function on CLKOUT pin, and CLKIN function on CLKIN pin 01 = INTOSC oscillator: CLKOUT function on CLKOUT pin, and I/O function on CLKIN pin 00 = INTOSCIO oscillator: I/O function on CLKOUT pin, and I/O function on CLKIN pin Note 1: Fixed Voltage Reference is automatically enabled whenever the BOR is enabled. DS40001430E-page 72 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 REGISTER 8-2: CONFIGURATION WORD 2 U-1 U-1 U-1 U-1 U-1 U-1 -- -- -- -- -- -- bit 13 bit 8 U-1 U-1 U-1 Reserved U-1 U-1 R/P-1 R/P-1 -- -- -- -- -- -- WRT1 WRT0 bit 7 bit 0 Legend: P = Programmable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 13-5 Unimplemented: Read as `1' bit 4 Reserved: Maintain as `1' bit 3-2 Unimplemented: Read as `1' bit 1-0 WRT<1:0>: Flash Memory Self-Write Protection bits x = Bit is unknown 2 kW Flash memory: PIC16(L)F720: 11 = Write protection off 10 = 000h to 1FFh write-protected, 200h to 7FFh may be modified by PMCON1 control 01 = 000h to 3FFh write-protected, 400h to 7FFh may be modified by PMCON1 control 00 = 000h to 7FFh write-protected, no addresses may be modified by PMCON1 control 4 kW Flash memory: PIC16(L)F721: 11 = Write protection off 10 = 000h to 1FFh write-protected, 200h to FFFh may be modified by PMCON1 control 01 = 000h to 7FFh write-protected, 800h to FFFh may be modified by PMCON1 control 00 = 000h to FFFh write-protected, no addresses may be modified by PMCON1 control 2010-2013 Microchip Technology Inc. DS40001430E-page 73 PIC16(L)F720/721 8.2 Code Protection If the code protection bit(s) have not been programmed, the on-chip program memory can be read out using ICSPTM for verification purposes. Note: 8.3 The entire Flash program memory will be erased when the code protection is turned off. See the "PIC16(L)F720/721 Memory Programming Specification" (DS41409) for more information. User ID Four memory locations (2000h-2003h) are designated as ID locations where the user can store checksum or other code identification numbers. These locations are not accessible during normal execution, but are readable and writable during Program/Verify mode. Only the Least Significant 7 bits of the ID locations are reported when using MPLAB(R) IDE. See the "PIC16(L)F720/721 Memory Programming Specification" (DS41409) for more information. DS40001430E-page 74 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 9.0 ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE The Analog-to-Digital Converter (ADC) allows conversion of an analog input signal to a 8-bit binary representation of that signal. This device uses analog inputs, which are multiplexed into a single sample and hold circuit. The output of the sample and hold is connected to the input of the converter. The converter generates a 8-bit binary result via successive approximation and stores the conversion result into the ADC result register (ADRES). Figure 9-1 shows the block diagram of the ADC. The ADC voltage reference, FVREF, is an internally generated supply only. The ADC can generate an interrupt upon completion of a conversion. This interrupt can be used to wake-up the device from Sleep. FIGURE 9-1: ADC BLOCK DIAGRAM VDD AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 0000 0001 0010 0011 0100 0101 AN11 1011 0110 0111 1000 1001 GO/DONE 1010 ADC 8 ADRES ADON VSS Temperature Indicator FVREF 1110 1111 CHS<3:0> 2010-2013 Microchip Technology Inc. DS40001430E-page 75 PIC16(L)F720/721 9.1 ADC Configuration When configuring and using the ADC the following functions must be considered: * * * * 9.1.3 Port configuration Channel selection ADC conversion clock source Interrupt control 9.1.1 When converting analog signals, the I/O pin selected as the input channel should be configured for analog by setting the associated TRIS and ANSEL bits. Refer to Section 6.0 "I/O Ports" for more information. Analog voltages on any pin that is defined as a digital input may cause the input buffer to conduct excess current. 9.1.2 CONVERSION CLOCK The source of the conversion clock is software selectable via the ADCS bits of the ADCON1 register. There are seven possible clock options: PORT CONFIGURATION Note: When changing channels, a delay is required before starting the next conversion. Refer to Section 9.2 "ADC Operation" for more information. * * * * * * * FOSC/2 FOSC/4 FOSC/8 FOSC/16 FOSC/32 FOSC/64 FRC (dedicated internal oscillator) The time to complete one bit conversion is defined as TAD. One full 8-bit conversion requires 10 TAD periods as shown in Figure 9-2. CHANNEL SELECTION For correct conversion, the appropriate TAD specification must be met. Refer to the A/D conversion requirements in Section 23.0 "Electrical Specifications" for more information. Table 9-1 gives examples of appropriate ADC clock selections. There are 14 channel selections available: - AN<11:0> pins - Temperature Indicator - FVR (Fixed Voltage Reference) Output Refer to Section 11.0 "Temperature Indicator Module" and Section 10.0 "Fixed Voltage Reference" for more information on these channel selections. Note: Unless using the FRC, any changes in the system clock frequency will change the ADC clock frequency, which may adversely affect the ADC result. The CHS bits of the ADCON0 register determine which channel is connected to the sample and hold circuit. TABLE 9-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES Device Frequency (FOSC) ADC Clock Period (TAD) ADC Clock Source FOSC/2 ADCS<2:0> 16 MHz 8 MHz 4 MHz 1 MHz 000 125 ns(2) 250 ns(2) 500 ns(2) 2.0 s (2) (2) FOSC/4 100 250 ns 1.0 s 4.0 s FOSC/8 001 0.5 s(2) 1.0 s 2.0 s 8 s(5) FOSC/16 101 1.0 s 2.0 s 4.0 s 16.0 s(5) s(5) 32.0 s(3) 500 ns FOSC/32 010 2.0 s 4.0 s FOSC/64 110 4.0 s 8 s(5) FRC x11 Legend: Note 1: 2: 3: 4: 5: 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 8 16.0 s(5) 1.0-6.0 s(1,4) 64.0 s(3) 1.0-6.0 s(1,4) Shaded cells are outside of recommended range. The FRC source has a typical TAD time of 1.6 s for VDD. These values violate the minimum required TAD time. For faster conversion times, the selection of another clock source is recommended. When the device frequency is greater than 1 MHz, the FRC clock source is only recommended if the conversion will be performed during Sleep. Recommended values for VDD 2.0V and temperature -40C to 85C. The 16.0 s setting should be avoided for temperature > 85C. DS40001430E-page 76 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 FIGURE 9-2: ANALOG-TO-DIGITAL CONVERSION TAD CYCLES TCY to TAD TAD0 TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 b7 b6 b5 b4 b3 b2 b1 b0 Conversion Starts Holding Capacitor is disconnected from Analog Input (typically 100 ns) Set GO/DONE bit 9.1.4 INTERRUPTS The ADC module allows for the ability to generate an interrupt upon completion of an Analog-to-Digital conversion. The ADC Interrupt Flag is the ADIF bit in the PIR1 register. The ADC Interrupt Enable is the ADIE bit in the PIE1 register. The ADIF bit must be cleared in software. Note 1: The ADIF bit is set at the completion of every conversion, regardless of whether or not the ADC interrupt is enabled. 2: The ADC operates during Sleep only when the FRC oscillator is selected. This interrupt can be generated while the device is operating or while in Sleep. If the device is in Sleep, the interrupt will wake-up the device. Upon waking from Sleep, the next instruction following the SLEEP instruction is always executed. If the user is attempting to wake-up from Sleep and resume in-line code execution, the GIE and PEIE bits of the INTCON register must be disabled. If the GIE and PEIE bits of the INTCON register are enabled, execution will switch to the Interrupt Service Routine. Please refer to Section 9.1.4 "Interrupts" for more information. ADRES register is loaded, GO/DONE bit is cleared, ADIF bit is set, Holding capacitor is connected to analog input 9.2 9.2.1 STARTING A CONVERSION To enable the ADC module, the ADON bit of the ADCON0 register must be set to a `1'. Setting the GO/ DONE bit of the ADCON0 register to a `1' will start the Analog-to-Digital conversion. Note: 9.2.2 The GO/DONE bit should not be set in the same instruction that turns on the ADC. Refer to Section 9.2.6 "A/D Conversion Procedure". COMPLETION OF A CONVERSION When the conversion is complete, the ADC module will: * Clear the GO/DONE bit * Set the ADIF Interrupt Flag bit * Update the ADRES register with new conversion result 9.2.3 TERMINATING A CONVERSION If a conversion must be terminated before completion, the GO/DONE bit can be cleared in software. The ADRES register will be updated with the partially complete Analog-to-Digital conversion sample. Incomplete bits will match the last bit converted. Note: 2010-2013 Microchip Technology Inc. ADC Operation A device Reset forces all registers to their Reset state. Thus, the ADC module is turned off and any pending conversion is terminated. DS40001430E-page 77 PIC16(L)F720/721 9.2.4 ADC OPERATION DURING SLEEP The ADC module can operate during Sleep. This requires the ADC clock source to be set to the FRC option. When the FRC clock source is selected, the ADC waits one additional instruction before starting the conversion. This allows the SLEEP instruction to be executed, which can reduce system noise during the conversion. If the ADC interrupt is enabled, the device will wake-up from Sleep when the conversion completes. If the ADC interrupt is disabled, the ADC module is turned off after the conversion completes, although the ADON bit remains set. When the ADC clock source is something other than FRC, a SLEEP instruction causes the present conversion to be aborted and the ADC module is turned off, although the ADON bit remains set. 9.2.5 SPECIAL EVENT TRIGGER The Special Event Trigger of the CCP module allows periodic ADC measurements without software intervention. When this trigger occurs, the GO/DONE bit is set by hardware and the Timer1 counter resets to zero. Using the Special Event Trigger does not assure proper ADC timing. It is the user's responsibility to ensure that the ADC timing requirements are met. Refer to Section 15.0 "Capture/Compare/PWM (CCP) Module" for more information. 9.2.6 A/D CONVERSION PROCEDURE This is an example procedure for using the ADC to perform an Analog-to-Digital conversion: 1. 2. 3. Configure Port: * Disable pin output driver (Refer to the TRIS register) * Configure pin as analog (Refer to the ANSEL register) Configure the ADC module: * Select ADC conversion clock * Select ADC input channel * Turn on ADC module Configure ADC interrupt (optional): * Clear ADC interrupt flag * Enable ADC interrupt * Enable peripheral interrupt * Enable global interrupt(1) DS40001430E-page 78 4. 5. 6. 7. 8. Wait the required acquisition time(2). Start conversion by setting the GO/DONE bit. Wait for ADC conversion to complete by one of the following: * Polling the GO/DONE bit * Waiting for the ADC interrupt (interrupts enabled) Read ADC Result. Clear the ADC interrupt flag (required if interrupt is enabled). Note 1: The global interrupt can be disabled if the user is attempting to wake-up from Sleep and resume in-line code execution. 2: Refer to Section 9.3 "A/D Acquisition Requirements". EXAMPLE 9-1: A/D CONVERSION ;This code block configures the ADC ;for polling, Vdd reference, Frc clock ;and AN0 input. ; ;Conversion start & polling for completion ; are included. ; BANKSEL ADCON1 ; MOVLW B'01110000' ;ADC Frc clock, ;VDD reference MOVWF ADCON1 ; BANKSEL TRISA ; BSF TRISA,0 ;Set RA0 to input BANKSEL ANSELA ; BSF ANSELA,0 ;Set RA0 to analog BANKSEL ADCON0 ; MOVLW B'00000001';AN0, On MOVWF ADCON0 ; CALL SampleTime ;Acquisiton delay BSF ADCON0,GO ;Start conversion BTFSC ADCON0,GO ;Is conversion done? GOTO $-1 ;No, test again BANKSEL ADRES ; MOVF ADRES,W ;Read result MOVWF RESULT ;store in GPR space 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 9.2.7 ADC REGISTER DEFINITIONS The following registers are used to control the operation of the ADC. REGISTER 9-1: ADCON0: A/D CONTROL REGISTER 0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- CHS3 CHS2 CHS1 CHS0 GO/DONE ADON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as `0' bit 5-2 CHS<3:0>: Analog Channel Select bits 0000 = AN0 0001 = AN1 0010 = AN2 0011 = AN3 0100 = AN4 0101 = AN5 0110 = AN6 0111 = AN7 1000 = AN8 1001 = AN9 1010 = AN10 1011 = AN11 1110 = Temperature Indicator(1) 1111 = Fixed Voltage Reference (FVREF)(2) bit 1 GO/DONE: A/D Conversion Status bit 1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle. This bit is automatically cleared by hardware when the A/D conversion has completed. 0 = A/D conversion completed/not in progress bit 0 ADON: ADC Enable bit 1 = ADC is enabled 0 = ADC is disabled and consumes no operating current Note 1: 2: See Section 11.0 "Temperature Indicator Module" for more information. See Section 10.0 "Fixed Voltage Reference" for more information. 2010-2013 Microchip Technology Inc. DS40001430E-page 79 PIC16(L)F720/721 REGISTER 9-2: ADCON1: A/D CONTROL REGISTER 1 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 -- ADCS2 ADCS1 ADCS0 -- -- -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7 Unimplemented: Read as `0' bit 6-4 ADCS<2:0>: A/D Conversion Clock Select bits 000 = FOSC/2 001 = FOSC/8 010 = FOSC/32 011 = FRC (clock supplied from a dedicated RC oscillator) 100 = FOSC/4 101 = FOSC/16 110 = FOSC/64 111 = FRC (clock supplied from a dedicated RC oscillator) bit 3-0 Unimplemented: Read as `0' REGISTER 9-3: x = Bit is unknown ADRES: ADC RESULT REGISTER R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x ADRES7 ADRES6 ADRES5 ADRES4 ADRES3 ADRES2 ADRES1 ADRES0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-0 x = Bit is unknown ADRES<7:0>: ADC Result Register bits 8-bit conversion result. DS40001430E-page 80 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 9.3 A/D Acquisition Requirements For the ADC to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The Analog Input model is shown in Figure 9-3. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), refer to Figure 9-3. The maximum recommended impedance for analog sources is 10 k. As the source impedance is decreased, the acquisition time may be decreased. After the analog input channel is EQUATION 9-1: Assumptions: selected (or changed), an A/D acquisition must be done before the conversion can be started. To calculate the minimum acquisition time, Equation 9-1 may be used. This equation assumes that 1/2 LSb error is used (256 steps for the ADC). The 1/2 LSb error is the maximum error allowed for the ADC to meet its specified resolution. It is noted that if the device is operated at or below 2.0V VDD with the FRC clock selected for the ADC and if the analog input changes by more than one or two LSBs from the previous conversion, then the use of at least 16 s TACQ time is recommended. ACQUISITION TIME EXAMPLE Temperature = 50C and external impedance of 10k 5.0V V DD T ACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient = T AMP + T C + T C OFF = 2s + T C + Temperature - 25C 0.05s/C Note: TCOFF is zero for temperatures below 25 degrees C. The value for TC can be approximated with the following equations: 1 = V CHOLD V AP P LI ED 1 - -------------------------n+1 2 -1 ;[1] VCHOLD charged to within 1/2 lsb -TC ---------- RC V AP P LI ED 1 - e = V CHOLD ;[2] VCHOLD charge response to VAPPLIED - Tc --------- RC 1 ;combining [1] and [2] V AP P LI ED 1 - e = V A PP LIE D 1 - -------------------------n+1 2 -1 Note: Where n = number of bits of the ADC. Solving for TC: T C = - C HOLD R IC + R SS + R S ln(1/511) = - 20pF 1k + 7k + 10k ln(0.001957) = 2.25 s Therefore: T ACQ = 2s + 2.25s + 50C- 25C 0.05s/C = 5.5s 2010-2013 Microchip Technology Inc. DS40001430E-page 81 PIC16(L)F720/721 Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out. 2: The charge holding capacitor (CHOLD) is not discharged after each conversion. 3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin leakage specification. FIGURE 9-3: ANALOG INPUT MODEL VDD Rs VA VT 0.6V ANx CPIN 5 pF VT 0.6V Sampling Switch SS Rss RIC 1k I LEAKAGE(1) CHOLD = 20 pF VSS 6V Legend: CHOLD CPIN = Sample/Hold Capacitance = Input Capacitance VDD 4V 2V I LEAKAGE = Leakage current at the pin due to various junctions RIC = Interconnect Resistance RSS = Resistance of Sampling Switch SS = Sampling Switch VT = Threshold Voltage 5 10 15 20 Sampling Switch, Typical (k) Note 1: Refer to Section 23.0 "Electrical Specifications". FIGURE 9-4: ADC TRANSFER FUNCTION Full-Scale Range FFh FEh FDh ADC Output Code FCh 1 LSB ideal FBh Full-Scale Transition 04h 03h 02h 01h 00h Analog Input Voltage 1 LSB ideal VSS DS40001430E-page 82 Zero-Scale Transition VREF 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 TABLE 9-2: SUMMARY OF ASSOCIATED ADC REGISTERS Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ADCON0 -- -- CHS3 CHS2 CHS1 CHS0 GO/ DONE ADON 79 ADCON1 -- ADCS2 ADCS1 ADCS0 -- -- -- -- 80 ANSELA -- -- ANSA5 ANSA4 -- ANSA2 ANSA1 ANSA0 47 Name ANSELB -- -- ANSB5 ANSB4 -- -- -- -- 56 ANSELC ANSC7 ANSC6 -- -- ANSC3 ANSC2 ANSC1 ANSC0 61 FVRRDY FVREN TSEN TSRNG -- -- ADFVR1 ADFVR0 86 ADRES FVRCON INTCON ADC Result Register 80 GIE PEIE TMR0IE INTE RABIE TMR0IF INTF RABIF 38 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 39 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 40 TRISA -- -- TRISA5 TRISA4 -- TRISA2 TRISA1 TRISA0 46 TRISB TRISB7 TRISB6 TRISB5 TRISB4 -- -- -- -- 55 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 61 Legend: x = unknown, u = unchanged, -- = unimplemented read as `0', q = value depends on condition. Shaded cells are not used for ADC module. 2010-2013 Microchip Technology Inc. DS40001430E-page 83 PIC16(L)F720/721 NOTES: DS40001430E-page 84 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 10.0 FIXED VOLTAGE REFERENCE This device contains an internal voltage regulator. To provide a reference for the regulator, a fixed voltage reference is provided. This fixed voltage is also user accessible via an A/D converter channel. User level fixed voltage functions are controlled by the FVRCON register, which is shown in Register 10-1. FIGURE 10-1: VOLTAGE REFERENCE BLOCK DIAGRAM ADFVR<1:0> 2 x1 x2 x4 FVR (To ADC Module) 1.024V Fixed Reference + FVREN - FVRRDY Any peripheral requiring the Fixed Reference (See Table 10-1) TABLE 10-1: PERIPHERALS REQUIRING THE FIXED VOLTAGE REFERENCE (FVR) Peripheral HFINTOSC BOR IVR Conditions Description FOSC = 1 EC on CLKIN pin. BOREN<1:0> = 11 BOR always enabled. BOREN<1:0> = 10 and BORFS = 1 BOR disabled in Sleep mode, BOR Fast Start enabled. BOREN<1:0> = 01 and BORFS = 1 BOR under software control, BOR Fast Start enabled. All PIC16F720/721 devices, when VREGPM1 = 1 and not in Sleep The device runs off of the Power-Save mode regulator when in Sleep mode. 2010-2013 Microchip Technology Inc. DS40001430E-page 85 PIC16(L)F720/721 REGISTER 10-1: FVRCON: FIXED VOLTAGE REFERENCE REGISTER R-q R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 FVRRDY FVREN TSEN TSRNG -- -- ADFVR1 ADFVR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown q = Value depends on condition bit 7 FVRRDY(1): Fixed Voltage Reference Ready Flag bit 0 = Fixed Voltage Reference output is not active or stable 1 = Fixed Voltage Reference output is ready for use bit 6 FVREN: Fixed Voltage Reference Enable bit 0 = Fixed Voltage Reference is disabled 1 = Fixed Voltage Reference is enabled bit 5 TSEN: Temperature Indicator Enable bit(3) 0 = Temperature indicator is disabled 1 = Temperature indicator is enabled bit 4 TSRNG: Temperature Indicator Range Selection bit(3) 1 = VOUT = VDD - 4VT (High Range) 0 = VOUT = VDD - 2VT (Low Range) bit 3-2 Unimplemented: Read as `0' bit 1-0 ADFVR<1:0>: A/D Converter Fixed Voltage Reference Selection bits 00 = A/D Converter Fixed Voltage Reference Peripheral output is off 01 = A/D Converter Fixed Voltage Reference Peripheral output is 1x (1.024V) 10 = A/D Converter Fixed Voltage Reference Peripheral output is 2x (2.048V)(2) 11 = A/D Converter Fixed Voltage Reference Peripheral output is 4x (4.096V)(2) Note 1: 2: 3: FVRRDY is always `1' for the PIC16F720/721 devices. Fixed Voltage Reference output cannot exceed VDD. See Section 11.0 "Temperature Indicator Module" for additional information. TABLE 10-2: Name FVRCON SUMMARY OF ASSOCIATED FIXED VOLTAGE REFERENCE REGISTERS Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page FVRRDY FVREN TSEN TSRNG -- -- ADFVR1 ADFVR0 86 Legend: x = unknown, u = unchanged, -- = unimplemented read as `0', q = value depends on condition. Shaded cells are not used for Fixed Voltage Reference. DS40001430E-page 86 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 11.0 TEMPERATURE INDICATOR MODULE FIGURE 11-1: This family of devices is equipped with a temperature circuit designed to measure the operating temperature of the silicon die. The circuit's range of operating temperature falls between -40C and +85C. The output is a voltage that is proportional to the device temperature. The output of the temperature indicator is internally connected to the device ADC. TEMPERATURE CIRCUIT DIAGRAM VDD TSEN TSRNG The circuit may be used as a temperature threshold detector or a more accurate temperature indicator, depending on the level of calibration performed. A onepoint calibration allows the circuit to indicate a temperature closely surrounding that point. A two-point calibration allows the circuit to sense the entire range of temperature more accurately. Reference Application Note AN1333, "Use and Calibration of the Internal Temperature Indicator" (DS01333) for more details regarding the calibration process. 11.1 Circuit Operation Figure 11-1 shows a simplified block diagram of the temperature circuit. The proportional voltage output is achieved by measuring the forward voltage drop across multiple silicon junctions. Equation 11-1 describes the output characteristics of the temperature indicator. VOUT 11.2 To ADC Minimum Operating VDD vs. Minimum Sensing Temperature When the temperature circuit is operated in low range, the device may be operated at any operating voltage that is within specifications. VOUT RANGES When the temperature circuit is operated in high range, the device operating voltage, VDD, must be high enough to ensure that the temperature circuit is correctly biased. High Range: VOUT = VDD - 4VT Table 11-1 shows the recommended minimum VDD vs. range setting. Low Range: VOUT = VDD - 2VT TABLE 11-1: EQUATION 11-1: The temperature sense circuit is integrated with the Fixed Voltage Reference (FVR) module. See Section 10.0 "Fixed Voltage Reference" for more information. The circuit is enabled by setting the TSEN bit of the FVRCON register. When disabled, the circuit draws no current. The circuit operates in either high or low range. The high range, selected by setting the TSRNG bit of the FVRCON register, provides a wider output voltage. This provides more resolution over the temperature range, but may be less consistent from part to part. This range requires a higher bias voltage to operate and thus, a higher VDD is needed. The low range is selected by clearing the TSRNG bit of the FVRCON register. The low range generates a lower voltage drop and thus, a lower bias voltage is needed to operate the circuit. The low range is provided for low voltage operation. 2010-2013 Microchip Technology Inc. RECOMMENDED VDD VS. RANGE Min. VDD, TSRNG = 1 Min. VDD, TSRNG = 0 3.6V 1.8V 11.3 Temperature Output The output of the circuit is measured using the internal Analog-to-Digital Converter. Channel 14 is reserved for the temperature circuit output. Refer to Section 9.0 "Analog-to-Digital Converter (ADC) Module" for detailed information. Note: Every time the ADC MUX is changed to the temperature indicator output selection (CHS bit in the ADCCON0 register), wait 500 usec for the sampling capacitor to fully charge before sampling the temperature indicator output. DS40001430E-page 87 PIC16(L)F720/721 NOTES: DS40001430E-page 88 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 12.0 TIMER0 MODULE 12.1.1 The Timer0 module will increment every instruction cycle, if used without a prescaler. 8-Bit Timer mode is selected by clearing the T0CS bit of the OPTION_REG register. The Timer0 module is an 8-bit timer/counter with the following features: * * * * * * 8-bit timer/counter register (TMR0) 8-bit prescaler (shared with Watchdog Timer) Programmable internal or external clock source Programmable external clock edge selection Interrupt on overflow TMR0 can be used to gate Timer1 When TMR0 is written, the increment is inhibited for two instruction cycles immediately following the write. Note: Figure 12-1 is a block diagram of the Timer0 module. 12.1 8-BIT TIMER MODE 12.1.2 Timer0 Operation The value written to the TMR0 register can be adjusted, in order to account for the two instruction cycle delay when TMR0 is written. 8-BIT COUNTER MODE In 8-Bit Counter mode, the Timer0 module will increment on every rising or falling edge of the T0CKI pin. The Timer0 module can be used as either an 8-bit timer or an 8-bit counter. 8-Bit Counter mode using the T0CKI pin is selected by setting the T0CS bit in the OPTION_REG register to `1'. The rising or falling transition of the incrementing edge for either input source is determined by the T0SE bit in the OPTION_REG register. FIGURE 12-1: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER FOSC/4 Data Bus 0 T0CKI 1 1 T0SE T0CS SYNC 2 TCY 0 0 8-bit Prescaler TMR0 Set Flag bit T0IF on Overflow PSA 1 T1GSS = 11 8 Overflow to Timer1 TMR1GE PSA 8 WDTEN Low-Power WDT PS<2:0> Divide by 512 1 WDT Time-out 0 PSA 2010-2013 Microchip Technology Inc. DS40001430E-page 89 PIC16(L)F720/721 12.1.3 SOFTWARE PROGRAMMABLE PRESCALER A single software programmable prescaler is available for use with either Timer0 or the Watchdog Timer (WDT), but not both simultaneously. The prescaler assignment is controlled by the PSA bit of the OPTION_REG register. To assign the prescaler to Timer0, the PSA bit must be cleared to a `0'. There are eight prescaler options for the Timer0 module ranging from 1:2 to 1:256. The prescale values are selectable via the PS<2:0> bits of the OPTION_REG register. In order to have a 1:1 prescaler value for the Timer0 module, the prescaler must be assigned to the WDT module. The prescaler is not readable or writable. When assigned to the Timer0 module, all instructions writing to the TMR0 register will clear the prescaler. Note: When the prescaler is assigned to WDT, a CLRWDT instruction will clear the prescaler along with the WDT. DS40001430E-page 90 12.1.4 TIMER0 INTERRUPT Timer0 will generate an interrupt when the TMR0 register overflows from FFh to 00h. The TMR0IF interrupt flag bit of the INTCON register is set every time the TMR0 register overflows, regardless of whether or not the Timer0 interrupt is enabled. The TMR0IF bit can only be cleared in software. The Timer0 interrupt enable is the TMR0IE bit of the INTCON register. Note: 12.1.5 The Timer0 interrupt cannot wake the processor from Sleep since the timer is frozen during Sleep. 8-BIT COUNTER MODE SYNCHRONIZATION When in 8-Bit Counter mode, the incrementing edge on the T0CKI pin must be synchronized to the instruction clock. Synchronization can be accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the instruction clock. The high and low periods of the external clocking source must meet the timing requirements as shown in Section 23.0 "Electrical Specifications". 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 12.2 Option Register REGISTER 12-1: OPTION_REG: OPTION REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RABPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 RABPU: PORTA or PORTB Pull-up Enable bit 1 = PORTA or PORTB pull-ups are disabled 0 = PORTA or PORTB pull-ups are enabled by individual PORT latch values bit 6 INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of INT pin 0 = Interrupt on falling edge of INT pin bit 5 T0CS: TMR0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (FOSC/4) bit 4 T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin bit 3 PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module bit 2-0 PS<2:0>: Prescaler Rate Select bits Bit Value 000 001 010 011 100 101 110 111 TABLE 12-1: Name INTCON OPTION_REG TMR0 Rate 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page GIE PEIE TMR0IE INTE RABIE TMR0IF INTF RABIF 38 RABPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 21 TMR0 TRISA WDT Rate Timer0 module Register -- -- TRISA5 TRISA4 -- TRISA2 89 TRISA1 TRISA0 46 Legend: - = Unimplemented locations, read as `0', u = unchanged, x = unknown. Shaded cells are not used by the Timer0 module. 2010-2013 Microchip Technology Inc. DS40001430E-page 91 PIC16(L)F720/721 NOTES: DS40001430E-page 92 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 13.0 TIMER1 MODULE WITH GATE CONTROL * * * * The Timer1 module is a 16-bit timer/counter with the following features: Figure 13-1 is a block diagram of the Timer1 module. * * * * * * * 16-bit timer/counter register pair (TMR1H:TMR1L) Programmable internal or external clock source 3-bit prescaler Synchronous or asynchronous operation Multiple Timer1 gate (count enable) sources Interrupt on overflow Wake-up on overflow (external clock, Asynchronous mode only) * Time base for the Capture/Compare function * Special Event Trigger (with CCP) * Selectable Gate Source Polarity FIGURE 13-1: Gate Toggle Mode Gate Single-pulse Mode Gate Value Status Gate Event Interrupt TIMER1 BLOCK DIAGRAM T1GSS<1:0> T1G 00 From Timer0 Overflow 01 From Timer2 Match PR2 10 From WDT Overflow 11 T1GSPM 0 T1G_IN T1GVAL 0 D Q CK R Q Single Pulse Acq. Control 1 1 Q1 D RD T1GCON EN Interrupt T1GGO/DONE det T1GPOL TMR1ON T1GTM Data Bus Q Set TMR1GIF TMR1GE TMR1ON TMR1(2) TMR1H Set flag bit TMR1IF on Overflow EN TMR1L Q D T1CLK Synchronized clock input 0 1 TMR1CS<1:0> T1SYNC (1) 10 T1CKI Reserved Synchronize(3) Prescaler 1, 2, 4, 8 det 11 FOSC/4 Internal Clock 00 FOSC Internal Clock 01 2 T1CKPS<1:0> FOSC/2 Internal Clock Sleep input Note 1: ST buffer is high speed type when using T1CKI. 2: Timer1 register increments on rising edge. 3: Synchronize does not operate while in Sleep. 2010-2013 Microchip Technology Inc. DS40001430E-page 93 PIC16(L)F720/721 13.1 Timer1 Operation 13.2 The Timer1 module is a 16-bit incrementing counter which is accessed through the TMR1H:TMR1L register pair. Writes to TMR1H or TMR1L directly update the counter. When used with an internal clock source, the module is a timer and increments on every instruction cycle. When used with an external clock source, the module can be used as either a timer or counter and increments on every selected edge of the external source. Timer1 is enabled by configuring the TMR1ON and TMR1GE bits in the T1CON and T1GCON registers, respectively. Table 13-1 displays the Timer1 enable selections. Clock Source Selection The TMR1CS<1:0> bits of the T1CON register are used to select the clock source for Timer1. Table 13-2 displays the clock source selections. 13.2.1 INTERNAL CLOCK SOURCE When the internal clock source is selected the TMR1H:TMR1L register pair will increment on multiples of FOSC as determined by the Timer1 prescaler. 13.2.2 EXTERNAL CLOCK SOURCE When the external clock source is selected, the Timer1 module may work as a timer or a counter. When enabled to count, Timer1 is incremented on the rising edge of the external clock input T1CKI. Note: TABLE 13-1: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge after any one or more of the following conditions: TIMER1 ENABLE SELECTIONS Timer1 Operation TMR1ON TMR1GE 0 0 Off 0 1 Off 1 0 Always On 1 1 Count Enabled *Timer1 enabled after POR Reset *Write to TMR1H or TMR1L *Timer1 is disabled *Timer1 is disabled (TMR1ON = 0) when T1CKI is high then Timer1 is enabled (TMR1ON=1) when T1CKI is low. TABLE 13-2: TMR1CS<1:0> DS40001430E-page 94 CLOCK SOURCE SELECTIONS Clock Source 01 System Clock (FOSC) 00 Instruction Clock (FOSC/4) 10 External Clocking on T1CKI Pin 11 Reserved 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 13.3 Timer1 Prescaler 13.5 Timer1 Gate Timer1 has four prescaler options allowing 1, 2, 4 or 8 divisions of the clock input. The T1CKPS bits of the T1CON register control the prescale counter. The prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to TMR1H or TMR1L. Timer1 can be configured to count freely or the count can be enabled and disabled using Timer1 gate circuitry. This is also referred to as Timer1 gate count enable. 13.4 13.5.1 Timer1 Operation in Asynchronous Counter Mode If control bit T1SYNC of the T1CON register is set, the external clock input is not synchronized. The timer increments asynchronously to the internal phase clocks. If external clock source is selected then the timer will continue to run during Sleep and can generate an interrupt on overflow, which will wake-up the processor. However, special precautions in software are needed to read/write the timer (see Section 13.4.1 "Reading and Writing Timer1 in Asynchronous Counter Mode"). Note: 13.4.1 When switching from synchronous to asynchronous operation, it is possible to skip an increment. When switching from asynchronous to synchronous operation, it is possible to produce an additional increment. READING AND WRITING TIMER1 IN ASYNCHRONOUS COUNTER MODE Reading TMR1H or TMR1L while the timer is running from an external asynchronous clock will ensure a valid read (taken care of in hardware). However, the user should keep in mind that reading the 16-bit timer in two 8-bit values itself, poses certain problems, since the timer may overflow between the reads. For writes, it is recommended that the user simply stop the timer and write the desired values. A write contention may occur by writing to the timer registers, while the register is incrementing. This may produce an unpredictable value in the TMR1H:TMR1L register pair. 2010-2013 Microchip Technology Inc. Timer1 gate can also be driven by multiple selectable sources. TIMER1 GATE COUNT ENABLE The Timer1 gate is enabled by setting the TMR1GE bit of the T1GCON register. The polarity of the Timer1 gate is configured using the T1GPOL bit of the T1GCON register. When Timer1 Gate (T1G) input is active, Timer1 will increment on the rising edge of the Timer1 clock source. When Timer1 gate input is inactive, no incrementing will occur and Timer1 will hold the current count. See Figure 13-3 for timing details. TABLE 13-3: TIMER1 GATE ENABLE SELECTIONS T1CLK T1GPOL T1G Timer1 Operation 0 0 Counts 0 1 Holds Count 1 0 Holds Count 1 1 Counts 13.5.2 TIMER1 GATE SOURCE SELECTION The Timer1 gate source can be selected from one of four different sources. Source selection is controlled by the T1GSS bits of the T1GCON register. The polarity for each available source is also selectable. Polarity selection is controlled by the T1GPOL bit of the T1GCON register. TABLE 13-4: T1GSS TIMER1 GATE SOURCES Timer1 Gate Source 00 Timer1 Gate Pin 01 Overflow of Timer0 (TMR0 increments from FFh to 00h) 10 Timer2 match PR2 (TMR2 increments to match PR2) 11 Count Enabled by WDT Overflow (Watchdog Time-out interval expired) DS40001430E-page 95 PIC16(L)F720/721 13.5.2.1 T1G Pin Gate Operation 13.5.2.4 The T1G pin is one source for Timer1 gate control. It can be used to supply an external source to the Timer1 gate circuitry. 13.5.2.2 Timer0 Overflow Gate Operation When Timer0 increments from FFh to 00h, a low-tohigh pulse will automatically be generated and internally supplied to the Timer1 gate circuitry. 13.5.2.3 Timer2 Match Gate Operation The TMR2 register will increment until it matches the value in the PR2 register. On the very next increment cycle, TMR2 will be reset to 00h. When this Reset occurs, a low-to-high pulse will automatically be generated and internally supplied to the Timer1 gate circuitry. Watchdog Overflow Gate Operation The Watchdog Timer oscillator, prescaler and counter will be automatically turned on when TMR1GE = 1 and T1GSS selects the WDT as a gate source for Timer1 (T1GSS = 11). TMR1ON does not factor into the oscillator, prescaler and counter enable. See Table 13-5. The PSA and PS bits of the OPTION_REG register still control what time-out interval is selected. Changing the prescaler during operation may result in a spurious capture. Enabling the Watchdog Timer oscillator does not automatically enable a Watchdog Reset or Wake-up from Sleep upon counter overflow. Note: When using the WDT as a gate source for Timer1, operations that clear the Watchdog Timer (CLRWDT, SLEEP instructions) will affect the time interval being measured. This includes waking from Sleep. All other interrupts that might wake the device from Sleep should be disabled to prevent them from disturbing the measurement period. As the gate signal coming from the WDT counter will generate different pulse widths depending on if the WDT is enabled, when the CLRWDT instruction is executed, and so on, Toggle mode must be used. A specific sequence is required to put the device into the correct state to capture the next WDT counter interval. TABLE 13-5: WDT/TIMER1 GATE INTERACTION WDTEN TMR1GE = 1 and T1GSS = 11 WDT Oscillator Enable WDT Reset Wake-up WDT Available for T1G Source 1 N Y Y Y N 1 Y Y Y Y Y 0 Y Y N N Y 0 N N N N N DS40001430E-page 96 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 13.5.3 TIMER1 GATE TOGGLE MODE When Timer1 Gate Toggle mode is enabled, it is possible to measure the full-cycle length of a Timer1 gate signal, as opposed to the duration of a single level pulse. The Timer1 gate source is routed through a flip-flop that changes state on every incrementing edge of the signal. See Figure 13-4 for timing details. Timer1 Gate Toggle mode is enabled by setting the T1GTM bit of the T1GCON register. When the T1GTM bit is cleared, the flip-flop is cleared and held clear. This is necessary in order to control which edge is measured. Note: 13.5.4 Enabling Toggle mode at the same time as changing the gate polarity may result in indeterminate operation. 13.5.5 TIMER1 GATE VALUE STATUS When Timer1 gate value status is utilized, it is possible to read the most current level of the gate control value. The value is stored in the T1GVAL bit in the T1GCON register. The T1GVAL bit is valid even when the Timer1 gate is not enabled (TMR1GE bit is cleared). 13.5.6 TIMER1 GATE EVENT INTERRUPT When Timer1 gate event interrupt is enabled, it is possible to generate an interrupt upon the completion of a gate event. When the falling edge of T1GVAL occurs, the TMR1GIF flag bit in the PIR1 register will be set. If the TMR1GIE bit in the PIE1 register is set, then an interrupt will be recognized. The TMR1GIF flag bit operates even when the Timer1 gate is not enabled (TMR1GE bit is cleared). TIMER1 GATE SINGLE-PULSE MODE When Timer1 Gate Single-Pulse mode is enabled, it is possible to capture a single pulse gate event. Timer1 Gate Single-Pulse mode is first enabled by setting the T1GSPM bit in the T1GCON register. Next, the T1GGO/DONE bit in the T1GCON register must be set. The Timer1 will be fully enabled on the next incrementing edge. On the next trailing edge of the pulse, the T1GGO/DONE bit will automatically be cleared. No other gate events will be allowed to increment Timer1 until the T1GGO/DONE bit is once again set in software. Clearing the T1GSPM bit of the T1GCON register will also clear the T1GGO/DONE bit. See Figure 13-5 for timing details. Enabling the Toggle mode and the Single-Pulse mode simultaneously will permit both sections to work together. This allows the cycle times on the Timer1 gate source to be measured. See Figure 13-6 for timing details. 2010-2013 Microchip Technology Inc. DS40001430E-page 97 PIC16(L)F720/721 13.6 Timer1 Interrupt The Timer1 register pair (TMR1H:TMR1L) increments to FFFFh and rolls over to 0000h. When Timer1 rolls over, the Timer1 interrupt flag bit of the PIR1 register is set. To enable the interrupt on rollover, you must set these bits: * * * * TMR1ON bit of the T1CON register TMR1IE bit of the PIE1 register PEIE bit of the INTCON register GIE bit of the INTCON register The interrupt is cleared by clearing the TMR1IF bit in the Interrupt Service Routine. Note: 13.7 The TMR1H:TMR1L register pair and the TMR1IF bit should be cleared before enabling interrupts. Timer1 Operation During Sleep Timer1 can only operate during Sleep when setup in Asynchronous Counter mode. In this mode, the clock source can be used to increment the counter. To set up the timer to wake the device: * * * * * TMR1ON bit of the T1CON register must be set TMR1IE bit of the PIE1 register must be set PEIE bit of the INTCON register must be set T1SYNC bit of the T1CON register must be set TMR1CS bits of the T1CON register must be configured * TMR1GE bit of the T1GCON register must be configured The device will wake-up on an overflow and execute the next instructions. If the GIE bit of the INTCON register is set, the device will call the Interrupt Service Routine (0004h). FIGURE 13-2: 13.8 CCP Capture/Compare Time Base The CCP module uses the TMR1H:TMR1L register pair as the time base when operating in Capture or Compare mode. In Capture mode, the value in the TMR1H:TMR1L register pair is copied into the CCPR1H:CCPR1L register pair on a configured event. In Compare mode, an event is triggered when the value CCPR1H:CCPR1L register pair matches the value in the TMR1H:TMR1L register pair. This event can be a Special Event Trigger. For more information, see Section 15.0 "Capture/ Compare/PWM (CCP) Module". 13.9 CCP Special Event Trigger When the CCP is configured to trigger a special event, the trigger will clear the TMR1H:TMR1L register pair. This special event does not cause a Timer1 interrupt. The CCP module may still be configured to generate a CCP interrupt. In this mode of operation, the CCPR1H:CCPR1L register pair becomes the period register for Timer1. Timer1 should be synchronized to the FOSC/4 to utilize the Special Event Trigger. Asynchronous operation of Timer1 can cause a Special Event Trigger to be missed. In the event that a write to TMR1H or TMR1L coincides with a Special Event Trigger from the CCP, the write will take precedence. For more information, see Section 9.2.5 "Special Event Trigger". TIMER1 INCREMENTING EDGE T1CKI = 1 when TMR1 Enabled T1CKI = 0 when TMR1 Enabled Note 1: 2: Arrows indicate counter increments. In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock. DS40001430E-page 98 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 FIGURE 13-3: TIMER1 GATE COUNT ENABLE MODE TMR1GE T1GPOL T1G_IN T1CKI T1GVAL TIMER1 N FIGURE 13-4: N+1 N+2 N+3 N+4 TIMER1 GATE TOGGLE MODE TMR1GE T1GPOL T1GTM T1G_IN T1CKI T1GVAL TIMER1 N 2010-2013 Microchip Technology Inc. N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 DS40001430E-page 99 PIC16(L)F720/721 FIGURE 13-5: TIMER1 GATE SINGLE-PULSE MODE TMR1GE T1GPOL T1GSPM T1GGO/ Cleared by hardware on falling edge of T1GVAL Set by software DONE Counting enabled on rising edge of T1G T1G_IN T1CKI T1GVAL TIMER1 TMR1GIF DS40001430E-page 100 N Cleared by software N+1 N+2 Set by hardware on falling edge of T1GVAL Cleared by software 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 FIGURE 13-6: TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE TMR1GE T1GPOL T1GSPM T1GTM T1GGO/ Cleared by hardware on falling edge of T1GVAL Set by software DONE Counting enabled on rising edge of T1G T1G_IN T1CKI T1GVAL TIMER1 TMR1GIF N Cleared by software 2010-2013 Microchip Technology Inc. N+1 N+2 N+3 Set by hardware on falling edge of T1GVAL N+4 Cleared by software DS40001430E-page 101 PIC16(L)F720/721 13.10 Timer1 Control Register The Timer1 Control register (T1CON), shown in Register 13-1, is used to control Timer1 and select the various features of the Timer1 module. REGISTER 13-1: T1CON: TIMER1 CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 R/W-0 TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 -- T1SYNC -- TMR1ON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7-6 TMR1CS<1:0>: Timer1 Clock Source Select bits 11 = Reserved 10 = Timer1 clock source is pin or oscillator. External clock from T1CKI pin (on the rising edge) 01 = Timer1 clock source is system clock (FOSC) 00 = Timer1 clock source is instruction clock (FOSC/4) bit 5-4 T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 3 Unimplemented: Read as `0' bit 2 T1SYNC: Timer1 External Clock Input Synchronization Control bit TMR1CS<1:0> = 1X 1 = Do not synchronize external clock input 0 = Synchronize external clock input with system clock (FOSC) TMR1CS<1:0> = 0X This bit is ignored. Timer1 uses the internal clock when TMR1CS<1:0> = 1X. bit 1 Unimplemented: Read as `0' bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Clears Timer1 gate flip-flop DS40001430E-page 102 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 13.11 Timer1 Gate Control Register The Timer1 Gate Control register (T1GCON), shown in Register 13-2, is used to control Timer1 gate. REGISTER 13-2: T1GCON: TIMER1 GATE CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-x R/W-0 R/W-0 TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ DONE T1GVAL T1GSS1 T1GSS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 TMR1GE: Timer1 Gate Enable bit If TMR1ON = 0: This bit is ignored If TMR1ON = 1: 1 = Timer1 counting is controlled by the Timer1 gate function 0 = Timer1 counts regardless of Timer1 gate function bit 6 T1GPOL: Timer1 Gate Polarity bit 1 = Timer1 gate is active-high (Timer1 counts when gate is high) 0 = Timer1 gate is active-low (Timer1 counts when gate is low) bit 5 T1GTM: Timer1 Gate Toggle mode bit 1 = Timer1 Gate Toggle mode is enabled. 0 = Timer1 Gate Toggle mode is disabled and toggle flip-flop is cleared Timer1 gate flip-flop toggles on every rising edge. bit 4 T1GSPM: Timer1 Gate Single Pulse mode bit 1 = Timer1 Gate Single-Pulse mode is enabled and is controlling Timer1 gate 0 = Timer1 Gate Single-Pulse mode is disabled bit 3 T1GGO/DONE: Timer1 Gate Single-Pulse Acquisition Status bit 1 = Timer1 gate single-pulse acquisition is ready, waiting for an edge 0 = Timer1 gate single-pulse acquisition has completed or has not been started This bit is automatically cleared when T1GSPM is cleared. bit 2 T1GVAL: Timer1 Gate Current State bit Indicates the current state of the Timer1 gate that could be provided to TMR1H:TMR1L. Unaffected by Timer1 Gate Enable (TMR1GE). bit 1-0 T1GSS<1:0>: Timer1 Gate Source Select bits 00 = Timer1 gate pin 01 = Timer0 overflow output 10 = TMR2 match PR2 output 11 = Watchdog Timer scaler overflow Watchdog Timer oscillator is turned on if TMR1GE = 1, regardless of the state of TMR1ON 2010-2013 Microchip Technology Inc. DS40001430E-page 103 PIC16(L)F720/721 TABLE 13-6: Name SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1 Bit 7 Bit 6 Bit 5 Bit 4 ANSELB -- -- ANSB5 ANSB4 CCP1CON -- -- DC1 B1 INTCON Bit 3 Bit 2 Bit 1 Bit 0 -- -- -- -- CCP1M3 CCP1M2 CCP1M1 CCP1M0 Register on Page 56 107 GIE PEIE TMR0IE INTE RABIE TMR0IF INTF RABIF 38 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 39 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 40 RB7 RB6 RB5 RB4 -- -- -- -- 55 PORTB TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register 98 TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register 98 TRISB TRISB7 TRISB6 TRISB5 TRISB4 -- -- -- -- 55 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 61 -- T1SYNC -- TMR1ON 102 T1GGO/ DONE T1GVAL T1GSS1 T1GSS0 103 T1CON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1GCON TMR1GE T1GPOL T1GTM T1GSPM Legend: x = unknown, u = unchanged, -- = unimplemented, read as `0'. Shaded cells are not used by the Timer1 module. DS40001430E-page 104 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 14.0 TIMER2 MODULE The Timer2 module is an 8-bit timer with the following features: * * * * * 8-bit timer register (TMR2) 8-bit period register (PR2) Interrupt on TMR2 match with PR2 Software programmable prescaler (1:1, 1:4, 1:16) Software programmable postscaler (1:1 to 1:16) Timer2 is turned on by setting the TMR2ON bit in the T2CON register to a `1'. Timer2 is turned off by clearing the TMR2ON bit to a `0'. The Timer2 prescaler is controlled by the T2CKPS bits in the T2CON register. The Timer2 postscaler is controlled by the TOUTPS bits in the T2CON register. The prescaler and postscaler counters are cleared when: See Figure 14-1 for a block diagram of Timer2. 14.1 The TMR2 and PR2 registers are both fully readable and writable. On any Reset, the TMR2 register is set to 00h and the PR2 register is set to FFh. Timer2 Operation The clock input to the Timer2 module is the system instruction clock (FOSC/4). The clock is fed into the Timer2 prescaler, which has prescale options of 1:1, 1:4 or 1:16. The output of the prescaler is then used to increment the TMR2 register. * A write to TMR2 occurs. * A write to T2CON occurs. * Any device Reset occurs (Power-on Reset, MCLR Reset, Watchdog Timer Reset, or Brown-out Reset). Note: The values of TMR2 and PR2 are constantly compared to determine when they match. TMR2 will increment from 00h until it matches the value in PR2. When a match occurs, two things happen: TMR2 is not cleared when T2CON is written. * TMR2 is reset to 00h on the next increment cycle. * The Timer2 postscaler is incremented. The match output of the Timer2/PR2 comparator is then fed into the Timer2 postscaler. The postscaler has postscale options of 1:1 to 1:16 inclusive. The output of the Timer2 postscaler is used to set the TMR2IF interrupt flag bit in the PIR1 register. FIGURE 14-1: TIMER2 BLOCK DIAGRAM TMR2 Output FOSC/4 Prescaler 1:1, 1:4, 1:16 2 TMR2 Comparator Sets Flag bit TMR2IF Reset EQ Postscaler 1:1 to 1:16 T2CKPS<1:0> PR2 4 TOUTPS<3:0> 2010-2013 Microchip Technology Inc. DS40001430E-page 105 PIC16(L)F720/721 14.2 Timer2 Control Register REGISTER 14-1: T2CON: TIMER2 CONTROL REGISTER U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7 Unimplemented: Read as `0' bit 6-3 TOUTPS<3:0>: Timer2 Output Postscaler Select bits 0000 = 1:1 Postscaler 0001 = 1:2 Postscaler 0010 = 1:3 Postscaler 0011 = 1:4 Postscaler 0100 = 1:5 Postscaler 0101 = 1:6 Postscaler 0110 = 1:7 Postscaler 0111 = 1:8 Postscaler 1000 = 1:9 Postscaler 1001 = 1:10 Postscaler 1010 = 1:11 Postscaler 1011 = 1:12 Postscaler 1100 = 1:13 Postscaler 1101 = 1:14 Postscaler 1110 = 1:15 Postscaler 1111 = 1:16 Postscaler bit 2 TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16 TABLE 14-1: x = Bit is unknown SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page INTCON GIE PEIE TMR0IE INTE RABIE TMR0IF INTF RABIF 38 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 39 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 40 PR2 TMR2 T2CON -- Timer2 module Period Register 105 Timer2 module Register 105 TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 106 Legend: x = unknown, u = unchanged, - = unimplemented read as `0'. Shaded cells are not used for Timer2 module. DS40001430E-page 106 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 15.0 CAPTURE/COMPARE/PWM (CCP) MODULE TABLE 15-1: The Capture/Compare/PWM module is a peripheral which allows the user to time and control different events. In Capture mode, the peripheral allows the timing of the duration of an event. The Compare mode allows the user to trigger an external event when a predetermined amount of time has expired. The PWM mode can generate a Pulse-Width Modulated signal of varying frequency and duty cycle. CCP MODE - TIMER RESOURCES REQUIRED CCP Mode Timer Resource Capture Timer1 Compare Timer1 PWM Timer2 The timer resources used by the module are shown in Table 15-1. Additional information on CCP modules is available in the Application Note AN594, "Using the CCP Modules" (DS00594). REGISTER 15-1: CCP1CON: CCP1 CONTROL REGISTER U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- DC1 B1 CCP1M3 CCP1M2 CCP1M1 CCP1M0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as `0' bit 5-4 DC1:B1: PWM Duty Cycle Least Significant bits Capture mode: Unused Compare mode: Unused PWM mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPR1L. bit 3-0 CCP1M<3:0>: CCP mode Select bits 0000 = Capture/Compare/PWM off (resets CCP module) 0001 = Unused (reserved) 0010 = Compare mode, toggle output on match (CCP1IF bit of the PIRx register is set) 0011 = Unused (reserved) 0100 = Capture mode, every falling edge 0101 = Capture mode, every rising edge 0110 = Capture mode, every 4th rising edge 0111 = Capture mode, every 16th rising edge 1000 = Compare mode, set output on match (CCP1IF bit of the PIR1 register is set) 1001 = Compare mode, clear output on match (CCP1IF bit of the PIR1 register is set) 1010 = Compare mode, generate software interrupt on match (CCP1IF bit is set of the PIRx register, CCP1 pin is unaffected) 1011 = Compare mode, trigger special event (CCP1IF bit of the PIR1register is set, TMR1 is reset and A/D conversion is started if the ADC module is enabled. CCP1 pin is unaffected.) 11xx = PWM mode. 2010-2013 Microchip Technology Inc. DS40001430E-page 107 PIC16(L)F720/721 15.1 Capture Mode 15.1.3 In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an event occurs on pin CCP1. An event is defined as one of the following and is configured by the CCP1M<3:0> bits of the CCP1CON register: * * * * Every falling edge Every rising edge Every 4th rising edge Every 16th rising edge 15.1.1 CCP1 PIN CONFIGURATION In Capture mode, the CCP1 pin should be configured as an input by setting the associated TRIS control bit. Note: If the CCP1 pin is configured as an output, a write to the port can cause a capture condition. FIGURE 15-1: Prescaler 1, 4, 16 CAPTURE MODE OPERATION BLOCK DIAGRAM Set Flag bit CCP1IF (PIR1 register) CCP1 CCPR1H and Edge Detect CCPR1L Capture Enable TMR1H TMR1L TIMER1 MODE SELECTION Timer1 must be running in Timer mode or Synchronized Counter mode for the CCP module to use the capture feature. In Asynchronous Counter mode or when Timer1 is clocked at FOSC, the capture operation may not work. Note: CCP PRESCALER There are four prescaler settings specified by the CCP1M<3:0> bits of the CCP1CON register. Whenever the CCP module is turned off, or the CCP module is not in Capture mode, the prescaler counter is cleared. Any Reset will clear the prescaler counter. Switching from one capture prescaler to another does not clear the prescaler and may generate a false interrupt. To avoid this unexpected operation, turn the module off by clearing the CCP1CON register before changing the prescaler (refer to Example 15-1). EXAMPLE 15-1: CHANGING BETWEEN CAPTURE PRESCALERS BANKSEL CCP1CON CLRF MOVLW MOVWF 15.1.5 CCP1CON<3:0> System Clock (FOSC) 15.1.2 When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the CCP1IE interrupt enable bit of the PIE1 register clear to avoid false interrupts. Additionally, the user should clear the CCP1IF interrupt flag bit of the PIR1 register following any change in operating mode 15.1.4 When a capture is made, the Interrupt Request Flag bit CCP1IF of the PIR1 register is set. The interrupt flag must be cleared in software. If another capture occurs before the value in the CCPR1H, CCPR1L register pair is read, the old captured value is overwritten by the new captured value (refer to Figure 15-1). SOFTWARE INTERRUPT ;Set Bank bits to point ;to CCP1CON CCP1CON ;Turn CCP module off NEW_CAPT_PS ;Load the W reg with ; the new prescaler ; move value and CCP ON CCP1CON ;Load CCP1CON with this ; value CAPTURE DURING SLEEP Capture mode depends upon the Timer1 module for proper operation. There are two options for driving the Timer1 module in Capture mode. It can be driven by the instruction clock (FOSC/4), or by an external clock source. If Timer1 is clocked by FOSC/4, then Timer1 will not increment during Sleep. When the device wakes from Sleep, Timer1 will continue from its previous state. If Timer1 is clocked by an external clock source, then Capture mode will operate as defined in Section 15.1 "Capture Mode". Clocking Timer1 from the system clock (FOSC) should not be used in Capture mode. In order for Capture mode to recognize the trigger event on the CCP1 pin, Timer1 must be clocked from the Instruction Clock (FOSC/4) or from an external clock source. DS40001430E-page 108 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 TABLE 15-2: SUMMARY OF REGISTERS ASSOCIATED WITH CAPTURE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSELB -- -- ANSB5 ANSB4 -- -- -- -- 56 CCP1CON -- -- DC1 B1 Name CCPR1L CCP1M3 CCP1M2 CCP1M1 CCP1M0 Capture/Compare/PWM Register Low Byte CCPR1H 107 -- Capture/Compare/PWM Register High Byte -- GIE PEIE TMR0IE INTE RABIE TMR0IF INTF RABIF 38 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 39 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 40 T1CON TMR1CS1 TMR1CS0 -- T1SYNC -- TMR1ON 102 T1GCON TMR1GE T1GSS0 103 INTCON T1GPOL T1CKPS1 T1CKPS0 T1GTM T1GSPM T1GGO/ DONE T1GVAL T1GSS1 TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register 98 98 TRISB TRISB7 TRISB6 TRISB5 TRISB4 -- -- -- -- 55 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 61 Legend: - = Unimplemented locations, read as `0', u = unchanged, x = unknown. Shaded cells are not used by the capture. 2010-2013 Microchip Technology Inc. DS40001430E-page 109 PIC16(L)F720/721 15.2 Compare Mode 15.2.2 In Compare mode, the 16-bit CCPR1 register value is constantly compared against the TMR1 register pair value. When a match occurs, the CCP1 module may: * * * * * Toggle the CCP1 output Set the CCP1 output Clear the CCP1 output Generate a Special Event Trigger Generate a Software Interrupt In Compare mode, Timer1 must be running in either Timer mode or Synchronized Counter mode. The compare operation may not work in Asynchronous Counter mode. Note: The action on the pin is based on the value of the CCP1M<3:0> control bits of the CCP1CON register. All Compare modes can generate an interrupt. FIGURE 15-2: COMPARE MODE OPERATION BLOCK DIAGRAM CCP1CON<3:0> Mode Select Set CCP1IF Interrupt Flag (PIR1) 4 CCPR1H CCPR1L CCP1 Q S R Output Logic Match TRIS Output Enable Comparator TMR1H TMR1L Special Event Trigger Special Event Trigger will: * Clear TMR1H and TMR1L registers. * NOT set interrupt flag bit TMR1IF of the PIR1 register. * Set the GO/DONE bit to start the ADC conversion. 15.2.1 CCP1 PIN CONFIGURATION The user must configure the CCP1 pin as an output by clearing the associated TRIS bit. Note: Clearing the CCP1CON register will force the CCP1 compare output latch to the default low level. This is not the PORT I/O data latch. TIMER1 MODE SELECTION 15.2.3 Clocking Timer1 from the system clock (FOSC) should not be used in Compare mode. For the Compare operation of the TMR1 register to the CCPR1 register to occur, Timer1 must be clocked from the instruction clock (FOSC/4) or from an external clock source. SOFTWARE INTERRUPT MODE When Software Interrupt mode is chosen (CCP1M<3:0> = 1010), the CCP1IF bit in the PIR1 register is set and the CCP1 module does not assert control of the CCP1 pin (refer to the CCP1CON register). 15.2.4 SPECIAL EVENT TRIGGER When Special Event Trigger mode is chosen (CCP1M<3:0> = 1011), the CCP1 module does the following: * Resets Timer1 * Starts an ADC conversion if ADC is enabled The CCP1 module does not assert control of the CCP1 pin in this mode (refer to the CCP1CON register). The Special Event Trigger output of the CCP occurs immediately upon a match between the TMR1H, TMR1L register pair and the CCPR1H, CCPR1L register pair. The TMR1H, TMR1L register pair is not reset until the next rising edge of the Timer1 clock. This allows the CCPR1H, CCPR1L register pair to effectively provide a 16-bit programmable period register for Timer1. Note 1: The Special Event Trigger from the CCP module does not set interrupt flag bit TMR1IF of the PIR1 register. 2: Removing the match condition by changing the contents of the CCPR1H and CCPR1L register pair, between the clock edge that generates the Special Event Trigger and the clock edge that generates the Timer1 Reset, will preclude the Reset from occurring. 15.2.5 COMPARE DURING SLEEP The Compare mode is dependent upon the system clock (FOSC) for proper operation. Since FOSC is shut down during Sleep mode, the Compare mode will not function properly during Sleep. DS40001430E-page 110 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 TABLE 15-3: SUMMARY OF REGISTERS ASSOCIATED WITH COMPARE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ADCON0 -- -- CHS3 CHS2 CHS1 CHS0 GO/ DONE ADON 79 ANSELB -- -- ANSB5 ANSB4 -- -- -- -- CCP1CON -- -- DC1 B1 CCP1M3 Name CCP1M2 CCP1M1 CCP1M0 CCPR1L Capture/Compare/PWM Register Low Byte CCPR1H Capture/Compare/PWM Register High Byte 56 107 -- -- GIE PEIE TMR0IE PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 39 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 40 T1CON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 -- T1SYNC -- TMR1ON 102 T1GGO/ DONE T1GVAL T1GSS1 T1GSS0 103 INTCON T1GCON TMR1GE T1GPOL T1GTM INTE RABIE TMR0IF INTF RABIF 38 T1GSPM TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register 98 TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register 98 TRISB TRISB7 TRISB6 TRISB5 TRISB4 -- -- -- -- 55 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 61 Legend: - = Unimplemented locations, read as `0', u = unchanged, x = unknown. Shaded cells are not used by the compare. 2010-2013 Microchip Technology Inc. DS40001430E-page 111 PIC16(L)F720/721 15.3 PWM Mode The PWM mode generates a Pulse-Width Modulated signal on the CCP1 pin. The duty cycle, period and resolution are determined by the following registers: * * * * The PWM output (Figure 15-4) has a time base (period) and a time that the output stays high (duty cycle). FIGURE 15-4: PR2 T2CON CCPR1L CCP1CON CCP PWM OUTPUT Period Pulse Width In Pulse-Width Modulation (PWM) mode, the CCP module produces up to a 10-bit resolution PWM output on the CCP1 pin. TMR2 = PR2 TMR2 = CCPR1L:CCP1CON<5:4> TMR2 = 0 Figure 15-3 shows a simplified block diagram of PWM operation. 15.3.1 Figure 15-4 shows a typical waveform of the PWM signal. In PWM mode, the CCP1 pin is multiplexed with the PORT data latch. The user must configure the CCP1 pin as an output by clearing the associated TRIS bit. For a step-by-step procedure on how to set up the CCP module for PWM operation, refer to Section 15.3.8 "Setup for PWM Operation". FIGURE 15-3: Note: CCPX PIN CONFIGURATION Clearing the CCP1CON register will relinquish CCP1 control of the CCP1 pin. SIMPLIFIED PWM BLOCK DIAGRAM CCP1CON<5:4> Duty Cycle Registers CCPR1L CCPR1H(2) (Slave) CCP1 R Comparator TMR2 (1) Q S TRIS Comparator PR2 Note 1: 2: Clear Timer2, toggle CCP1 pin and latch duty cycle The 8-bit timer TMR2 register is concatenated with the 2-bit internal system clock (FOSC), or two bits of the prescaler, to create the 10-bit time base. In PWM mode, CCPR1H is a read-only register. DS40001430E-page 112 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 15.3.2 PWM PERIOD The PWM period is specified by the PR2 register of Timer2. The PWM period can be calculated using the formula of Equation 15-1. EQUATION 15-1: PWM PERIOD PWM Period = PR2 + 1 4 T OSC (TMR2 Prescale Value) Note: TOSC = 1/FOSC When TMR2 is equal to PR2, the following three events occur on the next increment cycle: * TMR2 is cleared * The CCP1 pin is set. (Exception: If the PWM duty cycle = 0%, the pin will not be set.) * The PWM duty cycle is latched from CCPR1L into CCPR1H. Note: The Timer2 postscaler (refer to Section 14.1 "Timer2 Operation") is not used in the determination of the PWM frequency. 15.3.3 PWM DUTY CYCLE The PWM duty cycle is specified by writing a 10-bit value to multiple registers: CCPR1L register and DC1 and B1 bits of the CCP1CON register. The CCPR1L contains the eight MSbs and the DC1 and B1 bits of the CCP1CON register contain the two LSbs. CCPR1L and DC1 and B1 bits of the CCP1CON register can be written to at any time. The duty cycle value is not latched into CCPR1H until after the period completes (i.e., a match between PR2 and TMR2 registers occurs). While using the PWM, the CCPR1H register is read-only. Equation 15-2 is used to calculate the PWM pulse width. Equation 15-3 is used to calculate the PWM duty cycle ratio. EQUATION 15-2: PULSE WIDTH Pulse Width = CCPR1L:CCP1CON<5:4> T OSC (TMR2 Prescale Value) Note: TOSC = 1/FOSC EQUATION 15-3: DUTY CYCLE RATIO CCPR1L:CCP1CON<5:4> Duty Cycle Ratio = ----------------------------------------------------------------------4 PR2 + 1 The CCPR1H register and a 2-bit internal latch are used to double buffer the PWM duty cycle. This double buffering is essential for glitchless PWM operation. The 8-bit timer TMR2 register is concatenated with either the 2-bit internal system clock (FOSC), or two bits of the prescaler, to create the 10-bit time base. The system clock is used if the Timer2 prescaler is set to 1:1. When the 10-bit time base matches the CCPR1H and 2-bit latch, then the CCP1 pin is cleared (refer to Figure 15-3). 2010-2013 Microchip Technology Inc. DS40001430E-page 113 PIC16(L)F720/721 15.3.4 PWM RESOLUTION EQUATION 15-4: The resolution determines the number of available duty cycles for a given period. For example, a 10-bit resolution will result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 discrete duty cycles. log 4 PR2 + 1 Resolution = ------------------------------------------ bits log 2 The maximum PWM resolution is 10 bits when PR2 is 255. The resolution is a function of the PR2 register value as shown by Equation 15-4. TABLE 15-4: 977 Hz Timer Prescale (1, 4, 16) PR2 Value 3.91 kHz PR2 Value 1 1 1 1 0xFF 0x3F 0x1F 0x0F 10 10 10 8 7 6 1.22 kHz 4.90 kHz 19.61 kHz 76.92 kHz 153.85 kHz 200.0 kHz 16 4 1 1 1 1 0x65 0x65 0x65 0x19 0x0C 0x09 8 8 8 6 5 5 OPERATION IN SLEEP MODE 4. 5. * * CHANGES IN SYSTEM CLOCK FREQUENCY The PWM frequency is derived from the system clock frequency (FOSC). Any changes in the system clock frequency will result in changes to the PWM frequency. Refer to Section 7.0 "Oscillator Module" for additional details. EFFECTS OF RESET Any Reset will force all ports to Input mode and the CCP registers to their Reset states. SETUP FOR PWM OPERATION The following steps should be taken when configuring the CCP module for PWM operation: 2. 3. 250.0 kHz 4 In Sleep mode, the TMR2 register will not increment and the state of the module will not change. If the CCP1 pin is driving a value, it will continue to drive that value. When the device wakes up, TMR2 will continue from its previous state. 1. 125.0 kHz 0xFF Maximum Resolution (bits) 15.3.8 62.50 kHz 16 Timer Prescale (1, 4, 16) 15.3.7 15.625 kHz EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz) PWM Frequency 15.3.6 If the pulse width value is greater than the period the assigned PWM pin(s) will remain unchanged. 0xFF Maximum Resolution (bits) 15.3.5 Note: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 16 MHz) PWM Frequency TABLE 15-5: PWM RESOLUTION * 6. * * Load the CCPR1L register and the DCxBx bits of the CCP1CON register, with the PWM duty cycle value. Configure and start Timer2: Clear the TMR2IF interrupt flag bit of the PIR1 register. See Note below. Configure the T2CKPS bits of the T2CON register with the Timer2 prescale value. Enable Timer2 by setting the TMR2ON bit of the T2CON register. Enable PWM output pin: Wait until Timer2 overflows, TMR2IF bit of the PIR1 register is set. See Note below. Enable the PWM pin (CCP1) output driver(s) by clearing the associated TRIS bit(s). Note: In order to send a complete duty cycle and period on the first PWM output, the above steps must be included in the setup sequence. If it is not critical to start with a complete PWM signal on the first output, then step 6 may be ignored. Disable the PWM pin (CCP1) output driver(s) by setting the associated TRIS bit(s). Load the PR2 register with the PWM period value. Configure the CCP module for the PWM mode by loading the CCP1CON register with the appropriate values. DS40001430E-page 114 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 TABLE 15-6: Name SUMMARY OF REGISTERS ASSOCIATED WITH PWM Bit 3 Bit 2 Bit 1 Bit 0 Register on Page Bit 7 Bit 6 Bit 5 Bit 4 ANSELB -- -- ANSB5 ANSB4 -- -- -- -- 56 CCP1CON -- -- DC1 B1 CCP1M3 CCP1M2 CCP1M1 CCP1M0 107 CCPR1L Capture/Compare/PWM Register Low Byte CCPR1H Capture/Compare/PWM Register High Byte -- Timer2 module Period Register 105 PR2 T2CON -- -- TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 TMR2 Timer2 module Register 106 105 TRISB TRISB7 TRISB6 TRISB5 TRISB4 -- -- -- -- 55 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 61 Legend: - = Unimplemented locations, read as `0', u = unchanged, x = unknown. Shaded cells are not used by the PWM. 2010-2013 Microchip Technology Inc. DS40001430E-page 115 PIC16(L)F720/721 NOTES: DS40001430E-page 116 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 16.0 ADDRESSABLE UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (AUSART) The AUSART module includes the following capabilities: * * * * * * * * * * The Addressable Universal Synchronous Asynchronous Receiver Transmitter (AUSART) module is a serial I/O communications peripheral. It contains all the clock generators, shift registers and data buffers necessary to perform an input or output serial data transfer independent of device program execution. The AUSART, also known as a Serial Communications Interface (SCI), can be configured as a full-duplex asynchronous system or half-duplex synchronous system. Full-Duplex mode is useful for communications with peripheral systems, such as CRT terminals and personal computers. Half-Duplex Synchronous mode is intended for communications with peripheral devices, such as A/D or D/A integrated circuits, serial EEPROMs or other microcontrollers. These devices typically do not have internal clocks for baud rate generation and require the external clock signal provided by a master synchronous device. FIGURE 16-1: Full-duplex asynchronous transmit and receive Two-character input buffer One-character output buffer Programmable 8-bit or 9-bit character length Address detection in 9-bit mode Input buffer overrun error detection Received character framing error detection Half-duplex synchronous master Half-duplex synchronous slave Sleep operation Block diagrams of the AUSART transmitter and receiver are shown in Figure 16-1 and Figure 16-2. AUSART TRANSMIT BLOCK DIAGRAM Data Bus TXIE Interrupt TXIF TXREG Register 8 TX/CK MSb LSb (8) 0 Pin Buffer and Control TRMT SPEN * * * Transmit Shift Register (TSR) TXEN Baud Rate Generator FOSC /n TX9 n +1 SPBRG Multiplier x4 SYNC 1 0 0 BRGH x 1 0 2010-2013 Microchip Technology Inc. x16 x64 TX9D DS40001430E-page 117 PIC16(L)F720/721 FIGURE 16-2: AUSART RECEIVE BLOCK DIAGRAM SPEN CREN RX/DT Baud Rate Generator +1 SPBRG RSR Register MSb Pin Buffer and Control Data Recovery FOSC Multiplier x4 x16 x64 SYNC 1 0 0 BRGH x 1 0 Stop OERR (8) *** 7 1 LSb 0 START RX9 /n n FERR RX9D RCREG Register 8 FIFO Data Bus RCIF RCIE Interrupt The operation of the AUSART module is controlled through two registers: * Transmit Status and Control (TXSTA) * Receive Status and Control (RCSTA) These registers are detailed in Register 16-1 and Register 16-2, respectively. DS40001430E-page 118 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 16.1 AUSART Asynchronous Mode The AUSART transmits and receives data using the standard non-return-to-zero (NRZ) format. NRZ is implemented with two levels: a VOH Mark state which represents a `1' data bit, and a VOL space state which represents a `0' data bit. NRZ refers to the fact that consecutively transmitted data bits of the same value stay at the output level of that bit without returning to a neutral level between each bit transmission. An NRZ transmission port idles in the Mark state. Each character transmission consists of one Start bit followed by eight or nine data bits and is always terminated by one or more Stop bits. The Start bit is always a space and the Stop bits are always marks. The most common data format is eight bits. Each transmitted bit persists for a period of 1/(baud rate). An on-chip dedicated 8-bit Baud Rate Generator is used to derive standard baud rate frequencies from the system oscillator. Refer to Table 16-5 for examples of baud rate configurations. The AUSART transmits and receives the LSb first. The AUSART's transmitter and receiver are functionally independent, but share the same data format and baud rate. Parity is not supported by the hardware, but can be implemented in software and stored as the ninth data bit. 16.1.1 AUSART ASYNCHRONOUS TRANSMITTER The AUSART transmitter block diagram is shown in Figure 16-1. The heart of the transmitter is the serial Transmit Shift Register (TSR), which is not directly accessible by software. The TSR obtains its data from the transmit buffer, which is the TXREG register. 16.1.1.1 Enabling the Transmitter The AUSART transmitter is enabled for asynchronous operations by configuring the following three control bits: * TXEN = 1 * SYNC = 0 * SPEN = 1 All other AUSART control bits are assumed to be in their default state. Setting the TXEN bit of the TXSTA register enables the transmitter circuitry of the AUSART. Clearing the SYNC bit of the TXSTA register configures the AUSART for asynchronous operation. Setting the SPEN bit of the RCSTA register enables the AUSART and automatically configures the TX/CK I/O pin as an output. 2010-2013 Microchip Technology Inc. Note 1: When the SPEN bit is set the RX/DT I/O pin is automatically configured as an input, regardless of the state of the corresponding TRIS bit and whether or not the AUSART receiver is enabled. The RX/DT pin data can be read via a normal PORT read but PORT latch data output is precluded. 2: The TXIF transmitter interrupt flag is set when the TXEN enable bit is set. 16.1.1.2 Transmitting Data A transmission is initiated by writing a character to the TXREG register. If this is the first character, or the previous character has been completely flushed from the TSR, the data in the TXREG is immediately transferred to the TSR register. If the TSR still contains all or part of a previous character, the new character data is held in the TXREG until the Stop bit of the previous character has been transmitted. The pending character in the TXREG is then transferred to the TSR in one TCY immediately following the Stop bit transmission. The transmission of the Start bit, data bits and Stop bit sequence commences immediately following the transfer of the data to the TSR from the TXREG. 16.1.1.3 Transmit Interrupt Flag The TXIF interrupt flag bit of the PIR1 register is set whenever the AUSART transmitter is enabled and no character is being held for transmission in the TXREG. In other words, the TXIF bit is only clear when the TSR is busy with a character and a new character has been queued for transmission in the TXREG. The TXIF flag bit is not cleared immediately upon writing TXREG. TXIF becomes valid in the second instruction cycle following the write execution. Polling TXIF immediately following the TXREG write will return invalid results. The TXIF bit is read-only, it cannot be set or cleared by software. The TXIF interrupt can be enabled by setting the TXIE interrupt enable bit of the PIE1 register. However, the TXIF flag bit will be set whenever the TXREG is empty, regardless of the state of TXIE enable bit. To use interrupts when transmitting data, set the TXIE bit only when there is more data to send. Clear the TXIE interrupt enable bit upon writing the last character of the transmission to the TXREG. DS40001430E-page 119 PIC16(L)F720/721 16.1.1.4 TSR Status 16.1.1.6 The TRMT bit of the TXSTA register indicates the status of the TSR register. This is a read-only bit. The TRMT bit is set when the TSR register is empty and is cleared when a character is transferred to the TSR register from the TXREG. The TRMT bit remains clear until all bits have been shifted out of the TSR register. No interrupt logic is tied to this bit, so the user has to poll this bit to determine the TSR status. Note: 16.1.1.5 1. 2. 3. The TSR register is not mapped in data memory, so it is not available to the user. Transmitting 9-bit Characters 4. The AUSART supports 9-bit character transmissions. When the TX9 bit of the TXSTA register is set, the AUSART will shift nine bits out for each character transmitted. The TX9D bit of the TXSTA register is the ninth, and Most Significant, data bit. When transmitting 9-bit data, the TX9D data bit must be written before writing the eight Least Significant bits into the TXREG. All nine bits of data will be transferred to the TSR shift register immediately after the TXREG is written. 5. 6. 7. A special 9-bit Address mode is available for use with multiple receivers. Refer to Section 16.1.2.7 "Address Detection" for more information on the Address mode. FIGURE 16-3: Write to TXREG BRG Output (Shift Clock) TX/CK pin TXIF bit (Transmit Buffer Empty Flag) TRMT bit (Transmit Shift Reg. Empty Flag) DS40001430E-page 120 Asynchronous Transmission Setup: Initialize the SPBRG register and the BRGH bit to achieve the desired baud rate (Refer to Section 16.2 "AUSART Baud Rate Generator (BRG)"). Enable the asynchronous serial port by clearing the SYNC bit and setting the SPEN bit. If 9-bit transmission is desired, set the TX9 control bit. A set ninth data bit will indicate that the eight Least Significant data bits are an address when the receiver is set for address detection. Enable the transmission by setting the TXEN control bit. This will cause the TXIF interrupt bit to be set. If interrupts are desired, set the TXIE interrupt enable bit of the PIE1 register. An interrupt will occur immediately provided that the GIE and PEIE bits of the INTCON register are also set. If 9-bit transmission is selected, the ninth bit should be loaded into the TX9D data bit. Load 8-bit data into the TXREG register. This will start the transmission. ASYNCHRONOUS TRANSMISSION Word 1 Start bit bit 0 bit 1 bit 7/8 Stop bit Word 1 1 TCY Word 1 Transmit Shift Reg 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 FIGURE 16-4: ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK) Write to TXREG Word 1 BRG Output (Shift Clock) TX/CK pin Start bit TXIF bit (Transmit Buffer Empty Flag) bit 1 Word 1 bit 7/8 Stop bit Start bit bit 0 Word 2 1 TCY Word 1 Transmit Shift Reg. Word 2 Transmit Shift Reg. This timing diagram shows two consecutive transmissions. TABLE 16-1: Name bit 0 1 TCY TRMT bit (Transmit Shift Reg. Empty Flag) Note: Word 2 REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page GIE PEIE TMR0IE INTE RABIE TMR0IF INTF RABIF 38 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 39 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 40 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 126 INTCON RCSTA SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 127 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 61 CSRC TX9 TXEN TRMT TX9D 125 AUSART Transmit Data Register TXREG TXSTA SYNC -- -- BRGH Legend: x = unknown, - = unimplemented read as `0'. Shaded cells are not used for asynchronous transmission. 16.1.2 AUSART ASYNCHRONOUS RECEIVER The Asynchronous mode is typically used in RS-232 systems. The receiver block diagram is shown in Figure 16-2. The data is received on the RX/DT pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at 16 times the baud rate, whereas the serial Receive Shift Register (RSR) operates at the bit rate. When all eight or nine bits of the character have been shifted in, they are immediately transferred to a two character First-In First-Out (FIFO) memory. The FIFO buffering allows reception of two complete characters and the start of a third character before software must start servicing the AUSART receiver. The FIFO and RSR registers are not directly accessible by software. Access to the received data is via the RCREG register. 16.1.2.1 The AUSART receiver is enabled for asynchronous operation by configuring the following three control bits: * CREN = 1 * SYNC = 0 * SPEN = 1 All other AUSART control bits are assumed to be in their default state. Setting the CREN bit of the RCSTA register enables the receiver circuitry of the AUSART. Clearing the SYNC bit of the TXSTA register configures the AUSART for asynchronous operation. Setting the SPEN bit of the RCSTA register enables the AUSART and automatically configures the RX/DT I/O pin as an input. Note: 2010-2013 Microchip Technology Inc. Enabling the Receiver When the SPEN bit is set, the TX/CK I/O pin is automatically configured as an output, regardless of the state of the corresponding TRIS bit and whether or not the AUSART transmitter is enabled. The PORT latch is disconnected from the output driver so it is not possible to use the TX/CK pin as a general purpose output. DS40001430E-page 121 PIC16(L)F720/721 16.1.2.2 Receiving Data The receiver data recovery circuit initiates character reception on the falling edge of the first bit. The first bit, also known as the Start bit, is always a zero. The data recovery circuit counts one-half bit time to the center of the Start bit and verifies that the bit is still a zero. If it is not a zero then the data recovery circuit aborts character reception, without generating an error, and resumes looking for the falling edge of the Start bit. If the Start bit zero verification succeeds then the data recovery circuit counts a full bit time to the center of the next bit. The bit is then sampled by a majority detect circuit and the resulting `0' or `1' is shifted into the RSR. This repeats until all data bits have been sampled and shifted into the RSR. One final bit time is measured and the level sampled. This is the Stop bit, which is always a `1'. If the data recovery circuit samples a `0' in the Stop bit position then a framing error is set for this character, otherwise the framing error is cleared for this character. Refer to Section 16.1.2.4 "Receive Framing Error" for more information on framing errors. Immediately after all data bits and the Stop bit have been received, the character in the RSR is transferred to the AUSART receive FIFO and the RCIF interrupt flag bit of the PIR1 register is set. The top character in the FIFO is transferred out of the FIFO by reading the RCREG register. Note: 16.1.2.3 If the receive FIFO is overrun, no additional characters will be received until the overrun condition is cleared. Refer to Section 16.1.2.5 "Receive Overrun Error" for more information on overrun errors. Receive Interrupts The RCIF interrupt flag bit of the PIR1 register is set whenever the AUSART receiver is enabled and there is an unread character in the receive FIFO. The RCIF interrupt flag bit is read-only, it cannot be set or cleared by software. RCIF interrupts are enabled by setting all of the following bits: * RCIE interrupt enable bit of the PIE1 register * PEIE, Peripheral Interrupt Enable bit of the INTCON register * GIE, Global Interrupt Enable bit of the INTCON register 16.1.2.4 Receive Framing Error Each character in the receive FIFO buffer has a corresponding framing error Status bit. A framing error indicates that a Stop bit was not seen at the expected time. The framing error status is accessed via the FERR bit of the RCSTA register. The FERR bit represents the status of the top unread character in the receive FIFO. Therefore, the FERR bit must be read before reading the RCREG. The FERR bit is read-only and only applies to the top unread character in the receive FIFO. A framing error (FERR = 1) does not preclude reception of additional characters. It is not necessary to clear the FERR bit. Reading the next character from the FIFO buffer will advance the FIFO to the next character and the next corresponding framing error. The FERR bit can be forced clear by clearing the SPEN bit of the RCSTA register which resets the AUSART. Clearing the CREN bit of the RCSTA register does not affect the FERR bit. A framing error by itself does not generate an interrupt. Note: 16.1.2.5 If all receive characters in the receive FIFO have framing errors, repeated reads of the RCREG will not clear the FERR bit. Receive Overrun Error The receive FIFO buffer can hold two characters. An overrun error will be generated if a third character, in its entirety, is received before the FIFO is accessed. When this happens the OERR bit of the RCSTA register is set. The characters already in the FIFO buffer can be read but no additional characters will be received until the error is cleared. The error must be cleared by either clearing the CREN bit of the RCSTA register or by setting the AUSART by clearing the SPEN bit of the RCSTA register. 16.1.2.6 Receiving 9-bit Characters The AUSART supports 9-bit character reception. When the RX9 bit of the RCSTA register is set, the AUSART will shift 9 bits into the RSR for each character received. The RX9D bit of the RCSTA register is the ninth and Most Significant data bit of the top unread character in the receive FIFO. When reading 9-bit data from the receive FIFO buffer, the RX9D data bit must be read before reading the 8 Least Significant bits from the RCREG. The RCIF interrupt flag bit of the PIR1 register will be set when there is an unread character in the FIFO, regardless of the state of interrupt enable bits. DS40001430E-page 122 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 16.1.2.7 Address Detection A special Address Detection mode is available for use when multiple receivers share the same transmission line, such as in RS-485 systems. Address detection is enabled by setting the ADDEN bit of the RCSTA register. Address detection requires 9-bit character reception. When address detection is enabled, only characters with the ninth data bit set will be transferred to the receive FIFO buffer, thereby setting the RCIF interrupt bit of the PIR1 register. All other characters will be ignored. Upon receiving an address character, user software determines if the address matches its own. Upon address match, user software must disable address detection by clearing the ADDEN bit before the next Stop bit occurs. When user software detects the end of the message, determined by the message protocol used, software places the receiver back into the Address Detection mode by setting the ADDEN bit. 16.1.2.8 1. 2. 3. 4. 5. 6. 7. 8. 9. Asynchronous Reception Setup: Initialize the SPBRG register and the BRGH bit to achieve the desired baud rate (refer to Section 16.2 "AUSART Baud Rate Generator (BRG)"). Enable the serial port by setting the SPEN bit. The SYNC bit must be clear for asynchronous operation. If interrupts are desired, set the RCIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. If 9-bit reception is desired, set the RX9 bit. Enable reception by setting the CREN bit. The RCIF interrupt flag bit of the PIR1 register will be set when a character is transferred from the RSR to the receive buffer. An interrupt will be generated if the RCIE bit of the PIE1 register was also set. Read the RCSTA register to get the error flags and, if 9-bit data reception is enabled, the ninth data bit. Get the received 8 Least Significant data bits from the receive buffer by reading the RCREG register. If an overrun occurred, clear the OERR flag by clearing the CREN receiver enable bit. 2010-2013 Microchip Technology Inc. 16.1.2.9 9-bit Address Detection Mode Setup This mode would typically be used in RS-485 systems. To set up an Asynchronous Reception with Address Detect Enable: 1. Initialize the SPBRG register and the BRGH bit to achieve the desired baud rate (refer to Section 16.2 "AUSART Baud Rate Generator (BRG)"). 2. Enable the serial port by setting the SPEN bit. The SYNC bit must be clear for asynchronous operation. 3. If interrupts are desired, set the RCIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. 4. Enable 9-bit reception by setting the RX9 bit. 5. Enable address detection by setting the ADDEN bit. 6. Enable reception by setting the CREN bit. 7. The RCIF interrupt flag bit of the PIR1 register will be set when a character with the ninth bit set is transferred from the RSR to the receive buffer. An interrupt will be generated if the RCIE interrupt enable bit of the PIE1 register was also set. 8. Read the RCSTA register to get the error flags. The ninth data bit will always be set. 9. Get the received 8 Least Significant data bits from the receive buffer by reading the RCREG register. Software determines if this is the device's address. 10. If an overrun occurred, clear the OERR flag by clearing the CREN receiver enable bit. 11. If the device has been addressed, clear the ADDEN bit to allow all received data into the receive buffer and generate interrupts. DS40001430E-page 123 PIC16(L)F720/721 FIGURE 16-5: ASYNCHRONOUS RECEPTION Start bit bit 0 RX/DT pin Start bit bit 7/8 Stop bit bit 1 Rcv Shift Reg Rcv Buffer Reg bit 0 Start bit bit 7/8 Stop bit Word 2 RCREG Word 1 RCREG Read Rcv Buffer Reg RCREG bit 7/8 Stop bit RCIF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set. TABLE 16-2: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page INTCON GIE PEIE TMR0IE INTE RABIE TMR0IF INTF RABIF 38 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 39 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 40 SPEN RX9 SREN OERR RX9D 126 RCREG RCSTA AUSART Receive Data Register CREN ADDEN FERR 123 SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 127 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 61 TXSTA CSRC TX9 TXEN SYNC -- BRGH TRMT TX9D 125 Legend: x = unknown, - = unimplemented read as `0'. Shaded cells are not used for asynchronous reception. DS40001430E-page 124 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 REGISTER 16-1: R/W-0 CSRC TXSTA: TRANSMIT STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 U-0 R/W-0 R-1 R/W-0 TX9 TXEN(1) SYNC -- BRGH TRMT TX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don't care Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source) bit 6 TX9: 9-bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission bit 5 TXEN: Transmit Enable bit(1) 1 = Transmit enabled 0 = Transmit disabled bit 4 SYNC: AUSART mode Select bit 1 = Synchronous mode 0 = Asynchronous mode bit 3 Unimplemented: Read as `0' bit 2 BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode bit 1 TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full bit 0 TX9D: Ninth bit of Transmit Data Can be address/data bit or a parity bit. Note 1: x = Bit is unknown SREN/CREN overrides TXEN in Synchronous mode. 2010-2013 Microchip Technology Inc. DS40001430E-page 125 PIC16(L)F720/721 REGISTER 16-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 SPEN: Serial Port Enable bit(1) 1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins) 0 = Serial port disabled (held in Reset) bit 6 RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5 SREN: Single Receive Enable bit Asynchronous mode: Don't care Synchronous mode - Master: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode - Slave: Don't care bit 4 CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables receiver 0 = Disables receiver Synchronous mode: 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 = Disables continuous receive bit 3 ADDEN: Address Detect Enable bit Asynchronous mode 9-bit (RX9 = 1): 1 = Enables address detection, enable interrupt and load the receive buffer when RSR<8> is set 0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit Asynchronous mode 8-bit (RX9 = 0): Don't care Synchronous mode: Must be set to `0' bit 2 FERR: Framing Error bit 1 = Framing error (can be updated by reading RCREG register and receive next valid byte) 0 = No framing error bit 1 OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN) 0 = No overrun error bit 0 RX9D: Ninth bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware. Note 1: The AUSART module automatically changes the pin from tri-state to drive as needed. Configure TRISx = 1. DS40001430E-page 126 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 16.2 AUSART Baud Rate Generator (BRG) EXAMPLE 16-1: CALCULATING BAUD RATE ERROR For a device with FOSC of 16 MHz, desired baud rate of 9600, and Asynchronous mode with SYNC = 0 and BRGH = 0 (as seen in Table 16-5): The Baud Rate Generator (BRG) is an 8-bit timer that is dedicated to the support of both the asynchronous and synchronous AUSART operation. F OS C Desired Baud Rate = --------------------------------------64 SPBRG + 1 The SPBRG register determines the period of the free running baud rate timer. In Asynchronous mode the multiplier of the baud rate period is determined by the BRGH bit of the TXSTA register. In Synchronous mode, the BRGH bit is ignored. Solving for SPBRG: F OS C SPBRG = --------------------------------------------------------- - 1 64 Desired Baud Rate Table 16-3 contains the formulas for determining the baud rate. Example 16-1 provides a sample calculation for determining the baud rate and baud rate error. 16000000 = ------------------------ - 1 64 9600 Typical baud rates and error values for various asynchronous modes have been computed for your convenience and are shown in Table 16-5. It may be advantageous to use the high baud rate (BRGH = 1), to reduce the baud rate error. = 25.042 = 25 16000000 Actual Baud Rate = --------------------------64 25 + 1 Writing a new value to the SPBRG register causes the BRG timer to be reset (or cleared). This ensures that the BRG does not wait for a timer overflow before outputting the new baud rate. = 9615 Actual Baud Rate - Desired Baud Rate % Error = -------------------------------------------------------------------------------------------------- 100 Desired Baud Rate 9615 - 9600 = ------------------------------ 100 = 0.16% 9600 TABLE 16-3: BAUD RATE FORMULAS Configuration Bits AUSART Mode Baud Rate Formula 0 Asynchronous FOSC/[64 (n+1)] 1 Asynchronous FOSC/[16 (n+1)] x Synchronous FOSC/[4 (n+1)] SYNC BRGH 0 0 1 Legend: x = Don't care, n = value of SPBRG register TABLE 16-4: Name REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 126 SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 127 TXSTA CSRC TX9 TXEN SYNC -- BRGH TRMT TX9D 125 Legend: x = unknown, - = unimplemented read as `0'. Shaded cells are not used for the Baud Rate Generator. 2010-2013 Microchip Technology Inc. DS40001430E-page 127 PIC16(L)F720/721 TABLE 16-5: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0 BAUD RATE FOSC = 16.0000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 11.0592 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 8.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 4.000 MHz Actual Rate % Error SPBRG value (decimal) 300 -- -- -- -- -- -- -- -- -- 300 0.16 207 1200 1201 0.08 207 1200 0.00 143 1202 0.16 103 1202 0.16 51 2400 2403 0.16 103 2400 0.00 71 2404 0.16 51 2404 0.16 25 9600 9615 0.16 25 9600 0.00 17 9615 0.16 12 -- -- -- 10417 10416 -0.01 23 10165 -2.42 16 10417 0.00 11 10417 0.00 5 19.2k 19.23k 0.16 12 19.20k 0.00 8 -- -- -- -- -- -- 57.6k -- -- -- 57.60k 0.00 2 -- -- -- -- -- -- 115.2k -- -- -- -- -- -- -- -- -- -- -- -- SYNC = 0, BRGH = 0 BAUD RATE FOSC = 3.6864 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 1.000 MHz Actual Rate % Error SPBRG value (decimal) 300 300 0.00 191 300 0.16 51 1200 1200 0.00 47 1202 0.16 12 2400 2400 0.00 23 -- -- -- -- 9600 9600 0.00 5 -- -- 10417 -- -- -- -- -- -- 19.2k 19.20k 0.00 2 -- -- -- 57.6k 57.60k 0.00 0 -- -- -- 115.2k -- -- -- -- -- -- DS40001430E-page 128 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 TABLE 16-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1 BAUD RATE FOSC = 16.0000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 11.0592 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 8.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 4.000 MHz Actual Rate % Error SPBRG value (decimal) 300 1200 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1202 -- 0.16 -- 207 2400 -- -- -- -- 0.00 -- 71 2404 0.16 207 2404 0.16 103 9600 9615 0.16 103 -- 9600 9615 0.16 51 9615 0.16 25 10417 10417 0.00 95 10473 0.53 65 10417 0.00 47 10417 0.00 23 19.2k 19.23k 0.16 51 19.20k 0.00 35 19231 0.16 25 19.23k 0.16 12 57.6k 58.8k 2.12 16 57.60k 0.00 11 55556 -3.55 8 -- -- -- 115.2k -- -- -- 115.2k 0.00 5 -- -- -- -- -- -- SYNC = 0, BRGH = 1 BAUD RATE FOSC = 3.6864 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 1.000 MHz Actual Rate % Error SPBRG value (decimal) 300 -- -- -- 300 0.16 207 1200 1200 0.00 191 1202 0.16 51 2400 2400 0.00 95 2404 0.16 25 -- 9600 9600 0.00 23 -- -- 10417 10473 0.53 21 10417 0.00 5 19.2k 19.2k 0.00 11 -- -- -- 57.6k 57.60k 0.00 3 -- -- -- 115.2k 115.2k 0.00 1 -- -- -- 2010-2013 Microchip Technology Inc. DS40001430E-page 129 PIC16(L)F720/721 16.3 AUSART Synchronous Mode Synchronous serial communications are typically used in systems with a single master and one or more slaves. The master device contains the necessary circuitry for baud rate generation and supplies the clock for all devices in the system. Slave devices can take advantage of the master clock by eliminating the internal clock generation circuitry. There are two signal lines in Synchronous mode: a bidirectional data line and a clock line. Slaves use the external clock supplied by the master to shift the serial data into and out of their respective receive and transmit shift registers. Since the data line is bidirectional, synchronous operation is half-duplex only. Half-duplex refers to the fact that master and slave devices can receive and transmit data but not both simultaneously. The AUSART can operate as either a master or slave device. 16.3.1.2 Data is transferred out of the device on the RX/DT pin. The RX/DT and TX/CK pin output drivers are automatically enabled when the AUSART is configured for synchronous master transmit operation. A transmission is initiated by writing a character to the TXREG register. If the TSR still contains all or part of a previous character, the new character data is held in the TXREG until the last bit of the previous character has been transmitted. If this is the first character, or the previous character has been completely flushed from the TSR, the data in the TXREG is immediately transferred to the TSR. The transmission of the character commences immediately following the transfer of the data to the TSR from the TXREG. Each data bit changes on the leading edge of the master clock and remains valid until the subsequent leading clock edge. Start and Stop bits are not used in synchronous transmissions. 16.3.1 SYNCHRONOUS MASTER MODE The following bits are used to configure the AUSART for Synchronous Master operation: * * * * * SYNC = 1 CSRC = 1 SREN = 0 (for transmit); SREN = 1 (for receive) CREN = 0 (for transmit); CREN = 1 (for receive) SPEN = 1 Setting the SYNC bit of the TXSTA register configures the device for synchronous operation. Setting the CSRC bit of the TXSTA register configures the device as a master. Clearing the SREN and CREN bits of the RCSTA register ensures that the device is in the Transmit mode, otherwise the device will be configured to receive. Setting the SPEN bit of the RCSTA register enables the AUSART. 16.3.1.1 Master Clock Synchronous data transfers use a separate clock line, which is synchronous with the data. A device configured as a master transmits the clock on the TX/CK line. The TX/CK pin output driver is automatically enabled when the AUSART is configured for synchronous transmit or receive operation. Serial data bits change on the leading edge to ensure they are valid at the trailing edge of each clock. One clock cycle is generated for each data bit. Only as many clock cycles are generated as there are data bits. DS40001430E-page 130 Synchronous Master Transmission Note: The TSR register is not mapped in data memory, so it is not available to the user. 16.3.1.3 Synchronous Master Transmission Setup: 1. 2. 3. 4. 5. 6. 7. 8. Initialize the SPBRG register and the BRGH bit to achieve the desired baud rate (refer to Section 16.2 "AUSART Baud Rate Generator (BRG)"). Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. Disable Receive mode by clearing bits SREN and CREN. Enable Transmit mode by setting the TXEN bit. If 9-bit transmission is desired, set the TX9 bit. If interrupts are desired, set the TXIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. If 9-bit transmission is selected, the ninth bit should be loaded in the TX9D bit. Start transmission by loading data to the TXREG register. 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 FIGURE 16-6: SYNCHRONOUS TRANSMISSION RX/DT pin bit 0 bit 1 Word 1 bit 2 bit 7 bit 0 bit 1 Word 2 bit 7 TX/CK pin Write to TXREG Reg Write Word 1 Write Word 2 TXIF bit (Interrupt Flag) TRMT bit TXEN bit `1' Note: `1' Synchronous Master mode, SPBRG = 0, continuous transmission of two 8-bit words. FIGURE 16-7: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RX/DT pin bit 0 bit 2 bit 1 bit 6 bit 7 TX/CK pin Write to TXREG reg TXIF bit TRMT bit TXEN bit TABLE 16-6: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page INTCON GIE PEIE TMR0IE INTE RABIE TMR0IF INTF RABIF 38 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 39 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 40 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 126 SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 127 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 61 AUSART Transmit Data Register TXREG TXSTA CSRC TX9 TXEN SYNC -- BRGH -- TRMT TX9D 125 Legend: x = unknown, - = unimplemented read as `0'. Shaded cells are not used for synchronous master transmission. 2010-2013 Microchip Technology Inc. DS40001430E-page 131 PIC16(L)F720/721 16.3.1.4 Synchronous Master Reception Data is received at the RX/DT pin. The RX/DT pin output driver is automatically disabled when the AUSART is configured for synchronous master receive operation. In Synchronous mode, reception is enabled by setting either the Single Receive Enable bit (SREN of the RCSTA register) or the Continuous Receive Enable bit (CREN of the RCSTA register). When SREN is set and CREN is clear, only as many clock cycles are generated as there are data bits in a single character. The SREN bit is automatically cleared at the completion of one character. When CREN is set, clocks are continuously generated until CREN is cleared. If CREN is cleared in the middle of a character the CK clock stops immediately and the partial character is discarded. If SREN and CREN are both set, then SREN is cleared at the completion of the first character and CREN takes precedence. To initiate reception, set either SREN or CREN. Data is sampled at the RX/DT pin on the trailing edge of the TX/CK clock pin and is shifted into the Receive Shift Register (RSR). When a complete character is received into the RSR, the RCIF bit of the PIR1 register is set and the character is automatically transferred to the two character receive FIFO. The Least Significant eight bits of the top character in the receive FIFO are available in RCREG. The RCIF bit remains set as long as there are un-read characters in the receive FIFO. 16.3.1.5 Slave Clock Synchronous data transfers use a separate clock line, which is synchronous with the data. A device configured as a slave receives the clock on the TX/CK line. The TX/ CK pin output driver is automatically disabled when the device is configured for synchronous slave transmit or receive operation. Serial data bits change on the leading edge to ensure they are valid at the trailing edge of each clock. One data bit is transferred for each clock cycle. Only as many clock cycles should be received as there are data bits. 16.3.1.6 Receive Overrun Error The receive FIFO buffer can hold two characters. An overrun error will be generated if a third character, in its entirety, is received before RCREG is read to access the FIFO. When this happens the OERR bit of the RCSTA register is set. Previous data in the FIFO will not be overwritten. The two characters in the FIFO buffer can be read, however, no additional characters will be received until the error is cleared. The OERR bit can only be cleared by clearing the overrun condition. If the overrun error occurred when the SREN bit is set and CREN is clear then the error is cleared by reading RCREG. If the overrun occurred when the CREN bit is set then the error condition is cleared by either clearing the CREN bit of the RCSTA register. DS40001430E-page 132 16.3.1.7 Receiving 9-bit Characters The AUSART supports 9-bit character reception. When the RX9 bit of the RCSTA register is set, the AUSART will shift nine bits into the RSR for each character received. The RX9D bit of the RCSTA register is the ninth, and Most Significant, data bit of the top unread character in the receive FIFO. When reading 9-bit data from the receive FIFO buffer, the RX9D data bit must be read before reading the eight Least Significant bits from the RCREG. Address detection in Synchronous modes is not supported, therefore the ADDEN bit of the RCSTA register must be cleared. 16.3.1.8 Synchronous Master Reception Setup 1. Initialize the SPBRG register for the appropriate baud rate. Set or clear the BRGH bit, as required, to achieve the desired baud rate. 2. Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. 3. Ensure bits CREN and SREN are clear. 4. If interrupts are desired, set the RCIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. 5. If 9-bit reception is desired, set bit RX9. 6. Verify address detection is disabled by clearing the ADDEN bit of the RCSTA register. 7. Start reception by setting the SREN bit or for continuous reception, set the CREN bit. 8. Interrupt flag bit RCIF of the PIR1 register will be set when reception of a character is complete. An interrupt will be generated if the RCIE interrupt enable bit of the PIE1 register was set. 9. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. 10. Read the 8-bit received data by reading the RCREG register. 11. If an overrun error occurs, clear the error by either clearing the CREN bit of the RCSTA register or by clearing the SPEN bit, which resets the AUSART. 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 FIGURE 16-8: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) RX/DT pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 TX/CK pin Write to bit SREN SREN bit CREN bit `0' `0' RCIF bit (Interrupt) Read RCREG Note: Timing diagram demonstrates Synchronous Master mode with bit SREN = 1 and bit BRGH = 0. TABLE 16-7: Name INTCON REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page GIE PEIE TMR0IE INTE RABIE TMR0IF INTF RABIF 38 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 39 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF RCREG AUSART Receive Data Register 40 123 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 126 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 61 TXSTA CSRC TX9 TXEN SYNC -- BRGH TRMT TX9D 125 Legend: x = unknown, - = unimplemented read as `0'. Shaded cells are not used for synchronous master reception. 2010-2013 Microchip Technology Inc. DS40001430E-page 133 PIC16(L)F720/721 16.3.2 SYNCHRONOUS SLAVE MODE The following bits are used to configure the AUSART for synchronous slave operation: * * * * * SYNC = 1 CSRC = 0 SREN = 0 (for transmit); SREN = 1 (for receive) CREN = 0 (for transmit); CREN = 1 (for receive) SPEN = 1 1. 2. 3. 4. Setting the SYNC bit of the TXSTA register configures the device for synchronous operation. Clearing the CSRC bit of the TXSTA register configures the device as a slave. Clearing the SREN and CREN bits of the RCSTA register ensures that the device is in the Transmit mode, otherwise the device will be configured to receive. Setting the SPEN bit of the RCSTA register enables the AUSART. 16.3.2.1 If two words are written to the TXREG and then the SLEEP instruction is executed, the following will occur: 5. 16.3.2.2 1. AUSART Synchronous Slave Transmit The operation of the Synchronous Master and Slave modes are identical (refer to Section 16.3.1.2 "Synchronous Master Transmission"), except in the case of the Sleep mode. 2. 3. 4. 5. 6. 7. 8. TABLE 16-8: Name The first character will immediately transfer to the TSR register and transmit. The second word will remain in TXREG register. The TXIF bit will not be set. After the first character has been shifted out of TSR, the TXREG register will transfer the second character to the TSR and the TXIF bit will now be set. If the PEIE and TXIE bits are set, the interrupt will wake the device from Sleep and execute the next instruction. If the GIE bit is also set, the program will call the Interrupt Service Routine. Synchronous Slave Transmission Setup Set the SYNC and SPEN bits and clear the CSRC bit. Clear the CREN and SREN bits. If using interrupts, ensure that the GIE and PEIE bits of the INTCON register are set and set the TXIE bit. If 9-bit transmission is desired, set the TX9 bit. Enable transmission by setting the TXEN bit. Verify address detection is disabled by clearing the ADDEN bit of the RCSTA register. If 9-bit transmission is selected, insert the Most Significant bit into the TX9D bit. Start transmission by writing the Least Significant 8 bits to the TXREG register. REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page GIE PEIE TMR0IE INTE RABIE TMR0IF INTF RABIF 38 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 39 PIR1 INTCON TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 40 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 126 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 61 TXREG TXSTA AUSART Transmit Data Register CSRC TX9 TXEN SYNC -- BRGH -- TRMT TX9D 125 Legend: x = unknown, - = unimplemented read as `0'. Shaded cells are not used for synchronous slave transmission. DS40001430E-page 134 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 16.3.2.3 AUSART Synchronous Slave Reception 16.3.2.4 1. The operation of the Synchronous Master and Slave modes is identical (Section 16.3.1.4 "Synchronous Master Reception"), with the following exceptions: 2. * Sleep * CREN bit is always set, therefore the receiver is never Idle * SREN bit, which is a "don't care" in Slave mode 3. 4. A character may be received while in Sleep mode by setting the CREN bit prior to entering Sleep. Once the word is received, the RSR register will transfer the data to the RCREG register. If the RCIE interrupt enable bit of the PIE1 register is set, the interrupt generated will wake the device from Sleep and execute the next instruction. If the GIE bit is also set, the program will branch to the interrupt vector. 5. 6. 7. 8. 9. TABLE 16-9: Name INTCON Synchronous Slave Reception Setup Set the SYNC and SPEN bits and clear the CSRC bit. If interrupts are desired, set the RCIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. If 9-bit reception is desired, set the RX9 bit. Verify address detection is disabled by clearing the ADDEN bit of the RCSTA register. Set the CREN bit to enable reception. The RCIF bit of the PIR1 register will be set when reception is complete. An interrupt will be generated if the RCIE bit of the PIE1 register was set. If 9-bit mode is enabled, retrieve the Most Significant bit from the RX9D bit of the RCSTA register. Retrieve the 8 Least Significant bits from the receive FIFO by reading the RCREG register. If an overrun error occurs, clear the error by either clearing the CREN bit of the RCSTA register. REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page GIE PEIE TMR0IE INTE RABIE TMR0IF INTF RABIF 38 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 39 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF RCREG AUSART Receive Data Register 40 123 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 126 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 61 TXSTA CSRC TX9 TXEN SYNC -- BRGH TRMT TX9D 125 Legend: x = unknown, - = unimplemented read as `0'. Shaded cells are not used for synchronous slave reception. 2010-2013 Microchip Technology Inc. DS40001430E-page 135 PIC16(L)F720/721 16.4 AUSART Operation During Sleep The AUSART will remain active during Sleep only in the Synchronous Slave mode. All other modes require the system clock and therefore cannot generate the necessary signals to run the Transmit or Receive Shift registers during Sleep. Synchronous Slave mode uses an externally generated clock to run the Transmit and Receive Shift registers. 16.4.1 SYNCHRONOUS RECEIVE DURING SLEEP To receive during Sleep, all the following conditions must be met before entering Sleep mode: * RCSTA and TXSTA Control registers must be configured for synchronous slave reception (refer to Section 16.3.2.4 "Synchronous Slave Reception Setup"). * If interrupts are desired, set the RCIE bit of the PIE1 register and the PEIE bit of the INTCON register. * The RCIF interrupt flag must be cleared by reading RCREG to unload any pending characters in the receive buffer. Upon entering Sleep mode, the device will be ready to accept data and clocks on the RX/DT and TX/CK pins, respectively. When the data word has been completely clocked in by the external device, the RCIF interrupt flag bit of the PIR1 register will be set. Thereby, waking the processor from Sleep. 16.4.2 SYNCHRONOUS TRANSMIT DURING SLEEP To transmit during Sleep, all the following conditions must be met before entering Sleep mode: * RCSTA and TXSTA Control registers must be configured for synchronous slave transmission (refer to Section 16.3.2.2 "Synchronous Slave Transmission Setup"). * The TXIF interrupt flag must be cleared by writing the output data to the TXREG, thereby filling the TSR and transmit buffer. * If interrupts are desired, set the TXIE bit of the PIE1 register and the PEIE bit of the INTCON register. Upon entering Sleep mode, the device will be ready to accept clocks on the TX/CK pin and transmit data on the RX/DT pin. When the data word in the TSR has been completely clocked out by the external device, the pending byte in the TXREG will transfer to the TSR and the TXIF flag will be set. Thereby, waking the processor from Sleep. At this point, the TXREG is available to accept another character for transmission, which will clear the TXIF flag. Upon waking from Sleep, the instruction following the SLEEP instruction will be executed. If the GIE, Global Interrupt Enable bit is also set then the Interrupt Service Routine at address 0004h will be called. Upon waking from Sleep, the instruction following the SLEEP instruction will be executed. If the GIE, Global Interrupt Enable bit of the INTCON register is also set, then the Interrupt Service Routine at address 0004h will be called. DS40001430E-page 136 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 17.0 SSP MODULE OVERVIEW The Synchronous Serial Port (SSP) module is a serial interface useful for communicating with other peripherals or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc. The SSP module can operate in one of two modes: * Serial Peripheral Interface (SPI) * Inter-Integrated Circuit (I2CTM) 17.1 A typical SPI connection between microcontroller devices is shown in Figure 17-1. Addressing of more than one slave device is accomplished via multiple hardware slave select lines. External hardware and additional I/O pins must be used to support multiple slave select addressing. This prevents extra overhead in software for communication. For SPI communication, typically three pins are used: * Serial Data Out (SDO) * Serial Data In (SDI) * Serial Clock (SCK) SPI Mode The SPI mode allows eight bits of data to be synchronously transmitted and received, simultaneously. The SSP module can be operated in one of two SPI modes: Additionally, a fourth pin may be used when in a Slave mode of operation: * Slave Select (SS) * Master mode * Slave mode SPI is a full-duplex protocol, with all communication being bidirectional and initiated by a master device. All clocking is provided by the master device and all bits are transmitted, MSb first. Care must be taken to ensure that all devices on the SPI bus are setup to allow all controllers to send and receive data at the same time. FIGURE 17-1: TYPICAL SPI MASTER/SLAVE CONNECTION SPI Master SSPM<3:0> = 00xx SPI Slave SSPM<3:0> = 010x SDO SDI Serial Input Buffer (SSPBUF) SDI Shift Register (SSPSR) MSb Serial Input Buffer (SSPBUF) LSb SCK General I/O Processor 1 2010-2013 Microchip Technology Inc. SDO Serial Clock Slave Select (optional) Shift Register (SSPSR) MSb LSb SCK SS Processor 2 DS40001430E-page 137 PIC16(L)F720/721 FIGURE 17-2: SPI MODE BLOCK DIAGRAM Internal Data Bus Read Write SSPBUF Reg SSPSR Reg SDI bit 0 Shift Clock bit 7 SDO SS Control Enable RA5/SS RA0/SS SSSEL 2 Clock Select Edge Select 2 Edge Select Prescaler 4, 16, 64 SCK TRISx TMR2 Output FOSC 4 SSPM<3:0> DS40001430E-page 138 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 17.1.1 MASTER MODE In Master mode, data transfer can be initiated at any time because the master controls the SCK line. Master mode determines when the slave (Figure 17-1, Processor 2) transmits data via control of the SCK line. 17.1.1.1 Master Mode Operation The SSP consists of a transmit/receive shift register (SSPSR) and a buffer register (SSPBUF). The SSPSR register shifts the data in and out of the device, MSb first. The SSPBUF register holds the data that is written out of the master until the received data is ready. Once the eight bits of data have been received, the byte is moved to the SSPBUF register. The Buffer Full Status bit, BF of the SSPSTAT register, and the SSP Interrupt Flag bit, SSPIF of the PIR1 register, are then set. Any write to the SSPBUF register during transmission/ reception of data will be ignored and the Write Collision Detect bit, WCOL of the SSPCON register, will be set. User software must clear the WCOL bit so that it can be determined if the following write(s) to the SSPBUF register completed successfully. When the application software is expecting to receive valid data, the SSPBUF should be read before the next byte of data is written to the SSPBUF. The BF bit of the SSPSTAT register is set when SSPBUF has been loaded with the received data (transmission is complete). When the SSPBUF is read, the BF bit is cleared. This data may be irrelevant if the SPI is only a transmitter. The SSP interrupt may be used to determine when the transmission/reception is complete and the SSPBUF must be read and/or written. If interrupts are not used, then software polling can be done to ensure that a write collision does not occur. Example 17-1 shows the loading of the SSPBUF (SSPSR) for data transmission. Note: 17.1.1.2 The SSPSR is not directly readable or writable and can only be accessed by addressing the SSPBUF register. Enabling Master I/O To enable the serial port, the SSPEN bit of the SSPCON register, must be set. To reset or reconfigure SPI mode, clear the SSPEN bit, re-initialize the SSPCON register and then set the SSPEN bit. If a Master mode of operation is selected in the SSPM bits of the SSPCON register, the SDI, SDO and SCK pins will be assigned as serial port pins. 17.1.1.3 Master Mode Setup In Master mode, the data is transmitted/received as soon as the SSPBUF register is loaded with a byte value. If the master is only going to receive, SDO output could be disabled (programmed and used as an input). The SSPSR register will continue to shift in the signal present on the SDI pin at the programmed clock rate. When initializing SPI Master mode operation, several options need to be specified. This is accomplished by programming the appropriate control bits in the SSPCON and SSPSTAT registers. These control bits allow the following to be specified: * * * * * SCK as clock output Idle state of SCK (CKP bit) Data input sample phase (SMP bit) Output data on rising/falling edge of SCK (CKE bit) Clock bit rate In Master mode, the SPI clock rate (bit rate) is user selectable to be one of the following: * * * * FOSC/4 (or TCY) FOSC/16 (or 4 TCY) FOSC/64 (or 16 TCY) (Timer2 output)/2 This allows a maximum data rate of 5 Mbps (at FOSC = 16 MHz). Figure 17-3 shows the waveforms for Master mode. The clock polarity is selected by appropriately programming the CKP bit of the SSPCON register. When the CKE bit is set, the SDO data is valid before there is a clock edge on SCK. The sample time of the input data is shown based on the state of the SMP bit and can occur at the middle or end of the data output time. The time when the SSPBUF is loaded with the received data is shown. 17.1.1.4 Sleep in Master Mode In Master mode, all module clocks are halted and the transmission/reception will remain in their current state, paused, until the device wakes from Sleep. After the device wakes up from Sleep, the module will continue to transmit/receive data. For these pins to function as serial port pins, they must have their corresponding data direction bits set or cleared in the associated TRIS register as follows: * SDI configured as input * SDO configured as output * SCK configured as output 2010-2013 Microchip Technology Inc. DS40001430E-page 139 PIC16(L)F720/721 FIGURE 17-3: SPI MASTER MODE WAVEFORM Write to SSPBUF SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) 4 Clock Modes SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) SDO (CKE = 0) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDO (CKE = 1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI (SMP = 0) bit 0 bit 7 Input Sample (SMP = 0) SDI (SMP = 1) bit 0 bit 7 Input Sample (SMP = 1) SSPIF SSPSR to SSPBUF EXAMPLE 17-1: LOOP BANKSEL BTFSS GOTO BANKSEL MOVF MOVWF MOVF MOVWF LOADING THE SSPBUF (SSPSR) REGISTER SSPSTAT SSPSTAT, BF LOOP SSPBUF SSPBUF, W RXDATA TXDATA, W SSPBUF DS40001430E-page 140 ; ;Has data been received(transmit complete)? ;No ; ;WREG reg = contents of SSPBUF ;Save in user RAM, if data is meaningful ;W reg = contents of TXDATA ;New data to xmit 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 17.1.2 SLAVE MODE For any SPI device acting as a slave, the data is transmitted and received as external clock pulses appear on SCK pin. This external clock must meet the minimum high and low times as specified in the electrical specifications. 17.1.2.1 Slave Mode Operation The SSP consists of a transmit/receive shift register (SSPSR) and a buffer register (SSPBUF). The SSPSR shifts the data in and out of the device, MSb first. The SSPBUF holds the data that was written to the SSPSR until the received data is ready. The slave has no control as to when data will be clocked in or out of the device. All data that is to be transmitted, to a master or another slave, must be loaded into the SSPBUF register before the first clock pulse is received. Once eight bits of data have been received: * Received byte is moved to the SSPBUF register * BF bit of the SSPSTAT register is set * SSPIF bit of the PIR1 register is set Any write to the SSPBUF register during transmission/ reception of data will be ignored and the Write Collision Detect bit, WCOL of the SSPCON register, will be set. User software must clear the WCOL bit so that it can be determined if the following write(s) to the SSPBUF register completed successfully. The user's firmware must read SSPBUF, clearing the BF flag, or the SSPOV bit of the SSPCON register will be set with the reception of the next byte and communication will be disabled. A SPI module transmits and receives at the same time, occasionally causing dummy data to be transmitted/ received. It is up to the user to determine which data is to be used and what can be discarded. 2010-2013 Microchip Technology Inc. 17.1.2.2 Enabling Slave I/O To enable the serial port, the SSPEN bit of the SSPCON register must be set. If a Slave mode of operation is selected in the SSPM bits of the SSPCON register, the SDI, SDO and SCK pins will be assigned as serial port pins. For these pins to function as serial port pins, they must have their corresponding data direction bits set or cleared in the associated TRIS register as follows: * SDI configured as input * SDO configured as output * SCK configured as input Optionally, a fourth pin, Slave Select (SS) may be used in Slave mode. Slave Select may be configured to operate on the RC6/SS pin via the SSSEL bit in the APFCON register. Upon selection of a Slave Select pin, the appropriate bits must be set in the ANSELA and TRISA registers. Slave Select must be set as an input by setting the corresponding bit in TRISA, and digital I/O must be enabled on the SS pin by clearing the corresponding bit of the ANSELA register. 17.1.2.3 Slave Mode Setup When initializing the SSP module to SPI Slave mode, compatibility must be ensured with the master device. This is done by programming the appropriate control bits of the SSPCON and SSPSTAT registers. These control bits allow the following to be specified: * * * * SCK as clock input Idle state of SCK (CKP bit) Data input sample phase (SMP bit) Output data on rising/falling edge of SCK (CKE bit) Figure 17-4 and Figure 17-5 show example waveforms of Slave mode operation. DS40001430E-page 141 PIC16(L)F720/721 FIGURE 17-4: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO bit 7 SDI (SMP = 0) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 0 bit 7 Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF FIGURE 17-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SS Not Optional SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPBUF SDO SDI (SMP = 0) bit 6 bit 7 bit 7 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 0 Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF DS40001430E-page 142 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 17.1.2.4 Slave Select Operation The SS pin allows Synchronous Slave mode operation. The SPI must be in Slave mode with SS pin control enabled (SSPM<3:0> = 0100). The associated TRIS bit for the SS pin must be set, making SS an input. Note: In Slave Select mode, when: * SS = 0, The device operates as specified in Section 17.1.2 "Slave Mode". * SS = 1, The SPI module is held in Reset and the SDO pin will be tri-stated. Note 1: When the SPI is in Slave mode with SS pin control enabled (SSPM<3:0> = 0100), the SPI module will reset if the SS pin is driven high. 2: If the SPI is used in Slave mode with CKE set, the SS pin control must be enabled. FIGURE 17-6: When the SPI module resets, the bit counter is cleared to `0'. This can be done by either forcing the SS pin to a high level or clearing the SSPEN bit. Figure 17-6 shows the timing waveform for such a synchronization event. 17.1.2.5 SSPSR must be reinitialized by writing to the SSPBUF register before the data can be clocked out of the slave again. Sleep in Slave Mode While in Sleep mode, the slave can transmit/receive data. The SPI Transmit/Receive Shift register operates asynchronously to the device on the externally supplied clock source. This allows the device to be placed in Sleep mode and data to be shifted into the SPI Transmit/Receive Shift register. When all eight bits have been received, the SSP Interrupt Flag bit will be set and, if enabled, will wake the device from Sleep. SLAVE SELECT SYNCHRONIZATION WAVEFORM SS SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO SDI (SMP = 0) SSPSR must be reinitialized by writing to the SSPBUF register before the data can be clocked out of the slave again. bit 7 bit 6 bit 7 bit 0 bit 0 bit 7 bit 7 Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF 2010-2013 Microchip Technology Inc. DS40001430E-page 143 PIC16(L)F720/721 REGISTER 17-1: SSPCON: SYNC SERIAL PORT CONTROL REGISTER (SPI MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 WCOL: Write Collision Detect bit 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision bit 6 SSPOV: Receive Overflow Indicator bit 1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user must read the SSPBUF, even if only transmitting data, to avoid setting overflow. In Master mode the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. 0 = No overflow bit 5 SSPEN: Synchronous Serial Port Enable bit 1 = Enables serial port and configures SCK, SDO and SDI as serial port pins(1) 0 = Disables serial port and configures these pins as I/O port pins bit 4 CKP: Clock Polarity Select bit 1 = Idle state for clock is a high level 0 = Idle state for clock is a low level bit 3-0 SSPM<3:0>: Synchronous Serial Port mode Select bits 0000 = SPI Master mode, clock = FOSC/4 0001 = SPI Master mode, clock = FOSC/16 0010 = SPI Master mode, clock = FOSC/64 0011 = SPI Master mode, clock = TMR2 output/2 0100 = SPI Slave mode, clock = SCK pin. SS pin control enabled. 0101 = SPI Slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin. Note 1: When enabled, these pins must be properly configured as input or output. DS40001430E-page 144 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 REGISTER 17-2: SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (SPI MODE) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7 SMP: SPI Data Input Sample Phase bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave mode: SMP must be cleared when SPI is used in Slave mode bit 6 CKE: SPI Clock Edge Select bit SPI mode, CKP = 0: 1 = Data stable on rising edge of SCK 0 = Data stable on falling edge of SCK SPI mode, CKP = 1: 1 = Data stable on falling edge of SCK 0 = Data stable on rising edge of SCK bit 5 D/A: Data/Address bit Used in I2C mode only. bit 4 P: Stop bit Used in I2C mode only. bit 3 S: Start bit Used in I2C mode only. bit 2 R/W: Read/Write Information bit Used in I2C mode only. bit 1 UA: Update Address bit Used in I2C mode only. bit 0 BF: Buffer Full Status bit 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty 2010-2013 Microchip Technology Inc. x = Bit is unknown DS40001430E-page 145 PIC16(L)F720/721 TABLE 17-1: Name SUMMARY OF REGISTERS ASSOCIATED WITH SPI OPERATION Bit 7 Bit 6 ANSELC ANSC7 ANSC6 INTCON GIE PEIE PIE1 TMR1GIE ADIE PIR1 TMR1GIF ADIF Bit 5 Bit 2 Bit 1 Bit 0 Register on Page ANSC3 ANSC2 ANSC1 ANSC0 61 RABIE TMR0IF INTF RABIF 38 TXIE SSPIE CCP1IE TMR2IE TMR1IE 39 TXIF SSPIF CCP1IF TMR2IF TMR1IF Bit 4 Bit 3 -- -- TMR0IE INTE RCIE RCIF PR2 Timer2 module Period Register SSPBUF 40 105 Synchronous Serial Port Receive Buffer/Transmit Register 139 SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 144 SSPSTAT SMP CKE D/A P S R/W UA BF 145 55 TRISB TRISB7 TRISB6 TRISB5 TRISB4 -- -- -- -- TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 T2CON -- TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 61 106 Legend: x = unknown, u = unchanged, - = unimplemented, read as `0'. Shaded cells are not used by the SSP in SPI mode. DS40001430E-page 146 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 I2C Mode 17.2 FIGURE 17-8: The SSP module, in I2C mode, implements all slave functions except general call support. It provides interrupts on Start and Stop bits in hardware to facilitate firmware implementations of the master functions. The SSP module implements the I2C Standard mode specifications: VDD Data is sampled on the rising edge and shifted out on the falling edge of the clock. This ensures that the SDA signal is valid during the SCL high time. The SCL clock input must have minimum high and low times for proper operation. Refer to Section 23.0 "Electrical Specifications". I2CTM MODE BLOCK DIAGRAM FIGURE 17-7: Internal Data Bus Read Write SSPBUF Reg SCL Shift Clock LSb MSb Slave 1 SDA SDA SCL SCL Slave 2 SDA SCL (optional) The SSP module has six registers for I2C operation. They are: * * * * SSP Control (SSPCON) register SSP Status (SSPSTAT) register Serial Receive/Transmit Buffer (SSPBUF) register SSP Shift Register (SSPSR), not directly accessible * SSP Address (SSPADD) register * SSP Address Mask (SSPMSK) register 17.2.1 HARDWARE SETUP Selection of I2C mode, with the SSPEN bit of the SSPCON register set, forces the SCL and SDA pins to be open drain, provided these pins are programmed as inputs by setting the appropriate TRISC bits. The SSP module will override the input state with the output data, when required, such as for Acknowledge and slavetransmitter sequences. Note: SSPSR Reg SDA VDD Master I2C Slave mode (7-bit address) I2C Slave mode (10-bit address) Start and Stop bit interrupts enabled to support firmware Master mode * Address masking * * * Two pins are used for data transfer; the SCL pin (clock line) and the SDA pin (data line). The user must configure the two pin's data direction bits as inputs in the appropriate TRIS register. Upon enabling I2C mode, the I2C slew rate limiters in the I/O pads are controlled by the SMP bit of SSPSTAT register. The SSP module functions are enabled by setting the SSPEN bit of SSPCON register. TYPICAL I2CTM CONNECTIONS Pull-up resistors must be provided externally to the SCL and SDA pins for proper operation of the I2C module. SSPMSK Reg Match Detect Addr Match SSPADD Reg Start and Stop bit Detect 2010-2013 Microchip Technology Inc. DS40001430E-page 147 PIC16(L)F720/721 17.2.2 START AND STOP CONDITIONS During times of no data transfer (Idle time), both the clock line (SCL) and the data line (SDA) are pulled high through external pull-up resistors. The Start and Stop conditions determine the start and stop of data transmission. The Start condition is defined as a high-to-low transition of the SDA line while SCL is high. The Stop condition is defined as a low-to-high transition of the SDA line while SCL is high. FIGURE 17-9: Figure 17-9 shows the Start and Stop conditions. A master device generates these conditions for starting and terminating data transfer. Due to the definition of the Start and Stop conditions, when data is being transmitted, the SDA line can only change state when the SCL line is low. START AND STOP CONDITIONS SDA SCL S Start P Change of Change of Data Allowed Data Allowed Condition 17.2.3 Stop Condition ACKNOWLEDGE After the valid reception of an address or data byte, the hardware automatically will generate the Acknowledge (ACK) pulse and load the SSPBUF register with the received value currently in the SSPSR register. There are certain conditions that will cause the SSP module not to generate this ACK pulse. They include any or all of the following: In such a case, the SSPSR register value is not loaded into the SSPBUF, but bit SSPIF of the PIR1 register is set. Table 17-2 shows the results of when a data transfer byte is received, given the status of bits BF and SSPOV. Flag bit BF is cleared by reading the SSPBUF register, while bit SSPOV is cleared through software. * The Buffer Full bit, BF of the SSPSTAT register, was set before the transfer was received. * The SSP Overflow bit, SSPOV of the SSPCON register, was set before the transfer was received. * The SSP module is being operated in Firmware Master mode. TABLE 17-2: DATA TRANSFER RECEIVED BYTE ACTIONS Status Bits as Data Transfer is Received SSPSR SSPBUF Generate ACK Pulse Set bit SSPIF (SSP Interrupt occurs if enabled) BF SSPOV 0 0 Yes Yes Yes 1 0 No No Yes 1 1 No No Yes 0 1 No No Yes Note 1: Shaded cells show the conditions where the user software did not properly clear the overflow condition. DS40001430E-page 148 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 17.2.4 ADDRESSING Once the SSP module has been enabled, it waits for a Start condition to occur. Following the Start condition, the 8 bits are shifted into the SSPSR register. All incoming bits are sampled with the rising edge of the clock line (SCL). 17.2.4.1 7-bit Addressing In 7-bit Addressing mode (Figure 17-10), the value of register SSPSR<7:1> is compared to the value of register SSPADD<7:1>. The address is compared on the falling edge of the eighth clock (SCL) pulse. If the addresses match, and the BF and SSPOV bits are clear, the following events occur: * The SSPSR register value is loaded into the SSPBUF register. * The BF bit is set. * An ACK pulse is generated. * SSP Interrupt Flag bit, SSPIF of the PIR1 register, is set (interrupt is generated if enabled) on the falling edge of the ninth SCL pulse. 17.2.4.2 10-bit Addressing In 10-bit Address mode, two address bytes need to be received by the slave (Figure 17-11). The five Most Significant bits (MSbs) of the first address byte specify if it is a 10-bit address. The R/W bit of the SSPSTAT register must specify a write so the slave device will receive the second address byte. For a 10-bit address, the first byte would equal `1111 0 A9 A8 0', where A9 and A8 are the two MSbs of the address. The sequence of events for 10-bit address is as follows for reception: 1. 2. 3. 4. 5. 6. 7. 8. 9. Load SSPADD register with high byte of address. Receive first (high) byte of address (bits SSPIF, BF and UA of the SSPSTAT register are set). Read the SSPBUF register (clears bit BF). Clear the SSPIF flag bit. Update the SSPADD register with second (low) byte of address (clears UA bit and releases the SCL line). Receive low byte of address (bits SSPIF, BF and UA are set). Update the SSPADD register with the high byte of address. If match releases SCL line, this will clear bit UA. Read the SSPBUF register (clears bit BF). Clear flag bit SSPIF. If data is requested by the master, once the slave has been addressed: 1. 2. 3. 4. 5. Receive repeated Start condition. Receive repeat of high byte address with R/W = 1, indicating a read. BF bit is set and the CKP bit is cleared, stopping SCL and indicating a read request. SSPBUF is written, setting BF, with the data to send to the master device. CKP is set in software, releasing the SCL line. 17.2.4.3 Address Masking The Address Masking register (SSPMSK) is only accessible while the SSPM bits of the SSPCON register are set to `1001'. In this register, the user can select which bits of a received address the hardware will compare when determining an address match. Any bit that is set to a zero in the SSPMSK register, the corresponding bit in the received address byte and SSPADD register are ignored when determining an address match. By default, the register is set to all ones, requiring a complete match of a 7-bit address or the lower eight bits of a 10-bit address. 2010-2013 Microchip Technology Inc. DS40001430E-page 149 PIC16(L)F720/721 17.2.5 RECEPTION When the R/W bit of the received address byte is clear, the master will write data to the slave. If an address match occurs, the received address is loaded into the SSPBUF register. An address byte overflow will occur if that loaded address is not read from the SSPBUF before the next complete byte is received. An SSP interrupt is generated for each data transfer byte. The BF, R/W and D/A bits of the SSPSTAT register are used to determine the status of the last received byte. I2CTM WAVEFORMS FOR RECEPTION (7-BIT ADDRESS) FIGURE 17-10: R/W = 0 Receiving Address SCL S 1 2 3 SSPIF BF 4 5 6 Receiving Data ACK A7 A6 A5 A4 A3 A2 A1 SDA 7 ACK D7 D6 D5 D4 D3 D2 D1 D0 8 9 1 2 3 4 5 6 7 8 9 Receiving Data ACK D7 D6 D5 D4 D3 D2 D1 D0 1 2 3 4 5 6 7 8 Cleared in software 9 P Bus Master sends Stop condition SSPBUF register is read SSPOV Bit SSPOV is set because the SSPBUF register is still full. ACK is not sent. DS40001430E-page 150 2010-2013 Microchip Technology Inc. 2010-2013 Microchip Technology Inc. CKP UA SSPOV BF SSPIF 1 SCL S 1 3 1 4 1 5 0 6 A9 7 8 UA is set indicating that the SSPADD needs to be updated SSPBUF is written with contents of SSPSR Cleared in software 2 1 9 R/W ACK A8 0 2 A6 4 A4 5 A3 6 A2 Cleared in software 3 A5 7 A1 UA is set indicating that SSPADD needs to be updated Cleared by hardware when SSPADD is updated with low byte of address Dummy read of SSPBUF to clear BF flag 1 A7 Receive Second Byte of Address 8 A0 9 ACK 1 D7 4 5 6 7 8 D2 D1 D0 Cleared in software 3 D3 Receive Data Byte D5 D4 Cleared by hardware when SSPADD is updated with high byte of address 2 D6 Clock is held low until update of SSPADD has taken place 9 ACK 1 2 D7 D6 4 5 6 D3 D2 Cleared in software 3 D5 D4 Receive Data Byte 7 8 D1 D0 P Bus master sends Stop condition SSPOV is set because SSPBUF is still full. ACK is not sent. 9 ACK FIGURE 17-11: SDA Receive First Byte of Address Clock is held low until update of SSPADD has taken place PIC16(L)F720/721 I2CTM SLAVE MODE TIMING (RECEPTION, 10-BIT ADDRESS) DS40001430E-page 151 PIC16(L)F720/721 17.2.6 TRANSMISSION When the R/W bit of the received address byte is set and an address match occurs, the R/W bit of the SSPSTAT register is set and the slave will respond to the master by reading out data. After the address match, an ACK pulse is generated by the slave hardware and the SCL pin is held low (clock is automatically stretched) until the slave is ready to respond. See Section 17.2.7 "Clock Stretching". The data the slave will transmit must be loaded into the SSPBUF register, which sets the BF bit. The SCL line is released by setting the CKP bit of the SSPCON register. Following the 8th falling clock edge, control of the SDA line is released back to the master so that the master can acknowledge or not acknowledge the response. If the master sends a not acknowledge, the slave's transmission is complete and the slave must monitor for the next Start condition. If the master acknowledges, control of the bus is returned to the slave to transmit another byte of data. Just as with the previous byte, the clock is stretched by the slave, data must be loaded into the SSPBUF and CKP must be set to release the clock line (SCL). An SSP interrupt is generated for each transferred data byte. The SSPIF flag bit of the PIR1 register initiates an SSP interrupt, and must be cleared by software before the next byte is transmitted. The BF bit of the SSPSTAT register is cleared on the falling edge of the 8th received clock pulse. The SSPIF flag bit is set on the falling edge of the ninth clock pulse. I 2C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS) FIGURE 17-12: Receiving Address A7 SDA SCL S A6 1 2 Data in sampled R/W A5 A4 A3 A2 A1 3 4 5 6 7 8 ACK Transmitting Data ACK 9 D7 1 SCL held low while CPU responds to SSPIF D6 D5 D4 D3 D2 D1 D0 2 3 4 5 6 7 8 9 P Cleared in software SSPIF BF Dummy read of SSPBUF to clear BF flag SSPBUF is written in software From SSP Interrupt Service Routine CKP Set bit after writing to SSPBUF (the SSPBUF must be written to before the CKP bit can be set) DS40001430E-page 152 2010-2013 Microchip Technology Inc. 2010-2013 Microchip Technology Inc. CKP UA BF SSPIF 1 SCL S 1 2 1 4 1 5 0 6 7 A9 A8 UA is set indicating that the SSPADD needs to be updated SSPBUF is written with contents of SSPSR 3 1 8 9 ACK R/W = 0 1 3 4 5 Cleared in software 2 7 UA is set indicating that SSPADD needs to be updated Cleared by hardware when SSPADD is updated with low byte of address. 6 A6 A5 A4 A3 A2 A1 8 A0 Receive Second Byte of Address Dummy read of SSPBUF to clear BF flag A7 9 ACK Clock is held low until update of SSPADD has taken place 2 3 1 4 1 Cleared in software 1 1 5 0 6 7 A9 A8 Cleared by hardware when SSPADD is updated with high byte of address. Dummy read of SSPBUF to clear BF flag Sr 1 Receive First Byte of Address Bus Master sends Restarts condition 8 9 ACK R/W = 1 4 5 6 Cleared in software 3 Write of SSPBUF 2 9 P Completion of data transmission clears BF flag 8 ACK CKP is automatically cleared in hardware holding SCL low CKP is set in software, initiates transmission 7 D4 D3 D2 D1 D0 Dummy read of SSPBUF to clear BF flag 1 D7 D6 D5 Transmitting Data Byte Clock is held low until CKP is set to `1' Bus Master sends Stop condition FIGURE 17-13: SDA Receive First Byte of Address Clock is held low until update of SSPADD has taken place PIC16(L)F720/721 I2C SLAVE MODE TIMING (TRANSMISSION 10-BIT ADDRESS) DS40001430E-page 153 PIC16(L)F720/721 17.2.7 CLOCK STRETCHING 2 During any SCL low phase, any device on the I C bus may hold the SCL line low and delay, or pause, the transmission of data. This "stretching" of a transmission allows devices to slow down communication on the bus. The SCL line must be constantly sampled by the master to ensure that all devices on the bus have released SCL for more data. Stretching usually occurs after an ACK bit of a transmission, delaying the first bit of the next byte. The SSP module hardware automatically stretches for two conditions: * After a 10-bit address byte is received (update SSPADD register) * Anytime the CKP bit of the SSPCON register is cleared by hardware The module will hold SCL low until the CKP bit is set. This allows the user slave software to update SSPBUF with data that may not be readily available. In 10-bit addressing modes, the SSPADD register must be updated after receiving the first and second address bytes. The SSP module will hold the SCL line low until the SSPADD has a byte written to it. The UA bit of the SSPSTAT register will be set, along with SSPIF, indicating an address update is needed. 17.2.8 FIRMWARE MASTER MODE Master mode of operation is supported in firmware using interrupt generation on the detection of the Start and Stop conditions. The Stop (P) and Start (S) bits of the SSPSTAT register are cleared from a Reset or when the SSP module is disabled (SSPEN cleared). The Stop (P) and Start (S) bits will toggle based on the Start and Stop conditions. Control of the I2C bus may be taken when the P bit is set or the bus is Idle and both the S and P bits are clear. Refer to Application Note AN554, "Software Implementation of I2CTM Bus Master" (DS00554) for more information. 17.2.9 MULTI-MASTER MODE In Multi-Master mode, the interrupt generation on the detection of the Start and Stop conditions allow the determination of when the bus is free. The Stop (P) and Start (S) bits are cleared from a Reset or when the SSP module is disabled. The Stop (P) and Start (S) bits will toggle based on the Start and Stop conditions. Control of the I2C bus may be taken when the P bit of the SSPSTAT register is set or when the bus is Idle, and both the S and P bits are clear. When the bus is busy, enabling the SSP Interrupt will generate the interrupt when the Stop condition occurs. In Multi-Master operation, the SDA line must be monitored to see if the signal level is the expected output level. This check only needs to be done when a high level is output. If a high level is expected and a low level is present, the device needs to release the SDA and SCL lines (set TRIS bits). There are two stages where this arbitration of the bus can be lost. They are the Address Transfer and Data Transfer stages. When the slave logic is enabled, the slave continues to receive. If arbitration was lost during the address transfer stage, communication to the device may be in progress. If addressed, an ACK pulse will be generated. If arbitration was lost during the data transfer stage, the device will need to re-transfer the data at a later time. Refer to Application Note AN578, "Use of the SSP Module in the I2CTM Multi-Master Environment" (DS00578) for more information. In Firmware Master mode, the SCL and SDA lines are manipulated by setting/clearing the corresponding TRIS bit(s). The output level is always low, irrespective of the value(s) in the corresponding PORT register bit(s). When transmitting a `1', the TRIS bit must be set (input) and a `0', the TRIS bit must be clear (output). The following events will cause the SSP Interrupt Flag bit, SSPIF, to be set (SSP Interrupt will occur if enabled): * Start condition * Stop condition * Data transfer byte transmitted/received Firmware Master mode of operation can be done with either the Slave mode Idle (SSPM<3:0> = 1011), or with either of the Slave modes in which interrupts are enabled. When both master and slave functionality is enabled, the software needs to differentiate the source(s) of the interrupt. DS40001430E-page 154 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 17.2.10 CLOCK SYNCHRONIZATION When the CKP bit is cleared, the SCL output is held low once it is sampled low. Therefore, the CKP bit will not stretch the SCL line until an external I2C master device has already asserted the SCL line low. The SCL output will remain low until the CKP bit is set and all other devices on the I2C bus have released SCL. This ensures that a write to the CKP bit will not violate the minimum high time requirement for SCL (Figure 17-14). FIGURE 17-14: 17.2.11 SLEEP OPERATION While in Sleep mode, the I2C module can receive addresses of data, and when an address match or complete byte transfer occurs, wake the processor from Sleep (if SSP interrupt is enabled). CLOCK SYNCHRONIZATION TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 SDA DX DX-1 SCL CKP Master device asserts clock Master device de-asserts clock WR SSPCON 2010-2013 Microchip Technology Inc. DS40001430E-page 155 PIC16(L)F720/721 SSPCON: SYNCHRONOUS SERIAL PORT CONTROL REGISTER (I2C MODE) REGISTER 17-3: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 WCOL: Write Collision Detect bit 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision bit 6 SSPOV: Receive Overflow Indicator bit 1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a "don't care" in Transmit mode. SSPOV must be cleared in software in either mode. 0 = No overflow bit 5 SSPEN: Synchronous Serial Port Enable bit 1 = Enables the serial port and configures the SDA and SCL pins as serial port pins(2) 0 = Disables serial port and configures these pins as I/O port pins bit 4 CKP: Clock Polarity Select bit 1 = Release control of SCL 0 = Holds clock low (clock stretch). (Used to ensure data setup time.) bit 3-0 SSPM<3:0>: Synchronous Serial Port mode Select bits 0110 = I2C Slave mode, 7-bit address 0111 = I2C Slave mode, 10-bit address 1000 = Reserved 1001 = Load SSPMSK register at SSPADD SFR Address(1) 1010 = Reserved 1011 = I2C Firmware Controlled Master mode (Slave Idle) 1100 = Reserved 1101 = Reserved 1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled 1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled Note 1: When this mode is selected, any reads or writes to the SSPADD SFR address accesses the SSPMSK register. 2: When enabled, these pins must be properly configured as input or output using the associated TRIS bit. DS40001430E-page 156 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 REGISTER 17-4: SSPSTAT: SYNCHRONOUS SERIAL PORT STATUS REGISTER (I2C MODE) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 SMP: SPI Data Input Sample Phase bit 1 = Slew Rate Control (limiting) disabled. Operating in I2C Standard mode (100 kHz and 1 MHz). 0 = Slew Rate Control (limiting) enabled. Operating in I2C Fast mode (400 kHz). bit 6 CKE: SPI Clock Edge Select bit This bit must be maintained clear. Used in SPI mode only. bit 5 D/A: DATA/ADDRESS bit (I2C mode only) 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address bit 4 P: Stop bit This bit is cleared when the SSP module is disabled, or when the Start bit is detected last. 1 = Indicates that a Stop bit has been detected last (this bit is `0' on Reset) 0 = Stop bit was not detected last bit 3 S: Start bit This bit is cleared when the SSP module is disabled, or when the Stop bit is detected last. 1 = Indicates that a Start bit has been detected last (this bit is `0' on Reset) 0 = Start bit was not detected last bit 2 R/W: READ/WRITE bit Information This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit or ACK bit. 1 = Read 0 = Write bit 1 UA: Update Address bit (10-bit I2C mode only) 1 = Indicates that the user needs to update the address in the SSPADD register 0 = Address does not need to be updated bit 0 BF: Buffer Full Status bit Receive: 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty Transmit: 1 = Transmit in progress, SSPBUF is full 0 = Transmit complete, SSPBUF is empty 2010-2013 Microchip Technology Inc. DS40001430E-page 157 PIC16(L)F720/721 REGISTER 17-5: SSPMSK: SSP MASK REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7-1 MSK<7:1>: Mask bits 1 = The received address bit n is compared to SSPADD<n> to detect I2C address match 0 = The received address bit n is not used to detect I2C address match bit 0 MSK<0>: Mask bit for I2C Slave Mode, 10-bit Address I2C Slave mode, 10-bit Address (SSPM<3:0> = 0111): 1 = The received address bit `0' is compared to SSPADD<0> to detect I2C address match 0 = The received address bit `0' is not used to detect I2C address match All other SSP modes: this bit has no effect. SSPADD: SSP I2C ADDRESS REGISTER REGISTER 17-6: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-0 x = Bit is unknown ADD<7:0>: Address bits Received address TABLE 17-3: Name REGISTERS ASSOCIATED WITH I2C OPERATION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page GIE PEIE TMR0IE INTE RABIE TMR0IF INTF RABIF 38 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 40 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE INTCON SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register SSPADD ADD<7:0> SSPCON WCOL SSPOV SSPEN SSPSTAT SMP(1) CKE(1) D/A P TRISB TRISB7 TRISB6 TRISB5 TRISB4 (2) CKP 158 SSPM3 SSPM2 SSPM1 SSPM0 S R/W UA BF 145 -- -- -- -- 55 MSK<7:0> SSPMSK 39 139 156 158 Legend: x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by SSP module in I2C mode. Note 1: Maintain these bits clear in I2C mode. 2: Accessible only when SSPM<3:0> = 1001. DS40001430E-page 158 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 18.0 FLASH PROGRAM MEMORY SELF READ/SELF WRITE CONTROL The Flash Program Memory is readable and writable during normal operation of the device. This memory is not directly mapped in the register file space. Instead, it is indirectly addressed through the Special Function Registers. There are six SFRs used to read/write this memory: * * * * * * PMCON1 PMCON2 PMDATL PMDATH PMADRL PMADRH 18.1 Program Memory Read Operation To read a program memory location, the user must write two bytes of the address to the PMADRH and PMADRL registers, then set control bit RD (PMCON1<0>). Once the read control bit is set, the Program Memory Read (PMR) controller uses the two instruction cycles to read the data. This causes the two instructions immediately following the `BSF PMCON1, RD' instruction to be ignored. The data is available in the third cycle, following the set of the RD bit, in the PMDATH and PMDATL registers. PMDATL and PMDATH registers will hold this value until another read is executed. See Example 18-1 and Figure 18-1 for more information. Note: When interfacing the program memory block, the PMDATL and PMDATH registers form a two byte word which holds the 14-bit program data for reading, and the PMADRL and PMADRH registers form a two byte word which holds the 13-bit address of the program Flash location being accessed. These devices have 2K to 4K words of program memory with an address range from 0000h to 0FFFh. Interrupts must be disabled during the time from setting PMCON1<0> (RD) to the third instruction thereafter. Devices without a full map of memory will shadow accesses to unused blocks back to the implemented memory. EXAMPLE 18-1: FLASH PROGRAM MEMORY READ * This code block will read 1 word of program * memory at the memory address: PROG_ADDR_HI: PROG_ADDR_LO * data will be returned in the variables; * PROG_DATA_HI, PROG_DATA_LO BANKSEL MOVLW MOVWF MOVLW MOVWL PMADRL PROG_ADDR_LO PMADRL PROG_ADDR_HI PMADRH ; Select Bank 2 ; ; Store LSB of address ; ; Store MSB of address BANKSEL BCF BSF NOP NOP BSF PMCON1 INTCON,GIE PMCON1,RD INTCON,GIE ; ; ; ; ; ; Select Bank 3 Disable interrupts Initiate read Ignored (Figure 18-1) Ignored (Figure 18-1) Restore interrupts BANKSEL MOVF MOVWF MOVF MOVWF PMDATL PMDATL,W PROG_DATA_LO PMDATH,W PROG_DATA_HI ; ; ; ; ; Select Bank 2 Get LSB of word Store in user location Get MSB of word Store in user location 2010-2013 Microchip Technology Inc. DS40001430E-page 159 PIC16(L)F720/721 FIGURE 18-1: Q1 Flash ADDR FLASH PROGRAM MEMORY READ CYCLE EXECUTION - NORMAL MODE Q2 Q3 Q4 PC Flash DATA Q1 Q2 Q4 Q1 Q2 Q3 Q4 Q1 Q2 PMADRH, PMADRL PC + 1 INSTR (PC) INSTR (PC - 1) Executed here Q3 INSTR (PC + 1) BSF PMCON1, RD Executed here Q3 Q1 Q2 Q3 Q4 PC + 4 PC+3 PMDATH, PMDATL Forced NOP Executed here Q4 INSTR (PC + 3) Forced NOP Executed here Q1 Q2 Q3 Q4 PC + 5 INSTR (PC + 4) INSTR (PC + 3) Executed here INSTR (PC + 4) Executed here RD bit PMDATH PMDATL Register Force NOP Stop PC 18.2 Code Protection When the device is code-protected, the CPU may continue to read and write the Flash program memory. Depending on the settings of the Flash program memory enable (WRT<1:0>) bits, the device may or may not be able to write certain blocks of the program memory. However, reads of the program memory are allowed. When the Flash program memory Code Protection (CP) bit in the Configuration Word register is enabled, the program memory is code-protected, and the device programmer (ICSPTM) cannot access data or program memory. Note: 18.3 Code-protect does not affect the CPU from performing a read operation on the program memory. For more information, refer to Section 8.2 "Code Protection". 18.4 PMCON1 and PMCON2 Registers PMCON1 is the control register for the data program memory accesses. Control bits RD and WR initiate read and write, respectively. These bits cannot be cleared, but only set in software. They are cleared in hardware at the completion of the read or write operation. The inability to clear the WR bit in software prevents the accidental premature termination of a write operation. Setting the control bit WR initiates a write operation. For program memory writes, WR initiates a write cycle if FREE = 0 and an erase cycle if FREE = 1. The WREN bit, when set, will allow a write operation. On power-up, the WREN bit is clear. PMCON2 is not a physical register. Reading PMCON2 will read all `0's. The PMCON2 register is used exclusively in the Flash memory write sequence. PMADRH and PMADRL Registers The PMADRH:PMADRL register pair can address up to a maximum of 4K words of program Flash. The Most Significant Byte (MSB) of the address is written to the PMADRH register and the Least Significant Byte (LSB) is written to the PMADRL register. DS40001430E-page 160 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 18.5 Writing to Flash Program Memory A word of the Flash program memory may only be written to if the word is in an unprotected segment of memory. Flash program memory may only be written to if the destination address is in a segment of memory that is not write-protected, as defined in bits WRT<1:0> of the Configuration Word Register 2. Flash program memory must be written in 32-word rows. See Figure 18-2 for more details. A row consists of 32 words with sequential addresses, with a lower boundary defined by an address, where PMADR<4:0>= 00000. All row writes to program memory are done as 32-word erase and one to 32-word write operations. The write operation is edge-aligned. Crossing boundaries is not recommended, as the operation will only affect the new boundary, wrapping the data values at the same time. Once the write control bit is set, the Program Memory (PM) controller will immediately write the data. Program execution is stalled while the write is in progress. To erase a program memory row, the address of the row to erase must be loaded into the PMADRH:PMADRL register pair. A row consists of 32 words so, when selecting a row, PMADR<4:0> are ignored. After the Address has been set up, then the following sequence of events must be executed: 1. 2. 3. Set the WREN and FREE control bits of the PMCON1 register. Write 55h, then AAh, to PMCON2 (Flash programming sequence). Set the WR control bit of the PMCON1 register. To write program data, it must first be loaded into the buffer latches (see Figure 18-2). This is accomplished by first writing the destination address to PMADRL and PMADRH and then writing the data to PMDATA and PMDATH. After the address and data have been set up, then the following sequence of events must be executed: 1. 2. 3. Set the WREN control bit of the PMCON1 register. Write 55h, then AAh, to PMCON2 (Flash programming sequence). Set the WR control bit of the PMCON1 register. All 32 buffer register locations should be written to with correct data. If less than 32 words are being written to in the block of 32 words, then a read from the program memory location(s) not being written to must be performed. This takes the data from the program location(s) not being written and loads it into the PMDATL and PMDATH registers. Then, the sequence of events to transfer data to the buffer registers must be executed. 2010-2013 Microchip Technology Inc. When the LWLO bit is `1', the write sequence will only load the buffer register and will not actually initiate the write to program Flash: 1. 2. 3. Set the WREN and LWLO bits of the PMCON1 register. Write 55h, then AAh, to PMCON2 (Flash programming unlock sequence). Set control bit WR of the PMCON1 register to begin the write operation. Note: Self-write execution to Flash memory cannot be done while running in low power PFM and Voltage Regulator modes. Therefore, executing a self-write will put the PFM and voltage regulator into High Power mode for the duration of the sequence. To transfer data from the buffer registers to the program memory, the last word to be written should be written to the PMDATH:PMDATL register pair. Then, the following sequence of events must be executed: 1. 2. 3. 4. Clear the LWLO bit of the PMCON1 Register. Write 55h, then AAh, to PMCON2 (Flash programming sequence). Set control bit WR of the PMCON1 register to begin the write operation. Two NOP must follow the setting of the WR bit. This is necessary to provide time for the address and to be provided to the program Flash memory to be put in the write latches. Note: An ICD break that occurs during the 55h AAh - Set WR bit sequence will interrupt the timing of the sequence and prevent the unlock sequence from occurring. In this case, no write will be initiated, as there was no operation to complete. No automatic erase occurs upon the initiation of the write; if the program Flash needs to be erased before writing, the row (32 words) must be previously erased. After the "BSF PMCON1, WR" instruction, the processor requires two cycles to set up the erase/write operation. The user must place two NOP instructions after the WR bit is set. These two instructions will also be forced in hardware to NOP, but if an ICD break occurs at this point, the forcing to NOP will be lost. DS40001430E-page 161 PIC16(L)F720/721 Since data is being written to buffer registers, the writing of the first 31 words of the block appears to occur immediately. The processor will halt internal operations for the typical 2ms, only during the cycle in which the erase takes place (i.e., the last word of the 32-word block erase). This is not Sleep mode as the clocks and peripherals will continue to run. After the 32word write cycle, the processor will resume operation with the third instruction after the PMCON1 write instruction. FIGURE 18-2: BLOCK OF 32 WRITES TO FLASH PROGRAM MEMORY 7 5 PMDATH 14 PMADRL<4:0> = 00000 PMADRL<4:0> = 00001 Buffer Register 0 0 7 PMDATL 6 8 14 14 PMADRL<4:0> = 00010 Buffer Register 14 PMADRL<4:0> = 11111 Buffer Register Buffer Register Program Memory DS40001430E-page 162 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 18.6 Protection Against Spurious Write There are conditions when the device should not write to the program memory. To protect against spurious writes, various mechanisms have been built in. On power-up, WREN is cleared. Also, the Power-up Timer (64 ms duration) prevents program memory writes. The write initiates sequence and the WREN bit helps prevent an accidental write during brown-out, power glitch or software malfunction. REGISTER 18-1: 18.7 Operation During Code-Protect When the device is code-protected, the CPU is able to read and write unscrambled data to the program memory. 18.8 Operation During Write-Protect When the program memory is write-protected, the CPU can read and execute from the program memory. The portions of program memory that are write-protected can be modified by the CPU using the PMCON registers, but the protected program memory cannot be modified using ICSP mode. PMCON1: PROGRAM MEMORY CONTROL 1 REGISTER U-1 R/W-0/0 R/W-0/0 R/W/HC-0/0 U-0 R/W-0/0 R/S/HC-0/0 R/S/HC-0/0 -- CFGS LWLO FREE -- WREN WR RD bit 7 bit 0 Legend: S = Setable bit, cleared in hardware R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as `1' bit 6 CFGS: Flash Program/Configuration Select bit 1 = Accesses Configuration, user ID and device ID registers 0 = Accesses Flash program bit 5 LWLO: Load Write Latches Only bit 1= The next WR command does not initiate a write to the PFM; only the program memory latches are updated. 0= The next WR command writes a value from PMDATH:PMDATL into program memory latches and initiates a write to the PFM of all the data stored in the program memory latches. bit 4 FREE: Program Flash Erase Enable bit 1= Perform an program Flash erase operation on the next WR command (cleared by hardware after completion of erase). 0= Perform a program Flash write operation on the next WR command bit 3 Unimplemented: Read as `0' bit 2 WREN: Program/Erase Enable bit 1 = Allows program/erase cycles 0 = Inhibits programming/erasing of Program Flash bit 1 WR: Write Control bit 1 = Initiates a program Flash program/erase operation. The operation is self-timed and the bit is cleared by hardware once operation is complete. The WR bit can only be set (not cleared) in software. 0 = Program/erase operation to the Flash is complete and inactive bit 0 RD: Read Control bit 1 = Initiates an program memory read (The RD is cleared in hardware; the RD bit can only be set (not cleared) in software). 0 = Does not initiate a program memory read 2010-2013 Microchip Technology Inc. DS40001430E-page 163 PIC16(L)F720/721 REGISTER 18-2: PMDATH: PROGRAM MEMORY DATA HIGH REGISTER U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x -- -- PMD13 PMD12 PMD11 PMD10 PMD9 PMD8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as `0' bit 5-0 PMD<13:8>: The value of the program memory word pointed to by PMADRH and PMADRL after a program memory read command. REGISTER 18-3: PMDATL: PROGRAM MEMORY DATA LOW REGISTER R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x PMD7 PMD6 PMD5 PMD4 PMD3 PMD2 PMD1 PMD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-0 x = Bit is unknown PMD<7:0>: The value of the program memory word pointed to by PMADRH and PMADRL after a program memory read command. REGISTER 18-4: PMADRH: PROGRAM MEMORY ADDRESS HIGH REGISTER U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x -- -- -- PMA12 PMA11 PMA10 PMA9 PMA8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-5 Unimplemented: Read as `0' bit 4-0 PMA<12:8>: Program Memory Read Address bits DS40001430E-page 164 x = Bit is unknown 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 REGISTER 18-5: PMADRL: PROGRAM MEMORY ADDRESS LOW REGISTER R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x PMA7 PMA6 PMA5 PMA4 PMA3 PMA2 PMA1 PMA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-0 TABLE 18-1: Name PMCON1 PMA<7:0>: Program Memory Read Address bits SUMMARY OF REGISTERS ASSOCIATED WITH PROGRAM MEMORY READ Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page -- CFGS LWLO FREE -- WREN WR RD 163 PMCON2 PMADRH Program Memory Control Register 2 (not a physical register) -- -- PMADRL PMDATH PMDATL x = Bit is unknown -- Program Memory Read Address Register High Byte Program Memory Read Address Register Low Byte -- -- -- Program Memory Read Data Register High Byte Program Memory Read Data Register Low Byte 164 165 164 164 Legend: x = unknown, u = unchanged, - = unimplemented, read as `0'. Shaded cells are not used by the program memory read. 2010-2013 Microchip Technology Inc. DS40001430E-page 165 PIC16(L)F720/721 NOTES: DS40001430E-page 166 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 19.0 POWER-DOWN MODE (SLEEP) 19.1 Wake-up from Sleep The Power-down mode is entered by executing a SLEEP instruction. The device can wake-up from Sleep through one of the following events: If the Watchdog Timer is enabled: 1. 2. * * * * * WDT will be cleared but keeps running. PD bit of the STATUS register is cleared. TO bit of the STATUS register is set. Oscillator driver is turned off. I/O ports maintain the status they had before SLEEP was executed (driving high, low or highimpedance). For lowest current consumption in this mode, all I/O pins should be either at VDD or VSS, with no external circuitry drawing current from the I/O pin. I/O pins that are high-impedance inputs should be pulled high or low externally to avoid switching currents caused by floating inputs. The T0CKI input should also be at VDD or VSS for lowest current consumption. The contribution from on-chip pull-ups on PORTB should be considered. The MCLR pin must be at a logic high level when external MCLR is enabled. Note: A Reset generated by a WDT time-out does not drive MCLR pin low. 3. External Reset input on MCLR pin. Watchdog Timer wake-up (if WDT was enabled). Interrupt from RA2/INT pin, PORTB change or a peripheral interrupt. The first event will cause a device Reset. The two latter events are considered a continuation of program execution. The TO and PD bits in the STATUS register can be used to determine the cause of a device Reset. The PD bit, which is set on power-up, is cleared when Sleep is invoked. TO bit is cleared if WDT wake-up occurred. The following peripheral interrupts can wake the device from Sleep: 1. 2. 3. 4. 5. 6. 7. TMR1 interrupt. Timer1 must be operating as an asynchronous counter. USART Receive Interrupt (Synchronous Slave mode only) A/D conversion (when A/D clock source is RC) Interrupt-on-change External interrupt from INT pin Capture event on CCP1 SSP interrupt in SPI or I2C Slave mode Other peripherals cannot generate interrupts since during Sleep, no on-chip clocks are present. When the SLEEP instruction is being executed, the next instruction (PC + 1) is prefetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). Wake-up is regardless of the state of the GIE bit. If the GIE bit is clear (disabled), the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is set (enabled), the device executes the instruction after the SLEEP instruction, then branches to the interrupt address (0004h). In cases where the execution of the instruction following SLEEP is not desirable, the user should have a NOP after the SLEEP instruction. Note: If the global interrupts are disabled (GIE is cleared), but any interrupt source has both its interrupt enable bit and the corresponding interrupt flag bits set, the device will immediately wake-up from Sleep. The SLEEP instruction is completely executed. The WDT is cleared when the device wakes up from Sleep, regardless of the source of wake-up. 2010-2013 Microchip Technology Inc. DS40001430E-page 167 PIC16(L)F720/721 19.2 Wake-up Using Interrupts When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: * If the interrupt occurs before the execution of a SLEEP instruction, the SLEEP instruction will complete as a NOP. Therefore, the WDT and WDT prescaler and postscaler (if enabled) will not be cleared, the TO bit will not be set and the PD bit will not be cleared. * If the interrupt occurs during or after the execution of a SLEEP instruction, the device will immediately wake-up from Sleep. The SLEEP instruction will be completely executed before the wake-up. Therefore, the WDT and WDT prescaler and postscaler (if enabled) will be cleared, the TO bit will be set and the PD bit will be cleared. FIGURE 19-1: Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. To ensure that the WDT is cleared, a CLRWDT instruction should be executed before a SLEEP instruction. WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Oscillator CLKOUT(2) INT pin INTF flag (INTCON reg.) Interrupt Latency (1) GIE bit (INTCON reg.) Processor in Sleep Instruction Flow PC Instruction Fetched Instruction Executed Note 1: 2: PC Inst(PC) = Sleep Inst(PC - 1) PC + 1 PC + 2 PC + 2 Inst(PC + 1) Inst(PC + 2) Sleep Inst(PC + 1) Dummy Cycle 0004h 0005h Inst(0004h) Inst(0005h) Dummy Cycle Inst(0004h) GIE = 1 assumed. In this case after wake-up, the processor jumps to 0004h. If GIE = 0, execution will continue in-line. CLKOUT is not available in EC Oscillator mode, but shown here for timing reference. TABLE 19-1: SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE Name Bit 7 Bit 6 IOCB IOCB7 GIE PIE1 PIR1 INTCON PC + 2 Bit 5 Bit 4 Bit 3 Bit 2 IOCB6 IOCB5 IOCB4 -- -- PEIE TMR0IE INTE RABIE TMR0IF TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF Bit 0 Register on Page -- -- 56 INTF RABIF 38 TMR2IE TMR1IE 39 TMR2IF TMR1IF 40 Bit 1 Legend: x = unknown, u = unchanged, - = unimplemented, read as `0'. Shaded cells are not used in Power-Down mode. DS40001430E-page 168 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 20.0 IN-CIRCUIT SERIAL PROGRAMMINGTM (ICSPTM) The device is placed into Program/Verify mode by holding the ICSPCLK and ICSPDAT pins low then raising the voltage on MCLR/VPP from 0V to VPP. In Program/Verify mode the program memory, user IDs and the Configuration Words are programmed through serial communications. The ICSPDAT pin is a bidirectional I/O used for transferring the serial data and the ISCPCLK pin is the clock input. For more information on ICSPTM refer to the "PIC16F72x/PIC16LF72x Programming Specification" (DS41332). ICSPTM programming allows customers to manufacture circuit boards with unprogrammed devices. Programming can be done after the assembly process, allowing the device to be programmed with the most recent firmware or a custom firmware. Five pins are needed for ICSPTM programming: * ICSPCLK * ICSPDAT * MCLR/VPP * VDD * VSS FIGURE 20-1: TYPICAL CONNECTION FOR ICSPTM PROGRAMMING External Programming Signals VDD Device to be Programmed VDD VDD 10k VPP MCLR/VPP GND VSS Data ICSPDAT Clock ICSPCLK * * * To Normal Connections * Isolation devices (as required). 2010-2013 Microchip Technology Inc. DS40001430E-page 169 PIC16(L)F720/721 NOTES: DS40001430E-page 170 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 21.0 INSTRUCTION SET SUMMARY The PIC16(L)F720/721 instruction set is highly orthogonal and is comprised of three basic categories: * Byte-oriented operations * Bit-oriented operations * Literal and control operations TABLE 21-1: OPCODE FIELD DESCRIPTIONS Field Description Register file address (0x00 to 0x7F) f W Working register (accumulator) b Bit address within an 8-bit file register k Literal field, constant data or label x Table 21-2 lists the instructions recognized by the MPASMTM assembler. Don't care location (= 0 or 1). The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. d For byte-oriented instructions, `f' represents a file register designator and `d' represents a destination designator. The file register designator specifies which file register is to be used by the instruction. Destination select; d = 0: store result in W, d = 1: store result in file register f. Default is d = 1. PC Program Counter TO Time-out bit Each PIC16 instruction is a 14-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. The formats for each of the categories is presented in Figure 21-1, while the various opcode fields are summarized in Table 21-1. The destination designator specifies where the result of the operation is to be placed. If `d' is zero, the result is placed in the W register. If `d' is one, the result is placed in the file register specified in the instruction. For bit-oriented instructions, `b' represents a bit field designator, which selects the bit affected by the operation, while `f' represents the address of the file in which the bit is located. For literal and control operations, `k' represents an 8bit or 11-bit constant, or literal value. One instruction cycle consists of four oscillator periods; for an oscillator frequency of 4 MHz, this gives a nominal instruction execution time of 1 s. All instructions are executed within a single instruction cycle, unless a conditional test is true, or the program counter is changed as a result of an instruction. When this occurs, the execution takes two instruction cycles, with the second cycle executed as a NOP. All instruction examples use the format `0xhh' to represent a hexadecimal number, where `h' signifies a hexadecimal digit. 21.1 Read-Modify-Write Operations Any instruction that specifies a file register as part of the instruction performs a Read-Modify-Write (R-M-W) operation. The register is read, the data is modified, and the result is stored according to either the instruction, or the destination designator `d'. A read operation is performed on a register even if the instruction writes to that register. For example, a CLRF PORTB instruction will read PORTB, clear all the data bits, then write the result back to PORTB. This example would have the unintended consequence of clearing the condition that set the RABIF flag. 2010-2013 Microchip Technology Inc. Carry bit C DC Digit carry bit Zero bit Z PD Power-down bit FIGURE 21-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 13 8 7 6 OPCODE d f (FILE #) 0 d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 7 6 OPCODE b (BIT #) f (FILE #) 0 b = 3-bit bit address f = 7-bit file register address Literal and control operations General 13 8 7 0 OPCODE k (literal) k = 8-bit immediate value CALL and GOTO instructions only 13 11 OPCODE 10 0 k (literal) k = 11-bit immediate value DS40001430E-page 171 PIC16(L)F720/721 TABLE 21-2: PIC16(L)F720/721 INSTRUCTION SET Mnemonic, Operands Description Cycles 14-Bit Opcode MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f, d f, d f - f, d f, d f, d f, d f, d f, d f, d f - f, d f, d f, d f, d f, d Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W to f No Operation Rotate Left f through Carry Rotate Right f through Carry Subtract W from f Swap nibbles in f Exclusive OR W with f BCF BSF BTFSC BTFSS f, b f, b f, b f, b Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set 1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 dfff dfff lfff 0xxx dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff ffff ffff ffff xxxx ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk 0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110 C, DC, Z Z Z Z Z Z Z Z Z C C C, DC, Z Z 1, 2 1, 2 2 1, 2 1, 2 1, 2, 3 1, 2 1, 2, 3 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 BIT-ORIENTED FILE REGISTER OPERATIONS 1 1 1 (2) 1 (2) 01 01 01 01 1, 2 1, 2 3 3 LITERAL AND CONTROL OPERATIONS ADDLW ANDLW CALL CLRWDT GOTO IORLW MOVLW RETFIE RETLW RETURN SLEEP SUBLW XORLW Note 1: 2: 3: k k k - k k k - k - - k k Add literal and W AND literal with W Call Subroutine Clear Watchdog Timer Go to address Inclusive OR literal with W Move literal to W Return from interrupt Return with literal in W Return from Subroutine Go into Standby mode Subtract W from literal Exclusive OR literal with W 1 1 2 1 2 1 1 2 2 2 1 1 1 11 11 10 00 10 11 11 00 11 00 00 11 11 C, DC, Z Z TO, PD Z TO, PD C, DC, Z Z When an I/O register is modified as a function of itself (e.g., MOVF PORTA, 1), the value used will be that value present on the pins themselves. For example, if the data latch is `1' for a pin configured as input and is driven low by an external device, the data will be written back with a `0'. If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if assigned to the Timer0 module. If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. DS40001430E-page 172 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 21.2 Instruction Descriptions ADDLW Add literal and W Syntax: [ label ] ADDLW Operands: 0 k 255 Operation: (W) + k (W) Status Affected: C, DC, Z Description: The contents of the W register are added to the eight-bit literal `k' and the result is placed in the W register. k BCF Bit Clear f Syntax: [ label ] BCF Operands: 0 f 127 0b7 Operation: 0 (f<b>) Status Affected: None Description: Bit `b' in register `f' is cleared. BSF Bit Set f Syntax: [ label ] BSF f,b ADDWF Add W and f Syntax: [ label ] ADDWF Operands: 0 f 127 d 0,1 Operands: 0 f 127 0b7 Operation: (W) + (f) (destination) Operation: 1 (f<b>) Status Affected: C, DC, Z Status Affected: None Description: Add the contents of the W register with register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'. Description: Bit `b' in register `f' is set. ANDLW AND literal with W BTFSC Bit Test f, Skip if Clear Syntax: [ label ] ANDLW Syntax: [ label ] BTFSC f,b Operands: 0 k 255 Operands: Operation: (W) .AND. (k) (W) 0 f 127 0b7 Status Affected: Z Operation: skip if (f<b>) = 0 Description: The contents of W register are AND'ed with the eight-bit literal `k'. The result is placed in the W register. Status Affected: None Description: ANDWF AND W with f If bit `b' in register `f' is `1', the next instruction is executed. If bit `b' in register `f' is `0' the next instruction is discarded and a NOP is executed instead, making this a 2-cycle instruction. f,d k Syntax: [ label ] ANDWF Operands: 0 f 127 d 0,1 Operation: (W) .AND. (f) (destination) f,d Status Affected: Z Description: AND the W register with register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'. 2010-2013 Microchip Technology Inc. f,b DS40001430E-page 173 PIC16(L)F720/721 BTFSS Bit Test f, Skip if Set CLRWDT Clear Watchdog Timer Syntax: [ label ] BTFSS f,b Syntax: [ label ] CLRWDT Operands: 0 f 127 0b<7 Operands: None Operation: 00h WDT 0 WDT prescaler, 1 TO 1 PD Status Affected: TO, PD Description: CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler of the WDT. Status bits TO and PD are set. COMF Complement f Syntax: [ label ] COMF Operands: 0 f 127 d [0,1] Operation: skip if (f<b>) = 1 Status Affected: None Description: If bit `b' in register `f' is `0', the next instruction is executed. If bit `b' is `1', then the next instruction is discarded and a NOP is executed instead, making this a 2-cycle instruction. CALL Call Subroutine Syntax: [ label ] CALL Operands: 0 k 2047 Operation: (PC)+ 1 TOS, k PC<10:0>, (PCLATH<4:3>) PC<12:11> k f,d Operation: (f) (destination) Status Affected: Z Description: The contents of register `f' are complemented. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f'. DECF Decrement f Syntax: [ label ] DECF f,d Status Affected: None Description: Call Subroutine. First, return address (PC + 1) is pushed onto the stack. The eleven-bit immediate address is loaded into PC bits <10:0>. The upper bits of the PC are loaded from PCLATH. CALL is a two-cycle instruction. CLRF Clear f Syntax: [ label ] CLRF Operands: 0 f 127 Operands: Operation: 00h (f) 1Z 0 f 127 d [0,1] Operation: (f) - 1 (destination) Status Affected: Z Status Affected: Z Description: The contents of register `f' are cleared and the Z bit is set. Description: Decrement register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'. CLRW Clear W Syntax: [ label ] CLRW f Operands: None Operation: 00h (W) 1Z Status Affected: Z Description: W register is cleared. Zero bit (Z) is set. DS40001430E-page 174 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0 Syntax: [ label ] DECFSZ f,d Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 f 127 d [0,1] Operation: (f) - 1 (destination); skip if result = 0 Operation: (f) + 1 (destination), skip if result = 0 Status Affected: None Status Affected: None Description: The contents of register `f' are decremented. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'. If the result is `1', the next instruction is executed. If the result is `0', then a NOP is executed instead, making it a 2-cycle instruction. Description: The contents of register `f' are incremented. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'. If the result is `1', the next instruction is executed. If the result is `0', a NOP is executed instead, making it a 2-cycle instruction. GOTO Unconditional Branch IORLW Syntax: [ label ] Syntax: [ label ] Operands: 0 k 2047 Operands: 0 k 255 Operation: k PC<10:0> PCLATH<4:3> PC<12:11> Operation: (W) .OR. k (W) Status Affected: Z Status Affected: None Description: Description: GOTO is an unconditional branch. The eleven-bit immediate value is loaded into PC bits <10:0>. The upper bits of PC are loaded from PCLATH<4:3>. GOTO is a two-cycle instruction. The contents of the W register are OR'ed with the eight-bit literal `k'. The result is placed in the W register. INCF Increment f IORWF Inclusive OR W with f Syntax: [ label ] Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 f 127 d [0,1] Operation: (f) + 1 (destination) Operation: (W) .OR. (f) (destination) Status Affected: Z Status Affected: Z Description: The contents of register `f' are incremented. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'. Description: Inclusive OR the W register with register `f'. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'. GOTO k INCF f,d 2010-2013 Microchip Technology Inc. INCFSZ f,d Inclusive OR literal with W IORLW k IORWF f,d DS40001430E-page 175 PIC16(L)F720/721 MOVWF Move W to f Syntax: [ label ] MOVF Move f Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 f 127 Operation: (W) (f) Operation: (f) (dest) Status Affected: None Status Affected: Z Description: Description: The contents of register f is moved to a destination dependent upon the status of d. If d = 0, destination is W register. If d = 1, the destination is file register f itself. d = 1 is useful to test a file register since status flag Z is affected. Move data from W register to register `f'. Words: 1 Cycles: 1 Words: 1 Cycles: 1 Example: MOVF f,d MOVF Example: MOVW F MOVWF OPTION Before Instruction OPTION = W = After Instruction OPTION = W = FSR, 0 f 0xFF 0x4F 0x4F 0x4F After Instruction W = value in FSR register Z = 1 MOVLW Move literal to W NOP No Operation Syntax: [ label ] Syntax: [ label ] Operands: 0 k 255 Operands: None Operation: k (W) Operation: No operation Status Affected: None Status Affected: None Description: The eight-bit literal `k' is loaded into W register. The "don't cares" will assemble as `0's. Description: No operation. Words: 1 Cycles: 1 Words: 1 Cycles: 1 Example: MOVLW k Example: MOVLW NOP 0x5A After Instruction W = DS40001430E-page 176 NOP 0x5A 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 RETFIE Return from Interrupt RETLW Return with literal in W Syntax: [ label ] Syntax: [ label ] Operands: None Operands: 0 k 255 Operation: TOS PC, 1 GIE Operation: k (W); TOS PC Status Affected: None Status Affected: None Description: Return from Interrupt. Stack is POPed and Top-of-Stack (TOS) is loaded in the PC. Interrupts are enabled by setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a two-cycle instruction. Description: The W register is loaded with the eight bit literal `k'. The program counter is loaded from the top of the stack (the return address). This is a two-cycle instruction. Words: 1 Cycles: 2 Example: RETFIE Words: 1 Cycles: 2 Example: RETFIE After Interrupt PC = GIE = TABLE TOS 1 RETLW k CALL TABLE;W contains table ;offset value * ;W now has table value * * ADDWF PC ;W = offset RETLW k1 ;Begin table RETLW k2 ; * * * RETLW kn ; End of table Before Instruction W = 0x07 After Instruction W = value of k8 RETURN 2010-2013 Microchip Technology Inc. Return from Subroutine Syntax: [ label ] Operands: None RETURN Operation: TOS PC Status Affected: None Description: Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a two-cycle instruction. DS40001430E-page 177 PIC16(L)F720/721 RLF Rotate Left f through Carry SLEEP Enter Sleep mode Syntax: [ label ] Syntax: [ label ] SLEEP Operands: 0 f 127 d [0,1] Operands: None Operation: Operation: See description below Status Affected: C Description: The contents of register `f' are rotated one bit to the left through the Carry flag. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is stored back in register `f'. 00h WDT, 0 WDT prescaler, 1 TO, 0 PD RLF f,d C Words: 1 Cycles: 1 Example: Status Affected: TO, PD Description: The power-down Status bit, PD is cleared. Time-out Status bit, TO is set. Watchdog Timer and its prescaler are cleared. The processor is put into Sleep mode with the oscillator stopped. Register f RLF REG1,0 Before Instruction REG1 C = = 1110 0110 0 = = = 1110 0110 1100 1100 1 After Instruction REG1 W C RRF Rotate Right f through Carry SUBLW Syntax: [ label ] Syntax: [ label ] SUBLW k Operands: 0 k 255 k - (W) W) RRF f,d Subtract W from literal Operands: 0 f 127 d [0,1] Operation: Operation: See description below Status Affected: C, DC, Z Status Affected: C Description: Description: The contents of register `f' are rotated one bit to the right through the Carry flag. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'. C DS40001430E-page 178 Register f The W register is subtracted (2's complement method) from the eight-bit literal `k'. The result is placed in the W register. C=0 Wk C=1 Wk DC = 0 W<3:0> k<3:0> DC = 1 W<3:0> k<3:0> 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 SUBWF Subtract W from f XORLW Exclusive OR literal with W Syntax: [ label ] SUBWF f,d Syntax: [ label ] XORLW k Operands: 0 f 127 d [0,1] Operands: 0 k 255 (f) - (W) destination) Operation: Operation: (W) .XOR. k W) Status Affected: C, DC, Z Description: SWAPF Status Affected: Z Description: The contents of the W register are XOR'ed with the eight-bit literal `k'. The result is placed in the W register. Subtract (2's complement method) W register from register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f. C=0 Wf C=1 Wf DC = 0 W<3:0> f<3:0> DC = 1 W<3:0> f<3:0> Swap Nibbles in f XORWF Exclusive OR W with f Syntax: [ label ] SWAPF f,d Syntax: [ label ] XORWF Operands: 0 f 127 d [0,1] Operands: 0 f 127 d [0,1] Operation: (f<3:0>) (destination<7:4>), (f<7:4>) (destination<3:0>) Operation: (W) .XOR. (f) destination) Status Affected: Z Status Affected: None Description: Description: The upper and lower nibbles of register `f' are exchanged. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed in register `f'. Exclusive OR the contents of the W register with register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'. 2010-2013 Microchip Technology Inc. f,d DS40001430E-page 179 PIC16(L)F720/721 NOTES: DS40001430E-page 180 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 22.0 DEVELOPMENT SUPPORT The PIC(R) microcontrollers and dsPIC(R) digital signal controllers are supported with a full range of software and hardware development tools: * Integrated Development Environment - MPLAB(R) IDE Software * Compilers/Assemblers/Linkers - MPLAB C Compiler for Various Device Families - HI-TECH C(R) for Various Device Families - MPASMTM Assembler - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB Assembler/Linker/Librarian for Various Device Families * Simulators - MPLAB SIM Software Simulator * Emulators - MPLAB REAL ICETM In-Circuit Emulator * In-Circuit Debuggers - MPLAB ICD 3 - PICkitTM 3 Debug Express * Device Programmers - PICkitTM 2 Programmer - MPLAB PM3 Device Programmer * Low-Cost Demonstration/Development Boards, Evaluation Kits, and Starter Kits 22.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market. The MPLAB IDE is a Windows(R) operating system-based application that contains: * A single graphical interface to all debugging tools - Simulator - Programmer (sold separately) - In-Circuit Emulator (sold separately) - In-Circuit Debugger (sold separately) * A full-featured editor with color-coded context * A multiple project manager * Customizable data windows with direct edit of contents * High-level source code debugging * Mouse over variable inspection * Drag and drop variables from source to watch windows * Extensive on-line help * Integration of select third party tools, such as IAR C Compilers The MPLAB IDE allows you to: * Edit your source files (either C or assembly) * One-touch compile or assemble, and download to emulator and simulator tools (automatically updates all project information) * Debug using: - Source files (C or assembly) - Mixed C and assembly - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power. 2010-2013 Microchip Technology Inc. DS40001430E-page 181 PIC16(L)F720/721 22.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip's PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. 22.3 HI-TECH C for Various Device Families The HI-TECH C Compiler code development systems are complete ANSI C compilers for Microchip's PIC family of microcontrollers and the dsPIC family of digital signal controllers. These compilers provide powerful integration capabilities, omniscient code generation and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. The compilers include a macro assembler, linker, preprocessor, and one-step driver, and can run on multiple platforms. 22.4 MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for PIC10/12/16/18 MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel(R) standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging. The MPASM Assembler features include: 22.5 MPLINK Object Linker/ MPLIB Object Librarian The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: * Efficient linking of single libraries instead of many smaller files * Enhanced code maintainability by grouping related modules together * Flexible creation of libraries with easy module listing, replacement, deletion and extraction 22.6 MPLAB Assembler, Linker and Librarian for Various Device Families MPLAB Assembler produces relocatable machine code from symbolic assembly language for PIC24, PIC32 and dsPIC devices. MPLAB C Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: * * * * * * Support for the entire device instruction set Support for fixed-point and floating-point data Command line interface Rich directive set Flexible macro language MPLAB IDE compatibility * Integration into MPLAB IDE projects * User-defined macros to streamline assembly code * Conditional assembly for multi-purpose source files * Directives that allow complete control over the assembly process DS40001430E-page 182 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 22.7 MPLAB SIM Software Simulator The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC(R) DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, most peripherals and internal registers. The MPLAB SIM Software Simulator fully supports symbolic debugging using the MPLAB C Compilers, and the MPASM and MPLAB Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool. 22.8 MPLAB REAL ICE In-Circuit Emulator System MPLAB REAL ICE In-Circuit Emulator System is Microchip's next generation high-speed emulator for Microchip Flash DSC and MCU devices. It debugs and programs PIC(R) Flash MCUs and dsPIC(R) Flash DSCs with the easy-to-use, powerful graphical user interface of the MPLAB Integrated Development Environment (IDE), included with each kit. The emulator is connected to the design engineer's PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with incircuit debugger systems (RJ11) or with the new highspeed, noise tolerant, Low-Voltage Differential Signal (LVDS) interconnection (CAT5). The emulator is field upgradable through future firmware downloads in MPLAB IDE. In upcoming releases of MPLAB IDE, new devices will be supported, and new features will be added. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. 2010-2013 Microchip Technology Inc. 22.9 MPLAB ICD 3 In-Circuit Debugger System MPLAB ICD 3 In-Circuit Debugger System is Microchip's most cost effective high-speed hardware debugger/programmer for Microchip Flash Digital Signal Controller (DSC) and microcontroller (MCU) devices. It debugs and programs PIC(R) Flash microcontrollers and dsPIC(R) DSCs with the powerful, yet easyto-use graphical user interface of MPLAB Integrated Development Environment (IDE). The MPLAB ICD 3 In-Circuit Debugger probe is connected to the design engineer's PC using a high-speed USB 2.0 interface and is connected to the target with a connector compatible with the MPLAB ICD 2 or MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3 supports all MPLAB ICD 2 headers. 22.10 PICkit 3 In-Circuit Debugger/ Programmer and PICkit 3 Debug Express The MPLAB PICkit 3 allows debugging and programming of PIC(R) and dsPIC(R) Flash microcontrollers at a most affordable price point using the powerful graphical user interface of the MPLAB Integrated Development Environment (IDE). The MPLAB PICkit 3 is connected to the design engineer's PC using a full speed USB interface and can be connected to the target via an Microchip debug (RJ-11) connector (compatible with MPLAB ICD 3 and MPLAB REAL ICE). The connector uses two device I/O pins and the reset line to implement in-circuit debugging and In-Circuit Serial ProgrammingTM. The PICkit 3 Debug Express include the PICkit 3, demo board and microcontroller, hookup cables and CDROM with user's guide, lessons, tutorial, compiler and MPLAB IDE software. DS40001430E-page 183 PIC16(L)F720/721 22.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express 22.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits The PICkitTM 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip's Flash families of microcontrollers. The full featured Windows(R) programming interface supports baseline (PIC10F, PIC12F5xx, PIC16F5xx), midrange (PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30, dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit microcontrollers, and many Microchip Serial EEPROM products. With Microchip's powerful MPLAB Integrated Development Environment (IDE) the PICkitTM 2 enables in-circuit debugging on most PIC(R) microcontrollers. In-Circuit-Debugging runs, halts and single steps the program while the PIC microcontroller is embedded in the application. When halted at a breakpoint, the file registers can be examined and modified. A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. The PICkit 2 Debug Express include the PICkit 2, demo board and microcontroller, hookup cables and CDROM with user's guide, lessons, tutorial, compiler and MPLAB IDE software. 22.12 MPLAB PM3 Device Programmer The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages and a modular, detachable socket assembly to support various package types. The ICSPTM cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an MMC card for file storage and data applications. DS40001430E-page 184 The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory. The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEMTM and dsPICDEMTM demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ(R) security ICs, CAN, IrDA(R), PowerSmart battery management, SEEVAL(R) evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Also available are starter kits that contain everything needed to experience the specified device. This usually includes a single application and debug capability, all on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 23.0 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings() Ambient temperature under bias....................................................................................................... -40C to +125C Storage temperature ........................................................................................................................ -65C to +150C Voltage on VDD with respect to VSS, PIC16F720/721 ........................................................................ -0.3V to +6.5V Voltage on VDD with respect to VSS, PIC16LF720/721 ...................................................................... -0.3V to +4.0V Voltage on MCLR with respect to VSS ................................................................................................. -0.3V to +9.0V Voltage on all other pins with respect to VSS ........................................................................... -0.3V to (VDD + 0.3V) Total power dissipation(1) ............................................................................................................................... 800 mW Maximum current out of VSS pin ...................................................................................................................... 95 mA Maximum current into VDD pin ......................................................................................................................... 70 mA Clamp current, IK (VPIN < 0 or VPIN > VDD)20 mA Maximum output current sunk by any I/O pin.................................................................................................... 25 mA Maximum output current sourced by any I/O pin .............................................................................................. 25 mA Maximum current sunk by all ports, -40C TA +85C for industrial............................................................ 200 mA Maximum current sunk by all ports, -40C TA +125C for extended ........................................................... 90 mA Maximum current sourced by all ports, 40C TA +85C for industrial....................................................... 140 mA Maximum current sourced by all ports, -40C TA +125C for extended ...................................................... 65 mA Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD - IOH} + {(VDD - VOH) x IOH} + (VOl x IOL). NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for extended periods may affect device reliability. 2010-2013 Microchip Technology Inc. DS40001430E-page 185 PIC16(L)F720/721 23.1 DC Characteristics: PIC16(L)F720/721-I/E (Industrial, Extended) PIC16LF720/721 Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended PIC16F720/721 Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Param. No. D001 Sym. VDD Characteristic Min. Typ Max. Units Conditions Supply Voltage PIC16LF720/721 1.8 -- 3.6 V FOSC 16 MHz: HFINTOSC, EC D001 PIC16F720/721 1.8 -- 5.5 V FOSC 16 MHz: HFINTOSC, EC D002* Voltage(1) PIC16LF720/721 1.5 -- -- V Device in Sleep mode PIC16F720/721 1.7 -- -- V Device in Sleep mode -- 1.6 -- V V VDR RAM Data Retention D002* VPOR* Power-on Reset Release Voltage VPORR* Power-on Reset Rearm Voltage PIC16LF720/721 -- 0.9 -- PIC16F720/721 -- 1.5 -- V -8 -- 6 % 0.05 -- -- V/ms D003 VFVR Fixed Voltage Reference Voltage, Initial Accuracy D004* SVDD VDD Rise Rate to ensure internal Power-on Reset signal VFVR = 1.024V, VDD 2.5V VFVR = 2.048V, VDD 2.5V VFVR = 4.096V, VDD 4.75V; See Section 3.2 "Power-on Reset (POR)" for details. * These parameters are characterized but not tested. Data in "Typ" column is at 3.3V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data. DS40001430E-page 186 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 FIGURE 23-1: POR AND POR REARM WITH SLOW RISING VDD VDD VPOR VPORR VSS NPOR POR REARM VSS TVLOW(2) Note 1: 2: 3: TPOR(3) When NPOR is low, the device is held in Reset. TPOR 1 s typical. TVLOW 2.7 s typical. 2010-2013 Microchip Technology Inc. DS40001430E-page 187 PIC16(L)F720/721 23.2 DC Characteristics: PIC16(L)F720/721-I/E (Industrial, Extended) PIC16LF720/721 Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended PIC16F720/721 Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Param. No. Device Characteristics Conditions Min. Typ Max. Units -- 100 180 A 1.8 -- 210 270 A 3.0 -- 120 205 A 1.8 -- 220 320 A 3.0 -- 250 410 A 5.0 -- 220 330 A 1.8 -- 420 500 A 3.0 -- 250 430 A 1.8 -- 450 655 A 3.0 VDD Note Supply Current (IDD)(1, 2) D013 D013 D014 D014 -- 500 730 A 5.0 D015 -- 105 203 A 1.8 -- 130 235 A 3.0 D015 -- 120 219 A 1.8 -- 145 284 A 3.0 -- 160 348 A 5.0 D016 D016 D017 D017 Note 1: 2: -- 600 800 A 1.8 -- 1000 1200 A 3.0 -- 610 850 A 1.8 -- 1010 1200 A 3.0 -- 1150 1500 A 5.0 -- 900 1200 A 1.8 -- 1450 1850 A 3.0 -- 910 1200 A 1.8 -- 1460 1900 A 3.0 -- 1700 2100 A 5.0 FOSC = 1 MHz EC mode FOSC = 1 MHz EC mode FOSC = 4 MHz EC mode FOSC = 4 MHz EC mode FOSC = 500 kHz MFINTOSC mode FOSC = 500 kHz MFINTOSC mode FOSC = 8 MHz HFINTOSC mode FOSC = 8 MHz HFINTOSC mode FOSC = 16 MHz HFINTOSC mode FOSC = 16 MHz HFINTOSC mode The test conditions for all IDD measurements in active EC Mode are: CLKIN = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. DS40001430E-page 188 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 23.3 DC Characteristics: PIC16(L)F720/721-I/E (Power-Down) PIC16LF720/721 Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended PIC16F720/721 Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Param. No. Device Characteristics Power-down Base Current D020 D020 D021 D021 D021A D021A Conditions Typ Max. +85C Max. +125C Units -- 0.04 1 8 A -- 0.05 2 9 A 3.0 -- 18 47 55 A 1.8 -- 20 58 72 A 3.0 -- 23 60 84 A 5.0 -- 0.5 4 9 A 1.8 -- 0.8 5 11 A 3.0 -- 20 49 57 A 1.8 -- 22 60 74 A 3.0 5.0 Min. VDD 1.8 -- 25 63 86 A -- 14 29 35 A 1.8 -- 15 31 38 A 3.0 -- 39 77 90 A 1.8 -- 46 98 108 A 3.0 -- 91 160 170 A 5.0 D022 -- -- -- -- A 1.8 -- 7 15 26 A 3.0 D022 -- -- -- -- A 1.8 -- 26 64 78 A 3.0 -- 29 67 91 A 5.0 -- 1.5 4 10 A 1.8 -- 2 5 11 A 3.0 -- 19 48 57 A 1.8 -- 21 59 74 A 3.0 5.0 D027 D027 D027A D027A Note 1: 2: 3: Note (IPD)(2) -- 24 62 87 A -- 250 400 410 A 1.8 -- 260 420 430 A 3.0 -- 280 430 440 A 1.8 -- 300 450 460 A 3.0 -- 320 470 480 A 5.0 Base IPD Base IPD IPD LPWDT on (Note 1) IPD LPWDT on (Note 1) IPD FVR on (Note 1) IPD FVR on (Note 1) IPD BOR on (Note 1) IPD BOR on (Note 1) IPD ADC on (Note 1, Note 3) non-convert IPD ADC on (Note 1, Note 3) non-convert IPD ADC on (Note 1, Note 3) convert IPD ADC on (Note 1, Note 3) convert Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD. A/D oscillator source is FRC. 2010-2013 Microchip Technology Inc. DS40001430E-page 189 PIC16(L)F720/721 23.4 DC Characteristics: PIC16(L)F720/721-I/E DC CHARACTERISTICS Param. No. Sym. VIL Characteristic Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Min. Typ Max. Units Conditions Input Low Voltage I/O PORT: D030 -- -- 0.8 V 4.5V VDD 5.5V -- -- 0.15 VDD V 1.8V VDD 4.5V with Schmitt Trigger buffer -- -- 0.2 VDD V 2.0V VDD 5.5V with I2CTM levels -- -- 0.3 VDD V -- -- 2.0 -- -- V 4.5V VDD 5.5V 0.25 VDD + 0.8 -- -- V 1.8V VDD 4.5V with Schmitt Trigger buffer 0.8 VDD -- -- V 2.0V VDD 5.5V with I2CTM levels 0.7 VDD -- -- V 0.8 VDD -- -- V nA with TTL buffer D030A D031 VIH Input High Voltage I/O ports: D040 with TTL buffer D040A D041 D042 MCLR IIL Input Leakage Current(1) D060 I/O ports -- 5 125 5 1000 nA VSS VPIN VDD, Pin at highimpedance, 85C 125C D061 MCLR(2) -- 50 200 nA VSS VPIN VDD, 85C 25 25 100 140 200 300 A VDD = 3.3V, VPIN = VSS VDD = 5.0V, VPIN = VSS -- -- 0.6 V IOL = 8mA, VDD = 5V IOL = 6mA, VDD = 3.3V IOL = 1.8mA, VDD = 1.8V VDD - 0.7 -- -- V IOH = 3.5mA, VDD = 5V IOH = 3mA, VDD = 3.3V IOH = 1mA, VDD = 1.8V -- -- 50 pF 1k 10k -- E/W VMIN -- -- V IPUR PORTB Weak Pull-up Current D070* VOL D080 Output Low Voltage I/O ports VOH D090 Output High Voltage I/O ports CIO Capacitive Loading Specs on Output Pins EP Program Flash Memory D101A* All I/O pins D130 Cell Endurance D131 D132 Temperature during programming: 10C TA 40C VPR VDD for Read VIHH Voltage on MCLR/VPP during Erase/Program 8.0 -- 9.0 V Temperature during programming: 10C TA 40C VPEW VDD for Write or Row Erase 1.8 1.8 -- -- 5.5 3.6 V V PIC16F720/721 PIC16LF720/721 IPPPGM* Current on MCLR/VPP during Erase/Write -- 1.0 -- mA Temperature during programming: 10C TA 40C IDDPGM* Current on VDD during Erase/ Write -- 5.0 -- mA Temperature during programming: 10C TA 40C * These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Negative current is defined as current sourced by the pin. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. DS40001430E-page 190 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 23.4 DC Characteristics: PIC16(L)F720/721-I/E (Continued) DC CHARACTERISTICS Param. No. Sym. Characteristic Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Min. Typ Max. Units Conditions 2.8 ms Temperature during programming: 10C TA 40C D133 TPEW Erase/Write cycle time -- D134* TRETD Characteristic Retention -- 40 -- Year Provided no other specifications are violated D135 EHEFC High-Endurance Flash Cell 100K -- -- E/W 0C to +60C Lower byte, Last 128 Addresses in Flash memory * These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Negative current is defined as current sourced by the pin. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 2010-2013 Microchip Technology Inc. DS40001430E-page 191 PIC16(L)F720/721 23.5 Thermal Considerations Standard Operating Conditions (unless otherwise stated) Operating temperature-40C TA +125C Param. No. Sym. Characteristic TH01 JA Thermal Resistance Junction to Ambient TH02 JC Thermal Resistance Junction to Case TH03 TH04 TH05 TH06 TJMAX PD Maximum Junction Temperature Power Dissipation PINTERNAL Internal Power Dissipation PI/O I/O Power Dissipation Typ. Units 62.2 75.0 89.3 43.0 27.5 23.1 31.1 5.3 150 -- -- -- C/W C/W C/W C/W C/W C/W C/W C/W C W W W Conditions 20-pin PDIP package 20-pin SOIC package 20-pin SSOP package 20-pin QFN 4x4mm package 20-pin PDIP package 20-pin SOIC package 20-pin SSOP package 20-pin QFN 4x4mm package PD = PINTERNAL + PI/O PINTERNAL = IDD x VDD(1) PI/O = (IOL * VOL) + (IOH * (VDD VOH)) TH07 PDER Derated Power -- W PDER = PDMAX (TJ - TA)/JA(2) Note 1: IDD is current to run the chip alone without driving any load on the output pins. 2: TA = Ambient Temperature; TJ = Junction Temperature DS40001430E-page 192 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 23.6 Timing Parameter Symbology The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings: pp cc CCP1 ck CLKOUT cs CS di SDI do SDO dt Data in io I/O PORT mc MCLR Uppercase letters and their meanings: S F Fall H High I Invalid (High-impedance) L Low FIGURE 23-2: T Time osc rd rw sc ss t0 t1 wr CLKIN RD RD or WR SCK SS T0CKI T1CKI WR P R V Z Period Rise Valid High-impedance LOAD CONDITIONS Load Condition Pin CL VSS Legend: CL = 50 pF for all pins 2010-2013 Microchip Technology Inc. DS40001430E-page 193 PIC16(L)F720/721 23.7 AC Characteristics: PIC16F720/721-I/E PIC16F720/721 VOLTAGE FREQUENCY GRAPH, -40C TA +125C FIGURE 23-3: VDD (V) 5.5 1.8 8 0 16 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. PIC16LF720/721 VOLTAGE FREQUENCY GRAPH, -40C TA +125C VDD (V) FIGURE 23-4: 3.6 1.8 0 8 16 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. DS40001430E-page 194 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 FIGURE 23-5: HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE 125 5% Temperature (C) 85 3% 60 2% 25 0 5% -40 1.8 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) 2010-2013 Microchip Technology Inc. DS40001430E-page 195 PIC16(L)F720/721 FIGURE 23-6: CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 CLKIN OS02 OS03 CLKOUT TABLE 23-1: CLOCK OSCILLATOR TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C Param. No. Sym. Characteristic Min. Typ Max. Units Conditions OS01 FOSC External CLKIN Frequency(1) DC -- 16 MHz EC Oscillator mode OS02 TOSC External CLKIN Period(1) 63 -- ns EC Oscillator mode 250 TCY DC ns TCY = 4/FOSC OS03 TCY Instruction Cycle Time (1) * These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min" values with an external clock applied to CLKIN pin. When an external clock input is used, the "max" cycle time limit is "DC" (no clock) for all devices. DS40001430E-page 196 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 TABLE 23-2: OSCILLATOR PARAMETERS(1) Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param. No. OS08 OS08 OS10* Sym HFOSC MFOSC Characteristic Internal Calibrated HFINTOSC Frequency(2, 3) Internal Calibrated MFINTOSC Frequency(2, 3) TIOSC ST HFINTOSC 16 MHz and MFINTOSC 500 kHz Oscillator Wake-up from Sleep Start-up Time Freq. Tolerance Min. 2% -- 16.0 -- MHz 0C TA +60C, VDD 2.5V 3% -- 16.0 -- MHz +60C TA +85C, VDD 2.5V Typ Max. Units Conditions 5% -- 16.0 -- MHz -40C TA +125C 2% -- 500 -- kHz 0C TA +60C, VDD 2.5V 3% -- 500 -- kHz +60C TA +85C, VDD 2.5V 5% -- 500 -- kHz -40C TA +125C -- -- 5 8 s * These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min" values with an external clock applied to the CLKIN pin. When an external clock input is used, the "max" cycle time limit is "DC" (no clock) for all devices. 2: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 F and 0.01 F values in parallel are recommended. 3: The frequency tolerance of the internal oscillator is 2% from 0-60C and 3% from 60-85C (see Figure 23-5). 2010-2013 Microchip Technology Inc. DS40001430E-page 197 PIC16(L)F720/721 FIGURE 23-7: CLKOUT AND I/O TIMING Cycle Write Fetch Read Execute Q4 Q1 Q2 Q3 FOSC OS12 OS11 OS20 OS21 CLKOUT OS19 OS18 OS16 OS13 OS17 I/O pin (Input) OS14 OS15 I/O pin (Output) New Value Old Value OS18, OS19 TABLE 23-3: CLKOUT AND I/O TIMING PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param. No. OS11* OS12* OS13* Sym. TOSH2CKL Characteristic Min. Typ Max. Units Conditions FOSC to CLKOUT (1) -- -- 70 ns VDD = 3.3-5.0V (1) -- -- 72 ns VDD = 3.3-5.0V -- -- 20 ns TOSH2CKH FOSC to CLKOUT TCKL2IOV CLKOUT to Port out valid(1) CLKOUT(1) OS14* TIOV2CKH Port input valid before TOSC + 200 ns -- -- ns OS15* TOSH2IOV FOSC (Q1 cycle) to Port out valid -- 50 70* ns VDD = 3.3-5.0V OS16* TOSH2IOI FOSC (Q2 cycle) to Port input invalid (I/O in hold time) 50 -- -- ns VDD = 3.3-5.0V OS17* TIOV2OSH Port input valid to FOSC(Q2 cycle) (I/O in setup time) 20 -- -- ns OS18* TIOR Port output rise time -- -- 15 40 32 72 ns VDD = 2.0V VDD = 3.3-5.0V OS19* TIOF Port output fall time -- -- 28 15 55 30 ns VDD = 2.0V VDD = 3.3-5.0V OS20* TINP INT pin input high or low time 25 -- -- ns OS21* TRBP PORTB interrupt-on-change new input level time TCY -- -- ns * These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. Note 1: Measurements are taken in EC mode where CLKOUT output is 4 x TOSC. DS40001430E-page 198 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 FIGURE 23-8: BROWN-OUT RESET TIMING AND CHARACTERISTICS VDD VBOR + VHYST VBOR (Device not in Brown-out Reset) (Device in Brown-out Reset) TBORDC Reset (due to BOR) TPWRT(1) Note 1: The additional delay of TPWRT, prior to releasing Reset, only occurs when the Power-up Timer is enabled (PWRTE = 0). 2010-2013 Microchip Technology Inc. DS40001430E-page 199 PIC16(L)F720/721 TABLE 23-4: RESET, WATCHDOG TIME, POWER-UP TIMER, AND BROWN-OUT RESET PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param. No. Sym. Characteristic Min. Typ Max. Units Conditions 30* TMCL MCLR Pulse Width (low) 2 5 -- -- -- -- s s VDD = 5V, -40C to +85C VDD = 5V(1) 31 TWDT Standard Watchdog Timer Time-out Period (No Prescaler)(2) 10 10 18 18 27 33 ms ms VDD = 3.3V-5V, -40C to +85C VDD = 3.3V-5V(1) 33* TPWRT Power-up Timer Period, PWRTE = 0 40 65 140 ms 34* TIOZ I/O high-impedance from MCLR Low or Watchdog Timer Reset -- -- 2.0 s 35 VBOR Brown-out Reset Voltage 1.80 1.9 2.1 V 36* VHYST Brown-out Reset Hysteresis 0 25 50 mV 37* TBORDC Brown-out Reset DC Response Time 1 3 5 10 s VDD VBOR, -40C to +85C VDD VBOR * These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Voltages above 3.6V require that the regulator be enabled. 2: Design Target. If unable to meet this target, the maximum can be increased, but the minimum cannot be changed. FIGURE 23-9: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 40 41 42 T1CKI 45 46 47 49 TMR0 or TMR1 DS40001430E-page 200 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 TABLE 23-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param. No. Sym. TT0H 40* 41* TT0L Characteristic Min. Typ Max. Units No Prescaler 0.5 TCY + 20 -- -- ns With Prescaler 10 -- -- ns No Prescaler 0.5 TCY + 20 -- -- ns With Prescaler 10 -- -- ns Greater of: 20 or TCY + 40 N -- -- ns Synchronous, No Prescaler 0.5 TCY + 20 -- -- ns Synchronous, with Prescaler 15 -- -- ns T0CKI High Pulse Width T0CKI Low Pulse Width 42* TT0P T0CKI Period 45* TT1H T1CKI High Time Asynchronous 46* TT1L 47* TT1P 49* 30 -- -- ns 0.5 TCY + 20 -- -- ns Synchronous, with Prescaler 15 -- -- ns Asynchronous 30 -- -- ns Synchronous Greater of: 30 or TCY + 40 N -- -- ns Asynchronous 60 -- -- ns 2 TOSC -- 7 TOSC -- T1CKI Synchronous, No Low Time Prescaler T1CKI Input Period TCKEZ Delay from External Clock Edge to TMR1 Timer Increment * Conditions N = prescale value (2, 4, ..., 256) N = prescale value (1, 2, 4, 8) Timers in Sync mode These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 23-10: CAPTURE/COMPARE/PWM TIMINGS (CCP) CCP (Capture mode) CC01 CC02 CC03 Note: Refer to Figure 23-2 for load conditions. 2010-2013 Microchip Technology Inc. DS40001430E-page 201 PIC16(L)F720/721 TABLE 23-6: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP) Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param. No. Sym. CC01* TccL Characteristic CCP Input Low Time CC02* TccH CCP Input High Time CC03* TccP CCP Input Period Min. Max. Units No Prescaler 0.5TCY + 20 -- -- ns With Prescaler 20 -- -- ns No Prescaler 0.5TCY + 20 -- -- ns 20 -- -- ns 3TCY + 40 N -- -- ns With Prescaler * Typ Conditions N = prescale value (1, 4 or 16) These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. TABLE 23-7: PIC16F720/721 A/D CONVERTER (ADC) CHARACTERISTICS Operating Conditions (unless otherwise stated) VDD = 3.0V, TA 25C Param. Sym. No. Characteristic Min. Typ Max. Units Conditions AD01 NR Resolution -- -- 8 bit AD02 EIL Integral Error -- -- 1.7 LSb VDD = 3.0V AD03 EDL Differential Error -- -- 1 LSb No missing codes VDD = 3.0V AD04 EOFF Offset Error -- -- 2.2 LSb VDD = 3.0V AD07 EGN Gain Error -- -- 1.5 LSb VDD = 3.0V AD07 VAIN Full-Scale Range VSS -- VDD V AD08* ZAIN Recommended Impedance of Analog Voltage Source -- -- 10 k * These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. DS40001430E-page 202 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 TABLE 23-8: PIC16F720/721 A/D CONVERSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C Param. No. Sym. Characteristic AD130* TAD A/D Clock Period A/D Internal RC Oscillator Period AD131 TCNV Min. Typ Max. Units 1.0 -- 9.0 S VDD 2.0V(2) 4.0 -- 16.0 S VDD 2.0V(2) 1.0 2.0 6.0 S -- 10.5 -- TAD Set GO/DONE bit to new data in A/D Result register 2 -- S VDD = 3.0V, EC or INTOSC Clock mode(3) (ADRC mode) Conversion Time (not including Acquisition Time)(1) Acquisition Time AD132* TACQ Conditions * These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The ADRES register may be read on the following TCY cycle. 2: Setting of 16.0 s TAD not recommended for temperature > 85C. 3: If ADRC mode is selected for use with VDD 2.0V, longer acquisition times will be required (see Section 9.3 "A/D Acquisition Requirements") FIGURE 23-11: PIC16F720/721 A/D CONVERSION TIMING (NORMAL MODE) BSF ADCON0, GO AD134 1 TCY (TOSC/2(1)) AD131 Q4 AD130 A/D CLK 7 A/D Data 6 5 4 3 OLD_DATA ADRES 1 0 NEW_DATA 1 TCY ADIF GO Sample 2 DONE AD132 Sampling Stopped Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 2010-2013 Microchip Technology Inc. DS40001430E-page 203 PIC16(L)F720/721 FIGURE 23-12: PIC16F720/721 A/D CONVERSION TIMING (SLEEP MODE) BSF ADCON0, GO (TOSC/2 + TCY(1)) AD134 1 TCY AD131 Q4 AD130 A/D CLK 7 A/D Data 6 5 4 3 2 1 0 NEW_DATA OLD_DATA ADRES ADIF 1 TCY GO DONE Sampling Stopped AD132 Sample Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. FIGURE 23-13: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING CK US121 US121 DT US122 US120 Note: TABLE 23-9: Refer to Figure 23-2 for load conditions. USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param. No. Symbol Characteristic Min. Max. Units US120* TCKH2DTV SYNC XMIT (Master and Slave) Clock high to data-out valid 3.0-5.5V -- 80 ns 1.8-5.5V -- 100 ns Clock out rise time and fall time (Master mode) 3.0-5.5V -- 45 ns 1.8-5.5V -- 50 ns Data-out rise time and fall time 3.0-5.5V -- 45 ns 1.8-5.5V -- 50 ns US121* TCKRF US122* TDTRF Conditions * These parameters are characterized but not tested. DS40001430E-page 204 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 FIGURE 23-14: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING CK US125 DT US126 Note: Refer to Figure 23-2 for load conditions. TABLE 23-10: USART SYNCHRONOUS RECEIVE REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param. No. Symbol Characteristic Min. Max. Units 10 -- ns 15 -- ns US125* TDTV2CKL SYNC RCV (Master and Slave) Data-hold before CK (DT hold time) US126* TCKL2DTL Data-hold after CK (DT hold time) Conditions * These parameters are characterized but not tested. FIGURE 23-15: SPI MASTER MODE TIMING (CKE = 0, SMP = 0) SS SP70 SCK (CKP = 0) SP71 SP72 SP78 SP79 SP79 SP78 SCK (CKP = 1) SP80 bit 6 - - - - - -1 MSb SDO LSb SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 SP73 Note 1: Refer to Figure 23-2 for load conditions. 2010-2013 Microchip Technology Inc. DS40001430E-page 205 PIC16(L)F720/721 FIGURE 23-16: SPI MASTER MODE TIMING (CKE = 1, SMP = 1) SS SP81 SCK (CKP = 0) SP71 SP72 SP79 SP73 SCK (CKP = 1) SP80 LSb bit 6 - - - - - -1 MSb SDO SP78 SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 Note 1: Refer to Figure 23-2 for load conditions. FIGURE 23-17: SPI SLAVE MODE TIMING (CKE = 0) SS SP70 SCK (CKP = 0) SP83 SP71 SP72 SP78 SP79 SP79 SP78 SCK (CKP = 1) SP80 MSb SDO bit 6 - - - - - -1 LSb SP77 SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 SP73 Note 1: Refer to Figure 23-2 for load conditions. DS40001430E-page 206 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 FIGURE 23-18: SS SPI SLAVE MODE TIMING (CKE = 1) SP82 SP70 SP83 SCK (CKP = 0) SP71 SP72 SCK (CKP = 1) SP80 SDO MSb bit 6 - - - - - -1 LSb SP77 SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 Note 1: Refer to Figure 23-2 for load conditions. 2010-2013 Microchip Technology Inc. DS40001430E-page 207 PIC16(L)F720/721 TABLE 23-11: SPI MODE REQUIREMENTS Param. No. SP70* Symbol Characteristic TSSL2SCH, TSSL2SCL SS to SCK or SCK input Min. Typ Max. Units Conditions TCY -- -- ns SP71* TSCH SCK input high time (Slave mode) TCY + 20 -- -- ns SP72* TSCL SCK input low time (Slave mode) TCY + 20 -- -- ns SP73* TDIV2SCH, TDIV2SCL Setup time of SDI data input to SCK edge 100 -- -- ns SP74* TSCH2DIL, TSCL2DIL Hold time of SDI data input to SCK edge 100 -- -- ns SP75* TDOR SDO data output rise time -- 10 25 ns SP76* TDOF SDO data output fall time SP77* TSSH2DOZ SS to SDO output high-impedance SP78* TSCR SCK output rise time (Master mode) -- 25 50 ns SP79* TSCF SCK output fall time (Master mode) -- 10 25 ns SP80* TSCH2DOV, TSCL2DOV SDO data output valid after SCK edge 3.0-5.5V -- -- 50 ns 1.8-5.5V -- -- 145 ns SP81* TDOV2SCH, TDOV2SCL SDO data output setup to SCK edge Tcy -- -- ns SP82* TSSL2DOV SDO data output valid after SS edge -- -- 50 ns SP83* TSCH2SSH, TSCL2SSH SS after SCK edge 1.5TCY + 40 -- -- ns 3.0-5.5V 1.8-5.5V 3.0-5.5V 1.8-5.5V -- 25 50 ns -- 10 25 ns 10 -- 50 ns -- 10 25 ns * These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. DS40001430E-page 208 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 FIGURE 23-19: I2CTM BUS START/STOP BITS TIMING SCL SP93 SP91 SP90 SP92 SDA Stop Condition Start Condition Note 1: Refer to Figure 23-2 for load conditions. TABLE 23-12: I2CTM BUS START/STOP BITS REQUIREMENTS Param. No. Symbol SP90* TSU:STA SP91* THD:STA SP92* TSU:STO Characteristic Max. Units 100 kHz mode 4700 -- -- Setup time 400 kHz mode 600 -- -- Start condition 100 kHz mode 4000 -- -- Hold time 400 kHz mode 600 -- -- Stop condition 100 kHz mode 4700 -- -- Setup time 400 kHz mode 600 -- -- 100 kHz mode 4000 -- -- 400 kHz mode 600 -- -- Hold time * Typ Start condition THD:STO Stop condition SP93 Min. Conditions ns Only relevant for Repeated Start condition ns After this period, the first clock pulse is generated ns ns These parameters are characterized but not tested. FIGURE 23-20: I2CTM BUS DATA TIMING SP103 SCL SP100 SP90 SP102 SP101 SP106 SP107 SP91 SDA In SP92 SP110 SP109 SP109 SDA Out Note 1: Refer to Figure 23-2 for load conditions. 2010-2013 Microchip Technology Inc. DS40001430E-page 209 PIC16(L)F720/721 TABLE 23-13: I2CTM BUS DATA REQUIREMENTS Param. No. 100* Symbol THIGH Characteristic Clock high time Min. Max. Units Conditions 100 kHz mode 4.0 -- s Device must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 -- s Device must operate at a minimum of 10 MHz 1.5TCY -- 100 kHz mode 4.7 -- s Device must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 -- s Device must operate at a minimum of 10 MHz SSP module 101* TLOW Clock low time SSP module 102* 103* 90* 91* 106* 107* 92* 109* 110* TR TF TSU:STA THD:STA THD:DAT TSU:DAT TSU:STO TAA TBUF CB * Note 1: 2: 1.5TCY -- -- 1000 ns 20 + 0.1CB 300 ns 100 kHz mode -- 250 ns 400 kHz mode 20 + 0.1CB 250 ns CB is specified to be from 10-400 pF Only relevant for Repeated Start condition SDA and SCL rise time 100 kHz mode SDA and SCL fall time 400 kHz mode 100 kHz mode 4.7 -- s 400 kHz mode 0.6 -- s Start condition hold 100 kHz mode time 400 kHz mode 4.0 -- s 0.6 -- s Start condition setup time Data input hold time 100 kHz mode 0 -- ns 400 kHz mode 0 0.9 s Data input setup time 100 kHz mode 250 -- ns 400 kHz mode 100 -- ns Stop condition setup time Output valid from clock Bus free time 100 kHz mode 4.7 -- s 400 kHz mode 0.6 -- s 100 kHz mode -- 3500 ns 400 kHz mode -- -- ns 100 kHz mode 4.7 -- s 400 kHz mode 1.3 -- s -- 400 pF Bus capacitive loading CB is specified to be from 10-400 pF After this period the first clock pulse is generated (Note 2) (Note 1) Time the bus must be free before a new transmission can start These parameters are characterized but not tested. As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. A Fast mode (400 kHz) I2C bus device can be used in a Standard mode (100 kHz) I2C bus system, but the requirement TSU:DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit to the SDA line TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification), before the SCL line is released. DS40001430E-page 210 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 24.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS FIGURE 24-1: PIC16F720/721 MAX IDD vs. FOSC OVER VDD, EC MODE 1800 5.0V 3.6V Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) +3i (-40C to 125C) 1600 3.0V 1400 IDD (A) 1200 2.5V 1000 800 1.8V 600 400 200 0 0 2 4 6 8 10 12 14 16 18 FOSC (MHz) FIGURE 24-2: PIC16F720/721 TYPICAL IDD vs. FOSC OVER VDD, EC MODE 1800 Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) +3i (-40C to 125C) 1600 5.0V 3.6V 1400 3.0V IDD (A) 1200 2.5V 1000 800 1.8V 600 400 200 0 0 2 4 6 8 10 12 14 16 18 FOSC (MHz) 2010-2013 Microchip Technology Inc. DS40001430E-page 211 PIC16(L)F720/721 FIGURE 24-3: PIC16LF720/721 MAX. IDD vs. FOSC OVER VDD, EC MODE 2000 1800 Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) +3i (-40C to 125C) 1600 3.6V 3.3V 3.0V IDD (A) 1400 1200 2.5V 1000 2.0V 800 1.8V 600 400 200 0 0 2 4 6 8 10 12 14 16 18 FOSC (MHz) PIC16LF720/721 TYPICAL IDD vs. FOSC OVER VDD, EC MODE FIGURE 24-4: 1800 Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) +3i (-40C to 125C) 1600 3.6V 3.3V 1400 3.0V IDD (A) 1200 2.5V 1000 2.0V 800 1.8V 600 400 200 0 0 2 4 6 8 10 12 14 16 18 FOSC (MHz) DS40001430E-page 212 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 FIGURE 24-5: PIC16F720/721 MAX. IDD vs. FOSC OVER VDD, MFINTOSC 350 Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) +3 (-40C to 125C) 300 5V 250 3V 2.5V IDD (A) 200 1.8V 150 100 50 0 0 100 200 300 400 500 600 FOSC (kHZ) FIGURE 24-6: PIC16F720/721 TYPICAL IDD vs. FOSC OVER VDD, MFINTOSC 350 Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) +3 (-40C to 125C) 300 250 IDD (A) 200 5V 150 3V 2.5V 1.8V 100 50 0 0 100 200 300 400 500 600 FOSC (kHZ) 2010-2013 Microchip Technology Inc. DS40001430E-page 213 PIC16(L)F720/721 FIGURE 24-7: PIC16LF720/721 MAX. IDD vs. FOSC OVER VDD, MFINTOSC 250 Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) +3 (-40C to 125C) 200 3.6V 3V 2.5V 150 IDD (A) 1.8V 100 50 0 0 100 200 300 400 500 600 FOSC (kHZ) FIGURE 24-8: PIC16LF720/721 TYPICAL IDD vs. FOSC OVER VDD, MFINTOSC 250 Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) +3 (-40C to 125C) 200 IDD (A) 150 3.6V 3V 2.5V 1.8V 100 50 0 0 100 200 300 400 500 600 FOSC (kHZ) DS40001430E-page 214 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 FIGURE 24-9: PIC16F720/721 MAX. IDD vs. FOSC OVER VDD, HFINTOSC 2000 5.0V 1800 Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) +3i (-40C to 125C) 1600 3.6V 2.5V IDD (A) 1400 1200 1.8V 1000 800 600 400 200 0 0 2 4 6 8 10 12 14 16 18 FOSC (MHz) FIGURE 24-10: PIC16F720/721 TYPICAL IDD vs. FOSC OVER VDD, HFINTOSC 2000 1800 Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) +3i (-40C to 125C) 1600 5.0V 3.6V 1400 IDD (A) 2.5V 1200 1000 1.8V 800 600 400 200 0 0 2 4 6 8 10 12 14 16 18 FOSC (MHz) 2010-2013 Microchip Technology Inc. DS40001430E-page 215 PIC16(L)F720/721 FIGURE 24-11: PIC16LF720/721 MAX. IDD vs. FOSC OVER VDD, HFINTOSC 2500 Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) +3i (-40C to 125C) 2000 3.6V IDD (A) 3.0V 1500 2.5V 1.8V 1000 500 0 0 2 4 6 8 10 12 14 16 18 FOSC (MHz) FIGURE 24-12: PIC16LF720/721 TYPICAL IDD vs. FOSC OVER VDD, HFINTOSC 2000 3.6V Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) +3i (-40C to 125C) 1800 1600 3.0V 1400 IDD (A) 2.5V 1200 1000 1.8V 800 600 400 200 0 0 2 4 6 8 10 12 14 16 18 FOSC (MHz) DS40001430E-page 216 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 FIGURE 24-13: PIC16F720/721 BASE IPD vs. VDD 80 Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) +3 (-40C to 125C) 70 Max.125C 60 IPD (A) 50 Max. 85C 40 30 Typ. 25C 20 10 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 VDD (V) 2010-2013 Microchip Technology Inc. DS40001430E-page 217 PIC16(L)F720/721 FIGURE 24-14: PIC16LF720/721 MAXIMUM BASE IPD vs. VDD 8 Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) +3 (-40C to 125C) 7 6 Max. 125C IPD (A) 5 4 3 Max. 85C 2 1 0 1.5 2 2.5 3 3.5 4 VDD (V) FIGURE 24-15: PIC16LF720/721 TYPICAL BASE IPD vs. VDD 250 Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) +3 (-40C to 125C) 200 Typ. IPD (nA) 150 100 50 0 1.5 2 2.5 3 3.5 4 VDD (V) DS40001430E-page 218 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 FIGURE 24-16: PIC16F720/721 WDT IPD vs. VDD 80 Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) +3 (-40C to 125C) 70 Max. 125C 60 IPD (A) 50 Max. 85C 40 30 Typ. 25C 20 10 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 VDD (V) FIGURE 24-17: PIC16LF720/721 WDT IPD vs. VDD 14 Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) +3 (-40C to 125C) 12 10 Max. 125C IPD (A) 8 6 Max. 85C 4 2 Typ. 25C 0 1.5 2 2.5 3 3.5 4 VDD (V) 2010-2013 Microchip Technology Inc. DS40001430E-page 219 PIC16(L)F720/721 FIGURE 24-18: PIC16F720/721 FIXED VOLTAGE REFERENCE IPD vs. VDD 300 Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) +3 (-40C to 125C) 250 200 IPD (A) Max. 125C 150 Max. 85C 100 Typ. 50 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 VDD (V) FIGURE 24-19: PIC16LF720/721 FIXED VOLTAGE REFERENCE IPD vs. VDD 40 Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) +3 (-40C to 125C) 35 Max. 125C 30 25 IPD (A) Max. 85C 20 Typ. 15 10 5 0 1.5 2 2.5 3 3.5 4 VDD (V) DS40001430E-page 220 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 FIGURE 24-20: PIC16F720/721 BOR IPD vs. VDD 80 Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) +3 (-40C to 125C) 70 60 Max. 125C IPD (A) 50 Max. 85C 40 30 Typ. 25C 20 10 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 VDD (V) FIGURE 24-21: PIC16LF720/721 BOR IPD vs. VDD 30 Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) +3 (-40C to 125C) 25 Max. 125C IPD (A) 20 15 Max. 85C 10 Typ. 25C 5 0 1.5 2 2.5 3 3.5 4 VDD (V) 2010-2013 Microchip Technology Inc. DS40001430E-page 221 PIC16(L)F720/721 FIGURE 24-22: TTL INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE 1.8 1.6 Maximum: Mean + 3 (-40C to 125C) Typical: Mean @25C Minimum: Mean - 3 (-40C to 125C) 1.4 Max. -40 VIN (V) 1.2 Typ. 25 1 Min. 125 0.8 0.6 0.4 1.8 3.6 5.5 VDD (V) FIGURE 24-23: SCHMITT TRIGGER INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE 3.5 3.0 Maximum: Mean + 3 (-40C to 125C) Typical: Mean @25C Minimum: Mean - 3 (-40C to 125C) VIH Max. -40C 2.5 VIN (V) 2.0 1.5 VIH Min. 125C 1.0 0.5 0.0 1.8 3.6 5.5 VDD (V) DS40001430E-page 222 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 FIGURE 24-24: SCHMITT TRIGGER INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE 3.0 Maximum: Mean + 3 (-40C to 125C) Typical: Mean @25C Minimum: Mean - 3 (-40C to 125C) 2.5 VIL Max. -40C VIN (V) 2.0 1.5 1.0 VIL Min. 125C 0.5 0.0 1.8 3.6 5.5 VDD (V) FIGURE 24-25: VOH vs. IOH OVER TEMPERATURE, VDD = 5.5V 5.6 Maximum: Mean + 3 (-40C to 125C) Typical: Mean @25C Minimum: Mean - 3 (-40C to 125C) 5.5 VOH (V) 5.4 5.3 Max. -40 Typ. 25 5.2 Min. 125 5.1 5 -0.2 -1.0 -1.8 -2.6 -3.4 -4.2 -5.0 IOH (mA) 2010-2013 Microchip Technology Inc. DS40001430E-page 223 PIC16(L)F720/721 FIGURE 24-26: VOH vs. IOH OVER TEMPERATURE, VDD = 3.6V 3.8 Maximum: Mean + 3 (-40C to 125C) Typical: Mean @25C Minimum: Mean - 3 (-40C to 125C) 3.6 3.4 VOH (V) Max. -40 3.2 Typ. 25 3 Min. 125 2.8 2.6 -0.2 -1.0 -1.8 -2.6 -3.4 -4.2 -5.0 IOH (mA) VOH vs. IOH OVER TEMPERATURE, VDD = 1.8V FIGURE 24-27: 2 Maximum: Mean + 3 (-40C to 125C) Typical: Mean @25C Minimum: Mean - 3 (-40C to 125C) 1.8 1.6 Max. -40 1.4 VOH (V) 1.2 Typ. 25 1 0.8 0.6 Min. 125 0.4 0.2 0 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 -1.4 -1.6 -1.8 -2.0 IOH (mA) DS40001430E-page 224 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 FIGURE 24-28: VOL vs. IOL OVER TEMPERATURE, VDD = 5.5V 0.5 Maximum: Mean + 3 (-40C to 125C) Typical: Mean @25C Minimum: Mean - 3 (-40C to 125C) 0.45 0.4 0.35 Max. 125 VOL (V) 0.3 0.25 0.2 Typ. 25 0.15 0.1 Min. -40 0.05 0 5.0 6.0 7.0 8.0 9.0 10.0 IOL (mA) FIGURE 24-29: VOL vs. IOL OVER TEMPERATURE, VDD = 3.6 0.9 Maximum: Mean + 3 (-40C to 125C) Typical: Mean @25C Minimum: Mean - 3 (-40C to 125C) 0.8 0.7 0.6 Max. 125 VOL (V) 0.5 0.4 Typ. 25 0.3 0.2 Min. -40 0.1 0 4.0 5.0 2010-2013 Microchip Technology Inc. 6.0 7.0 IOL (mA) 8.0 9.0 10.0 DS40001430E-page 225 PIC16(L)F720/721 FIGURE 24-30: VOL vs. IOL OVER TEMPERATURE, VDD = 1.8V 1.2 1 Maximum: Mean + 3 (-40C to 125C) Typical: Mean @25C Minimum: Mean - 3 (-40C to 125C) 0.8 VOL (V) Max. 125 0.6 0.4 0.2 Min. -40 0 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 IOL (mA) FIGURE 24-31: PIC16F720/721 PWRT PERIOD 105 95 Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) + 3 (-40C to 125C) Max. -40C TIME (ms) 85 75 Typ. 25C 65 Min. 125C 55 45 1.8V 2V 2.2V 2.4V 3V 3.6V 4V 4.5V 5V 5.5V VDD DS40001430E-page 226 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 FIGURE 24-32: PIC16F720/721 WDT TIME-OUT PERIOD 24.00 22.00 Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) + 3 (-40C to 125C) Max. -40C 20.00 TIME (ms) 18.00 Typ. 25C 16.00 14.00 Min. 125C 12.00 10.00 1.8V 2V 2.2V 2.4V 3V 3.6V 4V 4.5V 5V VDD FIGURE 24-33: PIC16F720/721 HFINTOSC WAKE-UP FROM SLEEP START-UP TIME 6.0 5.5 Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) + 3 (-40C to 125C) 5.0 4.5 Max. TIME (us) 4.0 3.5 3.0 Typ. 2.5 2.0 1.5 1.0 1.8V 2V 3V 3.6V 4V 4.5V 5V 5.5V VDD 2010-2013 Microchip Technology Inc. DS40001430E-page 227 PIC16(L)F720/721 FIGURE 24-34: PIC16F720/721 A/D INTERNAL RC OSCILLATOR PERIOD 6.0 5.0 Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) + 3 (-40C to 125C) Period (s) 4.0 3.0 Max. Min. 2.0 1.0 0.0 1.8V 3.6V 5.5V VDD(V) FIGURE 24-35: TYPICAL FVR (X1 AND X2) VS. SUPPLY VOLTAGE (V) NORMALIZED AT 3.0V 1.5 Percent Change (%) 1 0.5 0 -0.5 -1 -1.5 1.8 2.5 3 3.6 4.2 5.5 Voltage DS40001430E-page 228 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 FIGURE 24-36: TYPICAL FVR CHANGE VS. TEMPERATURE NORMALIZED AT 25C 1.5 1 Percent Change (%) 0.5 0 -0.5 -1 -1.5 -2 -2.5 -3 -40 0 45 85 125 Temperature (C) 2010-2013 Microchip Technology Inc. DS40001430E-page 229 PIC16(L)F720/721 NOTES: DS40001430E-page 230 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 25.0 PACKAGING INFORMATION 25.1 Package Marking Information Example 20-Lead PDIP (300 mil) XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN PIC16F721-E/P e3 0810017 20-Lead QFN (4x4x0.9 mm) PIN 1 Example PIN 1 PIC16 F721 E/ML 810017 e3 Legend: XX...X Y YY WW NNN e3 * Note: * Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. Standard PICmicro(R) device marking consists of Microchip part number, year code, week code and traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. 2010-2013 Microchip Technology Inc. DS40001430E-page 231 PIC16(L)F720/721 25.1 Package Marking Information 20-Lead SOIC (7.50 mm) Example PIC16F720 -I/SO e3 0810017 20-Lead SSOP (5.30 mm) Example PIC16F720 -I/SS e3 0810017 Legend: XX...X Y YY WW NNN e3 * Note: * Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. Standard PICmicro(R) device marking consists of Microchip part number, year code, week code and traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. DS40001430E-page 232 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 25.2 Package Details The following sections give the technical details of the packages. /HDG3ODVWLF'XDO,Q/LQH 3 PLO%RG\>3',3@ 1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWSZZZPLFURFKLSFRPSDFNDJLQJ N E1 NOTE 1 1 2 3 D E A2 A L c A1 b1 b eB e 8QLWV 'LPHQVLRQ/LPLWV 1XPEHURI3LQV ,1&+(6 0,1 1 120 0$; 3LWFK H 7RSWR6HDWLQJ3ODQH $ 0ROGHG3DFNDJH7KLFNQHVV $ %DVHWR6HDWLQJ3ODQH $ 6KRXOGHUWR6KRXOGHU:LGWK ( 0ROGHG3DFNDJH:LGWK ( 2YHUDOO/HQJWK ' 7LSWR6HDWLQJ3ODQH / /HDG7KLFNQHVV F E E H% 8SSHU/HDG:LGWK /RZHU/HDG:LGWK 2YHUDOO5RZ6SDFLQJ %6& 1RWHV 3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD 6LJQLILFDQW&KDUDFWHULVWLF 'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRUSURWUXVLRQVVKDOOQRWH[FHHGSHUVLGH 'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0 %6& %DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &% 2010-2013 Microchip Technology Inc. DS40001430E-page 233 PIC16(L)F720/721 /HDG3ODVWLF4XDG)ODW1R/HDG3DFNDJH 0/ [[PP%RG\>4)1@ 1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWSZZZPLFURFKLSFRPSDFNDJLQJ D D2 EXPOSED PAD e E2 2 E b 2 1 1 K N N NOTE 1 TOP VIEW L BOTTOM VIEW A A1 A3 8QLWV 'LPHQVLRQ/LPLWV 1XPEHURI3LQV 0,//,0(7(56 0,1 1 120 0$; 3LWFK H 2YHUDOO+HLJKW $ 6WDQGRII $ &RQWDFW7KLFNQHVV $ 2YHUDOO:LGWK ( ([SRVHG3DG:LGWK ( 2YHUDOO/HQJWK ' ([SRVHG3DG/HQJWK %6& 5() %6& %6& ' &RQWDFW:LGWK E &RQWDFW/HQJWK / &RQWDFWWR([SRVHG3DG . 1RWHV 3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD 3DFNDJHLVVDZVLQJXODWHG 'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0 %6& %DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV 5() 5HIHUHQFH'LPHQVLRQXVXDOO\ZLWKRXWWROHUDQFHIRULQIRUPDWLRQSXUSRVHVRQO\ 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &% DS40001430E-page 234 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWSZZZPLFURFKLSFRPSDFNDJLQJ 2010-2013 Microchip Technology Inc. DS40001430E-page 235 PIC16(L)F720/721 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001430E-page 236 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2010-2013 Microchip Technology Inc. DS40001430E-page 237 PIC16(L)F720/721 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001430E-page 238 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 /HDG3ODVWLF6KULQN6PDOO2XWOLQH 66 PP%RG\>6623@ 1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWSZZZPLFURFKLSFRPSDFNDJLQJ D N E E1 NOTE 1 1 2 e b c A2 A A1 L1 8QLWV 'LPHQVLRQ/LPLWV 1XPEHURI3LQV L 0,//,0(7(56 0,1 1 120 0$; 3LWFK H 2YHUDOO+HLJKW $ %6& 0ROGHG3DFNDJH7KLFNQHVV $ 6WDQGRII $ 2YHUDOO:LGWK ( 0ROGHG3DFNDJH:LGWK ( 2YHUDOO/HQJWK ' )RRW/HQJWK / )RRWSULQW / 5() /HDG7KLFNQHVV F )RRW$QJOH /HDG:LGWK E 1RWHV 3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD 'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRUSURWUXVLRQVVKDOOQRWH[FHHGPPSHUVLGH 'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0 %6& %DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV 5() 5HIHUHQFH'LPHQVLRQXVXDOO\ZLWKRXWWROHUDQFHIRULQIRUPDWLRQSXUSRVHVRQO\ 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &% 2010-2013 Microchip Technology Inc. DS40001430E-page 239 PIC16(L)F720/721 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001430E-page 240 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 APPENDIX A: DATA SHEET REVISION HISTORY Revision A (September 2010) Original release of this document. Revision B (March 2011) Updated the Electrical Specifications section. APPENDIX B: MIGRATING FROM OTHER PIC(R) DEVICES This shows a comparison of features in the migration from another PIC(R) device, the PIC16F720, to the PIC16F721 device. B.1 PIC16F690 to PIC16F721 TABLE B-1: Revision C (September 2011) FEATURE COMPARISON Feature PIC16F690 PIC16F721 Reviewed title; Updated Table 1 and Table 1-1; Reviewed the Memory Organization section; Updated Section 3.6, Figures 3-4 and 3-5, Register 4-1 and Figure 4-2; Updated Registers 8-1 and 8-2; Reviewed the Oscillator Module section; Updated Table 10-1, Figures 11-1, 12-1 and Register 18-1; Updated the Summary of Registers Tables; Updated the Electrical Specifications section; Updated the DC and AC Characteristics Graphs and Charts section; Updated the Packaging Information section; Updated the Product Identification System section. Max. Operating Speed 20 MHz 16 MHz 4K 4K Revision D (February 2013) Updated Table 1-1, Table 15-4 and Table 16-5; Updated the Electrical Specifications section; Updated the DC and AC Characteristics Graphs and Charts section; Other minor corrections. Max. Program Memory (Words) Max. SRAM (Bytes) 256 256 10-bit 8-bit Timers (8/16-bit) 2/1 2/1 Oscillator Modes 8 4 A/D Resolution Brown-out Reset Y Y Internal Pull-ups RA<5:0>, RB<7:4> RA<5:0>, RB<7:4> Interrupt-on-change RA<5:0>, RB<7:4> RA<5:0>, RB<7:4> Comparator 2 0 EUSART Y Y Extended WDT Y N Revision E (August 2013) Software Control Option of WDT/BOR Y N Deleted Example 18-2; Revised Table 23-7. INTOSC Frequencies 31 kHz 8 MHz 500 kHz 16 MHz 20 20 Pin Count 2010-2013 Microchip Technology Inc. Note: This device has been designed to perform to the parameters of its data sheet. It has been tested to an electrical specification designed to determine its conformance with these parameters. Due to process differences in the manufacture of this device, this device may have different performance characteristics than its earlier version. These differences may cause this device to perform differently in your application than the earlier version of this device. Note: The user should verify that the device oscillator starts and performs as expected. Adjusting the loading capacitor values and/or the oscillator mode may be required. DS40001430E-page 241 PIC16(L)F720/721 NOTES: DS40001430E-page 242 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 INDEX A B A/D BF bit ........................................................................ 145, 157 Block Diagrams (CCP) Capture Mode Operation ............................... 108 ADC ............................................................................ 75 ADC Transfer Function............................................... 82 Analog Input Model..................................................... 82 AUSART Receive ..................................................... 118 AUSART Transmit .................................................... 117 CCP PWM ................................................................ 112 Clock Source .............................................................. 65 Compare................................................................... 110 Interrupt Logic............................................................. 35 MCLR Circuit .............................................................. 27 On-Chip Reset Circuit................................................. 25 RA0 Pins..................................................................... 49 RA1 Pins..................................................................... 50 RA2 Pin ...................................................................... 51 RA4 Pin ...................................................................... 52 RA5 Pin ................................................................ 52, 53 RB0 Pin ...................................................................... 57 RB3 Pin ...................................................................... 58 RC0 Pin ...................................................................... 62 RC5 Pin ...................................................................... 63 RC6 Pin ...................................................................... 63 RC7 Pin ...................................................................... 63 SPI Mode.................................................................. 138 SSP (I2C Mode)........................................................ 147 Timer1 .................................................. 93, 99, 100, 101 Timer2 ...................................................................... 105 TMR0/WDT Prescaler ................................................ 89 Voltage Reference...................................................... 85 Brown-out Reset (BOR)...................................................... 29 Timing and Characteristics ....................................... 199 Specifications.................................................... 202, 203 Absolute Maximum Ratings .............................................. 185 AC Characteristics Industrial and Extended ............................................ 194 Load Conditions ........................................................ 193 ADC .................................................................................... 75 Acquisition Requirements ........................................... 81 Associated registers.................................................... 83 Block Diagram............................................................. 75 Calculating Acquisition Time....................................... 81 Channel Selection....................................................... 76 Configuration............................................................... 76 Configuring Interrupt ................................................... 78 Conversion Clock........................................................ 76 Conversion Procedure ................................................ 78 Internal Sampling Switch (RSS) Impedance................ 81 Interrupts..................................................................... 77 Operation .................................................................... 77 Operation During Sleep .............................................. 78 Port Configuration ....................................................... 76 Source Impedance...................................................... 81 Special Event Trigger.................................................. 78 ADCON0 Register......................................................... 16, 79 ADCON1 Register......................................................... 17, 80 Addressable Universal Synchronous Asynchronous Receiver Transmitter (AUSART)............................... 117 ADRES Register ................................................................. 80 ADRESH Register............................................................... 16 Analog-to-Digital Converter. See ADC ANSELA Register ............................................................... 47 ANSELB Register ............................................................... 56 Assembler MPASM Assembler................................................... 182 AUSART ........................................................................... 117 Associated Registers Baud Rate Generator........................................ 127 Asynchronous Mode ................................................. 119 Associated Registers Receive..................................................... 124 Transmit.................................................... 121 Baud Rate Generator (BRG) ............................ 127 Receiver............................................................ 121 Setting up 9-bit Mode with Address Detect....... 123 Transmitter........................................................ 119 Baud Rate Generator (BRG) Baud Rate Error, Calculating ............................ 127 Baud Rates, Asynchronous Modes .................. 128 Formulas ........................................................... 127 High Baud Rate Select (BRGH Bit) .................. 127 Synchronous Master Mode ............................... 130, 134 Associated Registers Receive..................................................... 133 Transmit.................................................... 131 Reception.......................................................... 132 Transmission .................................................... 130 Synchronous Slave Mode Associated Registers Receive..................................................... 135 Transmit.................................................... 134 Reception.......................................................... 135 Transmission .................................................... 134 2010-2013 Microchip Technology Inc. C C Compilers MPLAB C18.............................................................. 182 Capture Module. See Capture/Compare/PWM (CCP) Capture/Compare/PWM (CCP) ........................................ 107 Associated registers w/ Capture............................... 109 Associated registers w/ Compare............................. 111 Associated registers w/ PWM................................... 115 Capture Mode........................................................... 108 CCPx Pin Configuration............................................ 108 Compare Mode......................................................... 110 CCPx Pin Configuration.................................... 110 Software Interrupt Mode ........................... 108, 110 Special Event Trigger ....................................... 110 Timer1 Mode Selection............................. 108, 110 Prescaler .................................................................. 108 PWM Mode............................................................... 112 Duty Cycle ........................................................ 113 Effects of Reset ................................................ 114 Example PWM Frequencies and Resolutions 16 MHZ..................................................... 114 8 MHz ....................................................... 114 Operation in Sleep Mode.................................. 114 Setup for Operation .......................................... 114 System Clock Frequency Changes .................. 114 PWM Period ............................................................. 113 Setup for PWM Operation ........................................ 114 Timer Resources ...................................................... 107 DS40001430E-page 243 PIC16(L)F720/721 CCP. See Capture/Compare/PWM (CCP) CCP1CON Register ............................................................ 16 CCPR1H Register ............................................................... 16 CCPR1L Register................................................................ 16 CCPxCON Register .......................................................... 107 CKE bit ...................................................................... 145, 157 CKP bit ...................................................................... 144, 156 Clock Sources External Modes ........................................................... 69 EC ....................................................................... 69 Code Examples A/D Conversion ........................................................... 78 Call of a Subroutine in Page 1 from Page 0................ 23 Changing Between Capture Prescalers .................... 108 Indirect Addressing ..................................................... 24 Initializing PORTA ....................................................... 45 Initializing PORTB ....................................................... 54 Initializing PORTC....................................................... 60 Loading the SSPBUF (SSPSR) Register .................. 140 Saving W, STATUS and PCLATH Registers in RAM .................................................................... 37 Comparators C2OUT as T1 Gate ..................................................... 95 Compare Module. See Capture/Compare/PWM (CCP) Customer Change Notification Service ............................. 249 Customer Notification Service........................................... 249 Customer Support ............................................................. 249 D D/A bit ............................................................................... 157 Data Memory....................................................................... 12 Data/Address bit (D/A) ...................................................... 157 DC and AC Characteristics ............................................... 211 DC Characteristics Extended and Industrial ............................................ 190 Industrial and Extended ............................................ 186 Development Support ....................................................... 181 Device Configuration........................................................... 71 Code Protection .......................................................... 74 Configuration Word ..................................................... 71 User ID ........................................................................ 74 Device Overview ................................................................... 7 E Effects of Reset PWM mode ............................................................... 114 Electrical Specifications .................................................... 185 Errata .................................................................................... 6 F Firmware Instructions........................................................ 171 Fixed Voltage Reference. See FVR FSR Register................................................................. 16, 17 FVR ..................................................................................... 85 Associated registers.................................................... 86 FVRCON Register............................................................... 86 G General Purpose Register File............................................ 13 I I2C Mode Associated Registers ................................................ 158 INDF Register ............................................................... 16, 17 Indirect Addressing, INDF and FSR Registers.................... 24 Instruction Format ............................................................. 171 DS40001430E-page 244 Instruction Set................................................................... 171 ADDLW..................................................................... 173 ADDWF..................................................................... 173 ANDLW..................................................................... 173 ANDWF..................................................................... 173 BCF .......................................................................... 173 BSF........................................................................... 173 BTFSC ...................................................................... 173 BTFSS ...................................................................... 174 CALL......................................................................... 174 CLRF ........................................................................ 174 CLRW ....................................................................... 174 CLRWDT .................................................................. 174 COMF ....................................................................... 174 DECF ........................................................................ 174 DECFSZ ................................................................... 175 GOTO ....................................................................... 175 INCF ......................................................................... 175 INCFSZ..................................................................... 175 IORLW ...................................................................... 175 IORWF...................................................................... 175 MOVF ....................................................................... 176 MOVLW .................................................................... 176 MOVWF .................................................................... 176 NOP .......................................................................... 176 RETFIE ..................................................................... 177 RETLW ..................................................................... 177 RETURN................................................................... 177 RLF ........................................................................... 178 RRF .......................................................................... 178 SLEEP ...................................................................... 178 SUBLW ..................................................................... 178 SUBWF..................................................................... 179 SWAPF ..................................................................... 179 XORLW .................................................................... 179 XORWF .................................................................... 179 Summary Table ........................................................ 172 INTCON Register................................................................ 38 Internal Oscillator Block INTOSC Specifications ........................................... 197, 198 Internal Sampling Switch (RSS) Impedance........................ 81 Internet Address ............................................................... 249 Interrupts............................................................................. 35 ADC ............................................................................ 78 Associated registers w/ Interrupts............................... 41 Interrupt-on-Change ................................................... 54 TMR1 .......................................................................... 98 INTOSC Specifications ............................................. 197, 198 IOCB Register..................................................................... 56 L Load Conditions................................................................ 193 M M....................................................................................... 201 MCLR.................................................................................. 27 Internal........................................................................ 27 Memory Organization ......................................................... 11 Data ............................................................................ 12 Program ...................................................................... 11 Microchip Internet Web Site.............................................. 249 Migrating from other PIC Microcontroller Devices ............ 241 MPLAB ASM30 Assembler, Linker, Librarian ................... 182 MPLAB Integrated Development Environment Software.. 181 MPLAB PM3 Device Programmer .................................... 184 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 MPLAB REAL ICE In-Circuit Emulator System................. 183 MPLINK Object Linker/MPLIB Object Librarian ................ 182 O OPCODE Field Descriptions ............................................. 171 OPTION_REG Register ...................................................... 91 OSCCON Register .............................................................. 67 Oscillator Associated registers............................................ 69, 104 Oscillator Module EC ............................................................................... 65 Oscillator Tuning ......................................................... 68 Oscillator Parameters ....................................................... 197 Oscillator Specifications .................................................... 196 OSCTUNE Register ............................................................ 68 P P (Stop) bit ........................................................................ 157 Packaging ......................................................................... 231 Marking ............................................................. 231, 232 PDIP Details.............................................................. 233 Paging, Program Memory ................................................... 23 PCL and PCLATH ............................................................... 23 Computed GOTO........................................................ 23 Stack ........................................................................... 23 PCL Register................................................................. 16, 17 PCLATH Register ......................................................... 16, 17 PCON Register ....................................................... 17, 22, 30 PIE1 Register ................................................................ 17, 39 PIR1 Register................................................................ 16, 40 PMADRH Register ............................................................ 164 PMADRL Register............................................................. 165 PMCON1 Register .................................................... 163, 165 PMDATH Register ............................................................ 164 PMDATL Register ............................................................. 164 PORTA................................................................................ 45 ANSELA Register ....................................................... 47 Associated Registers .................................................. 53 Pin Descriptions and Diagrams................................... 48 PORTA Register ......................................................... 16 RA0 ............................................................................. 48 RA1 ............................................................................. 48 RA2 ............................................................................. 48 RA3 ............................................................................. 48 RA4 ............................................................................. 48 RA5 ............................................................................. 48 RA6 ............................................................................. 48 Specifications............................................................ 198 PORTA Register ................................................................. 46 PORTB Additional Pin Functions ANSELB Register ............................................... 54 Weak Pull-up ...................................................... 54 Associated Registers .................................................. 59 Interrupt-on-Change.................................................... 54 Pin Descriptions and Diagrams................................... 57 PORTB Register ......................................................... 16 RB0 ............................................................................. 57 RB4 ............................................................................. 57 RB5 ............................................................................. 57 RB6 ............................................................................. 57 RB7 ............................................................................. 57 PORTB Register ................................................................. 55 PORTC PORTC Register ......................................................... 16 RC0............................................................................. 62 2010-2013 Microchip Technology Inc. RC2 ............................................................................ 62 RC3 ............................................................................ 62 RC4 ............................................................................ 62 RC5 ............................................................................ 62 RC6 ............................................................................ 62 RC7 ............................................................................ 62 Specifications ........................................................... 198 PORTC Register................................................................. 60 Power-Down Mode (Sleep)............................................... 167 Associated Registers................................................ 168 Power-on Reset .................................................................. 27 Power-up Timer (PWRT) .................................................... 27 Specifications ........................................................... 200 PR2 Register .............................................................. 17, 146 Precision Internal Oscillator Parameters .......................... 198 Prescaler Shared WDT/Timer0................................................... 90 Product Identification System ........................................... 251 Program Memory ................................................................ 11 Map and Stack (PIC16F720/LF720) ........................... 11 Map and Stack (PIC16F721/LF721) ........................... 11 Paging ........................................................................ 23 Program Memory Read (PMR) ......................................... 159 Associated Registers................................................ 165 Programming, Device Instructions.................................... 171 R R/W bit .............................................................................. 157 RCREG............................................................................. 123 RCSTA Register ......................................................... 16, 126 Read-Modify-Write Operations ......................................... 171 Receive Overflow Indicator bit (SSPOV) .................. 144, 156 Registers ADCON0 (ADC Control 0) .......................................... 79 ADCON1 (ADC Control 1) .......................................... 80 ADRES (ADC Result) ................................................. 80 ANSELA (PORTA Analog Select) .............................. 47 ANSELB (PORTB Analog Select) .............................. 56 CCPxCON (CCP Operation) .................................... 107 FVRCON (Fixed Voltage Reference Register) ........... 86 INTCON (Interrupt Control) ........................................ 38 IOCB (Interrupt-on-Change PORTB).......................... 56 OPTION_REG (Option) .............................................. 91 OSCCON (Oscillator Control)..................................... 67 OSCTUNE (Oscillator Tuning).................................... 68 PCON (Power Control Register)................................. 22 PCON (Power Control) ............................................... 30 PIE1 (Peripheral Interrupt Enable 1) .......................... 39 PIR1 (Peripheral Interrupt Register 1) ........................ 40 PMADRH (Program Memory Address High) ............ 164 PMADRL (Program Memory Address Low).............. 165 PMCON1 (Program Memory Control 1) ................... 163 PMDATH (Program Memory Data High) .................. 164 PMDATL (Program Memory Data Low).................... 164 PORTA ....................................................................... 46 PORTB ....................................................................... 55 PORTC ....................................................................... 60 RCSTA (Receive Status and Control) ...................... 126 Reset Values .............................................................. 32 Reset Values (Special Registers)............................... 34 SSPCON (Sync Serial Port Control) Register .. 144, 156 SSPSTAT (Sync Serial Port Status) Register .. 145, 157 STATUS ..................................................................... 20 T1CON (Timer1 Control) .......................................... 102 T1GCON (Timer1 Gate Control)............................... 103 T2CON ..................................................................... 106 DS40001430E-page 245 PIC16(L)F720/721 TRISA (Tri-State PORTA) ........................................... 46 TRISB (Tri-State PORTB) ........................................... 55 TRISC (Tri-State PORTC) .......................................... 61 TXSTA (Transmit Status and Control) ...................... 125 WPUB (Weak Pull-up PORTB) ................................... 55 Reset................................................................................... 25 Resets Associated Registers .................................................. 34 Revision History ................................................................ 241 S S (Start) bit ........................................................................ 157 SMP bit...................................................................... 145, 157 Software Simulator (MPLAB SIM)..................................... 183 SPBRG.............................................................................. 127 SPBRG Register ................................................................. 17 Special Event Trigger.......................................................... 78 Special Function Registers ................................................. 13 SPI Mode .......................................................................... 143 Associated Registers ................................................ 146 Typical Master/Slave Connection ............................. 137 SSP ................................................................................... 137 I2C Mode ................................................................... 147 Acknowledge..................................................... 148 Addressing ........................................................ 149 Clock Stretching................................................ 154 Clock Synchronization ...................................... 155 Firmware Master Mode ..................................... 154 Hardware Setup ................................................ 147 Multi-Master Mode ............................................ 154 Reception.......................................................... 150 Sleep Operation ................................................ 155 Start/Stop Conditions ........................................ 148 Transmission..................................................... 152 Master Mode ............................................................. 139 SPI Mode .................................................................. 137 Slave Mode ....................................................... 141 Typical SPI Master/Slave Connection....................... 137 SSPADD Register ............................................................... 17 SSPBUF Register ............................................................... 16 SSPCON Register............................................... 16, 144, 156 SSPEN bit ................................................................. 144, 156 SSPM bits ................................................................. 144, 156 SSPOV bit ................................................................. 144, 156 SSPSTAT Register ............................................. 17, 145, 157 STATUS Register................................................................ 20 Synchronous Serial Port Enable bit (SSPEN)........... 144, 156 Synchronous Serial Port Mode Select bits (SSPM) .. 144, 156 T T1CON Register.......................................................... 16, 102 TMR1ON Bit.............................................................. 103 T1GCON Register............................................................. 103 T2CON Register.................................................. 16, 106, 146 Temperature Indicator Module ............................................ 87 Thermal Considerations .................................................... 192 Time-out Sequence............................................................. 30 Timer0 ................................................................................. 89 Associated Registers .................................................. 91 Operation .............................................................. 89, 94 Specifications ............................................................ 201 Timer1 ................................................................................. 93 Associated registers.................................................. 104 Asynchronous Counter Mode ..................................... 95 Reading and Writing ........................................... 95 Interrupt....................................................................... 98 DS40001430E-page 246 Modes of Operation .................................................... 94 Module On/Off (TMR1ON Bit)................................... 103 Operation During Sleep .............................................. 98 Prescaler .................................................................... 95 Specifications ........................................................... 201 Timer1 Gate Selecting Source ................................................ 95 TMR1H Register ......................................................... 93 TMR1L Register.......................................................... 93 Timer2 Associated registers ................................................. 106 Timers Timer1 T1CON ............................................................. 102 T1GCON........................................................... 103 Timer2 T2CON ............................................................. 106 Timing Diagrams A/D Conversion......................................................... 203 A/D Conversion (Sleep Mode) .................................. 204 Asynchronous Reception.......................................... 124 Asynchronous Transmission..................................... 120 Asynchronous Transmission (Back-to-Back)............ 121 Brown-out Reset (BOR)............................................ 199 Brown-out Reset Situations ........................................ 29 CLKOUT and I/O ...................................................... 198 Clock Synchronization .............................................. 155 Clock Timing ............................................................. 196 I2C Bus Data............................................................. 209 I2C Bus Start/Stop Bits ............................................. 209 I2C Reception (7-bit Address)................................... 150 I2C Slave Mode with SEN = 0 (Reception, 10-bit Address) ................................................. 151 I2C Transmission (7-bit Address).............................. 152 INT Pin Interrupt ......................................................... 36 Slave Select Synchronization ................................... 143 SPI Master Mode ...................................................... 140 SPI Master Mode (CKE = 1, SMP = 1) ..................... 206 SPI Mode (Slave Mode with CKE = 0)...................... 142 SPI Mode (Slave Mode with CKE = 1)...................... 142 SPI Slave Mode (CKE = 0) ....................................... 206 SPI Slave Mode (CKE = 1) ....................................... 207 Synchronous Reception (Master Mode, SREN) ....... 133 Synchronous Transmission ...................................... 131 Synchronous Transmission (Through TXEN) ........... 131 Time-out Sequence Case 1 ................................................................ 30 Case 2 ................................................................ 31 Case 3 ................................................................ 31 Timer0 and Timer1 External Clock ........................... 200 Timer1 Incrementing Edge ......................................... 98 USART Synchronous Receive (Master/Slave) ......... 205 USART Synchronous Transmission (Master/Slave). 204 Wake-up from Interrupt............................................. 168 Timing Parameter Symbology .......................................... 193 Timing Requirements I2C Bus Data............................................................. 210 I2C Bus Start/Stop Bits ............................................. 209 SPI Mode .................................................................. 208 TMR0 Register.................................................................... 16 TMR1H Register ................................................................. 16 TMR1L Register.................................................................. 16 TMR2 Register.................................................................... 16 TMRO Register................................................................... 18 TRISA ................................................................................. 45 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 TRISA Register ............................................................. 17, 46 TRISB ................................................................................. 54 TRISB Register ............................................................. 17, 55 TRISC ................................................................................. 60 TRISC Register ............................................................. 17, 61 TXREG.............................................................................. 119 TXREG Register ................................................................. 16 TXSTA Register .......................................................... 17, 125 BRGH Bit .................................................................. 127 U UA ..................................................................................... 157 Update Address bit, UA .................................................... 157 USART Synchronous Master Mode Requirements, Synchronous Receive .............. 205 Requirements, Synchronous Transmission ...... 204 Timing Diagram, Synchronous Receive ........... 205 Timing Diagram, Synchronous Transmission ... 204 W Wake-up Using Interrupts ................................................. 168 Watchdog Timer (WDT) ...................................................... 27 Clock Source............................................................... 27 Modes ......................................................................... 28 Period.......................................................................... 27 Specifications............................................................ 200 WCOL bit .................................................................. 144, 156 WPUB Register ................................................................... 55 Write Collision Detect bit (WCOL)............................. 144, 156 WWW Address.................................................................. 249 WWW, On-Line Support ....................................................... 6 2010-2013 Microchip Technology Inc. DS40001430E-page 247 PIC16(L)F720/721 NOTES: DS40001430E-page 248 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: Users of Microchip products can receive assistance through several channels: * Product Support - Data sheets and errata, application notes and sample programs, design resources, user's guides and hardware support documents, latest software releases and archived software * General Technical Support - Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing * Business of Microchip - Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives * * * * Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Customers should contact their distributor, representative or Field Application Engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://microchip.com/support CUSTOMER CHANGE NOTIFICATION SERVICE Microchip's customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under "Support", click on "Customer Change Notification" and follow the registration instructions. 2010-2013 Microchip Technology Inc. DS40001430E-page 249 PIC16(L)F720/721 NOTES: DS40001430E-page 250 2010-2013 Microchip Technology Inc. PIC16(L)F720/721 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. X(1) PART NO. Device X Tape and Reel Temperature Option Range /XX XXX Package Pattern Examples: a) b) Device: PIC16F720, PIC16LF720, PIC16F721, PIC16LF721 Temperature Range: I E = = -40C to +85C -40C to +125C Package: ML P SO SS = = = = Micro Lead Frame (QFN) Plastic DIP SOIC SSOP Pattern: 3-Digit Pattern Code for QTP (blank otherwise) 2010-2013 Microchip Technology Inc. PIC16F720-E/P 301 = Extended Temp., PDIP package, QTP pattern #301 PIC16F721T-I/SO = Tape and Reel, Industrial Temp., SOIC package Note 1: T= Available in tape and reel for all industrial devices except PDIP. 2: Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option. DS40001430E-page 251 PIC16(L)F720/721 NOTES: DS40001430E-page 252 2010-2013 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: * Microchip products meet the specification contained in their particular Microchip Data Sheet. * Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. * There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. * Microchip is willing to work with the customer who is concerned about the integrity of their code. * Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MTP, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. Analog-for-the-Digital Age, Application Maestro, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O, Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA and Z-Scale are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. GestIC and ULPP are registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. (c) 2010-2013, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 9781620773970 QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 == 2010-2013 Microchip Technology Inc. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 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