1. Product profile
1.1 General description
140 W LDMOS power transistor for Industrial, Scientific and Medical (ISM) applications at
frequencies from 2400 MHz to 2500 MHz.
The BLF2425M7L140 and BLF2425M7LS140 are designed for high-power CW
applications and are assembled in high performance ceramic packages, available in
eared and earless versions
1.2 Features and benefits
High efficiency
High power gain
Excellent ruggedness
Excellent thermal stability
Integrated ESD protection
Designed for broadband operation (2400 MHz to 2500 MHz)
Internally matched
Compliant to Directive 2002/95/EC, rega rd in g Re stri ctio n of Hazard ou s Sub stances
(RoHS)
1.3 Applications
Industrial, scientific and med ical applications in the fre quency range from 2400 MHz to
2500 MHz
BLF2425M7L140;
BLF2425M7LS140
Power LDMOS transistor
Rev. 3 — 6 September 2012 Product data sheet
Table 1. Typical perform ance
Typical RF performance at Tcase = 25
C; IDq = 1300 mA in a common source class-AB production
test circuit.
Test signal f VDS PL(AV) GpD
(MHz) (V) (W) (dB) (%)
CW 2450 28 140 18.5 52
BLF2425M7L140; BLF2425M7LS140 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3 — 6 September 2012 2 of 11
NXP Semiconductors BLF2425M7L(S)140
Power LDMOS transistor
2. Pinning information
[1] Connected to flange.
3. Ordering information
4. Limiting values
5. Thermal characteristics
Table 2. Pinning
Pin Description Simplified outline Graphic symbol
BLF2425M7L140 (SOT502A)
1drain
2gate
3source [1]
BLF2425M7LS140 (SOT502B)
1drain
2gate
3source [1]
3
2
1
sym112
1
3
2
3
2
1
sym112
1
3
2
Tabl e 3. Ordering informati on
Type number Package
Name Description Version
BLF2425M7L140 - flanged ceramic package; 2 mounting holes; 2 leads SOT502A
BLF2425M7LS140 - earless flanged ceramic package; 2 leads SOT502B
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VDS drain-source voltage - 65 V
VGS gate-source voltage 0.5 +13 V
Tstg storage temperature 65 - C
Tjjunction temperature - 225 C
Table 5. Thermal characteristics
Symbol Parameter Conditions Typ Unit
Rth(j-c) thermal resistance from junction to case Tcase =80C; PL= 125 W 0.28 K/W
BLF2425M7L140; BLF2425M7LS140 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3 — 6 September 2012 3 of 11
NXP Semiconductors BLF2425M7L(S)140
Power LDMOS transistor
6. Characteristics
7. Test information
7.1 Ruggedness in class-AB operation
The BLF2425M7L140 and BLF2425M7LS140 are capable of withstanding a load
mismatch corr es po nd in g to VSWR = 10 : 1 through all ph ases under the follo win g
conditions: VDS =28V; I
Dq = 1300 mA; PL= 140 W (CW); f = 2450 MHz.
Table 6. DC charac teristics
Tj = 25
C unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
V(BR)DSS drain-source breakdown v ol tage VGS =0V; I
D=2.16mA 65 - - V
VGS(th) gate-source threshold voltage VDS = 10 V; ID= 216 mA 1.5 1.9 2.3 V
IDSS drain leakage current VGS =0V; V
DS =28V - - 5 A
IDSX drain cut-off current VGS =V
GS(th) + 3.75 V;
VDS =10V -41- A
IGSS gate leakage current VGS =11V; V
DS = 0 V - - 500 nA
gfs forward transconductance VDS =10V; I
D=10.8A - 16 - S
RDS(on) dr ain-source on-state resistance VGS =V
GS(th) + 3.75 V;
ID=7.56A -69- m
Table 7. RF char acteristics
Test signal: CW; f = 2450 MHz; VDS = 28 V; IDq = 1300 mA; Tcase = 25
C unless otherwise specified
in a class-AB production test circuit.
Symbol Parameter Conditions Min Typ Max Unit
Gppower gain PL= 140 W 16 18.5 - dB
RLin input return loss PL=140 W - 16 8dB
Ddrain efficiency PL=140 W 46 52 - %
BLF2425M7L140; BLF2425M7LS140 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3 — 6 September 2012 4 of 11
NXP Semiconductors BLF2425M7L(S)140
Power LDMOS transistor
7.2 Impedance information
7.3 Circuit information
Table 8. Typical impedance
Measured load-pull data. Typical values unless otherwise specified. IDq =1300mA; V
DS =28V.
ZS and ZL defined in Figure 1.
f ZSZL
(MHz) () ()
2400 3.7 5.4j 1.3 1.5j
2450 6.9 5.0j 1.5 1.6j
2500 8.7 2.0j 1.5 1.6j
Fig 1. De finition of transistor impeda nc e
001aaf059
drain
Z
L
Z
S
gate
Printed-Circuit Board (PCB): Rogers 4350B; r = 3.5; thickness = 0.508 mm;
thickness copper plating = 35 m.
See Table 9 for a list of components.
Fig 2. Comp on en t layout for application circuit
DDD
&
& & &
&
&
5
&
&
BLF2425M7L140; BLF2425M7LS140 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3 — 6 September 2012 5 of 11
NXP Semiconductors BLF2425M7L(S)140
Power LDMOS transistor
7.4 Graphical data
Table 9. List of components
For test circuit see Figure 2.
Component Description Value Remarks
C1, C4, C5 multilayer ceramic chip capacitor 15 pF ATC100B
C2, C6 multilayer ceramic chip capacitor 10 F, 50 V Murata
C3 multilayer ceramic chip capacitor 100 nF Murata
C7 multilayer ceramic chip capacitor 62 pF ATC100B
C8 electrolytic capacitor 22 F, 63 V
R1 resistor 10 SMD 0805; Bourns
VDS = 28 V; IDq = 1300 mA.
(1) Gp at f = 2400 MHz
(2) Gp at f = 2450 MHz
(3) Gp at f = 2500 MHz
(4) D at f = 2400 MHz
(5) D at f = 2450 MHz
(6) D at f = 2500 MHz
VDS = 28 V; IDq = 1300 mA.
(1) Gp at f = 2400 MHz
(2) Gp at f = 2450 MHz
(3) Gp at f = 2500 MHz
(4) D at f = 2400 MHz
(5) D at f = 2450 MHz
(6) D at f = 2500 MHz
Fig 3. Power gain and drain efficiency as function of
load power; typical values Fig 4. Power gain and drain efficiency as function of
load power; typical values
DDD
3/G%P
*S
S
S
G%
Ș'
DDD
3/:
*S
S
S
G%
Ș'
BLF2425M7L140; BLF2425M7LS140 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3 — 6 September 2012 6 of 11
NXP Semiconductors BLF2425M7L(S)140
Power LDMOS transistor
8. Package outline
Fig 5. Package outline SOT502A
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT502A 03-01-10
12-05-02
0 5 10 mm
scale
Flanged ceramic package; 2 mounting holes; 2 leads SOT502A
p
L
AF
b
D
U2
H
Q
c
1
3
2
D1
E
A
C
q
U1
C
B
E1
M M
w2
UNIT A
mm
Db
12.83
12.57 0.15
0.08 20.02
19.61 9.53
9.25 19.94
18.92 9.91
9.65
4.72
3.43
cU2
0.25 0.5127.94
qw
2
w1
F
1.14
0.89
U1
34.16
33.91
L
5.33
4.32
p
3.38
3.12
Q
1.70
1.45
EE
1
9.50
9.30
inches 0.505
0.495 0.006
0.003 0.788
0.772
D1
19.96
19.66
0.786
0.774 0.375
0.364 0.785
0.745 0.390
0.380
0.186
0.135 0.01 0.021.100
0.045
0.035 1.345
1.335
0.210
0.170 0.133
0.123 0.067
0.057
0.374
0.366
H
DIMENSIONS (millimetre dimensions are derived from the original inch dimensions)
w1AB
M M M
BLF2425M7L140; BLF2425M7LS140 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3 — 6 September 2012 7 of 11
NXP Semiconductors BLF2425M7L(S)140
Power LDMOS transistor
Fig 6. Package outline SOT502B
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT502B 07-05-09
12-05-02
0 5 10 mm
scale
Earless flanged ceramic package; 2 leads SOT502B
AF
b
D
U2
L
H
Q
c
1
3
2
D1
E
D
U1
D
E1
M M
w2
UNIT A
mm
Db
12.83
12.57 0.15
0.08 20.02
19.61 9.53
9.25 19.94
18.92 9.91
9.65
4.72
3.43
cU2
0.25
w2
F
1.14
0.89
U1
20.70
20.45
L
5.33
4.32
Q
1.70
1.45
EE
1
9.50
9.30
inches 0.505
0.495 0.006
0.003 0.788
0.772
D1
19.96
19.66
0.786
0.774 0.375
0.364 0.785
0.745 0.390
0.380
0.186
0.135 0.010
0.045
0.035 0.815
0.805
0.210
0.170 0.067
0.057
0.374
0.366
H
DIMENSIONS (millimetre dimensions are derived from the original inch dimensions)
BLF2425M7L140; BLF2425M7LS140 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3 — 6 September 2012 8 of 11
NXP Semiconductors BLF2425M7L(S)140
Power LDMOS transistor
9. Handling information
10. Abbreviations
11. Revision history
CAUTION
This device is sensitive to ElectroStatic Discharge (ESD). Observe precautions for handling
electrostatic sensitive devices.
Such precautions are described in the ANSI/ESD S20.20, IEC/ST 61340-5, JESD625-A or
equivalent standards.
Table 10. Abbreviations
Acronym Description
CW Continuous Wave
ESD ElectroStatic Discharge
LDMOS Laterally Diffused Metal Oxide Semiconductor
SMD Surface Mounted Device
VSWR Voltage Standing Wave Ratio
Table 11. Revision history
Document ID Release date Data sheet status Change notice Supersedes
BLF2425M7L140_2425M7LS140 v.3 20120906 Product data sheet - BLF2425M7L140_
2425M7LS140 v.2
Modifications: •The status of this document has been changed to Product data sheet.
•Table 1 on page 1: some changes have been made.
•Table 6 on page 3: some changes have been made.
•Table 7 on page 3: some changes have been made.
BLF2425M7L140_2425M7LS140 v.2 20120420 Objective data sheet - BLF2425M7L140_
2425M7LS140 v.1
BLF2425M7L140_2425M7LS140 v.1 20120130 Objective data sheet - -
BLF2425M7L140; BLF2425M7LS140 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3 — 6 September 2012 9 of 11
NXP Semiconductors BLF2425M7L(S)140
Power LDMOS transistor
12. Legal information
12.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
12.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
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Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall pre vail.
Product specificat io n — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
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Applications — Applications that are described herein for any of these
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representation or warranty tha t such application s will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applicati ons or customer product
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NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
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customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
the quality and reliability of the device.
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products are sold subject to the general terms and conditions of commercial
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other industrial or intellectual property rights.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] dat a sheet Production This document contain s the product specification.
BLF2425M7L140; BLF2425M7LS140 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3 — 6 September 2012 10 of 11
NXP Semiconductors BLF2425M7L(S)140
Power LDMOS transistor
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Non-automotive qualified products — Unless this data sheet expressly
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12.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
13. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors BLF2425M7L(S)140
Power LDMOS transistor
© NXP B.V. 2012. All rights reserved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 6 September 2012
Document identifier: BLF2425M7L140; BLF2425M7LS140
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
14. Contents
1 Product profile. . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 General description . . . . . . . . . . . . . . . . . . . . . 1
1.2 Features and benefits. . . . . . . . . . . . . . . . . . . . 1
1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 Pinning information. . . . . . . . . . . . . . . . . . . . . . 2
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2
5 Thermal characteristics . . . . . . . . . . . . . . . . . . 2
6 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 3
7 Test information. . . . . . . . . . . . . . . . . . . . . . . . . 3
7.1 Ruggedness in class-AB operation . . . . . . . . . 3
7.2 Impedance information. . . . . . . . . . . . . . . . . . . 4
7.3 Circuit information. . . . . . . . . . . . . . . . . . . . . . . 4
7.4 Graphical data . . . . . . . . . . . . . . . . . . . . . . . . . 5
8 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 6
9 Handling information. . . . . . . . . . . . . . . . . . . . . 8
10 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . . 8
11 Revision history. . . . . . . . . . . . . . . . . . . . . . . . . 8
12 Legal information. . . . . . . . . . . . . . . . . . . . . . . . 9
12.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 9
12.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
12.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
12.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 10
13 Contact information. . . . . . . . . . . . . . . . . . . . . 10
14 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
