© Semiconductor Components Industries, LLC, 2010
January, 2010 − Rev. 0
1Publication Order Number:
MC74HC151A/D
MC74HC151A
8-Input Data
Selector/Multiplexer
High−Performance Silicon−Gate CMOS
The MC74HC151 is identical in pinout to the LS151. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
This device selects one of the eight binary Data Inputs, as
determined by the Address Inputs. The Strobe pin must be at a low
level for the selected data to appear at the outputs. If Strobe is high, the
Y output is forced to a low level and the Y output is forced to a high
level.
The HC151 is similar in function to the HC251 which has 3−state
outputs.
Features
•Output Drive Capability: 10 LSTTL Loads
•Outputs Directly Interface to CMOS, NMOS, and TTL
•Operating Voltage Range: 2 to 6 V
•Low Input Current: 1 mA
•High Noise Immunity Characteristic of CMOS Devices
•These are Pb−Free Devices
Figure 1. Logic Diagram
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
STROBE
Y
Y
DATA
OUTPUTS
DATA
INPUTS
ADDRESS
INPUTS
5
6
4
3
2
1
15
14
13
12
11
10
9
7
PIN 16 = VCC
PIN 8 = GND
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MARKING
DIAGRAMS
SOIC−16
D SUFFIX
CASE 751B
TSSOP−16
DT SUFFIX
CASE 948F
1
16
1
16
HC151AG
AWLYWW
HC
151A
ALYWG
G
1
16
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G= Pb−Free Package
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
ORDERING INFORMATION
(Note: Microdot may be in either location)
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
D3
D0
D1
D2
STROBE
Y
Y
GND
D7
D6
D5
D4
VCC
A1
A0
A2
PIN ASSIGNMENT
FUNCTION TABLE
Inputs Outputs
A2 A1 A0 Strobe Y Y
XXX H LH
L L L L D0 D0
L L H L D1 D1
L H L L D2 D2
L H H L D3 D3
H L L L D4 D4
H L H L D5 D5
H H L L D6 D6
H H H L D7 D7
D0, D1, …, D7 = the level of the respective D in-
put.
1
16
MC74HC151A
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2
MAXIMUM RATINGS
Symbol Parameter Value Unit
VCC DC Supply Voltage (Referenced to GND) −0.5 to +7.0 V
Vin DC Input Voltage (Referenced to GND) −1.5 to VCC + 1.5 V
Vout DC Output Voltage (Referenced to GND) −0.5 to VCC + 0.5 V
Iin DC Input Current, per Pin ±20 mA
Iout DC Output Current, per Pin ±25 mA
ICC DC Supply Current, VCC and GND Pins ±50 mA
PDPower Dissipation in Still Air SOIC Package
TSSOP Package
500
TBD
mW
Tstg Storage Temperature −65 to +150 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect device
reliability.
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V
Vin, Vout DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V
TAOperating Temperature, All Package Types −55 +125 °C
tr, tfInput Rise and Fall Time VCC = 2.0 V
(Figure 2) VCC = 4.5 V
VCC = 6.0 V
0
0
0
1000
500
400
ns
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Symbol Parameter Test Conditions
VCC
V
Guaranteed Limit
Unit
− 55 to
25°Cv 85°Cv 125°C
VIH Minimum High−Level Input
Voltage
Vout = 0.1 V or VCC − 0.1 V
|Iout| v 20 mA
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
VIL Maximum Low−Level Input
Voltage
Vout = 0.1 V or VCC − 0.1 V
|Iout| v 20 mA
2.0
4.5
6.0
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
VOH Minimum High−Level Output
Voltage
Vin = VIH or VIL
|Iout| v 20 mA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
Vin = VIH |Iout| v 4.0 mA
|Iout| v 5.2 mA
4.5
6.0
3.98
5.48
3.84
5.34
3.70
5.20
VOL Maximum Low−Level Output
Voltage
Vin = VIH or VIL
|Iout| v 20 mA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
Vin = VIH or VIL |Iout| v 4.0 mA
|Iout| v 5.2 mA
4.5
6.0
0.26
0.26
0.33
0.33
0.40
0.40
Iin Maximum Input Leakage Current Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 mA
ICC Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0 mA
6.0 8 80 160 mA
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
MC74HC151A
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3
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Symbol Parameter
VCC
V
Guaranteed Limit
Unit
− 55 to
25°Cv 85°Cv 125°C
tPLH,
tPHL
Maximum Propagation Delay, Input D to Output Y
(Figures 2 and 7)
2.0
4.5
6.0
170
34
29
215
43
37
255
51
43
ns
tPLH,
tPHL
Maximum Propagation Delay, Input D to Output Y
(Figures 4 and 7)
2.0
4.5
6.0
185
37
31
230
46
39
280
56
48
ns
tPLH,
tPHL
Maximum Propagation Delay, Input D to Output Y
(Figures 3 and 7)
2.0
4.5
6.0
185
37
31
230
46
39
280
56
48
ns
tPLH,
tPHL
Maximum Propagation Delay, Input A to Output Y
(Figures 3 and 7)
2.0
4.5
6.0
205
41
35
255
51
43
310
62
53
ns
tPLH,
tPHL
Maximum Propagation Delay, Input D to Output Y
(Figures 5 and 7)
2.0
4.5
6.0
125
25
21
155
31
26
190
38
32
ns
tPLH,
tPHL
Maximum Propagation Delay, Strobe to Output Y
(Figures 6 and 7)
2.0
4.5
6.0
125
25
21
155
31
26
190
38
32
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 2, 4 and 7)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
Cin Maximum Input Capacitance −10 10 10 pF
CPD Power Dissipation Capacitance (Per Package)
Typical @ 25°C, VCC = 5.0 V
pF
36
PIN DESCRIPTIONS
INPUTS
D0, D1, … , D7 (Pins 4, 3, 2, 1, 15, 14, 13, 12)
Data inputs. Data on any one of these eight binary inputs
may be selected to appear on the output.
CONTROL INPUTS
A0, A1, A2 (Pins 11, 10, 9)
Address inputs. The data on these pins are the binary
address of the selected input (see the Function Table).
Strobe (Pin 7)
Strobe. This input pin must be at a low level for the
selected data to appear at the outputs. If the Strobe pin is
high, the Y output is forced to a low level and the Y output
is forced to a high level.
OUTPUTS
Y, Y (Pins 5, 6)
Data outputs. The selected data is presented at these pins
in both true (Y output) and complemented (Y output) forms.
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4
SWITCHING WAVEFORMS
STROBE
Y
Figure 2. Figure 3.
Figure 4.
tr
tf
tPHL
tPLH
tTHL
tTLH
STROBE 10%
50%
VCC
GND
tf
tr
INPUT D
OUTPUT Y
10%
50%
90%
10%
50%
90%
tTLH
tPLH tPHL
tTHL
trtf
VCC
GND
INPUT D
OUTPUT Y
tPHL tPLH
tTHL tTLH
10%
50%
90%
10%
50%
90%
tftr
VCC
GND
10%
50%
90%
tPHL tPLH
10%
50%
90%
tTHL tTLH
VCC
GND
VCC
GND
50%
INPUT A
tPLH tPHL
50%
OUTPUT
Y OR Y
10%
50%
90%
90%
Y
*Includes all probe and jig capacitance
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
Figure 5.
Figure 6. Figure 7. Test Circuit
VALIDVALID
MC74HC151A
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5
Y
Y
5
6
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
4
3
2
1
15
14
13
12
11
10
9
7
DATA
INPUTS
Figure 8. Expanded Logic Diagram
DATA
OUTPUTS
ADDRESS
INPUTS
STROBE
ORDERING INFORMATION
Device Package Shipping†
MC74HC151ADG SOIC−16
(Pb−Free)
48 Units / Rail
MC74HC151ADR2G SOIC−16
(Pb−Free)
2500 Tape & Reel
MC74HC151ADTR2G TSSOP−16* 2500 Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
MC74HC151A
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6
PACKAGE DIMENSIONS
SOIC−16
CASE 751B−05
ISSUE K NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
18
16 9
SEATING
PLANE
F
J
M
RX 45_
G
8 PLP
−B−
−A−
M
0.25 (0.010) B S
−T−
D
K
C
16 PL
S
B
M
0.25 (0.010) A S
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A9.80 10.00 0.386 0.393
B3.80 4.00 0.150 0.157
C1.35 1.75 0.054 0.068
D0.35 0.49 0.014 0.019
F0.40 1.25 0.016 0.049
G1.27 BSC 0.050 BSC
J0.19 0.25 0.008 0.009
K0.10 0.25 0.004 0.009
M0 7 0 7
P5.80 6.20 0.229 0.244
R0.25 0.50 0.010 0.019
____
6.40
16X
0.58
16X 1.12
1.27
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT*
16
89
8X
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
MC74HC151A
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7
PACKAGE DIMENSIONS
TSSOP−16
DT SUFFIX
CASE 948F−01
ISSUE B
ÇÇÇ
ÇÇÇ
ÇÇÇ
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A4.90 5.10 0.193 0.200
B4.30 4.50 0.169 0.177
C−−− 1.20 −−− 0.047
D0.05 0.15 0.002 0.006
F0.50 0.75 0.020 0.030
G0.65 BSC 0.026 BSC
H0.18 0.28 0.007 0.011
J0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L6.40 BSC 0.252 BSC
M0 8 0 8
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
____
SECTION N−N
SEATING
PLANE
IDENT.
PIN 1
18
16 9
DETAIL E
J
J1
B
C
D
A
K
K1
H
G
ÉÉÉ
ÉÉÉ
DETAIL E
F
M
L
2X L/2
−U−
S
U0.15 (0.006) T
S
U0.15 (0.006) T
S
U
M
0.10 (0.004) V S
T
0.10 (0.004)
−T−
−V−
−W−
0.25 (0.010)
16X REFK
N
N
7.06
16X
0.36 16X
1.26
0.65
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT*
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
MC74HC151A
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8
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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent
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MC74HC151A/D
PUBLICATION ORDERING INFORMATION
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Phone: 421 33 790 2910
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Phone: 81−3−5773−3850
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