HI-3282, HI-3282B
ARINC 429
Serial Transmitter and Dual Receiver
GENERAL DESCRIPTION
The HI-3282 is a silicon gate CMOS device for interfacing
the ARINC 429 serial data bus to a 16-bit parallel data bus.
Two receivers and an independent transmitter are
provided. The receiver input circuitry and logic are
designed to meet the ARINC 429 specifications for loading,
level detection, timing, and protocol. The ARINC inputs of
the HI-3282-10 configurations also have internal lightning
protection to DO-160D, Level 3. The transmitter section
provides the ARINC 429 communication protocol. An
external ARINC 429 Line Driver such as the Holt HI-3182 or
HI-8585 is required to translate the 5 volt logic outputs to
ARINC 429 drive levels.
The 16-bit parallel data bus exchanges the 32-bit ARINC
data word in two steps when either loading the transmitter
or interrogating the receivers. The data bus interfaces with
CMOS and TTL.
Timing of all the circuitry begins with the master clock input,
CLK. For ARINC 429 applications, the master clock
frequency is 1 MHz.
Each independent receiver monitors the data stream with a
sampling rate 10 times the data rate. The sampling rate is
software selectable at either 1MHz or 125KHz. The results
of a parity check are available as the 32ndARINC bit.
The transmitter has a First In, First Out (FIFO) memory to
store 8 ARINC words for transmission. The data rate of the
transmitter is software selectable by dividing the master
clock, CLK, by either 10 or 80. The master clock is used to
set the timing of the ARINC transmission within the required
resolution.
The HI-3282BPJx product has a minimum low speed data
rate of 6.5K BPS.
APPLICATIONS
• Avionics data communication
• Serial to parallel conversion
• Parallel to serial conversion
FEATURES
• ARINC specification 429 compatible
•
• 16-Bit parallel data bus
• Direct receiver interface to ARINC bus
• Timing control 10 times the data rate
• Selectable data clocks
• Automatic transmitter data timing
• Self test mode
• Parity functions
• Low power, single 5 volt supply
• Industrial & extended temperature ranges
Compatible with Industry-standard alternate
parts
• Small footprint 44-pin PQFP package option
• Internal Lightning Protection of ARINC inputs
per DO-160D, Level 3 in -10 configurations
44-Pin Plastic Quad Flat Pack (PQFP)
August 2013
PIN CONFIGURATION (Top View)
44 - N/C
43 - 429DI2(B)
42 - 429DI2(A)
41 - 429DI1(B)
40 - 429DI1(A)
39 - VCC
38 -
37 -
36 - TXCLK
35 - CLK
34 - N/C
DBCEN
MR
33 - N/C
32 - N/C
31 - X
30 - ENTX
29 -
28 -429DO
27 - TX/R
26 -
25 -
24 - BD00
23 - BD01
CWSTR
429DO
PL2
PL1
N/C-12
BD10 - 13
BD09 - 14
BD08 - 15
BD07 - 16
BD06 - 17
GND-18
BD05 - 19
BD04 - 20
BD03 - 21
BD02 - 22
N/C - 1
-2
-3
SEL - 4
-5
-6
BD15 - 7
BD14 - 8
BD13 - 9
BD12 - 10
BD11 - 11
D/R1
D/R2
EN1
EN2
HI-3282PQI
HI-3282PQI-10
HI-3282PQT
&
HI-3282PQT-10
(See page 10 for additional pin configurations)
(DS3282 Rev. P) 08/13
HOLT INTEGRATED CIRCUITS
www.holtic.com
(
PIN DESCRIPTION
HI-3282, HI-3282B
SYMBOL FUNCTION DESCRIPTION
VCC POWER +5V ±5%
429DI1 (A) INPUT ARINC receiver 1 positive input
429DI1 (B) INPUT ARINC receiver 1 negative input
429DI2 (A) INPUT ARINC receiver 2 positive input
429DI2 (B) INPUT ARINC receiver 2 negative input
OUTPUT Receiver 1 data ready flag
OUTPUT Receiver 2 data ready flag
SEL INPUT Receiver data byte selection (0 = BYTE 1) (1 = BYTE 2)
INPUT Data Bus control, enables receiver 1 data to outputs
INPUT Data Bus control, enables receiver 2 data to outputs if is high
BD15 I/O Data Bus
BD14 I/O Data Bus
BD13 I/O Data Bus
BD12 I/O Data Bus
BD11 I/O Data Bus
BD10 I/O Data Bus
BD09 I/O Data Bus
BD08 I/O Data Bus
BD07 I/O Data Bus
BD06 I/O Data Bus
GND POWER 0 V
BD05 I/O Data Bus
BD04 I/O Data Bus
BD03 I/O Data Bus
BD02 I/O Data Bus
BD01 I/O Data Bus
BD00 I/O Data Bus
INPUT Latch enable for byte 1 entered from data bus to transmitter FIFO.
INPUT Latch enable for byte 2 entered from data bus to transmitter FIFO. Must follow
TX/R OUTPUT Transmitter ready flag. Goes low when ARINC word loaded into FIFO. Goes high
after transmission and FIFO empty.
429DO OUTPUT "ONES" data output from transmitter.
OUTPUT "ZEROES" data output from transmitter.
ENTX INPUT Enable Transmission
INPUT Clock for control word register
CLK INPUT Master Clock input
TX CLK OUTPUT Transmitter Clock equal to Master Clock (CLK), divided by either 10 or 80.
INPUT Master Reset, active low
INPUT Data bit control Enable. (Active low, with internal pull up to VDD).
D/R1
D/R2
EN1
EN2 EN1
PL1
PL2 PL1.
429DO
CWSTR
MR
DBCEN
HOLT INTEGRATED CIRCUITS
2
ARINC 429 DATA FORMAT
The following table shows the bit positions in exchanging data with
the receiver or the transmitter. ARINC bit 1 is the first bit
transmitted or received.
DATA BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD
BUS 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
ARINC 13 12 11 10 9 31 30 32 12345678
BIT
BYTE 1
FUNCTIONAL DESCRIPTION
DATA
BUS FUNCTION CONTROL DESCRIPTION
PIN
BD04 PAREN Enables parity bit insertion into
Transmitter data bit 32
If enabled, an internal connection
BDO5 SELF TEST 0 = ENABLE is made passing 429DO and
to the receiver logic inputs
RECEIVER 1 If enabled, ARINC bits 9 and,
BDO6 DECODER 1 = ENABLE 10 must match the next two
control word bits
If Receiver 1 Decoder is
BDO7 - - enabled, the ARINC bit 9
must match this bit
If Receiver 1 Decoder is
BDO8 - - enabled, the ARINC bit 10
must match this bit
RECEIVER 2 If enabled, ARINC bits 9 and
BDO9 DECODER 1 = ENABLE 10 must match the next two
control word bits
If Receiver 2 Decoder is
BD10 - - enabled, then ARINC bit 9
must match this bit
If Receiver 2 Decoder is
BD11 - - enabled, then ARINC bit 10
must match this bit
INVERT Logic 0 enables normal odd parity
BD12 XMTR 1 = ENABLE and Logic 1 enables even parity
PARITY output in transmitter 32nd bit
BD13 XMTR DATA 0 = ÷10 CLK is divided either by 10 or
CLK SELECT 1 = ÷80 80 to obtain XMTR data clock
BD14 RCVR DTA 0 = ÷10 CLK is divided either by 10 or
CLK SELECT 1 = ÷80 80 to obtain RCVR data clock
429DO
CONTROL WORD REGISTER
The HI-3282 contains 11 data flip flops whose D inputs are con-
nected to the data bus and clocks connected to . Each
flip flop provides options to the user as follows:
CWSTR
RECEIVERS
ARINC BUS INTERFACE
Figure 1 shows the input circuit for each receiver. The ARINC 429
specification requires the following detection levels:
The HI-3282 guarantees recognition of these levels with a common
mode Voltage with respect to GND less than ±5V for the worst case
condition (4.75V supply and 13V signal level).
The tolerances in the design guarantee detection of the above
levels, so the actual acceptance ranges are slightly larger. If the
ARINC signal is out of the actual acceptance ranges, including the
nulls, the chip rejects the data.
STATE DIFFERENTIAL VOLTAGE
ONE +6.5 Volts to +13 Volts
NULL +2.5 Volts to -2.5 Volts
ZERO -6.5 Volts to -13 Volts
RECEIVER LOGIC OPERATION
Figure 2 shows a block diagram of the logic section of each receiver.
BYTE 2
DATA BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD
BUS 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
ARINC 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14
BIT
HI-3282, HI-3282B
v
cc
v
cc
GND
GND
429DI1 (B)
429DI2 (B)
OR
429DI1 (A)
429DI2 (A)
OR
DIFFERENTIAL
AMPLIFIERS
ONES
COMPARATORS
NULL
ZEROES
FIGURE 1.
ARINC RECEIVER INPUT
HOLT INTEGRATED CIRCUITS
3
NOTE: After writing to the Control Word a master reset should
be applied.
BIT TIMING
The ARINC 429 specification contains the following timing
specification for the received data:
100K BPS ± 1% 12K -14.5K BPS
(HI-3282BPJx-xx only - 6.5K BPS min.)
1.5 ± 0.5 µsec 10 ± 5 µsec
1.5 ± 0.5 µsec 10 ± 5 µsec
5 µsec ± 5% 34.5 to 41.7 µsec
HIGH SPEED LOW SPEED
BIT RATE
PULSE RISE TIME
PULSE FALL TIME
PULSE WIDTH
(HI-3282BPJx-xx only - 76.9 µsec max.)
The 32nd bit of received ARINC words stored in the receive FIFO
is used as a Parity Flag indicating whether good Odd parity is re-
ceived from the incoming ARINC word.
The parity bit is reset to indicate correct parity was received
and the resulting word is then written to the receive FIFO.
The receiver sets the 32nd bit to a “1”, indicating a parity error
and the resulting word is then written to the receive FIFO.
Therefore, the 32nd bit retrieved from the receiver FIFO will always
be a “0” when valid (odd parity) ARINC 429 words are received.
Once 32 valid bits are recognized, the receiver logic generates an
End of Sequence (EOS). If the receiver decoder is enabled and
the 9th and 10th ARINC bits match the control word program bits
or if the receiver decoder is disabled, then the EOS clocks the
RECEIVER PARITY
Odd Parity Received
Even Parity Received
RETRIEVING DATA
FUNCTIONAL DESCRIPTION (cont.)
SEL
EN
D/R
DECODER
CONTROL
BITS
/
MUX
CONTROL
LATCH
ENABLE
CONTROL
32 TO 16 DRIVER
32 BIT LATCH
32 BIT SHIFT REGISTER
TO PINS
CONTROL
BIT BD14
CLOCK
OPTION
CLOCK
CLK
BIT
COUNTER
AND
END OF
SEQUENCE
PARITY
CHECK
32ND
BIT
DATA
BIT CLOCK
EOS
WORD GAP
WORD GAP
TIMER
BIT CLOCK
END
START
SEQUENCE
CONTROL
ERROR
CLOCK
ERROR
DETECTION
SHIFT REGISTER
SHIFT REGISTER
NULL
ZEROS
SHIFT REGISTER
ONES
EOS
BITS9&10
FIGURE 2. RECEIVER BLOCK DIAGRAM
HI-3282, HI-3282B
data ready flag flip flop to a "1", or (or both) will go low.
The data flag for a receiver will remain low until after ARINC
bytes from that receiver are retrieved. This is accomplished by
activating with SEL, the byte selector, low to retrieve the first
byte and activating with SEL high to retrieve the second byte.
retrieves data from receiver 1 and retrieves data from
receiver 2. If another ARINC word is received and a new EOS
occurs before the two bytes are retrieved, the data is overwritten
by the new word.
D/R1 D/R2
EN
EN
EN1 EN2
both
INTERNAL LIGHTNING PROTECTION (-10 Only)
APPLICATION NOTE 300
The HI-3282-10 configurations are similar to the HI-3282 with the
exception that it allows an external 10K to 15K ohm resistor to be
added in series with each ARINC input without affecting the
ARINC input thresholds. This option is especially useful in
applications where lightning protection circuitry is also required.
The design of the HI-3282-10 device requires the external
10K to 15K ohm series resistors for proper ARINC level detection.
The typical 10 volt differential signal is translated and input to a
window comparator and latch. The comparator levels are set so
that, with the external 10K to 15K ohm resistors, they are just
below the standard 6.5 V minimum ARINC data threshold and just
above the 2.5 V maximum ARINC null threshold.
The receivers of the HI-3282-10 when used with external
15K ohm resistors will withstand DO-160F, Level 3, waveforms 3,
4, 5A and 5B. No additional lightning protection circuit is
necessary.
Please refer to the Holt AN-300 Application Note for additional
information and recommendations on lightning protection of Holt
Line Drivers and Receivers.
HOLT INTEGRATED CIRCUITS
4
CONTROL REGISTER
BIT BD13
FIGURE 3. TRANSMITTER BLOCK DIAGRAM
DATA
CLOCK
PL1
PL2
CLK
TX CLK
PARITY
GENERATOR DATA AND
NULL TIMER
SEQUENCER
BIT
AND
WORD GAP
COUNTER
START
SEQUENCE
WORD COUNTER
AND
FIFO CONTROL
INCREMENT
WORD COUNT
DATA CLOCK
DIVIDER
FIFO
LOADING
SEQUENCER
429DO
429DO
8 X 31 FIFO
31 BIT PARALLEL
LOAD SHIFT REGISTER
BIT CLOCK
WORD CLOCK
ADDRESS
LOAD
DATA BUS
TX/R
ENTX
CONTROL REGISTER BD04, BD12
DBCEN
FUNCTIONAL DESCRIPTION (cont.)
TRANSMITTER
Ablock diagram of the transmitter section is shown in Figure 3.
The FIFO is loaded sequentially by first pulsing to load byte 1
and then to load byte 2. The control logic automatically loads
the 31 bit word in the next available position of the FIFO. If TX/R,
the transmitter ready flag, is high (FIFO empty), then 8 words,
each 31 bits long, may be loaded. If TX/R is low, then only the
available positions may be loaded. If all 8 positions are full, the
FIFO ignores further attempts to load data.
When ENTX goes high, enabling transmission, the FIFO
positions are incremented with the top register loading into the
data transmission shift register. Within 2.5 data clocks the first
data bit appears at either 429DO or . The 31 bits in the
data transmission shift register are presented sequentially to the
outputs in theARINC 429 format with the following timing:
ARINC DATABIT TIME 10 Clocks 80 Clocks
DATA BIT TIME 5 Clocks 40 Clocks
NULL BIT TIME 5 Clocks 40 Clocks
WORD GAP TIME 40 Clocks 320 Clocks
The word counter detects when all loaded positions are
transmitted and sets the transmitter ready flag, TX/R, high.
FIFO OPERATION
DATA TRANSMISSION
PL1
PL2
429DO
HIGH SPEED LOW SPEED
TRANSMITTER PARITY
Control register bit BD04 (PAREN) enables parity bit insertion into
transmitter data bit 32. Parity is always inserted if DBCEN is open
or high. If DBCEN is low, logic 0 on PAREN inserts data on bit 32,
and logic 1 on PAREN inserts parity on bit 32.
HI-3282, HI-3282B
The parity generator counts the ONES in the 31-bit word. If the BD12
control word bit is set low, the 32nd bit transmitted will make parity
odd. If the control bit is high, the parity is even.
If the BD05 control word bit is set low, 429DO or are internally
connected to the receivers inputs, bypassing the interface circuitry.
Data to Receiver 1 is as transmitted and data to Recevier 2 is the
complement. 429DO and outputs remain active during self
test.
The two receivers are independent of the transmitter. Therefore,
control of data exchanges is strictly at the option of the user. The only
restrictions are:
1. The received data may be overwritten if not retrieved within
oneARINC word cycle.
2. The FIFO can store 8 words maximum and ignores attempts
to load addition data if full.
3. Byte 1 of the transmitter data must be loaded first.
4. Either byte of the received data may be retrieved first. Both
bytes must be retrieved to clear the data ready flag.
5. After ENTX, transmission enable, goes high it cannot go low
until TX/R, transmitter ready flag, goes high. Otherwise, one
ARINC word is lost during transmission.
SELF TEST
SYSTEM OPERATION
429DO
429DO
MASTER RESET ( )MR
On a Master Reset data transmission and reception are immedi-
ately terminated, the transmit FIFO and receivers cleared as are
the transmit and receive flags. The Control Register is not affected
by a Master Reset.
HOLT INTEGRATED CIRCUITS
5
REPEATER OPERATION
The repeater mode of operation allows a data word that has been
received by the HI-3282 to be placed directly into its FIFO for
transmission. After a 32-bit word has been shifted into the receiver
shift register, the flag will go low. A logic "0" is placed on the SEL
line and is strobed. This is the same procedure as for normal
receiver operation and it places the lower byte (16) of the data word
on the data bus. By strobing at the same time as
D/R
EN
PL1 EN, the byte
FUNCTIONAL DESCRIPTION (cont.)
will also be placed into the transmitter FIFO. SEL is then taken high
and is strobed again to place the upper byte of the data word on
the data bus. By strobing at the same time as , the second
byte will also be placed into the FIFO. The data word is now ready to
be transmitted according to the parity programmed into the control
word register.
In normal operation, either byte of a received data word may be read
from the receiver latches first by use of SEL input. During repeater
operation however, the lower byte of the data word must be read
first. This is necessary because, as the data is being read, it is also
being loaded into the FIFO and the transmitter FIFO is always
loaded with the lower byte of the data word first.
EN
PL2 EN
RECEIVER OPERATON
DATA READY FLAG D/R
ARINC DATA
BYTE SELECT SEL
ENABLE BYTE ON BUS EN
DATA BUS
BIT 31 BIT 32
SELEN
t
D/R
t
ENSEL
t
DATAEN
t
D/REN
t
END/R
t
EN
t
ENSEL
tSELEN
t
DATAEN
t
ENDATA
tENDATA
t
ENEN
t
DON'T CARE DON'T CARE DON'T CARE
BYTE 1 VALID BYTE 2 VALID
LOADING CONTROL WORD
CWHLD
t
CWSET
t
CWSTR
t
DATA BUS
CWSTR
VALID
DATA RATE - EXAMPLE PATTERN
429DO
429DO
ARINC BIT
NULL
DATA DATA DATA
NULL NULL
WORD GAP BIT 1
NEXT WORD
BIT 32
BIT 31
BIT 30
TIMING DIAGRAMS
HI-3282, HI-3282B
HOLT INTEGRATED CIRCUITS
6
TIMING DIAGRAMS (cont.)
REPEATER OPERATION TIMING
DON'T CARE
429DI
D/R
EN
PL1
PL2
SEL
TX/R
ENTX
429DO
BIT 32
DON'T CARE
D/R
tEN
t
D/REN
tENEN
tEN
t
END/R
t
SELEN
tENSEL
t
ENPL
tPLEN
tSELEN
t
ENSEL
t
ENPL
tPLEN
t
TX/R
t
TX/REN
t
ENDAT
t
ENTX/R
t
DTX/R
t
NULL
t
BIT 1 BIT 32
TRANSMITTING DATA
ARINC BIT
429DO
or
429DO
PL2
ENTX
TX/R
PL2EN
t
ENDAT
t
DTX/R
t
ENTX/R
t
DATA
BIT 1
DATA
BIT 2
DATA
BIT 32
TRANSMITTER OPERATION
PL2
DWSET
t
DWHLD
t
TX/R
t
DWHLD
t
PL12
t
PL
t
DATA BUS
PL1
TX/R
BYTE 2 VALID
PL
t
PL12
t
DWSET
t
BYTE 1 VALID
HI-3282, HI-3282B
HOLT INTEGRATED CIRCUITS
7
LIMITS
PARAMETER CONDITIONS UNIT
SYMBOL
Differential Input Voltage: ONE V Common 6.5 10.0 13.0 V
ZERO V mode voltage less than ±5V -13.0 -10.0 -6.5 V
NULL V with respect to GND -2.5 0 2.5 V
Input Resistance: Differential R Includes the external 10K 12 K
To GND R resistors in series with each ARINC 12 27 K
To Vcc R input of a -10 configuration 12 27 K
Input Current: Input Sink I 200 µA
Input Source I -450 µA
Input Capacitance: Differential C 20 pF
(Guaranteed but not tested) To GND C 20 pF
To Vcc C 20 pF
Input Voltage: Input Voltage HI V 2.0 V
Input Voltage LO V 0.8 V
Input Current: Input Sink I 1.5 µA
Input Source I -1.5 µA
Input Voltage: Input Voltage HI V 2.0 V
Input Voltage LO V 0.8 V
Input Current: Input Sink I 10 µA
Input Source I -10 µA
Pull-up Current ( Pin) I -150 -50 A
Output Voltage: Logic "1" Output Voltage V I = -1.5mA 2.7 V
Logic "0" Output Voltage V I = 1.6mA 0.4 V
Output Current: Output Sink I V = 0.4V 1.6 mA
(Bi-directional Pins) Output Source I V = V - 0.4V -1.0 mA
Output Current: Output Sink I V = 0.4V 1.6 mA
(All Other Outputs) Output Source I V = V - 0.4V -1.0 mA
Output Capacitance: C 15 pF
Standby Supply Current: I 10 mA
Operating Supply Current: I 10 mA
MIN TYP MAX
ARINC INPUTS - Pins: 429DI1(A), 429DI1(B), 429DI2(A), 429DI2(B)
BI-DIRECTIONAL INPUTS - Pins:BD00-BD15
ALL OTHER INPUTS
OUTPUTS
SUPPLY INPUT
IH
IL
NUL
I
G
H
IH
IL
I
G
H
IH
IL
IH
IL
IH
IL
IH
IL
PU
OH OH
OL OL
OL OUT
OH OUT CC
OL OUT
OH OUT CC
O
CC1
CC2
W
µ
W
W
W
DCBEN
Power Dissipation 500mW
Operating Temperature Range: (Industrial) -40°C to +85°C
(Extended) -55°C to +125°C
Storage Temperature Range: -65°C to +150°C
ABSOLUTE MAXIMUM RATINGS
Supply Voltage Vcc -0.3V to +7V
Voltage at ARINC input pins -120V to +120V
Voltage at any other pin -0.3V to Vcc +0.3V
DC Current Drain per input pin 10mA
NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only.
Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS
HI-3282, HI-3282B
Vcc = 5V ±5%, GND = 0V, TA = Operating Temperature Range (unless otherwise specified).
HOLT INTEGRATED CIRCUITS
8
LIMITS
PARAMETER SYMBOL UNITS
MIN TYP MAX
Pulse Width - t 50 ns
Setup - DATA BUS Valid to HIGH t 50 ns
Hold - HIGH to DATA BUS Hi-Z t 0 ns
Delay - Start ARINC 32nd Bit to LOW: High Speed t 16 µs
Low Speed t 128 µs
Delay - LOW to L0W t 0 ns
Delay - LOW to HIGH t 200 ns
Setup - SEL to L0W t 10 ns
Hold - SEL to HIGH t 10 ns
Delay - L0W to DATA BUS Valid t 50 80 ns
Delay - HIGH to DATA BUS Hi-Z t 30 ns
Pulse Width - or t 80 ns
Spacing - HIGH to next L0W t 50 ns
Pulse Width - or t 50 ns
Setup - DATA BUS Valid to HIGH t 50 ns
Hold - HIGH to DATA BUS Hi-Z t 10 ns
Spacing - or t 0 ns
Delay - HIGH to TX/R LOW t 840 ns
Spacing - HIGH to ENTX HIGH t 0 µs
Delay - ENTX HIGH to 429DO or : High Speed t 25 µs
Delay - ENTX HIGH to 429DO or : Low Speed t 200 µs
Delay - 32nd ARINC Bit to TX/R HIGH t 50 ns
Spacing - TX/R HIGH to ENTX L0W t 0 ns
Delay - LOW to LOW t 0 ns
Hold - HIGH to HIGH t 0 ns
Delay - TX/R LOW to ENTX HIGH t 0 ns
t50 ns
±1%
CONTROL WORD TIMING
RECEIVER TIMING
FIFO TIMING
TRANSMISSION TIMING
REPEATER OPERATION TIMING
Master Reset Pulse Width
ARINC Data Rate and Bit Timing
CWSTR
CWSTR
CWSTR
D/R
D/R EN
EN D/R
EN
EN
EN
EN
EN1 EN2
EN EN
PL1 PL2
PL
PL
PL1 PL2
PL2
PL2
429D0
429D0
EN PL
PL EN
CWSTR
CWSET
CWHLD
D/R
D/R
D/REN
END/R
SELEN
ENSEL
ENDATA
DATAEN
EN
ENEN
PL
DWSET
DWHLD
PL12
TX/R
PL2EN
ENDAT
ENDAT
DTX/R
ENTX/R
ENPL
PLEN
TX/REN
MR
AC ELECTRICAL CHARACTERISTICS
Vcc = 5V, GND = 0V, TA = Operating Temperature Range and fclk = 1mhz 0.1% with 60/40 duty cycle+
HI-3282, HI-3282B
HOLT INTEGRATED CIRCUITS
9
PIN CONFIGURATION (Top View)
HI-3282CDI / HI-3282CDT / HI-3282CDM
40-PIN CERAMIC SIDE-BRAZED DIP
HI-3282CDI-10 / HI-3282CDT-10 / HI-3282CDM-10
DBCEN
MR MASTER RESET
CWSTR CONTROL WORD STROBE
429DO XMIT DATA
PL2 XMIT BYTE 2 LE
PL1 XMIT BYTE 1 LE
()
TX CLK (XMIT CLOCK OUT)
CLK (MASTER CLK IN)
NC
NC
()
ENTX (ENABLE XMIT)
()
429DO (XMIT DATA)
TX/R (XMIT READY FLAG)
()
()
BD00
BD01
BD02
BD03
BD04
BD05
GND
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Vcc
(REC. 1 INPUT) 429DI1(A)
(REC.1 INPUT) 429DI1(B)
(REC. 2 INPUT) 429DI2(A)
(REC. 2 INPUT) 429DI2(B)
()
()
(REC. BYTE SELECT) SEL
()
()
BD15
BD14
BD13
BD12
BD11
BD10
BD09
BD08
BD07
BD06
REC.1 DATA FLAG D/R1
REC.2 DATA FLAG D/R2
REC. 1 OUTPUT ENABLE EN1
REC. 2 OUTPUT ENABLE EN2
N/C 7
8
9
SEL 10
11
12
BD15 13
BD14 14
BD13 15
BD12 16
BD11 17
D/R1
D/R2
EN1
EN2
39 N/C
38 N/C
37
36 ENTX
35
34 429DO
33 TX/R
32
31
30 BD00
29 BD01
CWSTR
429DO
PL2
PL1
N/C 18
BD10 19
BD09 20
BD08 21
BD07 22
BD06 23
GND 24
BD05 25
BD04 26
BD03 27
BD02 28
6 N/C
5 429DI2(B)
4 429DI2(A)
3 429DI1(B)
2 429DI1(A)
1 VCC
44
43
42 TX CLK
41 CLK
40 N/C
DBCEN
MR
HI-3282PJI / HI-3282BPJI
HI-3282PJT / HI-3282BPJT
HI-3282PJI-10 / HI-3282BPJI-10
HI-3282PJT-10 / HI-3282BPJT-10
44-Pin J-Lead PLCC
HI-3282CLI / HI-3282CT / HI-3282CLM
44-Pin Leadless Chip Carrier (LCC)
HI-3282CLI-10 / HI-3282CT-10 / HI-3282CLM-10
DBCEN
HI-3282, HI-3282B
ADDITIONAL HI-3282 PIN CONFIGURATIONS (See page 1 for the 44-pin Plastic QFP)
HOLT INTEGRATED CIRCUITS
10
ORDERING INFORMATION
HI - 3282 (Ceramic)Cx x -xx
HI - 3282 (Plastic)xPxxx-xx
HI-3282, HI-3282B
PART PACKAGE
NUMBER DESCRIPTION
PJ 44 PIN PLASTIC J-LEAD PLCC (44J)
PQ 44 PIN PLASTIC QUAD FLAT PACK (44PQS)
PART TEMPERATURE BURN
NUMBER RANGE FLOW IN
I -40°C TO +85°C I No
T -55°C TO +125°C T No
M -55°C TO +125°C M Yes
PART PACKAGE
NUMBER DESCRIPTION
Blank Tin / Lead (Sn / Pb) Solder
F 100% Matte Tin (Pb-free RoHS compliant)
No dash number 35K Ohm 0
-10 (See Note 1) 25K Ohm 10K to 15K Ohm
PART INPUT SERIES RESISTANCE
NUMBER BUILT-IN REQUIRED EXTERNALLY
PART PACKAGE
NUMBER DESCRIPTION
CD 40 PIN CERAMIC SIDE BRAZED DIP (40C)
CL 44 PIN CERAMIC LEADLESS CHIP CARRIER (44S)
PART TEMPERATURE BURN LEAD
NUMBER RANGE FLOW IN FINISH
I -40°C TO +85°C I No Gold (Pb-free, RoHS compliant)
T -55°C TO +125°C T No Gold (Pb-free, RoHS compliant)
M -55°C TO +125°C M Yes Tin / Lead (Sn / Pb) Solder
No dash number 35K Ohm 0
-10 (See Note 1) 25K Ohm 10K to 15K Ohm
PART INPUT SERIES RESISTANCE
NUMBER BUILT-IN REQUIRED EXTERNALLY
NOTES:
1. The -10 configuration requires an external 10K to 15K ohm resistor in series with each ARINC input to
guarantee specified voltage thresholds. The 15K ohm resistors are required to withstand DO-160F, Level 3,
Waveforms 3,4,5A&5Bpininjection.
PART MINIMUM
NUMBER LOW SPEED DATA RATE
Blank 10.4 K BPS
B 6.5K BPS (PJ package only)
HOLT INTEGRATED CIRCUITS
11
REVISION HISTORY
P/N Rev. Date Description of Change
DS3282 L 02/24/09 Clarified the temperature ranges, series resistance values for “-10” devices, and Note (1) in
the Ordering Information.
M 12/21/10 Added HI-3282BPJx standard product with minimum low speed receive data rate of
6.5K BPS
N 05/21/12 Change tSELEN and tENSEL in AC Characteristics table from 0ns to 10ns. Update
PQFP package drawing to 44PMQS
O 07/30/13 Updated Receiver Parity and PQFP package information. Update Voltage at ARINC
input pins from +/-29V to +/-120V
P 08/28/13 Added a note on page 3 in the Control Word section: After writing to the Control Word
a master reset should be applied.
HI-3282, HI-3282B
HOLT INTEGRATED CIRCUITS
12
HI-3282, HI-3282B PACKAGE DIMENSIONS
inches (millimeters)
Package Type: 40C
40-PIN CERAMIC SIDE-BRAZED DIP
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
2.020 MAX
(51.308 MAX)
.225 MAX
(5.715 MAX)
.018 TYP
(.457 TYP)
.050 TYP
(1.270 TYP)
.085 ±.009
(2.159 ±.229)
.125 MIN
(3.175 MIN)
.610 ±.010
(15.494 ±.254)
.600 ±.010
(15.240 ±.254)
.595 ±.010
(15.113 ±.254)
.010 +.002/-.001
(.254 +.051/-.025)
.100
(2.54) BSC
44-PIN PLASTIC PLCC inches (millimeters)
Package Type: 44J
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
PIN NO. 1 IDENT
.045 x 45°
.045 x 45°
PIN NO. 1
.173 ±.008
(4.394 ±.203)
.690 ±.005
(17.526 ±.127)
SQ.
.610 ±.020
(15.494±.508)
.031±.005
(.787 ±.127)
.653 ±.004
(16.586 ±.102)
SQ.
.017 ±.004
(.432 ±.102)
.050
(1.27) BSC
DETAIL A
R
.010 ± .001
(.254 ± .03)
.020
(.508) min
See Detail A
.035±.010
(.889 ±.254)
HOLT INTEGRATED CIRCUITS
13
HI-3282 PACKAGE DIMENSIONS
44-PIN CERAMIC LEADLESS CHIP CARRIER inches (millimeters)
Package Type: 44S
.651 ±.011
(16.535 ±.279)
SQ.
.075 ±.004
(1.905 ±.101)
.326 ±.006
(8.280 ±.152)
PIN 1
.050
(1.270)
.009R ± .006
(.229R ±.152)
.092 ± .028
(2.336 ±.711)
.025 ±.003
(.635 ±.076)
.050 ± .005
(1.270 ±.127)
PIN 1
BSC
.020
(.508) INDEX
.040 x 45°
(1.016 x 45°) 3 PLCS
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
Package Type:
0° £ Q £ 7°
Detail A
See Detail A
SQ.
44PMQS
44-PIN PLASTIC QUAD FLAT PACK (PQFP)
.009
(.23)
.520 ± .010
(13.20 ± .25)
.394 ± .004
(10.0 ± .10)
SQ.
MAX.
.014 ± .003
(.37 ± .08)
.035 .006±
(.88 .15)±
.005
(.13) R MIN.
.012
(.30) R MAX.
.079 .008±
(2.0 .20)±
.096
(2.45) MAX.
.0315
(.80)
inches (millimeters)
BSC
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
HOLT INTEGRATED CIRCUITS
14
