HEF 40438 MSI QUADRUPLE R/S LATCH WITH 3-STATE OUTPUTS The HEF 40438 is.a quadruple R/S latch with 3-state outputs with a common output enable input {EO}. Each latch has an active HIGH set input (Sq to $3), an active HIGH reset input (Ro to Ra} and an active HIGH 3-state output (Og to Og). When EO is HIGH, the state of the latch output (O,,} can be determined from the function table below, When EO is LOW, the fatch outputs are in the high impedance OF F-state. EO does not affect the state of the latch. The high impedance off-state feature allows common busing of the outputs. 4|So Oo |2 3]Ro 6]51 S119 711 3-STATE 12182 OUTPUTS O2}10 11]R2 14]83 03}1 15, R3 SEO | 7Z73687.3 Fig. 1 Functional diagram. FAMILY DATA | see Family Specifications tpp LIMITS category MSI Oy [15 314] [13h ft2p fit 10: 9! Vop Ra $3 nc. S2 Re O2 Oy ) HEF4043B 0; OQ, Ro So EO Sy Ry Vog 1 2 3 ua S 6 3 8 9Z73686.2 Fig. 2 Pinning diagram. HEF4043BP(N}: 16-lead DIL; plastic (SOT38-1) HEF4043BD(F): 16-lead DIL; ceramic (cerdip) (SOT74) HEF4043BT(D): 16-lead SO; plastic (SOT109-1)} (): Package Dsignator North America PINNING EO common output enable input So to $3 set inputs (active HtGH) Ro to Ra reset inputs (active HIGH) Og to Og 3-state buffered latch outputs FUNCTION TABLE inputs output EO | S, | Ry On L x Xx Zz H L H L H H X H H L L latched H = HIGH state (the more positive voltage) L = LOW state (the less positive voltage) X = state immaterial Z = high impedance state \=$s 0 O % s +> 0 latch 1 Ro R +> 7282341 Ss. 1 Fig. 4 Logic diagram (one latch). T>o- 4 latch 2 q R Ry $2 s 0 > >-- 02 latch t 3 q R Ra 83 S Oo > 03 latch EO > 7273769.3 Fig. 3 Logic diagram. ==)Quadruple R/S latch with 3-state outputs | L HEF4043B. MSI A.C. CHARACTERISTICS Vss = 9.V; Tamb = 25 OC; Cy = 50 pF; input transition times < 20 ns Vpp . typical extrapolation Vv symbol | min. typ. = max. formula Propagation delays Ry > Op 5 90 180 ns 63 ns + (0,55 ns/pF} C HIGH to LOW 10 | tpyL 35 70 ns 24 ns + (0,23 ns/pF) Ci 15 25 50 ns 17 ns + (0,16 ns/pF) Cy Sp * O, 5 65 135 ns 38 ns + (0,55 ns/pF) Cy. LOW to HIGH 10 | teLH 25 50 ns |: 14 ris + (0,23 ns/pF) Cy 15 15 35 ns 7 ns + (0,16 ns/pG) Cy Output transition 5 60 120 ns 10.ns+ (1,0.ns /pF) Cy times 10 | trHe 30 60 ns. |. Ons + (0,42 ns/pF} Cy HIGH to LOW 15 20 40 ns 6 ns + (0,28 ns/pF} Cy 5 60 120 ns | 10ns+(1,0.ns/pF) C_ LOW to HIGH 10 | ttLH 30 60 ns 9 ns + (0,42:ns/pF) Cr 15 20 40 ns 6 ns + (0,28 ns/pF) Cy 3-state propagation delays Output disable times EO 0, 5 45 90 ns HIGH 10 | tpyz 20-35 ns 15 10 25 ns 5 50 100 ns Low 10 | terz 20. 40 ns 15 10 25 ns Output enable times EO * 0, 5 25 50 ns HIGH 10 | tpzH 18 30ns 15 10 25 ns 5 40 80 ns LOW 10 | tpz7 20 45 ns 15 15 35 ns Minimum S,, 5 30 15 ns pulse width; HIGH 10 | twsH 20 10 ns 15 16 8 ns see also waveforms Minimum Rp, 30.15 ns Fig. 5 pulse width; HIGH 10 | twRH 20 10 ns 15 16 8 ns Vop . where typical formula for P (uW) f; = input freq. (MHz) fg = output freq. (MHz) Dynamic power 5 1100 f+ Z(fgCL} x VoD? C\_ = load capacitance {pF) dissipation per 10 4400 f, + Z(fyC_) x Vpp Z{fgC_) = sum of outputs package (P) 15 | 11400 f+ Z(fQCL) x Vpn Vopp = supply voltage (V)HEF 4043B MSI Sp INPUT = Eom Ry INPUT Feng, twsH = 'WRH > 7273758.1 Fig. 5 Waveforms showing minimum S,, and Ry, pulse widths. APPLICATION INFORMATION An example of application for the HE F40438B is: @ Four-bit storage with output enable 310 January 1995 +)