Dual 50MHz to 1000MHz High-Linearity,
Serial/Parallel-Controlled Analog/Digital VGA
MAX2062
19-5511; Rev 2; 8/15
General Description
The MAX2062 high-linearity, dual analog/digital variable-
gain amplifier (VGA) operates in the 50MHz to 1000MHz
frequency range with two independent attenuators in
each signal path. Each digital attenuator is controlled
as a slave peripheral using either the SPI-compatible
interface, or a 5-bit parallel bus with 31dB total adjust-
ment range in 1dB steps. An added feature allows
rapid-fire gain selection among each of the four steps,
preprogrammed by the user through the SPI-compatible
interface. A separate 2-pin control lets the user quickly
access any one of four customized attenuation states
without reprogramming the SPI bus. Each analog attenu-
ator is controlled using an external voltage or through the
SPI-compatible interface using an on-chip 8-bit DAC.
Since each of the stages has its own external RF input
and RF output, this component can be configured to
either optimize noise figure (NF) (amplifier configured
first), OIP3 (amplifier last), or a compromise of NF and
OIP3. The device’s performance features include 24dB
amplifier gain (amplifier only), 7.3dB NF at maximum
gain (includes attenuator insertion losses), and a high
OIP3 level of +41dBm. Each of these features makes
the device an ideal VGA for multipath receiver and trans-
mitter applications.
In addition, the device operates from a single +5V
supply with full performance or a +3.3V supply for an
enhanced power-savings mode with lower performance.
The device is available in a compact 48-pin TQFN
package (7mm x 7mm) with an exposed pad. Electrical
performance is guaranteed over the extended tempera-
ture range, from TC = -40NC to +85NC.
Applications
IF and RF Gain Stages
Temperature-Compensation Circuits
GSM/EDGE Base Stations
WCDMA, TD-SCDMA, and cdma2000M Base
Stations
WiMAXM, LTE, and TD-LTE Base Stations and
Customer-Premise Equipment
Fixed Broadband Wireless Access
Wireless Local Loop
Features
S Independently Controlled Dual Paths
S 50MHz to 1000MHz RF Frequency Range
S Pin-Compatible Family Includes
MAX2063 (Digital-Only VGA)
MAX2064 (Analog-Only VGA)
S 19.4dB (typ) Maximum Gain
S 0.34dB Gain Flatness Over 100MHz Bandwidth
S 64dB Gain Range (33dB Analog Plus 31dB Digital)
S 56dB Path Isolation (at 200MHz)
S Built-In 8-Bit DACs for Analog Attenuation Control
S Supports Four Rapid-Fire Preprogrammed
Attenuator States
Quickly Access Any One of Four Customized
Attenuator States
Ideal for Fast-Attack, High-Level Blocker
Protection
Protects ADC Overdrive Condition
S Excellent Linearity (Configured with Amp Last at
200MHz)
+41dBm OIP3
+56dBm OIP2
+19dBm Output 1dB Compression Point
S 7.3dB Typical Noise Figure (at 200MHz)
S Fast, 25ns Digital Switching
S Very Low Digital VGA Amplitude Overshoot/
Undershoot
S Single +5V Supply (or +3.3V Operation)
S Amplifier Power-Down Mode for TDD Applications
+Denotes lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
T = Tape and reel.
Ordering Information
cdma2000 is a registered certification mark and registered
service mark of the Telecommunications Industry Association.
WiMAX is a registered certification mark and registered ser-
vice mark of the WiMAX Forum.
PART TEMP RANGE PIN-PACKAGE
MAX2062ETM+ -40NC to +85NC48 TQFN-EP*
MAX2062ETM+T -40NC to +85NC48 TQFN-EP*
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
Dual 50MHz to 1000MHz High-Linearity,
Serial/Parallel-Controlled Analog/Digital VGA
MAX2062
2 Maxim Integrated
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
VCC_AMP_1, VCC_AMP_2, VCC_RG to GND ..........-0.3V to +5.5V
STA_A_1, STA_A_2, STA_B_1, STA_B_2,
PD_1, PD_2, AMPSET to GND .........................-0.3V to +3.6V
A_VCTL_1, A_VCTL_2 to GND .............................-0.3V to +3.6V
DAT, CS, CLK, AA_SP, DA_SP to GND ............... -0.3V to +3.6V
D0_1, D1_1, D2_1, D3_1, D4_1, D0_2, D1_2,
D2_2, D3_2, D4_2 to GND ...............................-0.3V to +3.6V
AMP_IN_1, AMP_IN_2 to GND .......................... +0.95V to +1.2V
AMP_OUT_1, AMP_OUT_2 to GND .....................-0.3V to +5.5V
D_ATT_IN_1, D_ATT_IN_2, D_ATT_OUT_1,
D_ATT_OUT_2 to GND ......................................... 0V to +3.6V
A_ATT_IN_1, A_ATT_IN_2, A_ATT_OUT_1,
A_ATT_OUT_2 to GND ......................................... 0V to +3.6V
REG_OUT to GND ................................................ -0.3V to +3.6V
RF Input Power (D_ATT_IN_1, D_ATT_IN_2) ............... +20dBm
RF Input Power (A_ATT_IN_1, A_ATT_IN_2) .............. +20dBm
RF Input Power (AMP_IN_1, AMP_IN_2) ...................... +18dBm
qJC (Notes 1, 2) ......................................................... +12.3NC/W
qJA (Notes 2, 3) ............................................................ +38NC/W
Continuous Power Dissipation (Note 1) ..............................5.3W
Operating Case Temperature Range (Note 4) .. -40NC to +85NC
Junction Temperature .....................................................+150NC
Storage Temperature Range ............................ -65NC to +150NC
Lead Temperature (soldering, 10s) ................................+300NC
Soldering Temperature (reflow) ......................................+260NC
5.0V SUPPLY DC ELECTRICAL CHARACTERISTICS
(Typical Application Circuit, VCC = VCC_AMP_1 = VCC_AMP_2 = VCC_RG = 4.75V to 5.25V, AMPSET = 0, PD_1 = PD_2 = 0,
TC = -40NC to +85NC. Typical values are at VCC_ = 5.0V and TC = +25NC, unless otherwise noted.)
3.3V SUPPLY DC ELECTRICAL CHARACTERISTICS
(Typical Application Circuit, VCC = VCC_AMP_1 = VCC_AMP_2 = VCC_RG = 3.135V to 3.465V, AMPSET = 1, PD_1 = PD_2 = 0,
TC = -40NC to +85NC. Typical values are at VCC_ = 3.3V and TC = +25NC, unless otherwise noted.)
ABSOLUTE MAXIMUM RATINGS
Note 1: Based on junction temperature TJ = TC + (qJC x VCC x ICC). This formula can be used when the temperature of the exposed
pad is known while the device is soldered down to a PCB. See the Applications Information section for details. The junction
temperature must not exceed +150NC.
Note 2: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Note 3: Junction temperature TJ = TA + (qJA x VCC x ICC). This formula can be used when the ambient temperature of the PCB is
known. The junction temperature must not exceed +150NC.
Note 4: TC is the temperature on the exposed pad of the package. TA is the ambient temperature of the device and PCB.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Supply Voltage VCC 4.75 5 5.25 V
Supply Current IDC 148 210 mA
Power-Down Current IDCPD PD_1 = PD_2 = 1, VIH = 3.3V 5.3 8 mA
Logic-Low Input Voltage VIL 0.5 V
Logic-High Input Voltage VIH 1.7 3.465 V
Input Logic Current IIH, IIL -1 +1 FA
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Supply Voltage VCC 3.135 3.3 3.465 V
Supply Current IDC 87 145 mA
Power-Down Current IDCPD PD_1 = PD_2 = 1, VIH = 3.3V 4.5 8 mA
Logic-Low Input Voltage VIL 0.5 V
Logic-High Input Voltage VIH 1.7 V
Dual 50MHz to 1000MHz High-Linearity,
Serial/Parallel-Controlled Analog/Digital VGA
MAX2062
3Maxim Integrated
RECOMMENDED AC OPERATING CONDITIONS
5.0V SUPPLY AC ELECTRICAL CHARACTERISTICS (Each Path, Unless Otherwise
Noted)
(Typical Application Circuit, VCC = VCC_AMP_1 = VCC_AMP_2 = VCC_RG = 4.75V to 5.25V, attenuators are set for maximum gain, RF
ports are driven from 50I sources, AMPSET = 0, PD_1 = PD_2 = 0, 100MHz P fRF P 500MHz, TC = -40NC to +85NC. Typical values
are at maximum gain setting, VCC_ = 5.0V, PIN = -20dBm, fRF = 350MHz, and TC = +25NC, unless otherwise noted.) (Note 6)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
RF Frequency fRF (Note 5) 50 1000 MHz
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Small-Signal Gain G
fRF = 50MHz 20.3
dB
fRF = 100MHz 19.9
fRF = 200MHz 19.4
fRF = 350MHz, TC = +25NC17.0 18.9 21.0
fRF = 450MHz 18.6
fRF = 750MHz 17.8
fRF = 900MHz 16.5
Gain vs. Temperature -0.01 dB/NC
Gain Flatness vs. Frequency
From 100MHz to 200MHz 0.5
dB
Any 100MHz frequency band from 200MHz
to 500MHz 0.34
Noise Figure NF
fRF = 50MHz 6.4
dB
fRF = 100MHz 6.8
fRF = 200MHz 7.3
fRF = 350MHz 7.6
fRF = 450MHz 7.8
fRF = 750MHz 8.7
fRF = 900MHz 9.0
Total Attenuation Range Analog and digital combined 64.1 dB
Output Second-Order Intercept
Point OIP2 POUT = 0dBm/tone, Df = 1MHz, f1 + f252.1 dBm
Path Isolation
RF input 1 amplified power measured at RF
output 2 relative to RF output 1, all unused
ports terminated to 50I
48.6
dB
RF input 2 amplified signal measured at RF
output 1 relative to RF output 2, all unused
ports terminated to 50I
47.7
Output Third-Order Intercept
Point OIP3
POUT = 0dBm/tone, Df = 1MHz, fRF = 50MHz 47.5
dBm
POUT = 0dBm/tone, Df = 1MHz, fRF = 100MHz 43.4
POUT = 0dBm/tone, Df = 1MHz, fRF = 200MHz 41.3
POUT = 0dBm/tone, Df = 1MHz, fRF = 350MHz 37.4
POUT = 0dBm/tone, Df = 1MHz, fRF = 450MHz 35.1
POUT = 0dBm/tone, Df = 1MHz, fRF = 750MHz 28.8
POUT = 0dBm/tone, Df = 1MHz, fRF = 900MHz 25.8
Output -1dB Compression Point P1dB fRF = 350MHz, TC = +25NC (Note 7) 17 18.8 dBm
Dual 50MHz to 1000MHz High-Linearity,
Serial/Parallel-Controlled Analog/Digital VGA
MAX2062
4 Maxim Integrated
5.0V SUPPLY AC ELECTRICAL CHARACTERISTICS (Each Path, Unless Otherwise
Noted) (continued)
(Typical Application Circuit, VCC = VCC_AMP_1 = VCC_AMP_2 = VCC_RG = 4.75V to 5.25V, attenuators are set for maximum gain, RF
ports are driven from 50I sources, AMPSET = 0, PD_1 = PD_2 = 0, 100MHz P fRF P 500MHz, TC = -40NC to +85NC. Typical values
are at maximum gain setting, VCC_ = 5.0V, PIN = -20dBm, fRF = 350MHz, and TC = +25NC, unless otherwise noted.) (Note 6)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Second Harmonic POUT = +3dBm -55.0 dBc
Third Harmonic POUT = +3dBm -72.7 dBc
Group Delay Includes EV kit PCB delays 1.03 ns
Amplifier Power-Down Time PD_1 or PD_2 from 0 to 1, amplifier DC
supply current settles to within 0.1mA 0.5 Fs
Amplifier Power-Up Time PD_1 or PD_2 from 1 to 0, amplifier DC
supply current settles to within 1% 0.5 Fs
Input Return Loss RLIN 50I source 16.1 dB
Output Return Loss RLOUT 50I load 30.8 dB
DIGITAL ATTENUATOR (Each Path, Unless Otherwise Noted)
Insertion Loss 3.0 dB
Input Second-Order Intercept
Point
PIN1 = 0dBm, PIN2 = 0dBm (minimum
attenuation), Df = 1MHz, f1 + f253.6 dBm
Input Third-Order Intercept Point PIN1 = 0dBm, PIN2 = 0dBm (minimum
attenuation), Df = 1MHz 41.5 dBm
Attenuation Range fRF = 350MHz, TC = +25NC, VCC = 5.0V 29.5 30.9 dB
Step Size 1 dB
Relative Attenuation Accuracy 0.13 dB
Absolute Attenuation Accuracy 0.14 dB
Insertion Phase Step fRF = 170MHz
0dB to 16dB 0
Degrees0dB to 24dB 1.1
0dB to 31dB 1.2
Amplitude Overshoot/Undershoot Between any two
states
Elapsed time = 15ns 1.0 dB
Elapsed time = 40ns 0.05
Switching Speed RF settled to
within Q0.1dB
31dB to 0dB 25 ns
0dB to 31dB 21
Input Return Loss 50I source 22.0 dB
Output Return Loss 50I load 21.9 dB
ANALOG ATTENUATOR (Each Path, Unless Otherwise Noted)
Insertion Loss 2.2 dB
Input Second-Order Intercept
Point
PIN1 = 0dBm, PIN2 = 0dBm (minimum
attenuation), Df = 1MHz, f1 + f261.9 dBm
Input Third-Order Intercept Point PIN1 = 0dBm, PIN2 = 0dBm (minimum
attenuation), Df = 1MHz 37.0 dBm
Dual 50MHz to 1000MHz High-Linearity,
Serial/Parallel-Controlled Analog/Digital VGA
MAX2062
5Maxim Integrated
5.0V SUPPLY AC ELECTRICAL CHARACTERISTICS (Each Path, Unless Otherwise
Noted) (continued)
(Typical Application Circuit, VCC = VCC_AMP_1 = VCC_AMP_2 = VCC_RG = 4.75V to 5.25V, attenuators are set for maximum gain, RF
ports are driven from 50I sources, AMPSET = 0, PD_1 = PD_2 = 0, 100MHz P fRF P 500MHz, TC = -40NC to +85NC. Typical values
are at maximum gain setting, VCC_ = 5.0V, PIN = -20dBm, fRF = 350MHz, and TC = +25NC, unless otherwise noted.) (Note 6)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Attenuation Range fRF = 350MHz, TC = +25NC, VCC = 5.0V 29.5 33.2 dB
Gain Control Slope Analog control input -13.3 dB/V
Maximum Gain Control Slope Over analog control input range -35.2 dB/V
Insertion Phase Change Over analog control input range 17.6 Deg
Attenuator Response Time RF settled to
within Q0.5dB
AA_SP = 0, VA_VCTL__
from 2.75V to 0.25V 500
ns
AA_SP = 1, DAC code
from 11111111 to
00000000, from CS rising
edge
500
AA_SP = 0, VA_VCTL__
from 0.25V to 2.75V 500
AA_SP = 1, DAC code
from 00000000 to
11111111, from CS rising
edge
500
Group Delay vs. Control Voltage Over analog control input from 0.25V to
2.75V -0.34 ns
Analog Control Input Range 0.25 2.75 V
Analog Control Input Impedance 19.2 kI
Input Return Loss 50I source 16.1 dB
Output Return Loss 50I load 16.8 dB
D/A CONVERTER
Number of Bits 8 Bits
Output Voltage DAC code = 00000000 0.35 V
DAC code = 11111111 2.7
SERIAL PERIPHERAL INTERFACE (SPI)
Maximum Clock Speed 20 MHz
Data-to-Clock Setup Time tCS 2 ns
Data-to-Clock Hold Time tCH 2.5 ns
Clock-to-CS Setup Time tES 3 ns
CS Positive Pulse Width tEW 7 ns
CS Setup Time tEWS 3.5 ns
Clock Pulse Width tCW 5 ns
Dual 50MHz to 1000MHz High-Linearity,
Serial/Parallel-Controlled Analog/Digital VGA
MAX2062
6 Maxim Integrated
Typical Operating Characteristics
(Typical Application Circuit, VCC = VCC_AMP_1 = VCC_AMP_2 = VCC_RG = 5.0V, attenuators are set for maximum gain, RF ports are
driven from 50I sources, AMPSET = 0, PD_1 = PD_2 = 0, PIN = -20dBm, fRF = 350MHz, and TC = +25NC, unless otherwise noted.)
3.3V SUPPLY AC ELECTRICAL CHARACTERISTICS (Each Path, Unless Otherwise Noted)
(Typical Application Circuit, VCC = VCC_AMP_1 = VCC_AMP_2 = VCC_RG = 3.135V to 3.465V, attenuators are set for maximum gain,
RF ports are driven from 50I sources, AMPSET = 1, PD_1 = PD_2 = 0, 100MHz P fRF P 500MHz, TC = -40NC to +85NC. Typical
values are at maximum gain setting, VCC_ = 3.3V, PIN = -20dBm, fRF = 350MHz, and TC = +25NC, unless otherwise noted.) (Note 6)
Note 5: Operation outside this range is possible, but with degraded performance of some parameters. See the Typical Operating
Characteristics section.
Note 6: All limits include external component losses. Output measurements are performed at the RF output port of the Typical
Application Circuit.
Note 7: It is advisable not to continuously operate the RF input 1 or RF input 2 above +15dBm.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Small-Signal Gain 18.8 dB
Output Third-Order Intercept Point OIP3 POUT = 0dBm/tone 29.4 dBm
Noise Figure 7.8 dB
Total Attenuation Range 64.1 dB
Path Isolation
RF input 1 amplified power measured at RF
output 2 relative to RF output 1, all unused
ports terminated to 50I
49.1
dB
RF input 2 amplified signal measured at RF
output 1 relative to RF output 2, all unused
ports terminated to 50I
48.0
Output -1dB Compression Point P1dB (Note 7) 13.4 dBm
SUPPLY CURRENT vs. VCC
MAX2062 toc01
VCC (V)
SUPPLY CURRENT (mA)
5.1255.004.875
140
150
160
170
130
4.750 5.250
TC = +25°C
TC = -40°C
TC = +85°C
GAIN vs. RF FREQUENCY
MAX2062 toc02
RF FREQUENCY (MHz)
GAIN (dB)
850650250 450
15
16
17
18
20
19
21
22
14
50 1050
TC = +25°C
TC = -40°C
TC = +85°C
NOTCH DUE TO SELF-RESONANCE OF
BIAS COIL. SEE TABLE 7.
GAIN vs. RF FREQUENCY
MAX2062 toc03
RF FREQUENCY (MHz)
GAIN (dB)
850650250 450
15
16
17
18
20
19
21
22
14
50 1050
VCC = 4.75V, 5.00V, 5.25V
7Maxim Integrated
Dual 50MHz to 1000MHz High-Linearity,
Serial/Parallel-Controlled Analog/Digital VGA
MAX2062
Typical Operating Characteristics (continued)
(Typical Application Circuit, VCC = VCC_AMP_1 = VCC_AMP_2 = VCC_RG = 5.0V, attenuators are set for maximum gain, RF ports are
driven from 50I sources, AMPSET = 0, PD_1 = PD_2 = 0, PIN = -20dBm, fRF = 350MHz, and TC = +25NC, unless otherwise noted.)
GAIN OVER DIGITAL ATTENUATOR
SETTING vs. RF FREQUENCY
MAX2062 toc04
RF FREQUENCY (MHz)
GAIN OVER DIGITAL ATTENUATOR SETTING (dB)
850650450250
-8
2
12
22
-18
50 1050
DIGITAL ATTENUATOR RELATIVE
ERROR vs. RF FREQUENCY
MAX2062 toc05
RF FREQUENCY (MHz)
RELATIVE ERROR (dB)
850650250 450
-0.75
-0.50
-0.25
0
0.50
0.25
0.75
1.00
-1.00
50 1050
ERROR FROM 23dB TO 24dB
DIGITAL ATTENUATOR ABSOLUTE
ERROR vs. RF FREQUENCY
MAX2062 toc06
RF FREQUENCY (MHz)
ABSOLUTE ERROR (dB)
850650250 450
-0.75
-0.50
-0.25
0
0.50
0.25
0.75
1.00
-1.00
50 1050
INPUT MATCH OVER DIGITAL ATTENUATOR
SETTING vs. RF FREQUENCY
MAX2062 toc07
RF FREQUENCY (MHz)
0dB
INPUT MATCH OVER DIGITAL ATTENUATOR SETTING (dB)
800600400200
-40
-30
-20
-10
0
-50
0 1000
1dB
31dB
4dB
2dB
8dB, 16dB
OUTPUT MATCH OVER DIGITAL
ATTENUATOR SETTING vs. RF FREQUENCY
MAX2062 toc08
RF FREQUENCY (MHz)
OUTPUT MATCH OVER DIGITAL ATTENUATOR SETTING (dB)
800600400200
-40
-30
-20
-10
0
-50
0 1000
0dB, 1dB, 4dB, 8dB
16dB, 31dB
2dB
CHANNEL-TO-CHANNEL ISOLATION
vs. RF FREQUENCY
MAX2062 toc09
RF FREQUENCY (MHz)
CHANNEL-TO-CHANNEL ISOLATION (dB)
850650450250
70
60
50
40
30
20
80
50 1050
BOTH DIGITAL ATTENUATORS = 31dB
BOTH DIGITAL ATTENUATORS = 0dB
BOTH ANALOG ATTENUATORS = 0dB
REVERSE ISOLATION OVER DIGITAL
ATTENUATOR SETTING vs. RF FREQUENCY
MAX2062 toc10
RF FREQUENCY (MHz)
REVERSE ISOLATION OVER DIGITAL
ATTENUATOR SETTING (dB)
850650450250
70
60
50
40
30
80
50 1050
DIGITAL ATTENUATOR 31dB
DIGITAL ATTENUATOR 0dB
DIGITAL ATTENUATOR PHASE CHANGE
BETWEEN STATES vs. RF FREQUENCY
MAX2062 toc11
RF FREQUENCY (MHz)
DIGITAL ATTENUATOR PHASE CHANGE
BETWEEN STATES (DEGREES)
850650250 450
-20
-10
0
10
30
20
40
50
-30
50 1050
REFERENCED TO HIGH GAIN STATE
POSITIVE PHASE = ELECTRICALLY SHORTER
GAIN OVER ANALOG ATTENUATOR
SETTING vs. RF FREQUENCY
MAX2062 toc12
RF FREQUENCY (MHz)
GAIN OVER ANALOG ATTENUATOR SETTING (dB)
850650250 450
-13
-8
-3
2
12
7
17
22
-18
50 1050
DAC CODE 0
DAC CODE 255
DAC CODE 32
DAC CODE 128
DAC CODE 64
Dual 50MHz to 1000MHz High-Linearity,
Serial/Parallel-Controlled Analog/Digital VGA
MAX2062
8 Maxim Integrated
Typical Operating Characteristics (continued)
(Typical Application Circuit, VCC = VCC_AMP_1 = VCC_AMP_2 = VCC_RG = 5.0V, attenuators are set for maximum gain, RF ports are
driven from 50I sources, AMPSET = 0, PD_1 = PD_2 = 0, PIN = -20dBm, fRF = 350MHz, and TC = +25NC, unless otherwise noted.)
GAIN vs. ANALOG ATTENUATOR SETTING
MAX2062 toc13
ANALOG ATTENUATOR SETTING (DAC CODE)
GAIN (dB)
22419232 64 96 128 160
-13
-8
-3
2
7
12
17
22
-18
0 256
50MHz
200MHz
350MHz
1000MHz
GAIN vs. ANALOG ATTENUATOR SETTING
MAX2062 toc14
ANALOG ATTENUATOR SETTING (DAC CODE)
GAIN (dB)
22419232 64 96 128 160
-13
-8
-3
2
7
12
17
22
-18
0 256
TC = -40°C, +25°C, +85°C
fRF = 350MHz
GAIN vs. ANALOG ATTENUATOR SETTING
MAX2062 toc15
ANALOG ATTENUATOR SETTING (DAC CODE)
GAIN (dB)
22419232 64 96 128 160
-13
-8
-3
2
7
12
17
22
-18
0 256
VCC = 4.75V, 5.00V, 5.25V
fRF = 350MHz
INPUT MATCH vs. ANALOG
ATTENUATOR SETTING
MAX2062 toc16
INPUT MATCH (dB)
-25
-20
-15
-10
-5
0
-30
ANALOG ATTENUATOR SETTING (DAC CODE)
22419232 64 96 128 1600 256
1000MHz
350MHz
50MHz
200MHz
OUTPUT MATCH vs. ANALOG
ATTENUATOR SETTING
MAX2062 toc17
OUTPUT MATCH (dB)
-40
-30
-20
-10
0
-50
ANALOG ATTENUATOR SETTING (DAC CODE)
22419232 64 96 128 1600 256
1000MHz
50MHz, 200MHz, 350MHz
CHANNEL-TO-CHANNEL ISOLATION
vs. RF FREQUENCY
MAX2062 toc18
RF FREQUENCY (MHz)
CHANNEL-TO-CHANNEL ISOLATION (dB)
850650450250
70
60
50
40
30
20
10
80
50 1050
BOTH DIGITAL ATTENUATORS = 0dB
BOTH ANALOG ATTENUATORS = CODE 0
BOTH ANALOG ATTENUATORS = CODE 255
REVERSE ISOLATION OVER ANALOG
ATTENUATOR SETTING vs. RF FREQUENCY
MAX2062 toc19
RF FREQUENCY (MHz)
REVERSE ISOLATION OVER ANALOG
ATTENUATOR SETTING (dB)
850650450250
80
70
60
50
40
30
90
50 1050
DAC CODE 0
DAC CODE 255
S21 PHASE CHANGE
vs. ANALOG ATTENUATOR SETTING
MAX2062 toc20
S21 PHASE CHANGE (DEGREES)
-40
-20
0
20
40
60
80
-60
ANALOG ATTENUATOR SETTING (DAC CODE)
224 25619232 64 96 128 1600
REFERENCED TO HIGH GAIN STATE
POSITIVE PHASE = ELECTRICALLY SHORTER
1000MHz 350MHz
200MHz
50MHz
NOISE FIGURE vs. RF FREQUENCY
MAX2062 toc21
RF FREQUENCY (MHz)
NOISE FIGURE (dB)
850650450250
5
6
7
8
9
10
11
4
50 1050
TC = +85°C
TC = -40°C
TC = +25°C
9Maxim Integrated
Dual 50MHz to 1000MHz High-Linearity,
Serial/Parallel-Controlled Analog/Digital VGA
MAX2062
Typical Operating Characteristics (continued)
(Typical Application Circuit, VCC = VCC_AMP_1 = VCC_AMP_2 = VCC_RG = 5.0V, attenuators are set for maximum gain, RF ports are
driven from 50I sources, AMPSET = 0, PD_1 = PD_2 = 0, PIN = -20dBm, fRF = 350MHz, and TC = +25NC, unless otherwise noted.)
NOISE FIGURE vs. RF FREQUENCY
MAX2062 toc22
RF FREQUENCY (MHz)
NOISE FIGURE (dB)
850650450250
5
6
7
8
9
10
11
4
50 1050
VCC = 4.75V, 5.00V, 5.25V
OUTPUT P1dB vs. RF FREQUENCY
MAX2062 toc23
RF FREQUENCY (MHz)
OUTPUT P1dB (dBm)
850650450250
13
15
17
19
21
11
50 1050
TC = +85°C
TC = -40°C
TC = +25°C
OUTPUT P1dB vs. RF FREQUENCY
MAX2062 toc24
RF FREQUENCY (MHz)
OUTPUT P1dB (dBm)
850650450250
13
15
17
19
21
11
50 1050
VCC = 5.25V
VCC = 4.75V
VCC = 5.00V
OUTPUT IP3 vs. RF FREQUENCY
MAX2062 toc25
RF FREQUENCY (MHz)
OUTPUT IP3 (dBm)
850650450250
25
30
35
40
45
50
20
50 1050
POUT = 0dBm/TONE
TC = +25°C
TC = -40°C
TC = +85°C
OUTPUT IP3 vs. RF FREQUENCY
MAX2062 toc26
RF FREQUENCY (MHz)
OUTPUT IP3 (dBm)
850650450250
25
30
35
40
45
50
20
50 1050
POUT = 0dBm/TONE
VCC = 5.25V
VCC = 4.75V
VCC = 5.00V
OUTPUT IP3 vs. DIGITAL
ATTENUATOR STATE
MAX2062 toc27
DIGITAL ATTENUATOR STATE (dB)
OUTPUT IP3 (dBm)
2420161284
32
34
36
38
40
42
44
30
02
8
TC = +85°C LSB
TC = -40°C USB TC = -40°C LSB
TC = +85°C USB
TC = +25°C LSB, USB
fRF = 350MHz
POUT = -3dBm/TONE
OUTPUT IP3 vs. ANALOG
ATTENUATOR STATE
MAX2062 toc28
ANALOG ATTENUATOR STATE (DAC CODE)
OUTPUT IP3 (dBm)
1681268442
30
35
40
45
25
0 210
TC = +25°C LSB, USB
TC = +85°C LSB, USB
TC = -40°C LSB, USB
POUT = -3dBm/TONE
fRF = 350MHz
2ND HARMONIC vs. RF FREQUENCY
MAX2062 toc29
RF FREQUENCY (MHz)
2ND HARMONIC (dBc)
850650450250
40
50
60
70
30
50 1050
POUT = 3dBm
TC = +25°C
TC = -40°C
TC = +85°C
2ND HARMONIC vs. RF FREQUENCY
MAX2062 toc30
RF FREQUENCY (MHz)
2ND HARMONIC (dBc)
850650450250
40
50
60
70
30
50 1050
POUT = 3dBm
VCC = 5.25V
VCC = 4.75V
VCC = 5.00V
Dual 50MHz to 1000MHz High-Linearity,
Serial/Parallel-Controlled Analog/Digital VGA
MAX2062
10 Maxim Integrated
Typical Operating Characteristics (continued)
(Typical Application Circuit, VCC = VCC_AMP_1 = VCC_AMP_2 = VCC_RG = 5.0V, attenuators are set for maximum gain, RF ports are
driven from 50I sources, AMPSET = 0, PD_1 = PD_2 = 0, PIN = -20dBm, fRF = 350MHz, and TC = +25NC, unless otherwise noted.)
2ND HARMONIC vs. DIGITAL
ATTENUATOR STATE
MAX2062 toc31
DIGITAL ATTENUATOR STATE (dB)
2ND HARMONIC (dBc)
2420161284
50
55
60
65
45
02
8
POUT = 0dBm
fRF = 350MHz
TC = +25°C
TC = -40°C
TC = +85°C
2ND HARMONIC vs. ANALOG
ATTENUATOR STATE
MAX2062 toc32
2ND HARMONIC (dBc)
50
55
60
65
70
45
ANALOG ATTENUATOR STATE (DAC CODE)
168 21012684420
TC = -40°C
TC = +85°C
TC = +25°C
POUT = 0dBm
fRF = 350MHz
3RD HARMONIC vs. RF FREQUENCY
MAX2062 toc33
3RD HARMONIC (dBc)
60
70
80
90
100
50
RF FREQUENCY (MHz)
850 105065045025050
TC = -40°C
TC = +85°C
TC = +25°C
POUT = 3dBm
3RD HARMONIC vs. RF FREQUENCY
MAX2062 toc34
3RD HARMONIC (dBc)
60
70
80
90
100
50
RF FREQUENCY (MHz)
850 105065045025050
POUT = 3dBm
VCC = 5.25V
VCC = 4.75V
VCC = 5.00V
3RD HARMONIC vs. DIGITAL
ATTENUATOR STATE
MAX2062 toc35
DIGITAL ATTENUATOR STATE (dB)
3RD HARMONIC (dBc)
2420161284
75
80
85
70
02
8
POUT = 0dBm
fRF = 350MHz
TC = -40°C TC = +25°C
TC = +85°C
3RD HARMONIC vs. ANALOG
ATTENUATOR STATE
MAX2062 toc36
3RD HARMONIC (dBc)
65
70
75
80
85
90
60
ANALOG ATTENUATOR STATE (DAC CODE)
168 21012684420
POUT = 0dBm
fRF = 350MHz
TC = -40°C
TC = +25°C
TC = +85°C
OIP2 vs. RF FREQUENCY
MAX2062 toc37
RF FREQUENCY (MHz)
OIP2 (dBm)
850650450250
40
50
60
70
30
50 1050
TC = +85°C
TC = +25°C
TC = -40°C
POUT = 0dBm/TONE
OIP2 vs. RF FREQUENCY
MAX2062 toc38
RF FREQUENCY (MHz)
OIP2 (dBm)
850650450250
40
50
60
70
30
50 1050
VCC = 5.25V
VCC = 5.00V
VCC = 4.75V
POUT = 0dBm/TONE
OIP2 vs. DIGITAL ATTENUATOR STATE
MAX2062 toc39
DIGITAL ATTENUATOR STATE (dB)
OIP2 (dBm)
2420161284
45
50
55
60
65
40
02
8
TC = -40°C
TC = +85°C
POUT = -3dBm/TONE
fRF = 350MHz
TC = +25°C
11Maxim Integrated
Dual 50MHz to 1000MHz High-Linearity,
Serial/Parallel-Controlled Analog/Digital VGA
MAX2062
Typical Operating Characteristics (continued)
(Typical Application Circuit, VCC = VCC_AMP_1 = VCC_AMP_2 = VCC_RG = 5.0V, attenuators are set for maximum gain, RF ports are
driven from 50I sources, AMPSET = 0, PD_1 = PD_2 = 0, PIN = -20dBm, fRF = 350MHz, and TC = +25NC, unless otherwise noted.)
OIP2 vs. ANALOG ATTENUATOR STATE
MAX2062 toc40
ANALOG ATTENUATOR STATE (DAC CODE)
OIP2 (dBm)
1681268442
40
45
50
55
60
35
0 210
TC = -40°C
TC = +85°C
POUT = -3dBm/TONE
fRF = 350MHz
TC = +25°C
DAC VOLTAGE vs. DAC CODE
MAX2062 toc41
DAC CODE
DAC VOLTAGE (V)
224192160128966432
0.5
1.0
1.5
2.0
2.5
3.0
0
0 256
TC = -40°C, +25°C, +85°C
DAC VOLTAGE vs. DAC CODE
MAX2062 toc42
DAC CODE
DAC VOLTAGE (V)
224192160128966432
0.5
1.0
1.5
2.0
2.5
3.0
0
0 256
VCC = 4.75V, 5.00V, 5.25V
DAC VOLTAGE DRIFT vs. DAC CODE
MAX2062 toc43
DAC CODE
DAC VOLTAGE DRIFT (V)
224192128 16064 9632
-0.04
-0.03
-0.02
-0.01
0
0.01
0.02
0.03
0.04
0.05
-0.05
0 256
TC CHANGED FROM +25°C TO -40°C
TC CHANGED FROM +25°C TO +85°C
DAC VOLTAGE DRIFT vs. DAC CODE
MAX2062 toc44
DAC CODE
DAC VOLTAGE DRIFT (V)
22419232 64 96 128 160
-0.0075
-0.0050
-0.0025
0
0.0025
0.0050
0.0075
0.0100
0.0100
0 256
VCC CHANGED FROM 5.00V TO 5.25V
VCC CHANGED FROM 5.00V TO 4.75V
GAIN vs. RF FREQUENCY
(DIGITAL ATTENUATOR ONLY)
MAX2062 toc45
RF FREQUENCY (MHz)
GAIN (dB)
850650450250
-4
-3
-2
-1
0
-5
50 1050
TC = +85°C TC = +25°C
TC = -40°C
GAIN vs. RF FREQUENCY
(DIGITAL ATTENUATOR ONLY)
MAX2062 toc46
RF FREQUENCY (MHz)
GAIN (dB)
850650450250
-4
-3
-2
-1
0
-5
50 1050
VCC = 4.75V, 5.00V, 5.25V
GAIN vs. RF FREQUENCY
(ANALOG ATTENUATOR ONLY)
MAX2062 toc47
RF FREQUENCY (MHz)
GAIN (dB)
850650450250
-4
-3
-2
-1
0
-5
50 1050
TC = +85°C TC = +25°C
TC = -40°C
GAIN vs. RF FREQUENCY
(ANALOG ATTENUATOR ONLY)
MAX2062 toc48
RF FREQUENCY (MHz)
GAIN (dB)
850650450250
-4
-3
-2
-1
0
-5
50 1050
VCC = 4.75V, 5.00V, 5.25V
Dual 50MHz to 1000MHz High-Linearity,
Serial/Parallel-Controlled Analog/Digital VGA
MAX2062
12 Maxim Integrated
Typical Operating Characteristics (continued)
(Typical Application Circuit, VCC = VCC_AMP_1 = VCC_AMP_2 = VCC_RG = 3.3V, attenuators are set for maximum gain, RF ports are
driven from 50I sources, AMPSET = 1, PD_1 = PD_2 = 0, PIN = -20dBm, fRF = 350MHz, and TC = +25NC, unless otherwise noted.)
SUPPLY CURRENT vs. VCC
MAX2062 toc49
VCC (V)
SUPPLY CURRENT (mA)
3.43.33.2
70
80
90
100
110
120
60
3.1 3.5
TC = -40°C
TC = +25°C
TC = +85°C
GAIN vs. RF FREQUENCY
MAX2062 toc50
RF FREQUENCY (MHz)
GAIN (dB)
850650250 450
15
16
17
18
20
19
21
22
14
50 1050
TC = -40°C
TC = +25°C
VCC = 3.3V
TC = +85°C
GAIN vs. RF FREQUENCY
MAX2062 toc51
RF FREQUENCY (MHz)
GAIN (dB)
850650250 450
15
16
17
18
20
19
21
22
14
50 1050
VCC = 3.465V
VCC = 3.135V
VCC = 3.30V
INPUT MATCH OVER DIGITAL ATTENUATOR
SETTING vs. RF FREQUENCY
MAX2062 toc52
RF FREQUENCY (MHz)
INPUT MATCH OVER DIGITAL ATTENUATOR SETTING (dB)
800600400200
-40
-30
-20
-10
0
-50
0 1000
VCC = 3.3V
0dB
1dB 8dB, 16dB
31dB
2dB
4dB
OUTPUT MATCH OVER DIGITAL
ATTENUATOR SETTING vs. RF FREQUENCY
MAX2062 toc53
RF FREQUENCY (MHz)
OUTPUT MATCH OVER DIGITAL ATTENUATOR SETTING (dB)
800600400200
-40
-30
-20
-10
0
-50
0 1000
VCC = 3.3V
2dB
16dB, 31dB
0dB, 1dB, 4dB, 8dB
INPUT MATCH vs. ANALOG
ATTENUATOR SETTING
MAX2062 toc54
ANALOG ATTENUATOR SETTING (DAC CODE)
INPUT MATCH (dB)
224192160128966432
-25
-20
-15
-10
-5
0
-30
0 256
50MHz 200MHz
1000MHz 350MHz
VCC = 3.3V
OUTPUT MATCH vs. ANALOG
ATTENUATOR SETTING
MAX2062 toc55
ANALOG ATTENUATOR SETTING (DAC CODE)
OUTPUT MATCH (dB)
224192160128966432
-40
-30
-20
-10
0
-50
0 256
1000MHz
50MHz, 200MHz, 350MHz
VCC = 3.3V
NOISE FIGURE vs. RF FREQUENCY
MAX2062 toc56
RF FREQUENCY (MHz)
NOISE FIGURE (dB)
850650450250
5
6
7
8
9
10
11
4
50 1050
TC = +85°C
TC = -40°C
TC = +25°C
VCC = 3.3V
NOISE FIGURE vs. RF FREQUENCY
MAX2062 toc57
RF FREQUENCY (MHz)
NOISE FIGURE (dB)
850650450250
5
6
7
8
9
10
11
4
50 1050
VCC = 3.135V
VCC = 3.465V
VCC = 3.30V
13Maxim Integrated
Dual 50MHz to 1000MHz High-Linearity,
Serial/Parallel-Controlled Analog/Digital VGA
MAX2062
Typical Operating Characteristics (continued)
(Typical Application Circuit, VCC = VCC_AMP_1 = VCC_AMP_2 = VCC_RG = 3.3V, attenuators are set for maximum gain, RF ports are
driven from 50I sources, AMPSET = 1, PD_1 = PD_2 = 0, PIN = -20dBm, fRF = 350MHz, and TC = +25NC, unless otherwise noted.)
OUTPUT P1dB vs. RF FREQUENCY
MAX2062 toc58
RF FREQUENCY (MHz)
OUTPUT P1dB (dBm)
850650450250
8
10
12
14
16
6
50 1050
TC = -40°C VCC = 3.3V
TC = +85°C
TC = +25°C
OUTPUT P1dB vs. RF FREQUENCY
MAX2062 toc59
RF FREQUENCY (MHz)
OUTPUT P1dB (dBm)
850650450250
8
10
12
14
16
6
50 1050
VCC = 3.30V
VCC = 3.465V
VCC = 3.135V
OUTPUT IP3 vs. RF FREQUENCY
MAX2062 toc60
RF FREQUENCY (MHz)
OUTPUT IP3 (dBm)
850650450250
15
20
25
30
35
40
10
50 1050
POUT = 0dBm/TONE
VCC = 3.3V
TC = +25°C
TC = -40°C
TC = +85°C
OUTPUT IP3 vs. RF FREQUENCY
MAX2062 toc61
RF FREQUENCY (MHz)
OUTPUT IP3 (dBm)
850650450250
15
20
25
30
35
40
10
50 1050
POUT = 0dBm/TONE
VCC = 3.465V
VCC = 3.30V
VCC = 3.135V
OUTPUT IP3
vs. DIGITAL ATTENUATOR STATE
MAX2062 toc62
DIGITAL ATTENUATOR STATE (dB)
OUTPUT IP3 (dBm)
2420161284
26
28
30
32
34
24
02
8
POUT = -3dBm/TONE
VCC = 3.3V
fRF = 350MHz
TC = -40°C LSB, USB
TC = +25°C LSB, USB
TC = +85°C LSB, USB
OUTPUT IP3
vs. ANALOG ATTENUATOR STATE
MAX2062 toc63
ANALOG ATTENUATOR STATE (DAC CODE)
OUTPUT IP3 (dBm)
1681268442
25
30
35
20
0 210
POUT = -3dBm/TONE
fRF = 350MHz
VCC = 3.3V
TC = +25°C LSB, USB
TC = +85°C LSB, USB
TC = -40°C LSB, USB
2ND HARMONIC vs. RF FREQUENCY
MAX2062 toc64
RF FREQUENCY (MHz)
2ND HARMONIC (dBc)
850650450250
35
45
55
65
25
50 1050
POUT = 3dBm
VCC = 3.3V
TC = +85°C
TC = +25°C
TC = -40°C
2ND HARMONIC vs. RF FREQUENCY
MAX2062 toc65
RF FREQUENCY (MHz)
2ND HARMONIC (dBc)
850650450250
35
45
55
65
25
50 1050
POUT = 3dBm
VCC = 3.465V
VCC = 3.135V
VCC = 3.30V
2ND HARMONIC
vs. DIGITAL ATTENUATOR STATE
MAX2062 toc66
DIGITAL ATTENUATOR STATE (dB)
2ND HARMONIC (dBc)
2420161284
50
60
70
40
02
8
POUT = 0dBm
fRF = 350MHz
VCC = 3.3V
TC = -40°C
TC = +25°C
TC = +85°C
Dual 50MHz to 1000MHz High-Linearity,
Serial/Parallel-Controlled Analog/Digital VGA
MAX2062
14 Maxim Integrated
Typical Operating Characteristics (continued)
(Typical Application Circuit, VCC = VCC_AMP_1 = VCC_AMP_2 = VCC_RG = 3.3V, attenuators are set for maximum gain, RF ports are
driven from 50I sources, AMPSET = 1, PD_1 = PD_2 = 0, PIN = -20dBm, fRF = 350MHz, and TC = +25NC, unless otherwise noted.)
2ND HARMONIC
vs. ANALOG ATTENUATOR STATE
MAX2062 toc67
ANALOG ATTENUATOR STATE (DAC CODE)
2ND HARMONIC (dBc)
1681268442
50
60
70
40
0 210
POUT = 0dBm
fRF = 350MHz
VCC = 3.3V
TC = -40°C
TC = +25°C
TC = +85°C
3RD HARMONIC vs. RF FREQUENCY
MAX2062 toc68
RF FREQUENCY (MHz)
3RD HARMONIC (dBc)
850650450250
50
60
70
80
40
50 1050
POUT = 3dBm
VCC = 3.3V
TC = -40°C
TC = +25°C
TC = +85°C
3RD HARMONIC vs. RF FREQUENCY
MAX2062 toc69
RF FREQUENCY (MHz)
3RD HARMONIC (dBc)
850650450250
50
60
70
80
40
50 1050
POUT = 3dBm
VCC = 3.30V
VCC = 3.135V
VCC = 3.465V
3RD HARMONIC
vs. DIGITAL ATTENUATOR STATE
MAX2062 toc70
DIGITAL ATTENUATOR STATE (dB)
3RD HARMONIC (dBc)
2420161284
55
60
65
70
75
50
02
8
POUT = 0dBm
VCC = 3.3V
fRF = 350MHz
TC = -40°C
TC = +25°C
TC = +85°C
3RD HARMONIC
vs. ANALOG ATTENUATOR STATE
MAX2062 toc71
ANALOG ATTENUATOR STATE (DAC CODE)
3RD HARMONIC (dBc)
1681268442
55
60
65
70
75
50
0 210
POUT = 0dBm
VCC = 3.3V
fRF = 350MHz
TC = -40°C
TC = +85°C
TC = +25°C
OIP2 vs. RF FREQUENCY
MAX2062 toc72
RF FREQUENCY (MHz)
OIP2 (dBm)
850650450250
30
40
50
60
70
20
50 1050
POUT = 0dBm/TONE
VCC = 3.3V
TC = +85°C
TC = -40°C
TC = +25°C
OIP2 vs. RF FREQUENCY
MAX2062 toc73
RF FREQUENCY (MHz)
OIP2 (dBm)
850650450250
30
40
50
60
70
20
50 1050
POUT = 0dBm/TONE
VCC = 3.465V
VCC = 3.30V
VCC = 3.135V
OIP2 vs. DIGITAL ATTENUATOR STATE
MAX2062 toc74
DIGITAL ATTENUATOR STATE (dB)
OIP2 (dBm)
2420161284
40
50
60
70
30
02
8
fRF = 350MHz POUT = -3dBm/TONE
VCC = 3.3V
TC = +85°C
TC = +25°C
TC = -40°C
OIP2 vs. ANALOG ATTENUATOR STATE
MAX2062 toc75
ANALOG ATTENUATOR STATE (DAC CODE)
OIP2 (dBm)
1681268442
40
50
60
70
30
0 210
TC = +85°C
TC = +25°C
TC = -40°C
POUT = -3dBm/TONE
VCC = 3.3V
fRF = 350MHz
Dual 50MHz to 1000MHz High-Linearity,
Serial/Parallel-Controlled Analog/Digital VGA
MAX2062
15Maxim Integrated
Pin Configuration
Pin Description
TOP VIEW
MAX2062
TQFN
+
13
14
15
16
17
18
19
20
21
22
23
24
GND
D0_2
D1_2
D2_2
D3_2
D_ATT_OUT_2
D4_2
A_ATT_IN_2
DA_SP
A_VCTL_2
A_ATT_OUT_2
VCC_AMP_2
48
47
46
45
44
43
42
41
40
39
38
37
12345678910 11 12
EP
GND
D0_1
D1_1
D2_1
D3_1
D_ATT_OUT_1
D4_1
A_ATT_IN_1
AA_SP
A_VCTL_1
A_ATT_OUT_1
VCC_AMP_1
GND
D_ATT_IN_2
STA_A_2
STA_B_2
VCC_RG
CLK
DAT
STA_B_1
STA_A_1
D_ATT_IN_1
GND
36 35 34 33 32 31 30 29 28 27 26 25
GND
AMP_IN_2
PD_2
GND
AMP_OUT_2
REG_OUT
AMPSET
AMP_OUT_1
GND
PD_1
AMP_IN_1
GND
CS
PIN NAME FUNCTION
1, 12, 13, 25,
28, 33, 36, 48 GND Ground
2 D_ATT_IN_1 5-Bit Digital Attenuator Input (50I), Path 1. Requires a DC-blocking capacitor.
3 STA_A_1
Digital Attenuator Preprogrammed Attenuation-State Logic Input, Path 1
State A State B Digital Attenuator
Logic = 0 Logic = 0 Preprogrammed State 1
Logic = 1 Logic = 0 Preprogrammed State 2
Logic = 0 Logic = 1 Preprogrammed State 3
Logic = 1 Logic = 1 Preprogrammed State 4
4 STA_B_1
5 DAT SPI Data Digital Input
6 CLK SPI Clock Digital Input
7CS SPI Chip-Select Digital Input
8 VCC_RG Regulator Supply Input. Connect to a 3.3V or 5V external power supply. VCC_RG powers all circuits
except for the driver amplifiers. Bypass with a 10nF capacitor as close as possible to the pin.
Dual 50MHz to 1000MHz High-Linearity,
Serial/Parallel-Controlled Analog/Digital VGA
MAX2062
16 Maxim Integrated
Pin Description (continued)
PIN NAME FUNCTION
9 STA_B_2
Digital Attenuator Preprogrammed Attenuation-State Logic Input, Path 2
State A State B Digital Attenuator
Logic = 0 Logic = 0 Preprogrammed State 1
Logic = 1 Logic = 0 Preprogrammed State 2
Logic = 0 Logic = 1 Preprogrammed State 3
Logic = 1 Logic = 1 Preprogrammed State 4
10 STA_A_2
11 D_ATT_IN_2 5-Bit Digital Attenuator Input (50I), Path 2. Requires a DC-blocking capacitor.
14 D0_2 1dB Attenuator Logic Input, Path 2. Logic 0 = disable, logic 1 = enable.
15 D1_2 2dB Attenuator Logic Input, Path 2. Logic 0 = disable, logic 1 = enable.
16 D2_2 4dB Attenuator Logic Input, Path 2. Logic 0 = disable, logic 1 = enable.
17 D3_2 8dB Attenuator Logic Input, Path 2. Logic 0 = disable, logic 1 = enable.
18 D_ATT_OUT_2 5-Bit Digital Attenuator Output (50I), Path 2. Requires a DC-blocking capacitor. Connect to
A_ATT_IN_2 through a 1000pF capacitor.
19 D4_2 16dB Attenuator Logic Input, Path 2. Logic 0 = disable, logic 1 = enable.
20 A_ATT_IN_2 Analog Attenuator Input (50I), Path 2. Requires a DC-blocking capacitor. Connect to
D_ATT_OUT_2 through a 1000pF capacitor.
21 DA_SP Digital Attenuator Serial/Parallel Control Select. Set DA_SP to logic 1 to select serial control.
Set DA_SP to logic 0 to select parallel control.
22 A_VCTL_2 Analog Attenuator Voltage Control Input, Path 2. Bypass to ground with a 150pF capacitor
if on-chip DAC is used (AA_SP = 1).
23 A_ATT_OUT_2 Analog Attenuator Output (50I), Path 2. Requires a DC-blocking capacitor. Connect to
AMP_IN_2 through a 1000pF capacitor.
24 VCC_AMP_2 Driver Amplifier Supply Voltage Input, Path 2. Bypass with a 10nF capacitor as close as
possible to the pin.
26 AMP_IN_2 Driver Amplifier Input (50I), Path 2. Requires a DC-blocking capacitor. Connect to
A_ATT_OUT_2 through a 1000pF capacitor.
27 PD_2 Power-Down, Path 2. See Table 2 for operation details.
29 AMP_OUT_2 Driver Amplifier Output (50I), Path 2. Connect a pullup inductor from AMP_OUT_2 to VCC_.
30 REG_OUT Regulator Output. Bypass with 1FF capacitor.
31 AMPSET Driver Amplifier Bias Setting for 3.3V Operation. Set to logic 1 for 3.3V operation on pins
VCC_AMP_1 and VCC_AMP_2. Set to logic 0 for 5V operation.
32 AMP_OUT_1 Driver Amplifier Output (50I), Path 1. Connect a pullup inductor from AMP_OUT_1 to VCC_.
34 PD_1 Power-Down, Path 1. See Table 2 for operation details.
35 AMP_IN_1 Driver Amplifier Input (50I), Path 1. Requires a DC-blocking capacitor. Connect to
A_ATT_OUT_1 through a 1000pF capacitor.
37 VCC_AMP_1 Driver Amplifier Supply Voltage Input, Path 1. Bypass with a 10nF capacitor as close as
possible to the pin.
38 A_ATT_OUT_1 Analog Attenuator Output (50I), Path 1. Requires a DC-blocking capacitor. Connect to
AMP_IN_1 through a 1000pF capacitor.
39 A_VCTL_1 Analog Attenuator Voltage Control Input, Path 1. Bypass to ground with a 150pF capacitor
if on-chip DAC is used (AA_SP = 1).
Dual 50MHz to 1000MHz High-Linearity,
Serial/Parallel-Controlled Analog/Digital VGA
MAX2062
17Maxim Integrated
Pin Description (continued)
Detailed Description
The MAX2062 high-linearity analog/digital VGA is a
general-purpose, high-performance amplifier designed
to interface with 50I systems operating in the 50MHz to
1000MHz frequency range.
Each channel of the device integrates one digital attenua-
tor and one analog attenuator to provide 64dB of total gain
control, as well as a driver amplifier optimized to provide
high gain, high IP3, low NF, and low power consumption.
Each digital attenuator is controlled as a slave periph-
eral using either the SPI-compatible interface, or a 5-bit
parallel bus with 31dB total adjustment range in 1dB
steps. An added feature allows rapid-fire gain selection
among each of the four steps, preprogrammed by the
user through the SPI-compatible interface. A separate
2-pin control lets the user quickly access any one of four
customized attenuation states without reprogramming
the SPI bus. Each analog attenuator is controlled using
an external voltage or through the SPI-compatible inter-
face using an on-chip 8-bit DAC. See the Applications
Information section for attenuator programming details.
Because each of the three stages in the separate signal
paths has its own RF input and RF output, this compo-
nent can be configured to either optimize NF (amplifier
configured first), OIP3 (amplifier last), or a compromise
of NF and OIP3. The device’s performance features
include 24dB amplifier gain (amplifier only), 7.3dB NF
at maximum gain (includes attenuator insertion losses),
and a high OIP3 level of +41dBm. Each of these features
makes the device an ideal VGA for multipath receiver
and transmitter applications.
In addition, the device operates from a single +5V
supply with full performance, or a +3.3V supply for an
enhanced power-savings mode with lower performance.
The device is available in a compact 48-pin TQFN pack-
age (7mm x 7mm) with an exposed pad. Electrical per-
formance is guaranteed over the extended temperature
range (TC = -40NC to +85NC).
Analog and 5-Bit Digital Attenuator Control
The device integrates two analog attenuators and two
5-bit digital attenuators to achieve a high level of dynam-
ic range. Each analog attenuator has a 33dB range
and is controlled using an external voltage or through
the 3-wire SPI interface using an on-chip 8-bit DAC.
Each digital attenuator has a 31dB control range, a 1dB
step size, and is programmed either through the 3-wire
SPI or through a separate 5-bit parallel bus. See the
Applications Information section and Table 1 for attenu-
ator programming details. The attenuators can be used
for both static and dynamic power control.
Note that when the analog attenuators are controlled
by the DACs through the SPI bus, the DAC output
voltage shows on pins A_VCTL_1 and A_VCTL_2 (pins
39 and 22, respectively). Therefore, in SPI mode, the
A_VCTL_1 and A_VCTL_2 pins must only connect to the
resistor and capacitor to ground, as shown in the Typical
Application Circuit.
PIN NAME FUNCTION
40 AA_SP
DAC Enable/Disable Logic Input for Analog Attenuators. Set AA_SP to logic 1 to enable on-chip
DAC circuit and digital SPI control. Set AA_SP to logic 0 to disable DAC circuit and digital SPI
control. When AA_SP = 0, use analog control lines (A_VCTL_1 and A_VCTL_2).
41 A_ATT_IN_1 Analog Attenuator Input (50I), Path 1. Requires a DC-blocking capacitor. Connect to
D_ATT_OUT_1 through a 1000pF capacitor.
42 D4_1 16dB Attenuator Logic Input, Path 1. Logic 0 = disable, logic 1 = enable.
43 D_ATT_OUT_1 5-Bit Digital Attenuator Output (50I), Path 1. Requires a DC-blocking capacitor. Connect to
A_ATT_IN_1 through a 1000pF capacitor.
44 D3_1 8dB Attenuator Logic Input, Path 1. Logic 0 = disable, logic 1 = enable.
45 D2_1 4dB Attenuator Logic Input, Path 1. Logic 0 = disable, logic 1 = enable.
46 D1_1 2dB Attenuator Logic Input, Path 1. Logic 0 = disable, logic 1 = enable.
47 D0_1 1dB Attenuator Logic Input, Path 1. Logic 0 = disable, logic 1 = enable.
— EP Exposed Pad. Internally connected to GND. Connect to GND for proper RF performance and
enhanced thermal dissipation.
Dual 50MHz to 1000MHz High-Linearity,
Serial/Parallel-Controlled Analog/Digital VGA
MAX2062
18 Maxim Integrated
Table 1. Control Logic
Driver Amplifier
Each path of the device includes a high-performance
driver with a fixed gain of 24dB. The driver amplifier
circuits are optimized for high linearity for the 50MHz to
1000MHz frequency range.
Applications Information
Operating Modes
The device features an optional +3.3V supply volt-
age operation with reduced linearity performance. The
AMPSET pin needs to be biased accordingly in each
mode, as listed in Table 2. In addition, the driver amplifiers
can be shut down independently to conserve DC power.
See the biasing scheme outlined in Table 2 for details.
SPI Interface and Attenuator Settings
The digital attenuators can be programmed through
the 3-wire SPI/MICROWIRE®-compatible serial interface
using 5-bit words. Fifty-six bits of data are shifted in
MSB first and are framed by CS. The first 28 bits set the
first attenuator and the following 28 bits set the second
attenuator. When CS is low, the clock is active and data
is shifted on the rising edge of the clock. When CS transi-
tions high, the data is latched and the attenuator setting
changes (Figure 1). See Table 3 for details on the SPI
data format.
Path 1 DAC and Digital Attenuator Programming
D0:D7 Sent to DAC register
D0 = LSB, D7 = MSB
D8:D12 Preprogrammed Attenuation State 1
D8 = 1dB bit, D9 = 2dB Bit, D10 = 4dB bit,
D11 = 8dB bit, D12 = 16dB bit
D13:D17 Preprogrammed Attenuation State 2
D13 = 1dB bit, D14 = 2dB bit, D15 = 4dB
bit, D16 = 8dB bit, D17 = 16dB bit
D18:D22 Preprogrammed Attenuation State 3
D18 = 1dB bit, D19 = 2dB bit, D20 = 4dB
bit, D21 = 8dB bit, D22 = 16dB bit
D23:D27 Preprogrammed Attenuation State 4
D23 = 1dB bit, D24 = 2dB bit, D25 = 4dB
bit, D26 = 8dB bit, D27 = 16dB bit
Path 2 DAC and Digital Attenuator Programming
D28:D35 Sent to DAC register
D28 = LSB, D35 = MSB
D36:D40 Preprogrammed Attenuation State 1
D36 = 1dB bit, D37 = 2dB bit, D38 = 4dB
bit, D39 = 8dB bit, D40 = 16dB bit
D41:D45 Preprogrammed Attenuation State 2
D41 = 1dB bit, D42 = 2dB bit, D43 = 4dB
bit, D44 = 8dB bit, D45 = 16dB bit
D46:D50 Preprogrammed Attenuation State 3
D46 = 1dB bit, D47 = 2dB bit, D48 = 4dB
bit, D49 = 8dB bit, D50 = 16dB bit
D51:D55 Preprogrammed Attenuation State 4
D51 = 1dB bit, D52 = 2dB bit, D53 = 4dB
bit, D54 = 8dB bit, D55 = 16dB bit
Table 2. Operating Modes
MICROWIRE is a registered trademark of National
Semiconductor Corp.
AA_SP ANALOG ATTENUATOR D/A CONVERTER
0 Controlled by external control voltage Disabled
1 Controlled by on-chip DAC Enabled (DAC output voltage shows on A_VCTL__ pins);
DAC uses on-chip voltage reference
DA_SP DIGITAL ATTENUATOR
0 Parallel controlled
1 SPI controlled (control voltages show up on the parallel control pins)
RESULT VCC (V) AMPSET PD_1 PD_2
All on 5000
3.3 1 0 0
AMP1 off
AMP2 on
5010
3.3 1 1 0
AMP1 on
AMP2 off
5001
3.3 1 0 1
All off 5011
3.3 1 1 1
Dual 50MHz to 1000MHz High-Linearity,
Serial/Parallel-Controlled Analog/Digital VGA
MAX2062
19Maxim Integrated
Table 3. SPI Data Format
FUNCTION BIT DESCRIPTION
Digital Attenuator State 4
(Path 2)
D55 (MSB) 16dB step (MSB of the 5-bit word used to program the Path 2 digital attenuator state 4)
D54 8dB step
D53 4dB step
D52 2dB step
D51 1dB step
Digital Attenuator State 3
(Path 2)
D50 16dB step (MSB of the 5-bit word used to program the Path 2 digital attenuator state 3)
D49 8dB step
D48 4dB step
D47 2dB step
D46 1dB step
Digital Attenuator State 2
(Path 2)
D45 16dB step (MSB of the 5-bit word used to program the Path 2 digital attenuator state 2)
D44 8dB step
D43 4dB step
D42 2dB step
D41 1dB step
Digital Attenuator State 1
(Path 2)
D40 16dB step (MSB of the 5-bit word used to program the Path 2 digital attenuator state 1)
D39 8dB step
D38 4dB step
D37 2dB step
D36 1dB step
On-Chip DAC
(Path 2)
D35 Bit 7 (MSB) of on-chip DAC used to program the Path 2 analog attenuator
D34 Bit 6 of DAC
D33 Bit 5 of DAC
D32 Bit 4 of DAC
D31 Bit 3 of DAC
D30 Bit 2 of DAC
D29 Bit 1 of DAC
D28 Bit 0 (LSB) of DAC
Digital Attenuator State 4
(Path 1)
D27 16dB step (MSB of the 5-bit word used to program the Path 1 digital attenuator state 4)
D26 8dB step
D25 4dB step
D24 2dB step
D23 1dB step
Digital Attenuator State 3
(Path 1)
D22 16dB step (MSB of the 5-bit word used to program the Path 1 digital attenuator state 3)
D21 8dB step
D20 4dB step
D19 2dB step
D18 1dB step
Dual 50MHz to 1000MHz High-Linearity,
Serial/Parallel-Controlled Analog/Digital VGA
MAX2062
20 Maxim Integrated
Table 3. SPI Data Format (continued)
Figure 1. SPI Timing Diagram
FUNCTION BIT DESCRIPTION
Digital Attenuator State 2
(Path 1)
D17 16dB step (MSB of the 5-bit word used to program the Path 1 digital attenuator state 2)
D16 8dB step
D15 4dB step
D14 2dB step
D13 1dB step
Digital Attenuator State 1
(Path 1)
D12 16dB step (MSB of the 5-bit word used to program the Path 1 digital attenuator state 1)
D11 8dB step
D10 4dB step
D9 2dB step
D8 1dB step
On-Chip DAC
(Path 1)
D7 Bit 7 (MSB) of on-chip DAC used to program the Path 1 analog attenuator
D6 Bit 6 of DAC
D5 Bit 5 of DAC
D4 Bit 4 of DAC
D3 Bit 3 of DAC
D2 Bit 2 of DAC
D1 Bit 1 of DAC
D0 (LSB) Bit 0 (LSB) of DAC
tCS
MSB LSB
DN D1 D0D(N-1)
tCH
tCW
tES
tEW
tEWS
DAT
CLK
CS
DATA ENTERED ON CLOCK RISING EDGE.
ATTENUATOR REGISTER STATE CHANGE ON CS RISING EDGE.
N = NUMBER OF DATA BITS.
NOTES:
Dual 50MHz to 1000MHz High-Linearity,
Serial/Parallel-Controlled Analog/Digital VGA
MAX2062
21Maxim Integrated
Attenuator and DAC Operation
The two analog attenuators are controlled by an external
control voltage applied at A_VCTL_1 and A_VCTL_2
(pins 39 and 22) or by the on-chip 8-bit DACs, while
the digital attenuators are controlled through the SPI-
compatible interface or through two independent,
parallel 5-bit buses. The DAC enable/disable logic-input
pin (AA_SP) and digital attenuator SPI/parallel control
selection logic-input pin (DA_SP) determine how the
attenuators are controlled.
Digital Attenuator Settings
Using the Parallel Control Bus
To capitalize on its fast 25ns switching capability, the
device offers a supplemental 5-bit parallel control inter-
face. The digital logic attenuator control pins (D0_–D4_)
enable the attenuator stages (see Tables 3 and 4).
Direct access to these 5-bit buses enables the user to
avoid any programming delays associated with the SPI
interface. One of the limitations of any SPI bus is the
speed at which commands can be clocked into each
peripheral device. By offering direct access to the 5-bit
parallel interface, the user can quickly shift between
digital attenuator states needed for critical fast-attack
automatic gain control (AGC) applications.
Note that when the digital attenuators are controlled by
the SPI bus, the control voltages of each digital attenua-
tor appears on the five parallel control pins (pins 14–17
and 19 for digital attenuator 2, pins 42 and 44–47 for
digital attenuator 1). When the digital attenuators are
in SPI mode, the parallel control pins must be left
unconnected.
Rapid-Fire Preprogrammed
Attenuation States
The device has an added feature that provides rapid-
fire gain selection among four preprogrammed attenu-
ation steps. As with the supplemental 5-bit buses
previously mentioned, this rapid-fire gain selection allows
the user to quickly access any one of four customized
digital attenuation states without incurring the delays
associated with reprogramming the device through the
SPI bus.
The switching speed is comparable to that achieved
using the supplemental 5-bit parallel buses. However, by
employing this specific feature, the digital attenuator I/O
is further reduced by a factor of either 5 or 2.5 (5 control
bits vs. 1 or 2, respectively), depending on the number
of states desired.
The user can employ the STA_A_1 and STA_B_1
(STA_A_2 and STA_B_2 for digital attenuator 2) logic-
input pins to apply each step as required (see Tables
5 and 6). Toggling just the STA_A_1 pin (1 control bit)
yields two preprogrammed attenuation states; toggling
both the STA_A_1 and STA_B_1 pins together (2 control
bits) yields four preprogrammed attenuation states.
Table 4. Digital Attenuator Settings (Parallel Control, DA_SP = 0)
Table 5. Programmed Attenuation State
Settings for Attenuator 1 (DA_SP = 1)
Table 6. Programmed Attenuation State
Settings for Attenuator 2 (DA_SP = 1)
*Defined by SPI programming bits D8:D27 (see Table 3 for
details).
**Defined by SPI programming bits D36:D55 (see Table 3 for
details).
INPUT LOGIC = 0 (OR GROUND) LOGIC = 1
D0 Disable 1dB attenuator Enable 1dB attenuator
D1 Disable 2dB attenuator Enable 2dB attenuator
D2 Disable 4dB attenuator Enable 4dB attenuator
D3 Disable 8dB attenuator Enable 8dB attenuator
D4 Disable 16dB attenuator Enable 16dB attenuator
STA_A_1 STA_B_1 SETTING FOR DIGITAL
ATTENUATOR 1*
0 0 Preprogrammed attenuation state 1
1 0 Preprogrammed attenuation state 2
0 1 Preprogrammed attenuation state 3
1 1 Preprogrammed attenuation state 4
STA_A_2 STA_B_2 SETTING FOR DIGITAL
ATTENUATOR 2**
0 0 Preprogrammed attenuation state 1
1 0 Preprogrammed attenuation state 2
0 1 Preprogrammed attenuation state 3
1 1 Preprogrammed attenuation state 4
Dual 50MHz to 1000MHz High-Linearity,
Serial/Parallel-Controlled Analog/Digital VGA
MAX2062
22 Maxim Integrated
As an example, assume that the AGC application
requires a static attenuation adjustment to trim out gain
inconsistencies within a receiver lineup. The same AGC
circuit can also be called upon to dynamically attenu-
ate an unwanted blocker signal that could desensitize
the receiver and lead to an ADC overdrive condition.
In this example, the device would be preprogrammed
(through the SPI bus) with two customized attenuation
states—one to address the static gain-trim adjustment,
the second to counter the unwanted blocker condition.
Toggling just the STA_A_1 control bit enables the user to
switch quickly between the static and dynamic attenua-
tion settings with only one I/O pin.
If desired, the user can also program two additional
attenuation states by using the STA_B_1 control bit as a
second I/O pin. These two additional attenuation settings
are useful for software-defined radio applications where
multiple static gain settings are needed to account for dif-
ferent frequencies of operation, or where multiple dynamic
attenuation settings are needed to account for different
blocker levels (as defined by multiple wireless standards).
Power-Supply Sequencing
The sequence to be used is:
1) Power supply
2) Control lines
Layout Considerations
The pin configuration of the device is optimized to facili-
tate a very compact physical layout of the device and its
associated discrete components. The exposed pad (EP)
of the device’s 48-pin TQFN-EP package provides a low
thermal-resistance path to the die. It is important that
the PCB on which the device is mounted be designed
to conduct heat from the EP. In addition, provide the EP
with a low inductance path to electrical ground. The EP
MUST be soldered to a ground plane on the PCB, either
directly or through an array of plated via holes. The lay-
out of the PCB should include proper top-layer ground
shielding to isolate the amplifier’s inputs and outputs
from each other. Shielding between the paths (inputs and
outputs) is important for channel-to-channel isolation.
Table 7. Typical Application Circuit Component Values
*Select the inductors to ensure that self-resonance of the inductors is outside the band of operation.
DESIGNATION QTY DESCRIPTION COMPONENT SUPPLIER
C1, C2, C5, C6, C8,
C9, C12, C13 81000pF ceramic capacitors (0402)
GRM1555C1H102J Murata Electronics North America, Inc.
C3, C10 2 150pF ceramic capacitors (0402)
GRM1555C1H151J Murata Electronics North America, Inc.
C4, C7, C11,
C14, C16 510nF ceramic capacitors (0402)
GRM155R71E103K Murata Electronics North America, Inc.
C15 1 1FF ceramic capacitor (0603)
GRM188R71C105K Murata Electronics North America, Inc.
L1, L2* 2 820nH inductors (1008)
Coilcraft 1008CS-821XJLC Coilcraft, Inc.
R1, R2 2 47.5kI resistors (0402) —
U1 1 48 TQFN-EP (7mm x 7mm)
Maxim MAX2062ETM Maxim Integrated Products, Inc.
Dual 50MHz to 1000MHz High-Linearity,
Serial/Parallel-Controlled Analog/Digital VGA
MAX2062
23Maxim Integrated
Typical Application Circuit
Chip Information
PROCESS: SiGe BiCMOS
Package Information
For the latest package outline information and land patterns, go
to www.maximintegrated.com/packages. Note that a “+”, “#”,
or “-” in the package code indicates RoHS status only. Package
drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND PATTERN
NO.
48 TQFN-EP T4877+7 21-0144 90-0133
MAX2062
13
14
15
16
17
18
19
20
21
22
23
24
GND
D0_2
D1_2
D2_2
D3_2
D_ATT_OUT_2
D4_2
A_ATT_IN_2
DA_SP
A_VCTL_2
C10
C12C5 C11C4
VCC
C9
C7
C15
RF
OUTPUT 1
RF
INPUT 1
RF
INPUT 2
R2
A_ATT_OUT_2
VCC_AMP_2
48
47
46
45 DIGITAL
ATTENUATOR
1
44
43
42
41
40
39
38
37
12345678910 11 12
GND
D0_1
D1_1
D2_1
D3_1
D_ATT_OUT_1
D4_1
A_ATT_IN_1
AA_SP_1
A_VCTL_1
A_ATT_OUT_1
VCC_AMP_1
GND
D_ATT_IN_2
STA_A_2
STA_B_2
VCC_RG
CLK
DAT
STA_B_1
STA_A_1
D_ATT_IN_1
GND
GND
AMP_IN_2
PD_2
GND
AMP_OUT_2
REG_OUT
AMPSET
AMP_OUT_1
GND
PD_1
AMP_IN_1
GND
28 26 25272930
33 31
3234
35
36
CS
ANALOG
ATTENUATOR
1
ANALOG
ATTENUATOR
2
DIGITAL
ATTENUATOR
2
SPI
ACTIVE
BIAS
ACTIVE
BIAS
AMP AMP
EXPOSED
PAD
C6
C14
RF
OUTPUT 2
C13
VCC
VCC
C8
C16
C1
VCC
+
C3
L1 L2
ANALOG
ATTENUATOR
CONTROL 2
ANALOG
ATTENUATOR
CONTROL 1
R1
C2
DAC 2DAC 1
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent
licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and
max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
24 Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000
© 2015 Maxim Integrated Products, Inc. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
Dual 50MHz to 1000MHz High-Linearity,
Serial/Parallel-Controlled Analog/Digital VGA
MAX2062
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 9/10 Initial release —
1 11/10 Updated Output Voltage specification 5
2 8/15 Removed military reference from Applications 1
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