Simultaneous Sampling Dual 175 kSPS 14-Bit ADC AD7863 FUNCTIONAL BLOCK DIAGRAM FEATURES VREF VA1 VB1 VA2 VB2 SIGNAL SCALING MUX TRACK/ HOLD SIGNAL SCALING TRACK/ HOLD SIGNAL SCALING SIGNAL SCALING MUX 14-BIT ADC OUTPUT LATCH 14-BIT ADC DB0 DB13 CS RD CONVERSION CONTROL LOGIC A0 BUSY CONVST CLOCK AGND AGND DGND Figure 1. The AD7863 is a high speed, low power, dual 14-bit analog-todigital converter that operates from a single 5 V supply. A single conversion start signal (CONVST) simultaneously places both track/holds into hold and initiates conversion on both channels. The BUSY signal indicates the end of conversion and at this time the conversion results for both channels are available to be read. The first read after a conversion accesses the result from VA1 or VB1, and the second read accesses the result from VA2 or VB2, depending on whether the multiplexer select (A0) is low or high, respectively. Data is read from the part via a 14-bit parallel data bus with standard CS and RD signals. In addition to the traditional dc accuracy specifications such as linearity, gain, and offset errors, the part is also specified for dynamic performance parameters including harmonic distortion and signal-to-noise ratio. 2.5V REFERENCE AD7863 GENERAL DESCRIPTION The part contains two 5.2 s successive approximation ADCs, two track/hold amplifiers, an internal 2.5 V reference and a high speed parallel interface. Four analog inputs are grouped into two channels (A and B) selected by the A0 input. Each channel has two inputs (VA1 and VA2 or VB1 and VB2) that can be sampled and converted simultaneously, thus preserving the relative phase information of the signals on both analog inputs. The part accepts an analog input range of 10 V (AD7863-10), 2.5 V (AD7863-3), and 0 V to 2.5 V (AD7863-2). Overvoltage protection on the analog inputs for the part allows the input voltage to go to 17 V, 7 V, or +7 V respectively, without causing damage. VDD 2k 06411-001 Two fast 14-bit ADCs Four input channels Simultaneous sampling and conversion 5.2 s conversion time Single supply operation Selection of input ranges 10 V for AD7863-10 2.5 V for AD7863-3 0 V to 2.5 V for AD7863-2 High speed parallel interface Low power, 70 mW typical Power saving mode, 105 W maximum Overvoltage protection on analog inputs 14-bit lead compatible upgrade to AD7862 process that combines precision bipolar circuits with low power CMOS logic. It is available in 28-lead SOIC_W and SSOP. PRODUCT HIGHLIGHTS 1. 2. 3. 4. 5. The AD7863 features two complete ADC functions allowing simultaneous sampling and conversion of two channels. Each ADC has a two-channel input mux. The conversion result for both channels is available 5.2 s after initiating conversion. The AD7863 operates from a single 5 V supply and consumes 70 mW typical. The automatic power-down mode, where the part goes into power-down once conversion is complete and wakes up before the next conversion cycle, makes the AD7863 ideal for batterypowered or portable applications. The part offers a high speed parallel interface for easy connection to microprocessors, microcontrollers, and digital signal processors. The part is offered in three versions with different analog input ranges. The AD7863-10 offers the standard industrial input range of 10 V; the AD7863-3 offers the common signal processing input range of 2.5 V, while the AD7863-2 can be used in unipolar 0 V to 2.5 V applications. The part features very tight aperture delay matching between the two input sample and hold amplifiers. The AD7863 is fabricated in the Analog Devices, Inc. linear compatible CMOS (LC2MOS) process, a mixed technology Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2006 Analog Devices, Inc. All rights reserved. AD7863 TABLE OF CONTENTS Features .............................................................................................. 1 Effective Number of Bits ........................................................... 14 General Description ......................................................................... 1 Total Harmonic Distortion (THD) .......................................... 15 Functional Block Diagram .............................................................. 1 Intermodulation Distortion ...................................................... 15 Product Highlights ........................................................................... 1 Peak Harmonic or Spurious Noise........................................... 15 Revision History ............................................................................... 2 DC Linearity Plot ....................................................................... 15 Specifications..................................................................................... 3 Power Considerations................................................................ 16 Timing Characteristics ................................................................ 5 Microprocessor Interfacing........................................................... 17 Absolute Maximum Ratings............................................................ 6 AD7863 to ADSP-2100 Interface ............................................. 17 ESD Caution.................................................................................. 6 AD7863 to ADSP-2101/ADSP-2102 Interface ....................... 17 Pin Configuration and Function Descriptions............................. 7 AD7863 to TMS32010 Interface .............................................. 17 Terminology ...................................................................................... 8 AD7863 to TMS320C25 Interface............................................ 17 Converter Details.............................................................................. 9 AD7863 to MC68000 Interface ................................................ 18 Track-and-Hold Section .............................................................. 9 AD7863 to 80C196 Interface .................................................... 18 Reference Section ......................................................................... 9 Vector Motor Control ................................................................ 18 Circuit Description......................................................................... 10 Multiple AD7863s ...................................................................... 19 Analog Input Section ................................................................. 10 Applications Hints.......................................................................... 20 Offset and Full-Scale Adjustment ............................................ 10 PC Board Layout Considerations............................................. 20 Timing and Control ................................................................... 11 Ground Planes ............................................................................ 20 Operating Modes ............................................................................ 13 Power Planes ............................................................................... 20 Mode 1 Operation ...................................................................... 13 Supply Decoupling ..................................................................... 20 Mode 2 Operation ...................................................................... 13 Outline Dimensions ....................................................................... 21 AD7863 Dynamic Specifications ............................................. 14 Ordering Guide .......................................................................... 22 Signal-to-Noise Ratio (SNR)..................................................... 14 REVISION HISTORY 11/06--Rev. A to Rev. B Updated Format..................................................................Universal Deleted Applications ........................................................................ 1 Changes to Specifications ................................................................ 3 Changes to Absolute Maximum Ratings ....................................... 6 Updated Outline Dimensions ....................................................... 21 Changes to Ordering Guide .......................................................... 22 5/99--Rev. 0 to Rev. A Rev. B | Page 2 of 24 AD7863 SPECIFICATIONS VDD = 5 V 5%, AGND = DGND = 0 V, REF = Internal. All specifications TMIN to TMAX, unless otherwise noted. Table 1. Parameter SAMPLE AND HOLD -3 dB Small Signal Bandwidth Aperture Delay 2 Aperture Jitter2 Aperture Delay Matching2 DYNAMIC PERFORMANCE 3 Signal-to-(Noise + Distortion) Ratio 4 @ 25C TMIN to TMAX Total Harmonic Distortion4 Peak Harmonic or Spurious Noise4 Intermodulation Distortion4 Second Order Terms Third Order Terms Channel-to-Channel Isolation4 DC ACCURACY Resolution Minimum Resolution for Which No Missing Codes are Guaranteed Relative Accuracy4 Differential Nonlinearity4 AD7863-10, AD7863-3 Positive Gain Error4 Positive Gain Error Match4 Negative Gain Error4 Negative Gain Error Match4 Bipolar Zero Error Bipolar Zero Error Match AD7863-2 Positive Gain Error4 Positive Gain Error Match4 Unipolar Offset Error Unipolar Offset Error Match ANALOG INPUTS AD7863-10 Input Voltage Range Input Resistance AD7863-3 Input Voltage Range Input Resistance AD7863-2 Input Voltage Range Input Current A Version 1 B Version1 Unit 7 35 50 350 7 35 50 350 MHz typ ns max ps typ ps max Test Conditions/Comments fIN = 80.0 kHz, fS = 175 kSPS 78 77 -82 -82 78 77 -82 -82 dB min dB min dB max dB max -93 -89 -86 -93 -89 -86 dB typ dB typ dB typ 14 14 Bits 14 2.5 +2 to -1 14 2 +2 to -1 Bits LSB max LSB max 10 10 10 10 10 8 8 10 8 10 8 6 LSB max LSB max LSB max LSB max LSB max LSB max 14 16 14 10 LSB max LSB max LSB max LSB max 10 9 10 9 V k typ 2.5 3 2.5 3 V k typ 2.5 100 2.5 100 V nA max Rev. B | Page 3 of 24 -87 dB typ -90 dB typ fa = 49 kHz, fb = 50 kHz fIN = 50 kHz sine wave Any channel AD7863 Parameter REFERENCE INPUT/OUTPUT REF IN Input Voltage Range REF IN Input Current REF OUT Output Voltage REF OUT Error @ 25C REF OUT Error TMIN to TMAX REF OUT Temperature Coefficient LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN 5 LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL DB11 to DB0 Floating-State Leakage Current Floating-State Capacitance5 Output Coding AD7863-10, AD7863-3 AD7863-2 CONVERSION RATE Conversion Time Mode 1 Operation Mode 2 Operation 6 Track/Hold Acquisition Time4, 7 POWER REQUIREMENTS VDD IDD Normal Mode (Mode 1) AD7863-10 AD7863-3 AD7863-2 Power-Down Mode (Mode 2) IDD @ 25C 8 Power Dissipation Normal Mode (Mode 1) AD7863-10 AD7863-3 AD7863-2 Power-Down Mode @ 25C A Version 1 B Version1 Unit Test Conditions/Comments 2.375 to 2.625 100 2.5 10 20 25 2.375 to 2.625 100 2.5 10 20 25 V A max V nom mV max mV max ppm/C typ 2.5 V 5% 2.4 0.8 10 10 2.4 0.8 10 10 V min V max A max pF max VDD = 5 V 5% VDD = 5 V 5% 4.0 0.4 4.0 0.4 V min V max ISOURCE = 200 A ISINK = 1.6 mA 10 10 10 10 A max pF max Twos complement Straight (natural) binary 5.2 10.0 0.5 5.2 10.0 0.5 s max s max s max For both channels For both channels 5 5 V nom 5% for specified performance 18 16 11 18 16 11 mA max mA max mA max 20 20 A max 40 nA typ. Logic inputs = 0 V or VDD 94.50 84 57.75 105 94.50 84 57.75 105 mW max mW max mW max W max VDD = 5.25 V, 70 mW typ VDD = 5.25 V, 70 mW typ VDD = 5.25 V, 45 mW typ 210 nW typ, VDD = 5.25 V 1 Temperature ranges are as follows: A Version and B Version, -40C to +85C. Sample tested during initial release. Applies to Mode 1 operation. See Operating Modes section. 4 See Terminology section. 5 Sample tested @ 25C to ensure compliance. 6 This 10 s includes the wake-up time from standby. This wake-up time is timed from the rising edge of CONVST, whereas conversion is timed from the falling edge of CONVST, for a narrow CONVST pulse width the conversion time is effectively the wake-up time plus conversion time, 10 s. This can be seen from Figure 6. Note that if the CONVST pulse width is greater than 5.2 s, the effective conversion time increases beyond 10 s. 7 Performance measured through full channel (multiplexer, SHA, and ADC). 8 For best dynamic performance of the AD7863, ATE device testing has to be performed with power supply decoupling in place. In the AD7863 power-down mode of operation, the leakage current associated with these decoupling capacitors is greater than that of the AD7863 supply current. Therefore, the 40 nA typical figure shown is characterized and guaranteed by design figure, which reflects the supply current of the AD7863 without decoupling in place. The maximum figure shown in the Conditions/Comments column reflects the AD7863 with supply decoupling in place--0.1 F in parallel with 10 F disc ceramic capacitors on the VDD pin and 2 x 0.1 F disc ceramic capacitors on the VREF pin, in both cases to the AGND plane. 2 3 Rev. B | Page 4 of 24 AD7863 TIMING CHARACTERISTICS VDD = 5 V 5%, AGND = DGND = 0 V, REF = Internal. All specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter 1, 2 tCONV tACQ Parallel Interface t1 t2 t3 t4 t5 3 t6 4 t7 t8 A, B Versions 5.2 0.5 Unit s max s max Test Conditions/Comments Conversion time Acquisition time 0 0 35 45 30 5 30 10 400 ns min ns min ns min ns min ns min ns min ns max ns min ns min CS to RD setup time CS to RD hold time CONVST pulse width RD pulse width Data access time after falling edge of RD Bus relinquish time after rising edge of RD Time between consecutive reads Quiet time 1 Sample tested at 25C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. See Figure 2. 3 Measured with the load circuit of Figure 3 and defined as the time required for an output to cross 0.8 V or 2.0 V. 4 These times are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 3. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances. 2 tACQ t8 CONVST t3 BUSY tCONV = 5.2s A0 CS t1 t7 t2 t4 RD t5 VA2 VB1 Figure 2. Timing Diagram 1.6mA TO OUTPUT PIN 50pF 200A Figure 3. Load Circuit for Access Time and Bus Relinquish Time Rev. B | Page 5 of 24 VB2 06411-002 VA1 06411-003 DATA t6 AD7863 ABSOLUTE MAXIMUM RATINGS TA = 25C, unless otherwise noted. Table 3. Parameter VDD to AGND VDD to DGND Analog Input Voltage to AGND AD7863-10 AD7863-3 AD7863-2 Reference Input Voltage to AGND Digital Input Voltage to DGND Digital Output Voltage to DGND Operating Temperature Range Commercial (A Version and B Version) Storage Temperature Range Junction Temperature SOIC Package, Power Dissipation JA Thermal Impedance JC Thermal Impedance Lead Temperature, Soldering Vapor Phase (60 sec) Infrared (15 sec) SSOP Package, Power Dissipation JA Thermal Impedance JC Thermal Impedance Lead Temperature, Soldering Vapor Phase (60 sec) Infrared (15 sec) Ratings -0.3 V to +7 V -0.3 V to +7 V 17 V 7 V 7V -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION -40C to +85C -65C to +150C 150C 450 mW 71.40C/W 23.0C/W 215C 220C 450 mW 109C/W 39.0C/W 215C 220C Rev. B | Page 6 of 24 AD7863 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS DB12 1 28 DB13 DB11 2 27 AGND DB10 3 26 VB1 DB9 4 25 VA1 DB8 5 24 VDD DB7 6 23 BUSY DGND 7 DB6 TOP VIEW 22 RD 8 (Not to Scale) 21 CS A0 9 20 DB5 10 19 VREF DB4 11 18 VA2 DB3 12 17 VB2 DB2 13 16 AGND DB1 14 15 DB0 06411-004 CONVST AD7863 Figure 4. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 to 6 7 8 Mnemonic DB12 to DB7 DGND CONVST 9 to 15 16 17 DB6 to DB0 AGND VB2 18 VA2 19 VREF 20 A0 21 22 CS RD 23 BUSY 24 25 VDD VA1 26 VB1 27 28 AGND DB13 Description Data Bit 12 to Data Bit 7. Three-state TTL outputs. Digital Ground. Ground reference for digital circuitry. Convert Start Input. Logic input. A high-to-low transition on this input puts both track/holds into their hold mode and starts conversion on both channels. Data Bit 6 to Data Bit 0. Three-state TTL outputs. Analog Ground. Ground reference for mux, track/hold, reference, and DAC circuitry. Input Number 2 of Channel B. Analog input voltage ranges of 10 V (AD7863-10), 2.5 V (AD7863-3), and 0 V to 2.5 V (AD7863-2). Input Number 2 of Channel A. Analog input voltage ranges of 10 V (AD7863-10), 2.5 V (AD7863-3), and 0 V to 2.5 V (AD7863-2). Reference Input/Output. This pin is connected to the internal reference through a series resistor and is the output reference source for the analog-to-digital converter. The nominal reference voltage is 2.5 V, and this appears at the pin. Multiplexer Select. This input is used in conjunction with CONVST to determine on which pair of channels the conversion is to be performed. If A0 is low when the conversion is initiated, then channels VA1 and VA2 are selected. If A0 is high when the conversion is initiated, channels VB1 and VB2 are selected. Chip Select Input. Active low logic input. The device is selected when this input is active. Read Input. Active low logic input. This input is used in conjunction with CS low to enable the data outputs and read a conversion result from the AD7863. Busy Output. The busy output is triggered high by the falling edge of CONVST and remains high until conversion is completed. Analog and Digital Positive Supply Voltage, 5.0 V 5%. Input Number 1 of Channel A. Analog input voltage ranges of 10 V (AD7863-10), 2.5 V (AD7863-3), and 0 V to 2.5 V (AD7863-2). Input Number 1 of Channel B. Analog input voltage ranges of 10 V (AD7863-10), 2.5 V (AD7863-3), and 0 V to 2.5 V (AD7863-2). Analog Ground. Ground reference for mux, track/hold, reference, and DAC circuitry. Data Bit 13 (MSB). Three-state TTL output. Output coding is twos complement for the AD7863-10 and AD7863-3. Output coding is straight (natural) binary for the AD7863-2. Rev. B | Page 7 of 24 AD7863 TERMINOLOGY Signal-to-(Noise + Distortion) Ratio This is the measured ratio of signal to (noise + distortion) at the output of the analog-to-digital converter. The signal is the rms amplitude of the fundamental. Noise is the rms sum of all nonfundamental signals up to half the sampling frequency (fS/2), excluding dc. The ratio is dependent upon the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal-to(noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by Signal to (Noise + Distortion) = (6.02N + 1.76) dB For a 14-bit converter, this is 86.04 dB. Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the rms sum of harmonics to the fundamental. For the AD7863 it is defined as THD (dB ) = 20 log V2 + V3 + V4 + V5 2 2 2 2 V1 where: V1 is the rms amplitude of the fundamental. V2, V3, V4, and V5 are the rms amplitudes of the second through the fifth harmonics. Peak Harmonic or Spurious Noise Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2 and excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for parts where the harmonics are buried in the noise floor, it is a noise peak. Intermodulation Distortion With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion products at sum and difference frequencies of mfa nfb where m, n = 0, 1, 2, 3. Intermodulation terms are those for which neither m nor n is equal to zero. For example, the second order terms include (fa + fb) and (fa - fb), and the third order terms include (2fa + fb), (2fa - fb), (fa + 2fb), and (fa - 2fb). The AD7863 is tested using two input frequencies. In this case, the second and third order terms are of different significance. The second order terms are usually distanced in frequency from the original sine waves, and the third order terms are usually at a frequency close to the input frequencies. As a result, the second and third order terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the fundamental, expressed in decibels (dB). Channel-to-Channel Isolation Channel-to-channel isolation is a measure of the level of crosstalk between channels. It is measured by applying a fullscale 50 kHz sine wave signal to all nonselected channels and determining how much that signal is attenuated in the selected channel. The figure given is the worst case across all channels. Relative Accuracy Relative accuracy or endpoint nonlinearity is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. Differential Nonlinearity This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Positive Gain Error (AD7863-10, 10 V, AD7863-3, 2.5 V) This is the deviation of the last code transition (01 . . . 110 to 01 . . . 111) from the ideal 4 x VREF - 1 LSB (AD7863-10, 10 V range) or VREF - 1 LSB (AD7863-3, 2.5 V range), after the bipolar offset error has been adjusted out. Positive Gain Error (AD7863-2, 0 V to 2.5 V) This is the deviation of the last code transition (11 . . . 110 to 11 . . . 111) from the ideal VREF - 1 LSB, after the unipolar offset error has been adjusted out. Bipolar Zero Error (AD7863-10, 10 V, AD7863-3, 2.5 V) This is the deviation of the midscale transition (all 0s to all 1s) from the ideal 0 V (AGND). Unipolar Offset Error (AD7863-2, 0 V to 2.5 V) This is the deviation of the first code transition (00 . . . 000 to 00 . . . 001) from the ideal AGND + 1 LSB. Negative Gain Error (AD7863-10, 10 V, AD7863-3, 2.5 V) This is the deviation of the first code transition (10 . . . 000 to 10 . . . 001) from the ideal -4 x VREF + 1 LSB (AD7863-10, 10 V range) or -VREF + 1 LSB (AD7863-3, 2.5 V range), after bipolar zero error has been adjusted out. Track-and-Hold Acquisition Time Track-and-hold acquisition time is the time required for the output of the track/hold amplifier to reach its final value, with 1/2 LSB, after the end of conversion (the point at which the track-and-hold returns to track mode). It also applies to situations where a change in the selected input channel takes place or where there is a step input change on the input voltage applied to the selected VAX/BX input of the AD7863. It means that the user must wait for the duration of the track-and-hold acquisition time after the end of conversion or after a channel change/step input change to VAX/BX before starting another conversion, to ensure that the part operates to specification. Rev. B | Page 8 of 24 AD7863 CONVERTER DETAILS The AD7863 is a high speed, low power, dual 14-bit analog-todigital converter that operates from a single 5 V supply. The part contains two 5.2 s successive approximation ADCs, two track-and-hold amplifiers, an internal 2.5 V reference, and a high speed parallel interface. Four analog inputs are grouped into two channels (A and B) selected by the A0 input. Each channel has two inputs (VA1 and VA2 or VB1 and VB2) that can be sampled and converted simultaneously, thus preserving the relative phase information of the signals on both analog inputs. The part accepts an analog input range of 10 V (AD7863-10), 2.5 V (AD7863-3), and 0 V to 2.5 V (AD7863-2). Overvoltage protection on the analog inputs for the part allows the input voltage to go to 17 V, 7 V, or +7 V, respectively, without causing damage. The AD7863 has two operating modes, the high sampling mode and the auto sleep mode, where the part automatically goes into sleep after the end of conversion. These modes are discussed in more detail in the Timing and Control section. Conversion is initiated on the AD7863 by pulsing the CONVST input. On the falling edge of CONVST, both on-chip track-andholds are simultaneously placed into hold and the conversion sequence is started on both channels. The conversion clock for the part is generated internally using a laser-trimmed clock oscillator circuit. The BUSY signal indicates the end of conversion and at this time the conversion results for both channels are available to be read. The first read after a conversion accesses the result from VA1 or VB1, and the second read accesses the result from VA2 or VB2, depending on whether the multiplexer select A0 is low or high, respectively, before the conversion is initiated. Data is read from the part via a 14-bit parallel data bus with standard CS and RD signals. Conversion time for the AD7863 is 5.2 s in the high sampling mode (10 s for the auto sleep mode), and the track/hold acquisition time is 0.5 s. To obtain optimum performance from the part, the read operation should not occur during the conversion or during the 400 ns prior to the next conversion. This allows the part to operate at throughput rates up to 175 kHz and achieve data sheet specifications. TRACK-AND-HOLD SECTION The track-and-hold amplifiers on the AD7863 allow the ADCs to accurately convert an input sine wave of full-scale amplitude to 14-bit accuracy. The input bandwidth of the track-and-hold is greater than the Nyquist rate of the ADC, even when the ADC is operated at its maximum throughput rate of 175 kHz (that is, the track-and hold can handle input frequencies in excess of 87.5 kHz). The track-and-hold amplifiers acquire input signals to 14-bit accuracy in less than 500 ns. The operation of the track-andholds is essentially transparent to the user. The two track-and-hold amplifiers sample their respective input channels simultaneously, on the falling edge of CONVST. The aperture time for the track-and-holds (that is, the delay time between the external CONVST signal and the track-and-hold actually going into hold) is well-matched across the two track-and-holds on one device and also well-matched from device to device. This allows the relative phase information between different input channels to be accurately preserved. It also allows multiple AD7863s to simultaneously sample more than two channels. At the end of conversion, the part returns to its tracking mode. The acquisition time of the track-and-hold amplifiers begins at this point. REFERENCE SECTION The AD7863 contains a single reference pin, labeled VREF, that provides access to the part's own 2.5 V reference. Alternatively, an external 2.5 V reference can be connected to this pin, thus providing the reference source for the part. The part is specified with a 2.5 V reference voltage. Errors in the reference source result in gain errors in the AD7863 transfer function and add to the specified full-scale errors on the part. On the AD7863-10 and AD7863-3, it also results in an offset error injected in the attenuator stage. The AD7863 contains an on-chip 2.5 V reference. To use this reference as the reference source for the AD7863, connect two 0.1 F disc ceramic capacitors from the VREF pin to AGND. The voltage that appears at this pin is internally buffered before being applied to the ADC. If this reference is required for use external to the AD7863, it should be buffered because the part has a FET switch in series with the reference output resulting in a source impedance for this output of 5.5 k nominal. The tolerance on the internal reference is 10 mV at 25C with a typical temperature coefficient of 25 ppm/C and a maximum error over temperature of 25 mV. If the application requires a reference with a tighter tolerance or the AD7863 needs to be used with a system reference, the user has the option of connecting an external reference to this VREF pin. The external reference effectively overdrives the internal reference and thus provides the reference source for the ADC. The reference input is buffered before being applied to the ADC with a maximum input current of 100 A. A suitable reference source for the AD7863 is the AD780 precision 2.5 V reference. Rev. B | Page 9 of 24 AD7863 CIRCUIT DESCRIPTION ANALOG INPUT SECTION The AD7863 is offered as three part types: the AD7863-10, which handles a 10 V input voltage range, the AD7863-3, which handles input voltage range 2.5 V and the AD7863-2, which handles a 0 V to 2.5 V input voltage range. 2.5V REFERENCE AD7863-10/AD7863-3 VREF VAX R1 TO ADC REFERENCE CIRCUITRY R2 TO INTERNAL COMPARATOR MUX R3 AGND Table 6. Ideal Input/Output Code (AD7863-2) TRACK/ HOLD 06411-005 2k Figure 5. AD7863-10/AD7863-3 Analog Input Structure Analog Input1 +FSR - 1 LSB2 +FSR - 2 LSB +FSR - 3 LSB GND + 3 LSB GND + 2 LSB GND + 1 LSB Digital Output Code Transition 111 . . . 110 to 111 . . . 111 111 . . . 101 to 111 . . . 110 111 . . . 100 to 111 . . . 101 000 . . . 010 to 000 . . . 011 000 . . . 001 to 000 . . . 010 000 . . . 000 to 000 . . . 001 1 FSR is full-scale range = 2.5 V for AD7863-2 with VREF = 2.5 V. 1 LSB = FSR/16,384 = 0.15 mV for AD7863-2 with VREF = 2.5 V. 2 Figure 5 shows the analog input section for the AD7863-10 and AD7863-3. The analog input range of the AD7863-10 is 10 V into an input resistance of typically 9 k. The analog input range of the AD7863-3 is 2.5 V into an input resistance of typically 3 k. This input is benign, with no dynamic charging currents because the resistor stage is followed by a high input impedance stage of the track-and-hold amplifier. For the AD7863-10, R1 = 8 k, R2 = 2 k and R3 = 2 k. For the AD7863-3, R1 = R2 = 2 k and R3 is open circuit. For the AD7863-10 and AD7863-3, the designed code transitions occur on successive integer LSB values (that is, 1 LSB, 2 LSBs, 3 LSBs . . .). Output coding is twos complement binary with 1 LSB = FS/16,384. The ideal input/output transfer function for the AD7863-10 and AD7863-3 is shown in Table 5. Table 5. Ideal Input/Output Code (AD7863-10/AD7863-3) Analog Input1 +FSR/2 - 1 LSB2 +FSR/2 - 2 LSBs +FSR/2 - 3 LSBs GND + 1 LSB GND GND - 1 LSB -FSR/2 + 3 LSBs -FSR/2 + 2 LSBs -FSR/2 + 1 LSB input current of less than 100 nA. This input is benign, with no dynamic charging currents. Once again, the designed code transitions occur on successive integer LSB values. Output coding is straight (natural) binary with 1 LSB = FS/16,384 = 2.5 V/16,384 = 0.15 mV. Table 6 shows the ideal input/output transfer function for the AD7863-2. Digital Output Code Transition 011 . . . 110 to 011 . . . 111 011 . . . 101 to 011 . . . 110 011 . . . 100 to 011 . . . 101 000 . . . 000 to 000 . . . 001 111 . . . 111 to 000 . . . 000 111 . . . 110 to 111 . . . 111 100 . . . 010 to 100 . . . 011 100 . . . 001 to 100 . . . 010 100 . . . 000 to 100 . . . 001 OFFSET AND FULL-SCALE ADJUSTMENT In most digital signal processing (DSP) applications, offset and full-scale errors have little or no effect on system performance. Offset error can always be eliminated in the analog domain by ac coupling. Full-scale error effect is linear and does not cause problems as long as the input signal is within the full dynamic range of the ADC. Invariably, some applications require that the input signal span the full analog input dynamic range. In such applications, offset and full-scale error have to be adjusted to zero. Figure 6 shows a typical circuit that can be used to adjust the offset and full-scale errors on the AD7863 (VA1 on the AD7863-10 version is shown for example purposes only). Where adjustment is required, offset error must be adjusted before full-scale error. This is achieved by trimming the offset of the op amp driving the analog input of the AD7863 while the input voltage is 1/2 LSB below analog ground. The trim procedure is as follows: apply a voltage of -0.61 mV (-1/2 LSB) at V1 in Figure 6 and adjust the op amp offset voltage until the ADC output code flickers between 11 1111 1111 1111 and 00 0000 0000 0000. INPUT RANGE = 10V V1 R1 10k R2 500 VA1 1 The analog input section for the AD7863-2 contains no biasing resistors and the VAX/BX pin drives the input directly to the multiplexer and track-and-hold amplifier circuitry. The analog input range is 0 V to 2.5 V into a high impedance stage with an Rev. B | Page 10 of 24 R3 10k R4 10k AD7863* R5 10k AGND *ADDITIONAL PINS OMITTED FOR CLARITY. Figure 6. Full-Scale Adjust Circuit 06411-006 FSR is full-scale range = 20 V (AD7863-10) and = 5 V (AD7863-3) with VREF = 2.5 V. 2 1 LSB = FSR/16,384 = 1.22 mV (AD7863-10) and 0.3 mV (AD7863-3) with VREF = 2.5 V. AD7863 signal indicates the end of conversion and at this time the conversion results for both channels are available to be read. A second conversion is then initiated. If the multiplexer select (A0) is low, the first and second read pulses after the first conversion accesses the result from Channel A (VA1 and VA2, respectively). The third and fourth read pulses, after the second conversion and A0 high, accesses the result from Channel B (VB1 and VB2, respectively). The state of A0 can be changed any time after the CONVST goes high, that is, track-and-holds into hold and 500 ns prior to the next falling edge of CONVST. Note that A0 should not be changed during conversion if the nonselected channels have negative voltages applied to them, which are outside the input range of the AD7863, because this affects the conversion in progress. Data is read from the part via a 14-bit parallel data bus with standard CS and RD signal, that is, the read operation consists of a negative going pulse on the CS pin combined with two negative going pulses on the RD pin (while the CS is low), accessing the two 14-bit results. Once the read operation has taken place, a further 400 ns should be allowed before the next falling edge of CONVST to optimize the settling of the trackand-hold amplifier before the next conversion is initiated. The achievable throughput rate for the part is 5.2 s (conversion time) plus 100 ns (read time) plus 0.4 s (quiet time). This results in a minimum throughput time of 5.7 s (equivalent to a throughput rate of 175 kHz). Gain error can be adjusted at either the first code transition (ADC negative full scale) or the last code transition (ADC positive full scale). The trim procedures for both cases are as follows: Positive Full-Scale Adjust (-10 Version) Apply a voltage of 9.9927 V (FS/2 - 1 LSBs) at V1. Adjust R2 until the ADC output code flickers between 01 1111 1111 1110 and 01 1111 1111 1111. Negative Full-Scale Adjust (-10 Version) Apply a voltage of -9.9976 V (-FS + 1 LSB) at V1. Adjust R2 until the ADC output code flickers between 10 0000 0000 0000 and 10 0000 0000 0001. An alternative scheme for adjusting full-scale error in systems that use an external reference is to adjust the voltage at the VREF pin until the full-scale error for any of the channels is adjusted out. The good full-scale matching of the channels ensures small full-scale errors on the other channels. TIMING AND CONTROL Figure 7 shows the timing and control sequence required to obtain optimum performance (Mode 1) from the AD7863. In the sequence shown, a conversion is initiated on the falling edge of CONVST. This places both track-and-holds into hold simultaneously and new data from this conversion is available in the output register of the AD7863 5.2 s later. The BUSY tACQ t8 CONVST t3 BUSY tCONV = 5.2s A0 CS t1 t7 t2 t4 RD t5 VA1 VA2 VB1 VB2 Figure 7. Mode 1 Timing Operation Diagram for High Sampling Performance Rev. B | Page 11 of 24 06411-007 DATA t6 AD7863 Read Options CS RD DATA CS VA2 VA1 Figure 9. Read Option B (A0 is Low) A0 VA1 VA2 06411-008 RD CS Figure 8. Read Option A (A0 is Low) RD DATA VA1 VA2 Figure 10. Read Option C Rev. B | Page 12 of 24 06411-010 DATA VA1 06411-009 Apart from the read operation previously described and displayed in Figure 7, other CS and RD combinations can result in different channels/inputs being read in different combinations. Suitable combinations are shown in Figure 8, Figure 9, and Figure 10. AD7863 OPERATING MODES MODE 1 OPERATION Normal Power, High Sampling Performance The timing diagram in Figure 7 is for optimum performance in operating Mode 1 where the falling edge of CONVST starts conversion and puts the track-and-hold amplifiers into their hold mode. This falling edge of CONVST also causes the BUSY signal to go high to indicate that a conversion is taking place. The BUSY signal goes low when the conversion is complete, which is 5.2 s max after the falling edge of CONVST and new data from this conversion is available in the output latch of the AD7863. A read operation accesses this data. If the multiplexer select A0 is low, the first and second read pulses after the first conversion accesses the result from Channel A (VA1 and VA2, respectively). The third and fourth read pulses, after the second conversion and A0 high, access the result from Channel B (VB1 and VB2, respectively). Data is read from the part via a 14-bit parallel data bus with standard CS and RD signals. This data read operation consists of a negative going pulse on the CS pin combined with two negative going pulses on the RD pin (while the CS is low), accessing the two 14-bit results. For the fastest throughput rate the read operation takes 100 ns. The read operation must be complete at least 400 ns before the falling edge of the next CONVST and this gives a total time of 5.7 s for the full throughput time (equivalent to 175 kHz). This mode of operation should be used for high sampling applications. MODE 2 OPERATION Power-Down, Auto-Sleep After Conversion The timing diagram in Figure 11 is for optimum performance in operating Mode 2 where the part automatically goes into sleep mode once BUSY goes low after conversion and wakes up before the next conversion takes place. This is achieved by keeping CONVST low at the end of the second conversion, whereas it was high at the end of the second conversion for Mode 1 operation. The operation shown in Figure 11 shows how to access data from both Channel A and Channel B, followed by the auto sleep mode. One can also set up the timing to access data from Channel A only or Channel B only (see the Read Options section) and then go into auto sleep mode. The rising edge of CONVST wakes up the part. This wake-up time is 4.8 s when using an external reference and 5 ms when using the internal reference, at which point the track-and-hold amplifiers go into their hold mode, provided the CONVST has gone low. The conversion takes 5.2 s after this giving a total of 10 s (external reference, 5.005 ms for internal reference) from the rising edge of CONVST to the conversion being complete, which is indicated by the BUSY going low. Note that because the wake-up time from the rising edge of CONVST is 4.8 s, if the CONVST pulse width is greater than 5.2 s the conversion takes more than the 10 s (4.8 s wake-up time + 5.2 s conversion time) shown in Figure 11 from the rising edge of CONVST. This is because the track-and-hold amplifiers go into their hold mode on the falling edge of CONVST and the conversion does not complete for a further 5.2 s. In this case, the BUSY is the best indicator of when the conversion is complete. Even though the part is in sleep mode, data can still be read from the part. The read operation is identical to that in Mode 1 operation and must also be complete at least 400 ns before the falling edge of the next CONVST to allow the track-and-hold amplifiers to have enough time to settle. This mode is very useful when the part is converting at a slow rate because the power consumption is significantly reduced from that of Mode 1 operation. 4.8s*/5ms** WAKE-UP TIME tACQ t8 CONVST t3 t3 BUSY tCONV = 5.2s tCONV = 5.2s A0 CS RD VA1 VB1 VA2 VB2 * WHEN USING AN EXTERNAL REFERENCE, WAKE-UP TIME = 4.8s. ** WHEN USING AN INTERNAL REFERENCE, WAKE-UP TIME = 5ms. Figure 11. Mode 2 Timing Diagram Where Automatic Sleep Function Is Initiated Rev. B | Page 13 of 24 06411-011 DATA AD7863 The AD7863 is specified and tested for dynamic performance as well as traditional dc specifications such as integral and differential nonlinearity. These ac specifications are required for the signal processing applications such as phased array sonar, adaptive filters, and spectrum analysis. These applications require information on the ADC's effect on the spectral content of the input signal. Hence, the parameters for which the AD7863 is specified include SNR, harmonic distortion, intermodulation distortion, and peak harmonics. These terms are discussed in more detail in the following sections. frequency of 175 kHz. The SNR obtained from this graph is -80.72 dB. It should be noted that the harmonics are taken into account when calculating the SNR. 0 -10 -50 -60 -70 -80 -90 -100 -110 SNR is the measured signal-to-noise ratio at the output of the ADC. The signal is the rms magnitude of the fundamental. Noise is the rms sum of all the nonfundamental signals up to half the sampling frequency (fS/2), excluding dc; SNR is dependent upon the number of quantization levels used in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal-to-noise ratio for a sine wave input is given by -130 (1) where N is the number of bits. -140 -150 4000 13.0 3000 12.5 06411-012 750 751 752 753 754 70 80 90 (2) 6.02 755 CODE 12.0 11.5 11.0 10.5 06411-014 749 60 Figure 14 shows a typical plot of effective numbers of bits vs. frequency for an AD7863-2 with a sampling frequency of 175 kHz. The effective number of bits typically falls between 13.11 and 11.05 corresponding to SNR figures of 80.68 dB and 68.28 dB. 13.5 748 50 The effective number of bits for a device can be calculated directly from its measured SNR. 5000 747 40 SNR - 1.76 14.0 1000 30 The formula given in Equation 1 relates the SNR to the number of bits. Rewriting the formula, as in Equation 2, it is possible to obtain a measure of performance expressed in effective number of bits (N). 6000 2000 20 EFFECTIVE NUMBER OF BITS ENOB COUNTS 7000 10 Figure 13. AD7863 FFT Plot N= 8000 0 FREQUENCY (kHz) Thus for an ideal 14-bit converter, SNR = 86.04 dB. Figure 12 shows a histogram plot for 8192 conversions of a dc input using the AD7863 with 5 V supply. The analog input was set at the center of a code transition. It can be seen that the codes appear mainly in the one output bin, indicating very good noise performance from the ADC. 06411-013 -120 SNR = (6.02N + 1.76) dB 746 SNR = +80.72dB THD = -92.96dB -40 SIGNAL-TO-NOISE RATIO (SNR) 0 fSAMPLE = 175kHz fIN = 10kHz -20 -30 (dB) AD7863 DYNAMIC SPECIFICATIONS Figure 12. Histogram of 8192 Conversions of a DC Input 10.0 The output spectrum from the ADC is evaluated by applying a sine wave signal of very low distortion to the VAX/BX input, which is sampled at a 175 kHz sampling rate. A fast fourier transform (FFT) plot is generated from which the SNR data can be obtained. Figure 13 shows a typical 8192 point FFT plot of the AD7863 with an input signal of 10 kHz and a sampling Rev. B | Page 14 of 24 0 200 400 600 800 FREQUENCY (kHz) Figure 14. Effective Numbers of Bits vs. Frequency 1000 AD7863 TOTAL HARMONIC DISTORTION (THD) PEAK HARMONIC OR SPURIOUS NOISE Total harmonic distortion (THD) is the ratio of the rms sum of harmonics to the rms value of the fundamental. For the AD7863, THD is defined as Harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2 and excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for parts where the harmonics are buried in the noise floor, the peak is a noise peak. V2 + V3 + V4 + V5 2 2 2 2 (3) V1 where: DC LINEARITY PLOT V1 is the rms amplitude of the fundamental. V2, V3, V4, and V5 are the rms amplitudes of the second through the fifth harmonic. Figure 16 and Figure 17 show typical DNL and INL plots for the AD7863. 1.0 THD is also derived from the FFT plot of the ADC output spectrum. In this case, the second and third order terms are of different significance. The second order terms are usually distanced in frequency from the original sine waves while the third order terms are usually at a frequency close to the input frequencies. As a result, the second and third order terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the fundamental expressed in dBs. In this case, the input consists of two equal amplitude, low distortion sine waves. Figure 15 shows a typical IMD plot for the AD7863. 0 2048 4096 6144 8192 10240 12288 14336 16383 12288 14336 16383 ADC CODE Figure 16. DC DNL Plot 1.0 0.5 0 -40 -1.0 IMD 2ND ORDER TERM -98.21dB 3RD ORDER TERM -93.91dB -50 -60 -70 -90 -110 -120 06411-015 10 20 30 40 50 60 70 80 2048 4096 6144 8192 10240 Figure 17. DC INL Plot -100 0 0 ADC CODE -80 -130 06411-017 INPUT FREQUENCIES F1 = 50.13kHz F2 = 49.13kHz fSAMPLE = 175kHz -20 -30 (dB) -1.0 -0.5 0 -10 -140 -150 0 -0.5 INL ERROR (LSB) With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion products at sum and difference frequencies of mfa nfb where m, n = 0, 1, 2, 3 . . . Intermodulation terms are those for which neither m nor n is equal to zero. For example, the second order terms include (fa + fb) and (fa - fb) and the third order terms include (2fa + fb), (2fa - fb), (fa + 2fb), and (fa - 2fb). DNL ERROR (LSB) 0.5 INTERMODULATION DISTORTION 06411-016 THD (dB ) = 20 log 90 FREQUENCY (kHz) Figure 15. IMD Plot Rev. B | Page 15 of 24 AD7863 POWER CONSIDERATIONS In the automatic power-down mode the part can be operated at a sample rate that is considerably less than 175 kHz. In this case, the power consumption is reduced and depends on the sample rate. Figure 18 shows a graph of the power consumption vs. sampling rates from 1 Hz to 100 kHz in the automatic powerdown mode. The conditions are 5 V supply at 25C. 50 45 40 30 25 20 15 10 06411-018 POWER (mW) 35 5 0 0 10 20 30 40 50 60 70 FREQUENCY (kHz) 80 90 100 Figure 18. Power vs. Sample Rate in Auto Power-Down Rev. B | Page 16 of 24 AD7863 MICROPROCESSOR INTERFACING The AD7863 high speed bus timing allows direct interfacing to DSP processors as well as modern 16-bit microprocessors. Suitable microprocessor interfaces are shown in Figure 19 through Figure 23. AD7863 TO ADSP-2100 INTERFACE Figure 19 shows an interface between the AD7863 and the ADSP-2100. The CONVST signal can be supplied from the ADSP-2100 or from an external source. The AD7863 BUSY line provides an interrupt to the ADSP-2100 when conversion is completed on both channels. The two conversion results can then be read from the AD7863 using two successive reads to the same memory address. The following instruction reads one of the two results: AD7863 TO TMS32010 INTERFACE An interface between the AD7863 and the TMS32010 is shown in Figure 20. Once again the CONVST signal can be supplied from the TMS32010 or from an external source, and the TMS32010 is interrupted when both conversions have been completed. The following instruction is used to read the conversion results from the AD7863: IN D, ADC where: D is data memory address. ADC is the AD7863 address. PA0 where: TMS32010 MEN MR0 is the ADSP-2100 MR0 register. ADC is the AD7863 address. EN AD7863* DB13 DB0 CS CONVST A0 D15 D0 AD7863* BUSY DMRD (RD) A0 RD ADDRESS BUS ADDR DECODE CS CONVST BUSY DEN OPTIONAL IRQn DATA BUS *ADDITIONAL PINS OMITTED FOR CLARITY. Figure 20. AD7863 to TMS32010 Interface RD AD7863 TO TMS320C25 INTERFACE DB13 DB0 06411-019 DMD15 DMD0 ADDRESS DECODE EN 06411-020 ADSP-2100 (ADSP-2101/ ADSP-2102) DMS ADDRESS BUS INT DMA13 DMA0 OPTIONAL PA2 MR0 = DM (ADC) DATA BUS *ADDITIONAL PINS OMITTED FOR CLARITY. Figure 19. AD7863 to ADSP-2100 Interface AD7863 TO ADSP-2101/ADSP-2102 INTERFACE The interface outlined in Figure 19 also forms the basis for an interface between the AD7863 and the ADSP-2101/ADSP-2102. The READ line of the ADSP-2101/ADSP-2102 is labeled RD. In this interface, the RD pulse width of the processor can be programmed using the data memory wait state control register. The instruction used to read one of the two results is as outlined for the ADSP-2100. Figure 21 shows an interface between the AD7863 and the TMS320C25. As with the two previous interfaces, conversion can be initiated from the TMS320C25 or from an external source, and the processor is interrupted when the conversion sequence is completed. The TMS320C25 does not have a separate RD output to drive the AD7863 RD input directly. This has to be generated from the processor STRB and R/W outputs with the addition of some logic gates. The RD signal is OR gated with the MSC signal to provide the one WAIT state required in the read cycle for correct interface timing. Conversion results are read from the AD7863 using the following instruction: IN D, ADC where: D is data memory address. ADC is the AD7863 address. Rev. B | Page 17 of 24 AD7863 OPTIONAL A15 A0 INTn CS CONVST A0 MC68000 AD7863* BUSY STRB ADDRESS DECODE EN CONVST CS DTACK AD7863* RD AS R/W R/W RD READY DB13 MSC DB0 D15 DB0 D0 DATA BUS *ADDITIONAL PINS OMITTED FOR CLARITY. 06411-021 DB13 DMD15 DMD0 A0 Figure 22. AD7863 to MC68000 Interface AD7863 TO 80C196 INTERFACE Figure 21. AD7863 to TMS320C25 Interface Some applications may require that the conversion be initiated by the microprocessor rather than an external timer. One option is to decode the AD7863 CONVST from the address bus so that a write operation starts a conversion. Data is read at the end of the conversion sequence as before. Figure 23 shows an example of initiating conversion using this method. Note that for all interfaces, it is preferred that a read operation not be attempted during conversion. Figure 23 shows an interface between the AD7863 and the 80C196 microprocessor. Here, the microprocessor initiates conversion. This is achieved by gating the 80C196 WR signal with a decoded address output (different from the AD7863 CS address). The AD7863 BUSY line is used to interrupt the microprocessor when the conversion sequence is completed. A15 A1 AD7863 TO MC68000 INTERFACE 80C196 An interface between the AD7863 and the MC68000 is shown in Figure 22. As before, conversion can be supplied from the MC68000 or from an external source. The AD7863 BUSY line can be used to interrupt the processor or, alternatively, software delays can ensure that conversion has been completed before a read to the AD7863 is attempted. Because of the nature of its interrupts, the MC68000 requires additional logic (not shown in Figure 23) to allow it to be interrupted correctly. For further information on MC68000 interrupts, consult the MC68000 users manual. The MC68000 AS and R/W outputs are used to generate a separate RD input signal for the AD7863. CS is used to drive the MC68000 DTACK input to allow the processor to execute a normal read operation to the AD7863. The conversion results are read using the following MC68000 instruction: MOVE.W ADC, D0 where: D0 is the 68000 D0 register. ADC is the AD7863 address. DATA BUS *ADDITIONAL PINS OMITTED FOR CLARITY. 06411-022 IS A0 ADDRESS DECODE EN ADDRESS BUS ADDRESS BUS ADDRESS DECODE EN CS A0 AD7863* BUSY WR RD RD DB13 DB0 D15 D0 DATA BUS *ADDITIONAL PINS OMITTED FOR CLARITY. 06411-023 TMS320C25 OPTIONAL A15 ADDRESS BUS Figure 23. AD7863-80C196 Interface VECTOR MOTOR CONTROL The current drawn by a motor can be split into two components: one produces torque and the other produces magnetic flux. For optimal performance of the motor, these two components should be controlled independently. In conventional methods of controlling a three-phase motor, the current (or voltage) supplied to the motor and the frequency of the drive are the basic control variables. However, both the torque and flux are functions of current (or voltage) and frequency. This coupling effect can reduce the performance of the motor because, for example, if the torque is increased by increasing the frequency, the flux tends to decrease. Rev. B | Page 18 of 24 AD7863 MULTIPLE AD7863S A block diagram of a vector motor control application using the AD7863 is shown in Figure 24. The position of the field is derived by determining the current in each phase of the motor. Only two phase currents need to be measured because the third can be calculated if two phases are known. VA1 and VA2 of the AD7863 are used to digitize this information. Figure 25 shows a system where a number of AD7863s can be configured to handle multiple input channels. This type of configuration is common in applications such as sonar and radar. The AD7863 is specified with typical limits on aperture delay. This means that the user knows the difference in the sampling instant between all channels. This allows the user to maintain relative phase information between the different channels. VA1 VB1 VA2 IC DAC DAC DAC IB DRIVE CIRCUITRY IA TORQUE SETPOINT VB VA1 VA VA1 VA2 AD7863 (2) VB2 CS VREF VA1 VB1 VA2 VB2 VA2 AD7863* VB1 VB2 VOLTAGE ATTENUATORS 06411-024 *ADDITIONAL PINS OMITTED FOR CLARITY. RD VB1 VREF ADDRESS DECODE ADDRESS RD AD7863 (n) CS A common read signal from the microprocessor drives the RD input of all AD7863s. Each AD7863 is designated a unique address selected by the address decoder. The reference output of AD7863 Number 1 is used to drive the reference input of all other AD7863s in the circuit shown in Figure 25. One VREF can be used to provide the reference to several other AD7863s. Alternatively, an external or system reference can be used to drive all VREF inputs. A common reference ensures good fullscale tracking between all channels. THREE PHASE MOTOR ISOLATION AMPLIFIERS TRANSFORMATION TO TORQUE AND FLUX CURRENT COMPONENTS CS VREF Figure 25. Multiple AD7863s in Multichannel System DSP MICROPROCESSOR FLUX SETPOINT RD (1) VB2 Simultaneous sampling is critical to maintaining the relative phase information between the two channels. A current sensing isolation amplifier, transformer, or Hall effect sensor is used between the motor and the AD7863. Rotor information is obtained by measuring the voltage from two of the inputs to the motor. VB1 and VB2 of the AD7863 are used to obtain this information. Once again the relative phase of the two channels is important. A DSP microprocessor is used to perform the mathematical transformations and control loop calculations on the information fed back by the AD7863. TORQUE AND FLUX CONTROL LOOP CALCULATIONS AND TWO TO THREE PHASE INFORMATION RD AD7863 06411-025 Vector control of an ac motor involves controlling the phase in addition to drive and current frequency. Controlling the phase of the motor requires feedback information on the position of the rotor relative to the rotating magnetic field in the motor. Using this information, a vector controller mathematically transforms the three phase drive currents into separate torque and flux components. The AD7863 is ideally suited for use in vector motor control applications. Figure 24. Vector Motor Control Using the AD7863 Rev. B | Page 19 of 24 AD7863 APPLICATIONS HINTS Fair-Rite 274300111 or Murata BL01/02/03) should be located within three inches of the AD7863. PC BOARD LAYOUT CONSIDERATIONS The AD7863 is optimally designed for lowest noise performance, both radiated and conducted noise. To complement the excellent noise performance of the AD7863 it is imperative that great care be given to the PC board layout. Figure 26 shows a recommended connection diagram for the AD7863. The PCB power plane (VCC) should provide power to all digital logic on the PC board, and the analog power plane (VDD) should provide power to all AD7863 power pins, voltage reference circuitry and any input amplifiers, if needed. A suitable low noise amplifier for the AD7863 is the AD797, one for each input. Ensure that the +VS and the -VS supplies to each amplifier are individually decoupled to AGND. GROUND PLANES The AD7863 and associated analog circuitry should have a separate ground plane, referred to as the analog ground plane (AGND). This analog ground plane should encompass all AD7863 ground pins (including the DGND pin), voltage reference circuitry, power supply bypass circuitry, the analog input traces, and any associated input/buffer amplifiers. The PCB power (VCC) and ground (DGND) should not overlay portions of the analog power plane (VDD). Keeping the VCC power and the DGND planes from overlaying the VDD contributes to a reduction in plane-to-plane noise coupling. SUPPLY DECOUPLING The regular PCB ground plane (referred to as the DGND for this discussion) area should encompass all digital signal traces, excluding the ground pins, leading up to the AD7863. Noise on the analog power plane (VDD) can be further reduced by use of multiple decoupling capacitors (Figure 26). POWER PLANES Optimum performance is achieved by the use of disc ceramic capacitors. The VDD and reference pins (whether using an external or an internal reference) should be individually decoupled to the analog ground plane (AGND). This should be done by placing the capacitors as close as possible to the AD7863 pins with the capacitor leads as short as possible, thus minimizing lead inductance. The PC board layout should have two distinct power planes, one for analog circuitry and one for digital circuitry. The analog power plane should encompass the AD7863 (VDD) and all associated analog circuitry. This power plane should be connected to the regular PCB power plane (VCC) at a single point, if necessary through a ferrite bead, as illustrated in Figure 26. This bead (part numbers for reference: L (FERRITE BEAD) VIN TEMP 0.1F 0.1F 10F 47F ANALOG SUPPLY +5V AD780 VOUT VDD VREF +15V 0.1F 0.1F 0.1F AGND DGND +VS AGND VA1 VA1 AD7863 VB1 VB1 VA2 VA2 VB2 VB2 4 x AD797s 0.1F ANALOG SUPPLY -15V 06411-026 -VS Figure 26. Typical Connections Diagram Including the Relevant Decoupling Rev. B | Page 20 of 24 AD7863 OUTLINE DIMENSIONS 18.10 (0.7126) 17.70 (0.6969) 15 28 7.60 (0.2992) 7.40 (0.2913) 1 10.65 (0.4193) 10.00 (0.3937) 14 0.75 (0.0295) 0.25 (0.0098) 2.65 (0.1043) 2.35 (0.0925) 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 1.27 (0.0500) BSC 0.51 (0.0201) 0.31 (0.0122) SEATING PLANE 45 8 0 0.33 (0.0130) 0.20 (0.0079) 1.27 (0.0500) 0.40 (0.0157) 060706-A COMPLIANT TO JEDEC STANDARDS MS-013-AE CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 27. 28-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-28) Dimensions shown in millimeters and (inches) 10.50 10.20 9.90 15 28 5.60 5.30 5.00 1 8.20 7.80 7.40 14 0.65 BSC 0.38 0.22 SEATING PLANE 8 4 0 COMPLIANT TO JEDEC STANDARDS MO-150-AH Figure 28. 28-Lead Shrink Small Outline Package [SSOP] (RS-28) Dimensions shown in millimeters Rev. B | Page 21 of 24 0.95 0.75 0.55 060106-A 0.05 MIN COPLANARITY 0.10 0.25 0.09 1.85 1.75 1.65 2.00 MAX AD7863 ORDERING GUIDE Model AD7863AR-10 AD7863AR-10REEL AD7863AR-10REEL7 AD7863ARZ-101 AD7863ARZ-10REEL1 AD7863ARZ-10REEL71 AD7863ARS-10 AD7863ARS-10REEL AD7863ARS-10REEL7 AD7863ARSZ-101 AD7863ARSZ-10REEL1 AD7863ARSZ-10REEL71 AD7863BR-10 AD7863BR-10REEL AD7863BR-10REEL7 AD7863BRZ-10 1 AD7863AR-3 AD7863AR-3REEL AD7863AR-3REEL7 AD7863ARZ-31 AD7863ARS-3 AD7863ARS-3REEL AD7863ARS-3REEL7 AD7863ARSZ-31 AD7863ARSZ-3REEL1 AD7863ARSZ-3REEL71 AD7863BR-3 AD7863BR-3REEL AD7863BR-3REEL7 AD7863BRZ-31 AD7863AR-2 AD7863AR-2REEL AD7863AR-2REEL7 AD7863ARZ-21 AD7863ARZ-2REEL1 AD7863ARZ-2REEL71 AD7863ARS-2 AD7863ARS-2REEL AD7863ARS-2REEL7 AD7863ARSZ-21 AD7863ARSZ-2REEL1 AD7863ARSZ-2REEL71 EVAL-AD7863CB 1 Input Range 10 V 10 V 10 V 10 V 10 V 10 V 10 V 10 V 10 V 10 V 10 V 10 V 10 V 10 V 10 V 10 V 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V 0 V to 2.5 V 0 V to 2.5 V 0 V to 2.5 V 0 V to 2.5 V 0 V to 2.5 V 0 V to 2.5 V 0 V to 2.5 V 0 V to 2.5 V 0 V to 2.5 V 0 V to 2.5 V 0 V to 2.5 V 0 V to 2.5 V Relative Accuracy 2.5 LSB 2.5 LSB 2.5 LSB 2.5 LSB 2.5 LSB 2.5 LSB 2.5 LSB 2.5 LSB 2.5 LSB 2.5 LSB 2.5 LSB 2.5 LSB 2.0 LSB 2.0 LSB 2.0 LSB 2.0 LSB 2.5 LSB 2.5 LSB 2.5 LSB 2.5 LSB 2.5 LSB 2.5 LSB 2.5 LSB 2.5 LSB 2.5 LSB 2.5 LSB 2.0 LSB 2.0 LSB 2.0 LSB 2.0 LSB 2.5 LSB 2.5 LSB 2.5 LSB 2.5 LSB 2.5 LSB 2.5 LSB 2.5 LSB 2.5 LSB 2.5 LSB 2.5 LSB 2.5 LSB 2.5 LSB Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C Z = Pb-free part. Rev. B | Page 22 of 24 Package Description 28-Lead SOIC_W 28-Lead SOIC_W 28-Lead SOIC_W 28-Lead SOIC_W 28-Lead SOIC_W 28-Lead SOIC_W 28-Lead SSOP 28-Lead SSOP 28-Lead SSOP 28-Lead SSOP 28-Lead SSOP 28-Lead SSOP 28-Lead SOIC_W 28-Lead SOIC_W 28-Lead SOIC_W 28-Lead SOIC_W 28-Lead SOIC_W 28-Lead SOIC_W 28-Lead SOIC_W 28-Lead SOIC_W 28-Lead SSOP 28-Lead SSOP 28-Lead SSOP 28-Lead SSOP 28-Lead SSOP 28-Lead SSOP 28-Lead SOIC_W 28-Lead SOIC_W 28-Lead SOIC_W 28-Lead SOIC_W 28-Lead SOIC_W 28-Lead SOIC_W 28-Lead SOIC_W 28-Lead SOIC_W 28-Lead SOIC_W 28-Lead SOIC_W 28-Lead SSOP 28-Lead SSOP 28-Lead SSOP 28-Lead SSOP 28-Lead SSOP 28-Lead SSOP Evaluation Board Package Option RW-28 RW-28 RW-28 RW-28 RW-28 RW-28 RS-28 RS-28 RS-28 RS-28 RS-28 RS-28 RW-28 RW-28 RW-28 RW-28 RW-28 RW-28 RW-28 RW-28 RS-28 RS-28 RS-28 RS-28 RS-28 RS-28 RW-28 RW-28 RW-28 RW-28 RW-28 RW-28 RW-28 RW-28 RW-28 RW-28 RS-28 RS-28 RS-28 RS-28 RS-28 RS-28 AD7863 NOTES Rev. B | Page 23 of 24 AD7863 NOTES (c)2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06411-0-11/06(B) Rev. B | Page 24 of 24