1
®
FN3137.6
DG508A
CMOS Analog Multiplexers
The DG508A is a CMOS Monolithic 8-Channel Analog
Multiplexer, which can also be used as a demultiplexer. An
enable input is provided. Wh en the enable input is high, a
channel is selected by the address inputs, and when low, all
channels are off.
A channel in the ON state conducts current equally well in
both directions. In the OFF state each channel blocks
voltages up to the supply rails. The address inputs and the
enable input are TTL and CMOS compatible over the full
specified operating temperature range.
The DG508A is pinout compatible with the industry standard
devices.
Features
Low Power Consumption
TTL and CMOS-Compatible Address and Enable Inputs
44V Maximum Power Supply Rating
High Latch-Up Immunity
Break-Before-Make Switching
Alternate Source
Pb-Free Available (RoHS Compliant)
Applications
Data Acquisition Systems
Communication Systems
Signal Multiplexing/Demultiplexing
Audio Signal Multiple xing
Truth Table
Ordering Information
PART NUMBER TEMP.
RANGE (°C) PACKAGE PKG.
DWG. #
DG508AAK -55 to +125 16 Ld CERDIP F16.3
DG508ABK -25 to +85 16 Ld CERDIP F16.3
DG508ACJ 0 to +70 16 Ld PDIP E16.3
DG508ACJZ
(See Note) 0 to +70 16 Ld PDIP
(Pb-free) E16.3
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which is compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020C.
Pinout DG508A (PDIP, CERDIP)
TOP VIEW
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
A0
EN
V-
S1
S2
S3
D
S4
A1
GND
V+
S5
S6
S7
S8
A2
DG508A
A2A1A0EN ON SWITCH
XXX0 None
0001 1
0011 2
0101 3
0111 4
1001 5
1011 6
1101 7
1111 8
A0, A1, A2, EN
Logic “1” = VAH 2.4V, Logic “0” = VAL 0.8V
Data Sheet March 4, 2009
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2001, 2004, 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
NOT RECOMMENDED FOR NEW DESIGNS
RECOMMENDED REPLACEMENT PART
DG408
2FN3137.6
March 4, 2009
Schematic Diagram
Functional Diagram
DG508A
3 Line Binary Address Inputs
(1 0 1) and EN = 1
Above example shows channel 6 turned ON.
S1
S3
S2
S4
S5
S6
S7
S8A0
D
ADDRESS DECODER
1 OF 8
A1A2EN (ENABLE INPUT)
LOGIC TRIP
POINT REF
LOGIC INTERFACE
AND LEVEL SHIFTER
+
-
DECODER
AX
V+
TYPICAL
SWITCH
SX
DX
V+
GND
LOGIC AX
INPUT OR EN
V-
DG508A
3FN3137.6
March 4, 2009
Absolute Maximum Ratings Thermal Information
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44V
V- to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25V
Digital Inputs, VS, VD (Note 1). . . . . . . . . . . . . (V- -2V) To (V+ +2V)
Continuous Current, (Any Terminal Except S or D) . . . . . . . . . 30mA
Continuous Current, (S or D). . . . . . . . . . . . . . . . . . . . . . . . . . 20mA
Peak Current, S or D (Pulsed 1ms, 10% Duty Cycle Max) . . . . . 40mA
Operating Conditions
Temperature Range
“A” Suffix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
“B” Suffix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25oC to 85oC
“C” Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC
Thermal Resistance (Typical, Note 2) θJA (oC/W) θJC (oC/W)
16 Ld CERDIP Package. . . . . . . . . . . . 75 20
16 Ld PDIP Package . . . . . . . . . . . . . . 90 N/A
Maximum Junction Temperature
CERDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175oC
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150oC
Maximum Storage Temperature
“A” and “B” Suffix . . . . . . . . . . . . . . . . . . . . . . . . . -65oC to 150oC
“C” Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65oC to 125oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the ope rational sections of this specification is not implied.
NOTES:
1. Signals on SX, D, EN, or AX exceeding V+ or V- are clamped by in ternal diodes. Limit diode current to maximum current ratings.
2. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications TA = 25oC, V+ = +15V, V- = -15V, GND = 0V, VEN = 2.4V, Unless Otherwise Specified
PARAMETER TEST CONDITIONS
“A” SUFFIX “B” AND “C” SUFFIX
UNITS
(NOTE 4)
MIN (NOTE 3)
TYP (NOTE 4)
MAX (NOTE 4)
MIN (NOTE 3)
TYP (NOTE 4)
MAX
DYNAMIC CHARACTERISTICS
Switching Time of
Multiplexer, tTRANSITION See Figure 1 - 0.6 1 - 0.6 - μs
Break-Before-Make
Interval, tOPEN See Figure 3 - 0.2 - - 0.2 - μs
Enable Turn-ON Time,
tON(EN) See Figure 2 - 1 1.5 - 1 - μs
Enable Turn-OFF Time,
tOFF(EN) See Figure 2 - 0.4 1.0 - 0.4 - μs
OFF Isolation, OIRR VEN = 0V, RL = 1kΩ, CL = 15pF,
VS=7V
RMS, f = 500kHz (Note 5) -68- -68-dB
Source OFF Capacitance,
CS(OFF) VS = 0V, VEN = 0V, f = 140kHz - 5 - - 5 - pF
Drain OFF Capacitance,
CD(OFF) VD = 0V, VEN = 0V, f = 140kHz - 25 - - 25 - pF
Charge Injection, Q See Figure 4 - 4 - - 4 - pC
DIGITAL INPUT CHARAC TERIST ICS
Address Input Current,
Input Voltage High, IAH VA = 2.4V -10 -0.002 - -10 -0.002 - μA
VA = 15V - 0.006 10 - 0.006 10 μA
Address Input Current Input
Voltage Low, IAL VEN = 2.4V VA = 0V -10 -0.002 - -10 -0.002 - μA
VEN = 0V -10 -0.002 - -10 -0.0002 - μA
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range,
VANALOG (Note 7) -15 - +15 -15 - +15 V
Drain-Source ON
Resistance, rDS(ON) Sequence Each
Switch ON
VAL = 0.8V,
VAH = 2.4V
IS = -200μA, VD = +10V - 270 400 - 270 450 Ω
IS = -200μA, VD = -10V - 230 400 - 230 450 Ω
rDS(ON) Matching
Between Channels -10V VS +10V - 6 - - 6 - %
ΔrDS ON()
rDS(ON)MAX rDS ON()MIN
rDS ON()AVG
-----------------------------------------------------------------------
=
DG508A
4FN3137.6
March 4, 2009
Source OFF Leakage
Current, IS(OFF) VEN = 0V VS = +10V, VD = -10V -1 0.002 1 -5 0.002 5 nA
VS = -10V, VD = +10V -1 -0.005 1 -5 -0.005 5 nA
Drain OFF Leakage
Current, ID(OFF) VEN = 0V VS = -10V, VD = +10V - 0.01 10 - 0.01 20 nA
VS = +10V, VD = -10V -10 -0.015 - -20 -0.015 - nA
Drain ON Leakage Current,
ID(ON) (Note 6)
Sequence Each
Switch ON
VAL = 0.8V,
VAH = 2.4V
VD = VS(ALL) = +10V - 0.015 10 - 0.015 20 nA
VD = VS(ALL) = -10V -10 -0.03 - -20 -0.03 - nA
POWER SUPPLY CHARACTERISTICS
Positive Supply Current, I+ VEN = 5.0V (Enabled) or
VEN = 0V (Standby), VA = 0V - 1.3 2.4 - 1.3 2.4 mA
Negative Supply Current, I- -1.5 -0.7 - -1.5 -0.7 - mA
Electrical Specifications TA = 25oC, V+ = +15V, V- = -15V, GND = 0V, VEN = 2.4V, Unless Otherwise Specified (Continued)
PARAMETER TEST CONDITIONS
“A” SUFFIX “B” AND “C” SUFFIX
UNITS
(NOTE 4)
MIN (NOTE 3)
TYP (NOTE 4)
MAX (NOTE 4)
MIN (NOTE 3)
TYP (NOTE 4)
MAX
Electrical Specifications TA = Over Operating Temperature Range, V+ = +15V, V- = -15V, GND = 0V, VEN = 2.4V,
Unless Otherwise Specified
PARAMETER TEST CONDITIONS
“A” SUFFIX
UNITSMIN (NOTE 3)
TYP MAX
DIGITAL INPUT CHARAC TERIST ICS
Address Input Current, Input Voltage
High, IAH VA = 2.4V -30 - - μA
VA = 15V - - 30 μA
Address Input Current Input Voltage
Low, IAL VEN = 2.4V VA = 0V -30 - - μA
VEN = 0V -30 - - μA
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG (Note 7) -15 - +15 V
Drain-Source ON Resistance, rDS(ON) Sequence Each Switch ON
VAL = 0.8V, VAH = 2.4V IS = -200μA, VD = +10V - - 500 Ω
IS = -200μA, VD = -10V - - 500 Ω
Source OFF Leakage Current, IS(OFF) VEN = 0V VS = +10V, VD = -10V - - 50 nA
VS = -10V, VD = +10V -50 - - nA
Drain OFF Leakage Current, ID(OFF) VEN = 0V VS = -10V, VD = +10V - - 200 nA
VS = +10V, VD = -10V -200 - - nA
Drain ON Leakage Current, ID(ON) (Note 6) Sequence Each Switch ON
VAL = 0.8V, VAH = 2.4V VD = VS(ALL) = +10V - - 200 nA
VD = VS(ALL) = -10V -200 - - nA
POWER SUPPLY CHARACTERISTICS
Positive Supply Current, I+ VEN = 5.0V, VA = 0V -3.2 - 4.5 mA
Negative Supply Current, I- -3.2 - 4.5 mA
Positive Standby Supply Current, I+ VEN = 0V, VA = 0V -3.2 - 4.5 mA
Negative Standby Supply Current, I- -3.2 - 4.5 mA
NOTES:
3. Typical values are for design aid only, not guaranteed and not subject to production testing.
4. The algebraic convention whereby the most negative value is a minimum, and the most positive value is a maximum, is used in this dat a sheet.
5. Off isolation = 20Log |VS|/|VD|, where VS = input to Off switch, and VD = output due to VS.
6. ID(ON) is leakage from driver into “ON” switch.
7. Parameter not tested. Parameter guaranteed by design or characterization.
DG508A
5FN3137.6
March 4, 2009
Test Circuits and Waveforms
FIGURE 1A. TEST CIRCUIT FIGURE 1B. MEASUREMENT POINTS
FIGURE 1. SWITCHING TIME
FIGURE 2A. TEST CIRCUIT FIGURE 2B. MEASUREMENT POINTS
FIGURE 2. ENABLE TIMES
FIGURE 3A. TEST CIRCUIT FIGURE 3B. MEASUREMENT POINTS
FIGURE 3. BREAK-BEFORE-MAKE INTERVAL
EN
A2
S2 THRU S7
A1
A0
LOGIC
INPUT
50Ω
+2.4V
SWITCH
OUTPUT
35pF
1MΩ
+15V
-15V
-10V
+10V
GND V-
DG508A S1
S8
D
V+
VO
3V
50%
0
VS1
0.8VS1
0
0.8VS8
VS8
SWITCH
OUTPUT
VO
TRANSITION
S1 ON
S8 ON
LOGIC INPUT tr < 20ns
tf < 20ns
TIME TRANSITION
TIME
EN
A2
S2 THRU S8
A1
A0
EN 50Ω
SWITCH
OUTPUT
35pF1kΩ
+15V
-15V
GND V-
DG508A S1
D
V+
VO
-5V 3V
50%
0V
SWITCH
OUTPUT
VO
tr < 20ns
tf < 20ns
0V
VO
tON (EN) tOFF (EN)
EN 50%
0.9VO
0.1VO
EN
A1
A2
LOGIC
INPUT
50Ω
+2.4V
SWITCH
OUTPUT
35pF1kΩ
+15V
-15V
GND V-
DG508A
S1 THRU S8
D
V+
VO
A0
+5V (VS)3V
50%
0V
SWITCH
OUTPUT
VO
tr < 20ns
tf < 20ns
0V
LOGIC
tOPEN
INPUT
50%
VS
DG508A
6FN3137.6
March 4, 2009
FIGURE 4A. TEST CIRCUIT FIGURE 4B. CHARGE INJECTION WAVEFORMS
FIGURE 4. CHARGE INJECTION
Test Circuits and Waveforms (Continued)
EN
A2
S1
A1
A0
1000pF
+15V
-15V
GND V-
DG508A
D
V+
VO
LOGIC
INPUT
3V
EN
0
VOΔVO
ΔVO is the measured voltage error due to charge injection.
The charge transfer error in Coulombs is Q = CL x ΔVO.
Typical Performance Curves
FIGURE 5. rDS(ON) vs ANALOG SIGNAL VOLTAGE vs
SUPPLY VOLTAGE FIGURE 6. TYPICAL rDS(ON) VARIATION WITH TEMPERATURE
ANALOG SIGNAL VOLTAGE (V)
550
-10 -5 0 5 10 15
rDS(ON) (Ω)
500
450
400
350
300
250
200
150
100
50
0
-15
V+ = +7.5V, V- = -7.5V
V+ = +10V, V- = -10V
V+ = +12V, V- = -12V
V+ = +15V, V- = -15V
TEMPERATURE (oC)
-25 0 45 70 100 125-55 20
rDS(ON) (Ω)
V+ = +15V V- = -15V
VEN = 2.4V
IO = -200µA +10V SIGNALS
-10V SIGNALS
400
300
200
100
0
DG508A
7FN3137.6
March 4, 2009
Die Characteristics
DIE DIMENSIONS:
3100μm x 2083μm
METALLIZATION:
Type: Al
Thickness: 10kÅ ±1kÅ
PASSIVATION:
Type: PSG/Nitride
Thickness: PSG: 7kÅ ±1.4kÅ
Nitride: 8kÅ ±1.2kÅ
WORST CASE CURRENT DENSITY:
9.1 x 104 A/cm2
Metallization Mask Layout DG508A
EN A0A1A2
GND
V+
S5
S6
S7
S4DS
8
V-
S1
S2
S3
DG508A
8FN3137.6
March 4, 2009
DG508A
Dual-In-Line Plastic Packages (PDIP)
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated in JE-
DEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and are measured with the leads constrained to be perpendic-
ular to datum .
7. eB and eC are measured at the lead tips with the leads unconstrained.
eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
eA
-C-
C
L
E
eA
C
eB
eC
-B-
E1
INDEX 12 3 N/2
N
AREA
SEATING
BASE
PLANE
PLANE
-C-
D1
B1 Be
D
D1
A
A2
L
A1
-A-
0.010 (0.25) C AMBS
E16.3 (JEDEC MS-001-BB ISSUE D)
16 LEAD DUAL-IN-LINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A-0.210 -5.33 4
A1 0.015 -0.39 -4
A2 0.115 0.195 2.93 4.95 -
B0.014 0.022 0.356 0.558 -
B1 0.045 0.070 1.15 1.77 8, 10
C0.008 0.014 0.204 0.355 -
D0.735 0.775 18.66 19.68 5
D1 0.005 -0.13 -5
E0.300 0.325 7.62 8.25 6
E1 0.240 0.280 6.10 7.11 5
e 0.100 BSC 2.54 BSC -
eA0.300 BSC 7.62 BSC 6
eB-0.430 -10.92 7
L0.115 0.150 2.93 3.81 4
N16 169
Rev. 0 12/93
9
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No lice nse is gran t ed by i mpli catio n or other wise u nder an y p a tent or patent rights of I nter sil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN3137.6
March 4, 2009
DG508A
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
NOTES:
1. Index area: A notch or a pin one identification mark shall be locat-
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
3. Dimensions b1 and c1 apply to lead base metal only . Dimension
M applies to lead plating and finish thickness.
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
bbb C A - B
S
c
Q
L
A
SEATING
BASE
D
PLANE
PLANE
-D-
-A-
-C-
-B-
α
D
E
S1
b2 b
A
e
M
c1
b1
(c)
(b)
SECTION A-A
BASE
LEAD FINISH
METAL
eA/2
A
M
SS
ccc C A - B
MD
SSaaa CA - B
MD
SS
eA
F16.3 MIL-STD-1835 GDIP1-T16 (D-2, CONFIGURATION A)
16 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A-0.200 -5.08 -
b0.014 0.026 0.36 0.66 2
b1 0.014 0.023 0.36 0.58 3
b2 0.045 0.065 1.14 1.65 -
b3 0.023 0.045 0.58 1.14 4
c0.008 0.018 0.20 0.46 2
c1 0.008 0.015 0.20 0.38 3
D-0.840 -21.34 5
E0.220 0.310 5.59 7.87 5
e 0.100 BSC 2.54 BSC -
eA 0.300 BSC 7.62 BSC -
eA/2 0.150 BSC 3.81 BSC -
L0.125 0.200 3.18 5.08 -
Q0.015 0.060 0.38 1.52 6
S1 0.005 -0.13 -7
α90o105o90o105o-
aaa - 0.015 -0.38 -
bbb - 0.030 -0.76 -
ccc - 0.010 -0.25 -
M-0.0015 -0.038 2, 3
N16 168
Rev. 0 4/94