SPOC - BTS5566G
SPI Power Controller
Data Sheet, Rev. 1.3, October 2007
Automotive Power
Data Sheet 2 Rev. 1.3, 2007-10-30
SPI Power Controller
SPOC - BTS5566G
1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1 Pin Assignment SPOC - BTS5566G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.1 Power Supply Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.4 Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6 Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.1 Output ON-State Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.2 Input Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.3 Power Stage Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.5 Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7ProtectionFunctions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.1 Over Load Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.2 Over Temperature Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.3 Reverse Polarity Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.4 Over Voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.5 Loss of Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.6 Loss of Vbb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.7 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.8 Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
8 Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
8.1 Diagnosis Word at SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8.2 Load Current Sense Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8.3 Switch Bypass Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.5 Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
9 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
9.1 SPI Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
9.2 Daisy Chain Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
9.3 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
9.4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9.5 SPI Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
9.6 Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
10 Application Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
11 Package Outlines SPOC - BTS5566G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
12 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table of Contents
PG-DSO-36-34
Type Package Marking
SPOC - BTS5566G PG-DSO-36-34 BTS5566G
Data Sheet 3 Rev. 1.3, 2007-10-30
SPI Power Controller
for Advanced Light Control
SPOC - BTS5566G
1Overview
The SPOC - BTS5566G is a five channel high-side smart power switch in
PG-DSO-36-34 package providing embedded protective functions. It is
especially designed to control standard exterior lighting in automotive
applications. It is designed to drive lamps up to 3*27W + 2*10W.
Configuration and status diagnosis is done via SPI. Additionally, there is
a current sense signal available for each channel that is routed via a
multiplexer to a single diagnosis pin.
The SPOC - BTS5566G provides a fail-safe function via limp home input
pin.
Product Summary
Operating Voltage Power Switch VBB 4.5 … 28 V
Logic Supply Voltage VDD 3.8 … 5.5 V
Over Voltage Protection VBB(AZ,min) 40 V
Maximum Stand-By Current at 25 °CIBB(OFF) 3µA
On-State Resistance at Tj = 150 °
channel 0, 1
channel 2
channel 3,4
RDS(ON) max
49 mΩ
64 mΩ
180 mΩ
SPI Access Frequency fSCLK(max) 2MHz
SPI Power Controller
SPOC - BTS5566G
Overview
Data Sheet 4 Rev. 1.3, 2007-10-30
Basic Features
• 8 bit serial peripheral interface (daisy chain capable SPI) for control and diagnostics
• CMOS compatible parallel input pins for each channel provide straightforward PWM operation
• Selectable AND- / OR-combination for parallel inputs (PWM control)
• Very low stand-by current
• Optimized electromagnetic compatibility (EMC) for bulbs
• Stable behavior at under voltage
• Device ground independent from load ground
• Green Product (RoHS-Compliant)
• AEC Qualified
Protective Functions
• Reverse battery protection with external components
• Short circuit protection
• Over load protection
• Multi step current limitation
• Thermal shutdown with latch
• Over voltage protection
• Loss of ground protection
• Electrostatic discharge protection (ESD)
Diagnostic Functions
• Multiplexed proportional load current sense signals (IS)
• Enable function for current sense signal configurable via SPI
• High accuracy of current sense signal at wide load current range
• Feedback on over temperature and over load via SPI
• Multiplexed switch bypass monitor provides short circuit to Vbb detection
Application Specific Functions
• Fail-safe activation via LHI pin and configuration via input pins
Applications
• High-side power switch for 12 V grounded loads in automotive application
• Especially designed for standard exterior lighting like tail light, brake light, reverse light, parking light, license
plate lighting and turn signal indicators
• Replaces electromechanical relays, fuses and discrete circuits
Data Sheet 5 Rev. 1.3, 2007-10-30
SPI Power Controller
SPOC - BTS5566G
Overview
Figure 1 Application Example
Abbreviations:
BL Brake Light (21 W, 27 W)
RL Reverse Light (21 W, 27 W)
TL Tail Light (5 W, 7 W, 10 W)
LIC License plate lighting (5 W, 10 W)
IND Indicator / Flasher (21 W, 27 W)
Applicat ion rear . emf
IND
TL
RL BL
IND
TL
RL
BL
SPOC
LIC
limp home control
fail safe system
limp home control
watchdog
SPOC - BTS5566G SPOC - BTS5566G
180 mΩ49 mΩ49 mΩ64 mΩ180 mΩ180 mΩ64 mΩ49 mΩ49 mΩ180 mΩ
SPI Power Controller
SPOC - BTS5566G
Block Diagram
Data Sheet 6 Rev. 1.3, 2007-10-30
2 Block Diagram
The SPOC - BTS5566G is a five channel high-side power switch in PG-DSO-36-34 package providing embedded
protective functions. An 8 bit serial peripheral interface (SPI) is used for configuration and diagnosis. The SPI can
be used in daisy chain configuration.
The device provides a current sense signal per channel that is multiplexed to the diagnosis pin IS. It can be
enabled and disabled via SPI commands. An over load and over temperature flag is provided in the SPI diagnosis
word. A multiplexed switch bypass monitor provides diagnosis at short-circuit to VBB.
The power transistors are built by N-channel vertical power MOSFETs with charge pumps. The device is
monolithically integrated in SMART SIPMOS technology.
Figure 2 Block Diagram SPOC - BTS5566G
4
3
2
1
channel 0
power
supply
driver
logic
gate control
&
charge pump
clamp for
inductive
load
load current
limitation
load cur rent
sense
tem perature
sensor
ESD
protection
IN2
IN3
IN4
IN0
IN1
GND
SPI
current sense m ultiplexerIS
SO
SCLK
SI
CS
LHI limp home control
switch bypass
monitor
PWM contr ol
VBB
OUT3
OUT2
OUT1
OUT0
OUT4
Data Sheet 7 Rev. 1.3, 2007-10-30
SPI Power Controller
SPOC - BTS5566G
Block Diagram
2.1 Terms
The following figure shows all terms used in this data sheet.
Figure 3 Terms
In all tables of electrical characteristics is valid: Channel related symbols without channel number are valid for each
channel separately (e.g. VDS specification is valid for VDS0 … VDS4).
All SPI register bits are marked as follows: ADDR.PARAMETER (e.g. HWCR.CTL). In SPI register description, the
values in bold letters (e.g. 0) are default values.
I
IN 0
V
IN 0
I
IN 1
V
IN 1
V
SO
I
IN 2
V
SI
I
IN 3
V
BB
V
CS
I
IS
I
BB
IN0
IN1
IN2
IN3
IS
VBB
I
CS
CS
SCLK
V
IN 2
V
IN 3
V
IN 4
V
dd
I
DD
I
SO
VDD
SO
I
IN 4
IN4
V
IS
I
LHI
LHI
I
SI
SI
V
LHI
OUT0
I
L0
OUT1
OUT3
OUT4
I
L1
I
L3
I
L4
OUT2
I
L2
GND
I
GND
I
SC L K
V
SC L K
V
OUT1
V
DS1
V
OUT4
V
DS4
V
OUT3
V
OUT2
V
OUT0
V
DS3
V
DS2
V
DS0
SPI Power Controller
SPOC - BTS5566G
Pin Configuration
Data Sheet 8 Rev. 1.3, 2007-10-30
3 Pin Configuration
3.1 Pin Assignment SPOC - BTS5566G
Figure 4 Pin Configuration PG-DSO-36-34
(top view)
OUT1
OUT1
OUT1
VBB
36
35
34
33
32
31
VBB
1
2
3
4
5
6
7
8
30
29
OUT0
OUT0
OUT0
OUT0
OUT3
OUT3
OUT4
OUT1
28
27
26
25
24
23
9
10
11
12
13
14
15
16
22
21
OUT2
OUT2
OUT2
OUT2
OUT4
VBB
18 19
VBB
2017
CS
SCLK
SI
SO
VDD
GND
LHI
n.c.
IS
IN1
IN0
IN2
IN3
IN4
n.c.
VBB
Data Sheet 9 Rev. 1.3, 2007-10-30
SPI Power Controller
SPOC - BTS5566G
Pin Configuration
3.2 Pin Definitions and Functions
Pin Symbol I/O Function
Power Supply Pins
1, 16, 18, 19, 36 1)
1) All VBB pins have to be connected.
VBB – Positive power supply for high-side power switch and limp home block
3 VDD – Logic supply (5 V)
2 GND – Ground connection
Parallel Input Pins
8 IN0 I Input signal of channel 0
9 IN1 I Input signal of channel 1
10 IN2 I Input signal of channel 2
11 IN3 I Input signal of channel 3
12 IN4 I Input signal of channel 4
Power Output Pins
32, 33, 34, 35 2)
2) All output pins of each channel have to be connected.
OUT0 O Protected high-side power output of channel 0
28, 29,30, 31 2) OUT1 O Protected high-side power output of channel 1
24, 25,26, 27 2) OUT2 O Protected high-side power output of channel 2
22, 23 2) OUT3 O Protected high-side power output of channel 3
20, 21 2) OUT4 O Protected high-side power output of channel 4
SPI & Diagnosis Pins
7 CS I Chip select of SPI interface (low active)
6 SCLK I Serial clock of SPI interface
5 SI I Serial input of SPI interface
4 SO O Serial output of SPI interface
13 IS O Diagnosis output signal
Limp Home Pins
14 LHI I Limp home mode activation
Other Pins
15, 17 n.c. – not connected, floating
SPI Power Controller
SPOC - BTS5566G
Electrical Characteristics
Data Sheet 10 Rev. 1.3, 2007-10-30
4 Electrical Characteristics
4.1 Absolute Maximum Ratings
Absolute Maximum Ratings1)
Tj = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin.
(unless otherwise specified).
Pos. Parameter Symbol Limit Values Unit Conditions
min. max.
Supply Voltage
4.1.1 Power supply voltage VBB -0.3 28 V –
4.1.2 Logic supply voltage VDD -0.3 5.5 V –
4.1.3 Reverse polarity voltage according Figure 23 -VBAT(rev) –16VTjStart = 25 °C
t ≤ 2min 2)
4.1.4 Supply voltage for full short circuit protection (single
pulse)
(Tj(0) = -40 °C … 150 °C)
VBB(SC) 020VRECU = 20mΩ
RCable=
16mΩ/m
LCable= 1µH/m
l = 0 or 5m 3)
4.1.5 Voltage at power transistor VDS –54V–
4.1.6 Supply Voltage for Load Dump protection VBB(LD) –41VRI = 2 Ω 4)
t = 400ms
4.1.7 Current through ground pin IGND -100 25 mA t ≤ 2min
4.1.8 Current through VDD pin IDD -25 12 mA t ≤ 2min
Power Stages
4.1.9 Load current IL-IL(LIM) IL(LIM) A5)
Diagnosis Pin
4.1.10 Current through sense pin IS IIS -10 10 mA t ≤ 2min
Input Pins
4.1.11 Voltage at input pins VIN -0.3 8.0 V –
4.1.12 Current through input pins IIN -0.75
-2.0
0.75
2.0
mA –
t ≤ 2min
SPI Pins
4.1.13 Voltage at chip select pin VCS -0.3 5.7 V –
4.1.14 Current through chip select pin ICS -2.0 2.0 mA t ≤ 2min
4.1.15 Voltage at serial input pin VSI -0.3 5.7 V –
4.1.16 Current through serial input pin ISI -2.0 2.0 mA t ≤ 2min
4.1.17 Voltage at serial clock pin VSCLK -0.3 5.7 V –
4.1.18 Current through serial clock pin ISCLK -2.0 2.0 mA t ≤ 2min
4.1.19 Current through serial output pin SO ISO -2.0 2.0 mA t ≤ 2min
Limp Home Pins
4.1.20 Voltage at limp home input pin VLHI -0.3 8.0 V –
4.1.21 Current through limp home input pin ILHI -0.75
-2.0
0.75
2.0
mA –
t ≤ 2min
Data Sheet 11 Rev. 1.3, 2007-10-30
SPI Power Controller
SPOC - BTS5566G
Electrical Characteristics
Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are
not designed for continuous repetitive operation.
Temperatures
4.1.22 Junction temperature Tj-40 150 °C–
4.1.23 Dynamic temperature increase while switching ∆Tj–60K–
4.1.24 Storage temperature TSTG -55 150 °C–
ESD Susceptibility
4.1.25 ESD resistivity HBM
OUT pins
other pins
VESD
-4
-2
4
2
kV HBM6)
–
–
1) Not subject to production test, specified by design.
2) Specified RthJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu).
3) In accordance to AEC Q100-012 and AEC Q101-006.
4) RI is the internal resistance of the load dump pulse generator.
5) Current limitation is a protection feature. Operation in current limitation is considered as “outside” normal operating range.
Protection features are not designed for continuous repetitive operation.
6) ESD resistivity, HBM according to EIA/JESD 22-A 114B (1.5kΩ, 100pF).
Absolute Maximum Ratings1)
Tj = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin.
(unless otherwise specified).
Pos. Parameter Symbol Limit Values Unit Conditions
min. max.
SPI Power Controller
SPOC - BTS5566G
Power Supply
Data Sheet 12 Rev. 1.3, 2007-10-30
5 Power Supply
The SPOC - BTS5566G is supplied by two supply voltages VBB and VDD. The VBB supply line is used by the power
switches. The VDD supply line is used by the SPI related circuitry and for driving the SO line. A capacitor between
pins VDD and GND is recommended.
There is a power-on reset function implemented for the VDD logic supply voltage. After start-up of the logic power
supply, all SPI registers are reset to their default values. The SPI interface including daisy chain function is active
as soon as VDD is provided in the specified range independent of VBB.
5.1 Power Supply Modes
The following table shows all possible power supply modes for VBB, VDD and the pin LHI.
To achieve stand-by mode, the limp home block must be disabled (LHI = 0 V), all channels must be switched off
and the thermal latches have to be cleared. As a result the stand-by current IBB(OFF) is valid as listed. In case of
active VDD supply, the idle mode parameters are valid only, when additionally all SPI registers are at default values
(see Section 9.6) e.g. after a reset command.
Power Supply Modes
VBB 0V 0V 0V 0V 13.5V 13.5V 13.5V 13.5V
VDD 0V0V5V5V0V0V5V5V
LHI 0V5V0V5V0V5V0V5V
PROFET operating ––––✓✓✓✓
Limp home mode –––––✓ – ✓
SPI (logic) reset reset ✓✓reset reset ✓reset
Stand-by current ––––✓–––
Idle current ––––––✓ 1)
1) When all channels are in OFF-state and all SPI registers are at default values.
–
Diagnosis ––––––✓✓ 2)
2) Current sense diagnosis not available in limp home mode.
Data Sheet 13 Rev. 1.3, 2007-10-30
SPI Power Controller
SPOC - BTS5566G
Power Supply
5.2 Reset
There are several reset trigger implemented in the device. They reset the SPI registers to their default values. The
power stages as well as the analog watchdog block are not affected by the reset signals.
The first SPI transmission after any kind of reset contains at pin SO the read information from register OUT, and
the transmission error bit TER is set.
Power-On Reset
The power-on reset is released, when VDD voltage level is higher than VDD(PO). The SPI interface can be accessed
after wake up time tWU(PO).
Reset Command
There is a reset command available to reset all register bits of the register bank and the diagnosis registers. As
soon as HWCR.RST = 1, a reset is triggered equivalent to power-on reset. The SPI interface can be accessed after
transfer delay time tCS(td).
Limp Home Mode
In limp home mode, the SPI write-registers are reset. The SPI interface is operating normally, so the limp home
register bit LHI as well as the error flags can be read.
SPI Power Controller
SPOC - BTS5566G
Power Supply
Data Sheet 14 Rev. 1.3, 2007-10-30
5.3 Electrical Characteristics
Note: Characteristics show the deviation of parameter at the given supply voltage and junction temperature.
Typical
values show the typical parameters expected from manufacturing at
V
BB
= 13.5 V,
V
DD
= 4.3 V and
T
j
= 25
°
C.
Electrical Characteristics Power Supply
Unless otherwise specified: VBB = 9 V to 16 V, VDD = 3.8 V to 5.5 V, Tj = -40 °C to +150 °C.
typical values: VBB = 13.5 V, VDD = 4.3 V, Tj = 25 °C.
Pos. Parameter Symbol Limit Values Unit Test Conditions
min. typ. max.
5.3.1 Operating voltage VBB 4.5 – 28 V –
5.3.2 Stand-by current for whole device with
loads
IBB(OFF)
–
–
–
1.2
–
–
3
3
50
µAVDD = 0 V
VLHI = 0 V
VIN = 0 V
Tj = 25 °C
Tj ≤ 85 °C 1)
Tj = 150 °C
1) Not subject to production test, specified by design.
Idle current for whole device with loads IBB(idle)
–
–
–
–
–
–
3
3
50
µAVDD = 5 V
VLHI = 0 V
VIN = 0 V
Tj = 25 °C
Tj ≤ 85 °C 1)
Tj = 150 °C
5.3.3 Logic supply voltage VDD 3.8 – 5.5 V –
5.3.4 Logic supply current IDD – 45 150 µAVCS = 0 V
fSCLK = 0 Hz
5.3.5 Logic idle current IDD(idle) –1535µAVCS = Vdd
fSCLK = 0 Hz
5.3.6 Operating current for whole device IGND –1020mAfSCLK = 0 Hz
5.3.7 Power-On reset threshold voltage VDD(PO) ––3.8V–
5.3.8 Power-On wake up time tWU(PO) – – 500 µs–
Data Sheet 15 Rev. 1.3, 2007-10-30
SPI Power Controller
SPOC - BTS5566G
Power Supply
5.4 Command Description
HWCR
Hardware Configuration Register
W/R 43210
read RST 0SBM PWM CTL
write RST 0 0 PWM CTL
Field Bits Type Description
RST 4 r Reset Command
0Normal operation
1 Device in reset due to limp home mode
RST 4 w Reset Command
0Normal operation
1 Execute reset command
SPI Power Controller
SPOC - BTS5566G
Power Stages
Data Sheet 16 Rev. 1.3, 2007-10-30
6 Power Stages
The high-side power stages are built by N-channel vertical power MOSFETs (DMOS) with charge pumps. There
are five channels implemented in the device. Each channel can be switched on via an input pin or via SPI register
OUT.
6.1 Output ON-State Resistance
The on-state resistance RDS(ON) depends on the supply voltage VBB as well as on the junction temperature Tj.
Figure 5 shows those dependencies. The behavior in reverse polarity mode is described in Section 7.3.
Figure 5 Typical On-State Resistance
6.2 Input Circuit
There are two ways of using the input pins in combination with the OUT SPI register by programming the
HWCR.PWM parameter.
•HWCR.PWM = 0: A channel is switched on either by the according OUT register bit or the input pin.
•
HWCR.PWM
= 1: A channel is switched on by the according
OUT
register bit only, when the input pin is high. In this
configuration, a PWM signal can be given to the input pin and the channel is activated by the SPI register
OUT.
Figure 6 shows the complete input switch matrix.
Figure 6 Input Switch Matrix
The current sink to ground at the input pins ensures that the input signal is low in case of an open input pin. The
zener diode protects the input circuit against ESD pulses.
50
100
150
200
250
0 5 10 15 20 25
RDS(ON) /mΩ
V
bb
/V
channel 0, 1 (bulb)
channel 2 (bulb)
channel 3, 4
0
50
100
150
200
250
-50 -25 0 25 50 75 100 125 150
RDS(ON) /mΩ
T /°C
channel 0, 1 (bulb)
channel 2 (bulb)
channel 3, 4
Vbb = 13.5 V Tj = 25 °C
InputMatrix.emf
IN0
IN1
IN2
IN3
IN4
Gate Driver 2
Gate Driver 1
Gate Driver 0
Gate Driver 4
Gate Driver 3
&
OR
OUT2 OUT1 OUT0OUT4 OUT3
&
OR
&
OR
&
OR
&
OR
PWM
I
IN0
I
IN1
I
IN2
I
IN3
I
IN4
Data Sheet 17 Rev. 1.3, 2007-10-30
SPI Power Controller
SPOC - BTS5566G
Power Stages
6.3 Power Stage Output
The power stages are built to be used in high side configuration (Figure 7).
Figure 7 Power Stage Output
The power DMOS switches with a dedicated slope, which is optimized in terms of EMC emission.
Figure 8 Switching a Load (resistive)
When switching off inductive loads with high-side switches, the voltage VOUT drops below ground potential,
because the inductance intends to continue driving the current. To prevent destruction of the device, there is a
voltage clamp mechanism implemented that limits that negative output voltage to a certain level (VON(CL) (6.4.3)).
See Figure 7 for details. The maximum allowed load inductance is limited.
Output.emf
OUT
GND V
OUT
VBB
V
ON
V
bb
IN
V
OUT
t
SwitchOn.emf
t
ON
t
OFF
t
90%
10%
70%
dV/
dt
ON
30%
70%
dV/
dt
OFF
30%
SPI Power Controller
SPOC - BTS5566G
Power Stages
Data Sheet 18 Rev. 1.3, 2007-10-30
6.4 Electrical Characteristics
Electrical Characteristic Power Stages
Unless otherwise specified: VBB = 9 V to 16 V, Tj = -40 °C to +150 °C.
typical values: VBB = 13.5 V, Tj = 25 °C.
Pos. Parameter Symbol Limit Values Unit Test Conditions
min. typ. max.
Output Characteristics
6.4.1 On-State resistance RDS(ON) mΩ
channel 0, 1 –
–
22.3
38
–
49
1)Tj = 25 °, IL=2.6A
Tj = 150 °, IL=2.6A
channel 2 –
–
25.2
49
–
64
1)Tj = 25 °C, IL=2.6A
Tj = 150 °C, IL=2.6A
channel 3, 4 –
–
72.9
141
–
180
1)Tj = 25 °C, IL=1A
Tj = 150 °C,IL=1A
6.4.2 Output voltage drop limitation at
small load currents
VDS(NL) mV
channel 0, 1, 2 – 35 – IL = 35 mA
channel 3, 4 – 35 – IL = 35 mA
6.4.3 Output clamp VON(CL) 40 47 54 V IL = 20 mA
6.4.4 Output leakage current per
channel
IL(OFF) µAVIN = 0 V
OUT.OUTn = 0
channel 0, 1 –
–
0.1
–
10
40
stand-by
not stand-by
channel 2 –
–
0.1
–
10
40
stand-by
not stand-by
channel 3, 4 –
–
0.1
–
8
40
stand-by
not stand-by
6.4.5 Inverse current capability per
channel
-IL(IC) A No influence on
functionality of
unaffected channels 1)
channel 0, 1, 2 – 2.5 – –
channel 3, 4 – 1.0 – –
Thermal Resistance
6.4.6 Junction to Case RthJC ––20 K/W
1)
6.4.7 Junction to Ambient, all channels
active
RthJA –40–K/W
1) 2)
Input Characteristics
6.4.8 L-input level VIN(L) -0.3 – 1.0 V –
6.4.9 H-input level VIN(H) 2.6–5.5V–
6.4.10 L-input current IIN(L) 32575µAVIN = 0.4 V
6.4.11 H-input current IIN(H) 10 40 75 µAVIN = 5 V
Data Sheet 19 Rev. 1.3, 2007-10-30
SPI Power Controller
SPOC - BTS5566G
Power Stages
Timings
6.4.12 Turn-on time to 90% VBB tON µsVBB = 13.5 V
channel 0, 1, 2 – – 250 RL = 6.8 Ω
channel 3, 4 – – 250 RL = 18 Ω
6.4.13 Turn-off time to 10% VBB tOFF µsVBB = 13.5 V
channel 0, 1, 2 – – 290 RL = 6.8 Ω
channel 3, 4 – – 290 RL = 18 Ω
6.4.14 Turn-on slew rate 30% to 70% VBB dV/ dtON V/µsVBB = 13.5 V
channel 0, 1, 2 0.1 – 0.5 RL = 6.8 Ω
channel 3, 4 0.1 – 0.5 RL = 18 Ω
6.4.15 Turn-off slew rate 70% to 30% VBB -dV/ dtOFF V/µsVBB = 13.5 V
channel 0, 1, 2 0.1 – 0.5 RL = 6.8 Ω
channel 3, 4 0.1 – 0.5 RL = 18 Ω
1) Not subject to production test, specified by design.
2) Specified RthJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu).
Electrical Characteristic Power Stages
Unless otherwise specified: VBB = 9 V to 16 V, Tj = -40 °C to +150 °C.
typical values: VBB = 13.5 V, Tj = 25 °C.
Pos. Parameter Symbol Limit Values Unit Test Conditions
min. typ. max.
SPI Power Controller
SPOC - BTS5566G
Power Stages
Data Sheet 20 Rev. 1.3, 2007-10-30
6.5 Command Description
OUT
Output Configuration Registers
W/R RB543210
read/write 0 0 OUT4 OUT3 OUT2 OUT1 OUT0
Field Bits Type Description
OUTn
n = 4 to 0
nr/wSet Output Mode for Channel n
0Channel n is switched off
1 Channel n is switched on
HWCR
Hardware Configuration Register
W/R 43210
read RST 0SBM PWM CTL
write RST 00PWMCTL
Field Bits Type Description
PWM 1 rw PWM Configuration
0Input signal OR-combined with according OUT register bit
1 Input signal AND-combined with according OUT register bit
Data Sheet 21 Rev. 1.3, 2007-10-30
SPI Power Controller
SPOC - BTS5566G
Protection Functions
7 Protection Functions
The device provides embedded protective functions, which are designed to prevent IC destruction under fault
conditions described in this data sheet. Fault conditions are considered as “outside” normal operating range.
Protective functions are neither designed for continuous nor for repetitive operation.
7.1 Over Load Protection
The load current IL is limited by the device itself in case of over load or short circuit to ground. There are multiple
steps of current limitation which are selected automatically depending on the voltage VDS across the power DMOS.
Please note that the voltage at the OUT pin is VBB -VDS. Please refer to following figures for details.
Figure 9 Current Limitation Channels 0, 1 (minimum values)
Figure 10 Current Limitation Channels 2 (minimum values)
Figure 11 Current Limitation Channels 3, 4 (minimum values)
Current limitation to the value IL(LIM) is realized by increasing the resistance of the output channel, which leads to
rapid temperature rise inside.
CurrentLimitation01.emf
5 101520 V
DS
25
I
L
5
10
15
20
25
CurrentLimitation2.emf
5 101520 V
DS
25
I
L
5
10
15
20
25
CurrentLimitation34.emf
I
L
5 101520 V
DS
25
2
4
6
8
10
12
SPI Power Controller
SPOC - BTS5566G
Protection Functions
Data Sheet 22 Rev. 1.3, 2007-10-30
7.2 Over Temperature Protection
A temperature sensor for each channel causes an overheated channel to switch off latched to prevent destruction
( also even in case of VDD = 0V). All over temperature latches are cleared by SPI command HWCR.CTL = 1.
Figure 12 Shut Down by Over Temperature
7.3 Reverse Polarity Protection
In reverse polarity mode, power dissipation is caused by the intrinsic body diode of each DMOS channel as well
as each ESD diode of the logic pins. The reverse current through the channels has to be limited by the connected
loads. The current trough the ground pin, sense pin IS, the logic power supply pin VDD, the SPI pins and the
watchdog pins has to be limited as well (please refer to the maximum ratings listed on Page 10).
Note: No other protection mechanism such as temperature protection or current limitation is active during reverse
polarity.
7.4 Over Voltage Protection
In addition to the output clamp for inductive loads as described in Section 6.3, there is a clamp mechanism
available for over voltage protection. The current through the ground connection has to be limited during over
voltage. Please note that in case of over voltage the pin GND may have a high voltage offset to the module ground.
7.5 Loss of Ground
In case of complete loss of the device ground connections, but connected load ground, the SPOC - BTS5566G
securely changes to or stays in off-state.
7.6 Loss of Vbb
In case of loss of Vbb connection in on-state, all inductance of the loads has to be demagnetized through the
ground connection or through an additional path from VBB to ground. When a diode is used in the ground path for
reverse polarity reasons, the ground connection is not available for demagnetization. Then for example, a resistor
can be placed in parallel to the diode or a suppressor diode can be used between VBB and GND.
IN
I
L
I
IS
t
I
L(LIM)
t
t
ERR
t
OverLoad.emf
CTL = 1
Data Sheet 23 Rev. 1.3, 2007-10-30
SPI Power Controller
SPOC - BTS5566G
Protection Functions
7.7 Electrical Characteristics
Electrical Characteristics Protection Functions
Unless otherwise specified: VBB = 9 V to 16 V, Tj = -40 °C to +150 °C
typical values: VBB = 13.5 V, Tj = 25 °C
Pos. Parameter Symbol Limit Values Unit Test Conditions
min. typ. max.
Over Load Protection
7.7.1 Load current limitation IL(LIM) AVDS = 7 V
channel 0 24 – 481) –
channel 1 24 – 481) –
channel 2 24 – 481) –
channel 3 12 – 271) –
channel 4 12 – 271) –
7.7.2 Initial short circuit shut down time tOFF(SC) µsTjStart = 25 °C 1)
1) Not subject to production test, specified by design.
channel 0, 1 – 550 – –
channel 2 – 400 – –
channel 3, 4 – 400 – –
Over Temperature Protection
7.7.3 Thermal shut down temperature Tj(SC) 150 1701) –°C–
7.7.4 Thermal hysteresis ∆Tj–7–K
1)
Reverse Battery
7.7.5 Drain-Source diode voltage
(VOUT >Vbb)
-VDS(rev) mV Tj = 150 °C
channel 0, 1 – 600 – IL = -2.5 A
channel 2 – 620 – IL = -2.5 A
channel 3, 4 – 600 – IL = -1 A
Over Voltage
7.7.6 Overvoltage protection VBB(AZ) 40 47 54 V IBB = 4 mA
Loss of GND protection
7.7.7 Output current while GND
disconnected
IL(GND) ––1mA
1)
SPI Power Controller
SPOC - BTS5566G
Protection Functions
Data Sheet 24 Rev. 1.3, 2007-10-30
7.8 Command Description
HWCR
Hardware Configuration Register
W/R 43210
read RST 0SBM PWM CTL
write RST 0 0 PWM CTL
Field Bits Type Description
CTL 0 rw Clear Thermal Latch
0Thermal latches are untouched
1 Command: Clear all thermal latches
Data Sheet 25 Rev. 1.3, 2007-10-30
SPI Power Controller
SPOC - BTS5566G
Diagnosis
8 Diagnosis
For diagnosis purpose, the SPOC - BTS5566G provides a current sense signal and the diagnosis word at SPI.
There is a current sense multiplexer implemented that is controlled via SPI. The sense signal can also be disabled
by SPI command. A switch bypass monitor allows to detect a short circuit between the output pin and the battery
voltage.
Please refer to Figure 13 for details.
Figure 13 Block Diagram: Diagnosis
For diagnosis feedback at different operation modes, please see following table.
Table 1 Operation Modes 1)
1) L = low level, H = high level, Z = high impedance, potential depends on leakage currents and external circuit x = undefined
Operation Mode Input Level
OUT.OUTn
Output Level
VOUT
Current
Sense IIS
Error Flag
ERRn2)
2) The error flags are latched until they are transmitted in the standard diagnosis word via SPI
HWCR.
SBM
Normal Operation (OFF) L / 0
(OFF-state)
GND Z 0 1
Short Circuit to GND GND Z 0 1
Over Temperature Z Z 0 x
Short Circuit to VBB VBB Z00
Open Load Z Z 0 x
Normal Operation (ON) H / 1
(ON-state)
~VBB IL/kILIS 00
Current Limitation < VBB Z1x
Short Circuit to GND ~GND Z 1 1
Over Temperature Z Z 13)
3) The over temperature flag is set latched and can be cleared by SPI command HWCR.CTL
x
Short Circuit to VBB VBB <IL/kILIS 00
Open Load VBB Z00
channel 0
load
current
sense
Diagnosis.emf
R
IS
current sense multiplexer
IS
T
gate
control
load cur rent
limitation
latch temperature
sensor
ERR0
OR
latch
DCR.MUX
SBM
HWCR.
OUT4
OUT3
OUT2
OUT1
OUT0
VBB
V
BB
V
DS(SB)
I
IS 0
SPI Power Controller
SPOC - BTS5566G
Diagnosis
Data Sheet 26 Rev. 1.3, 2007-10-30
8.1 Diagnosis Word at SPI
The standard diagnosis at the SPI interface provides information about each channel. The error flags, an OR
combination of the over temperature flags and the over load monitoring signals are provided in the SPI standard
diagnosis bits ERRn.
The over load monitoring signals are latched in the error flags and cleared each time the standard diagnosis is
transmitted via SPI. In detail, they are cleared between the second and third raising edge of the SCLK signal.
The over temperature flags, which cause an overheated channel to stay switched off, are latched directly at the
gate control block. The latches are cleared by SPI command HWCR.CTL.
Please note:
The over temperature information is latched twice. When transmitting a clear thermal latch command (HWCR.CLT),
the error flag is cleared during command transmission of the next SPI frame and ready for latching after the third
raising edge of the SCLK signal. As a result, the first standard diagnosis information after a CTL command will
indicate a failure mode at the previously affected channels although the thermal latches have been cleared
already. In case of continuous over load, the error flags are set again immediately because of the over load
monitoring signal.
In case of high duty cyle (off state of output < toff-state_min) the VDS might not be equal to VDD during the off state of
the power Mosfet. The over load monitoring signals might be set and latched in the error flags. See Application
Note “Software Strategy for Diagnosis during PWM-Operation“ for more details.
8.2 Load Current Sense Diagnosis
There is a current sense signal available at pin IS which provides a current proportional to the load current of one
selected channel. The selection is done by a multiplexer which is configured via SPI.
The current sense signal (ratio kILIS = IL / IS) is provided as long as no failure mode occurs. Usually a resistor RIS is
connected from the current sense pin to GND. It is recommended to use resistors 2.5 kΩ<
RIS <7kΩ. A typical
value is 3.3 kΩ.
Figure 14 Current Sense Ratio kILIS Channel 0,1 1)
1) The curves show the behavior based on characterization data. The marked points are guaranteed in this Data Sheet in
Section 8.4 (Position 8.4.1).
1000
2000
3000
4000
5000
6000
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6
kILIS
I
L0,1
/A
dummy
Tj = 150°C
dummy
Tj = -40°C
Data Sheet 27 Rev. 1.3, 2007-10-30
SPI Power Controller
SPOC - BTS5566G
Diagnosis
Figure 15 Current Sense Ratio kILIS Channel 2 1)
Figure 16
Current Sense Ratio kILIS Channel 3, 4 1)
In case of over current as well as over temperature, the current sense signal of the affected channel is switched
off. To distinguish between over temperature and over load, the SPI diagnosis word can be used. Whereas the
over load flag is cleared every time the diagnosis is transmitted, the over temperature flag is cleared by a dedicated
SPI command (HWCR.CTL).
Details about timings between the current sense signal IIS and the output voltage VOUT and the load current IL can
be found in Figure 17.
1) The curves show the behavior based on characterization data. The marked points are guaranteed in this Data Sheet in
Section 8.4 (Position 8.4.1).
1000
2000
3000
4000
5000
6000
0 0.5 1 1.5 2 2.5 3 3.5 4
kILIS
I
L2
/A
dummy
bulb: Tj = 150°C
dummy
bulb: Tj = -40°C
500
1000
1500
2000
2500
3000
0 0.5 1 1.5 2
kILIS
I
L3,4
/A
dummy
Tj = 150°C
dummy
Tj = -40°C
SPI Power Controller
SPOC - BTS5566G
Diagnosis
Data Sheet 28 Rev. 1.3, 2007-10-30
Figure 17 Timing of Current Sense Signal
Current Sense Multiplexer
There is a current sense multiplexer implemented in the SPOC - BTS5566G that routes the sense current of the
selected channel to the diagnosis pin IS. The channel is selected via SPI register DCR.MUX. The sense current
also can be disabled by SPI register DCR.MUX. For details on timing of the current sense multiplexer, please refer
to Figure 18.
Figure 18 Timing of Current Sense Multiplexer
8.3 Switch Bypass Diagnosis
To detect short circuit to VDD, there is a switch bypass monitor implemented. In case of short circuit between the
output pin OUT and VBB in ON-state, the current will flow through the power transistor as well as through the short
circuit (bypass) with undefined ratio. As a result, the current sense signal will show lower values than expected by
the load current. In OFF-state, the output voltage will stay close to VBB potential which means a small VDS.
The switch bypass monitor compares the voltage VDS across the power transistor of that channel which is selected
by the current sense multiplexer (DCR.MUX) with threshold VDS(SB). The result of comparison can be read in SPI
register HWCR.SBM. The switch bypass monitor is active in ON- as well as in OFF-state.
SenseTiming.emf
IN
V
OUT
I
IS
t
t
t
I
L
t
ON
t
ON
t
sIS(ON)
t
sIS(LC)
OFF
t
OFF
t
dIS(OFF)
OFF
M u xTim in g.e m f
CS
I
IS
t
t
000
DCR.MUX 001111 111
t
sIS(EN)
t
sIS(MUX)
t
dIS(MUX)
Data Sheet 29 Rev. 1.3, 2007-10-30
SPI Power Controller
SPOC - BTS5566G
Diagnosis
8.4 Electrical Characteristics
Electrical Characteristics Diagnosis
Unless otherwise specified: VBB = 9 V to 16 V, Tj = -40 °C to +150 °C
typical values: VBB = 13.5 V, Tj = 25 °C
Pos. Parameter Symbol Limit Values Unit Test Conditions
min. typ. max.
Load Current Sense
8.4.1 Current sense ratio kILIS
channel 0, 1:
IL = 1.3 A
IL = 2.6 A
IL = 6.0 A
2400
2400
2500
3100
3000
3000
3800
3500
3500
Tj = -40 °C
–
–
IL = 1.3 A
IL = 2.6 A
IL = 6.0 A
2450
2450
2700
3030
3000
3000
3600
3350
3300
Tj = 150 °C
–
–
channel 2:
IL = 1.3 A
IL = 2.6 A
IL = 3.5 A
2400
2400
2500
3100
3000
3000
3800
3500
3500
Tj = -40 °C
–
–
IL = 1.3 A
IL = 2.6 A
IL = 3.5 A
2450
2450
2700
3000
3000
3000
3600
3350
3300
Tj = 150 °C
–
–
channel 3, 4:
IL = 0.3 A
IL = 0.6 A
IL = 1.3 A
IL = 2.0 A
1220
1250
1280
1310
1625
1565
1520
1520
2030
1880
1760
1730
Tj = -40 °C
–
–
–
IL = 0.3 A
IL = 0.6 A
IL = 1.3 A
IL = 2.0 A
1270
1340
1360
1360
1520
1520
1520
1520
1770
1700
1680
1680
Tj = 150 °C
–
–
–
8.4.2 Current sense voltage limitation VIS(LIM) -8% Vdd 8% V IIS = 1 mA
8.4.3 Current sense leakage / offset current IIS(en) ––2µAIL = 0
DCR.MUX = 000B
8.4.4 Current sense leakage, while diagnosis
disabled
IIS(dis) ––1µAIL = IL(nom)
DCR.MUX = 111B
8.4.5 Current sense settling time after
channel activation
tsIS(ON) ––300µsVBB = 13.5 V
IL = IL(nom)
RIS = 4.7 kΩ
8.4.6 Current sense desettling time after
channel deactivation
tdIS(OFF) ––25µsVBB = 13.5 V 1)
IL = IL(nom)
RIS = 4.7 kΩ
SPI Power Controller
SPOC - BTS5566G
Diagnosis
Data Sheet 30 Rev. 1.3, 2007-10-30
8.4.7 Current sense settling time after change
of load current
channel 0, 1, 2
channel 3, 4
tsIS(LC)
–
–
–
–
30
30
µsVBB = 13.5 V
1)
RIS = 4.7 kΩ
IL = 1.3 A to 2.6 A
IL = 0.6 A to 1.3 A
8.4.8 Current sense settling time after current
sense activation
tsIS(EN) ––25µsRIS = 4.7 kΩ
DCR.MUX:111B -> 000B
8.4.9 Current sense settling time after
multiplexer channel change
tsIS(MUX) ––30µsRIS = 4.7 kΩ
DCR.MUX:000B -> 001B
8.4.10 Current sense deactivation time tdIS(MUX) ––25µs
1)
RIS = 4.7 kΩ
DCR.MUX: 001B -> 111B
8.4.11 Off state time during PWM operation toff
state_min
350 – – µs –
Switch Bypass Monitor
8.4.12 Switch bypass monitor threshold VDS(SB) 0.7 – 2.5 V –
1) Not subject to production test, specified by design.
Electrical Characteristics Diagnosis
Unless otherwise specified: VBB = 9 V to 16 V, Tj = -40 °C to +150 °C
typical values: VBB = 13.5 V, Tj = 25 °C
Pos. Parameter Symbol Limit Values Unit Test Conditions
min. typ. max.
Data Sheet 31 Rev. 1.3, 2007-10-30
SPI Power Controller
SPOC - BTS5566G
Diagnosis
8.5 Command Description
DCR
Diagnosis Control Registers
43210
00MUX
Field Bits Type Description
MUX 2:0 rw Set Current Sense Multiplexer Configuration
000 current sense of channel 0 is routed to IS pin
001 current sense of channel 1 is routed to IS pin
010 current sense of channel 2 is routed to IS pin
011 current sense of channel 3 is routed to IS pin
100 current sense of channel 4 is routed to IS pin
101 IS pin is high impedance
110 IS pin is high impedance
111 IS pin is high impedance
HWCR
Hardware Configuration Register
W/R 43210
read RST 0SBM PWM CTL
write RST 00PWM CTL
Field Bits Type Description
SBM 2 r Switch Bypass Monitor1)
0VDS < VDS(SB)
1VDS > VDS(SB)
1) Invalid in stand-by mode
Standard Diagnosis
CS76543210
TER 0LHI 0 ERR4 ERR3 ERR2 ERR1 ERR0
Field Bits Type Description
ERRn
n = 4 to 0
nrError flag Channel n
0 normal operation
1 failure mode occurred
SPI Power Controller
SPOC - BTS5566G
Serial Peripheral Interface (SPI)
Data Sheet 32 Rev. 1.3, 2007-10-30
9 Serial Peripheral Interface (SPI)
The serial peripheral interface (SPI) is a full duplex synchronous serial slave interface, which uses four lines: SO,
SI, SCLK and CS. Data is transferred by the lines SI and SO at the rate given by SCLK. The falling edge of CS
indicates the beginning of an access. Data is sampled in on line SI at the falling edge of SCLK and shifted out on
line SO at the rising edge of SCLK. Each access must be terminated by a rising edge of CS. A modulo 8 counter
ensures that data is taken only, when a multiple of 8 bit has been transferred. The interface provides daisy chain
capability.
Figure 19 Serial Peripheral Interface
9.1 SPI Signal Description
CS - Chip Select:
The system micro controller selects the SPOC - BTS5566G by means of the CS pin. Whenever the pin is in low
state, data transfer can take place. When CS is in high state, any signals at the SCLK and SI pins are ignored and
SO is forced into a high impedance state.
CS High to Low transition:
• The requested information is transferred into the shift register.
• SO changes from high impedance state to high or low state depending on the logic OR combination between
the transmission error flag (TER) and the signal level at pin SI. As a result, even in daisy chain configuration,
a high signal indicates a faulty transmission. This information stays available to the first rising edge of SCLK.
CS Low to High transition:
• Command decoding is only done, when after the falling edge of CS exactly a multiple (1, 2, 3, …) of eight SCLK
signals have been detected. In case of faulty transmission, the transmission error flag (TER) is set and the
command is ignored.
• Data from shift register is transferred into the addressed register.
SCLK - Serial Clock:
This input pin clocks the internal shift register. The serial input (SI) transfers data into the shift register on the falling
edge of SCLK while the serial output (SO) shifts diagnostic information out on the rising edge of the serial clock.
It is essential that the SCLK pin is in low state whenever chip select CS makes any transition.
SI - Serial Input:
Serial input data bits are shifted-in at this pin, the most significant bit first. SI information is read on the falling edge
of SCLK. The input data consists of two parts, control bits followed by data bits. Please refer to Section 9.5 for
further information.
SO Serial Output:
Data is shifted out serially at this pin, the most significant bit first. SO is in high impedance state until the CS pin
goes to low state. New data will appear at the SO pin following the rising edge of SCLK. Please refer to Section 9.5
for further information.
LSB6 5 4 3 2 1
LSB6 5 4 3 2 1CS MSB
MSB
SO
SI
CS
SCLK
time
SPI.emf
Data Sheet 33 Rev. 1.3, 2007-10-30
SPI Power Controller
SPOC - BTS5566G
Serial Peripheral Interface (SPI)
9.2 Daisy Chain Capability
The SPI of SPOC - BTS5566G provides daisy chain capability. In this configuration several devices are activated
by the same CS signal MCS. The SI line of one device is connected with the SO line of another device (see
Figure 20), in order to build a chain. The ends of the chain are connected with the output and input of the master
device, MO and MI respectively. The master device provides the master clock MCLK which is connected to the
SCLK line of each device in the chain.
Figure 20 Daisy Chain Configuration
In the SPI block of each device, there is one shift register where one bit from SI line is shifted in each SCLK. The
bit shifted out occures at the SO pin. After eight SCLK cycles, the data transfer for one device has been finished.
In single chip configuration, the CS line must turn high to make the device accept the transferred data. In daisy
chain configuration, the data shifted out at device 1 has been shifted in to device 2. When using three devices in
daisy chain, three times eight bits have to be shifted through the devices. After that, the MCS line must turn high
(see Figure 21).
Figure 21 Data Transfer in Daisy Chain Configuration
9.3 Timing Diagrams
Figure 22 Timing Diagram SPI Access
SI
device 1
SPI
SCLK
SO
CS
SI
device 2
SPI
SCLK
SO
CS
SI
device 3
SPI
SCLK
SO
CS
MO
MI
MCS
MCLK
SPI _Dasy Chain. emf
MI
MO
MCS
MCLK
SI device 3 SI device 2 SI device 1
SO device 3 SO device 2 SO device 1
time
SPI _Dasy Chain2. emf
CS
SCLK
SI
t
CS(lead)
t
CS( td )
t
CS( l a g )
t
SCLK( H)
t
SCL K( L )
t
SCL K(P)
t
SI( su)
t
SI( h )
SO
t
SO( v)
t
SO(en)
t
SO ( dis)
0.7V
dd
0.2V
dd
0.7V
dd
0.2V
dd
0.7V
dd
0.2V
dd
0.7V
dd
0.2V
dd
SPI Timing. emf
SPI Power Controller
SPOC - BTS5566G
Serial Peripheral Interface (SPI)
Data Sheet 34 Rev. 1.3, 2007-10-30
9.4 Electrical Characteristics
Electrical Characteristics SPI
Unless otherwise specified: Vbb = 9 V to 16 V, Tj = -40 °C to +150 °C, Vdd = 3.8 V to 5.5 V
typical values: Vbb = 13.5 V, Tj = 25 °C, Vdd = 4.3 V
Pos. Parameter Symbol Limit Values Unit Test Conditions
min. typ. max.
Input Characteristics (CS, SCLK, SI)
9.4.1 L level of pin
CS
SCLK
SI
VCS(L)
VSCLK(L)
VSI(L)
-0.3
-0.3
-0.3
–
–
–
1.0
1.0
1.0
VVDD = 4.3 V
–
–
–
9.4.2 H level of pin
CS
SCLK
SI
VCS(H)
VSCLK(H)
VSI(H)
2.6
2.6
2.6
–
–
–
5.5
5.5
5.5
VVDD = 4.3 V
–
–
–
9.4.3 L-input pull-up current at CS pin ICS(L) 10 30 85 µAVDD = 4.3 V,VCS = 0 V
9.4.4 H-input pull-up current at CS pin ICS(H) 3–85µAVDD = 4.3 V,VCS = 2.6 V
9.4.5 L-input pull-down current at pin
SCLK
SI
ISCLK(L)
ISI(L)
3
3
–
–
75
75
µAVDD = 4.3 V
VSCLK = 0.4 V
VSI = 0.4 V
9.4.6 H-input pull-down current at pin
SCLK
SI
ISCLK(H)
ISI(H)
10
10
30
30
75
75
µAVDD = 4.3 V
VSCLK = 4.3 V
VSI = 4.3 V
Output Characteristics (SO)
9.4.7 L level output voltage VSO(L) 0–0.5VISO = -0.5 mA
9.4.8 H level output voltage VSO(H) VDD -
0.5 V
–VDD V ISO = 0.5 mA,VDD = 4.3 V
9.4.9 Output tristate leakage current ISO(OFF) -10 – 10 µAVCS =VDD
Timings
9.4.10 Serial clock freqency fSCLK 0–2MHz–
9.4.11 Serial clock period tSCLK(P) 500 – – ns –
9.4.12 Serial clock high time tSCLK(H) 250 – – ns –
9.4.13 Serial clock low time tSCLK(L) 250 – – ns –
9.4.14 Enable lead time (falling CS to rising
SCLK)
tCS(lead) 1––µs–
9.4.15 Enable lag time (falling SCLK to
rising CS)
tCS(lag) 1––µs–
9.4.16 Transfer delay time (rising CS to
falling CS)
tCS(td) 1––µs–
9.4.17 Data setup time (required time SI to
falling SCLK)
tSI(su) 100 – – ns –
9.4.18 Data hold time (falling SCLK to SI) tSI(h) 100 – – ns –
9.4.19 Output enable time (falling CS to SO
valid)
tSO(en) ––1µsCL = 20 pF 1)
Data Sheet 35 Rev. 1.3, 2007-10-30
SPI Power Controller
SPOC - BTS5566G
Serial Peripheral Interface (SPI)
9.4.20 Output disable time (rising CS to SO
tri-state)
tSO(dis) ––1µsCL = 20 pF 1)
9.4.21 Output data valid time with
capacitive load
tSO(v) ––250nsCL = 20 pF 1)
1) Not subject to production test, specified by design.
Electrical Characteristics SPI
Unless otherwise specified: Vbb = 9 V to 16 V, Tj = -40 °C to +150 °C, Vdd = 3.8 V to 5.5 V
typical values: Vbb = 13.5 V, Tj = 25 °C, Vdd = 4.3 V
Pos. Parameter Symbol Limit Values Unit Test Conditions
min. typ. max.
SPI Power Controller
SPOC - BTS5566G
Serial Peripheral Interface (SPI)
Data Sheet 36 Rev. 1.3, 2007-10-30
9.5 SPI Protocol
Note: Reading a register needs two SPI frames. In the first frame the RD command is sent. In the second frame
the output at SPI signal SO will contain the requested information. A new command can be executed in the
second frame.
CS1)
1) The SO pin shows this information between CS hi -> lo and first SCLK lo -> hi transition.
76543210
Write Register
SI 1 ADDR DATA
Read Register
SI 0 ADDR xxxx0
Read Standard Diagnosis
SI 0xxxxxx1
Standard Diagnosis
SO TER 0 LHI X ERR4 ERR3 ERR2 ERR1 ERR0
Second Frame of Read Command
SO TER 1 ADDR DATA
Field Bits Type Description
TER CS r Transmission Error
0 Previous transmission was successful (modulo 8 clocks received)
1Previous transmission failed or first transmission after reset
ADDR 6:5 rw Address
Pointer to register for read and write command
DATA 4:0 rw Data
Data written to or read from register selected by address ADDR
LHI 6 r Limp Home Input Pin
0 L-input signal at pin LHI
1 H-input signal at pin LHI
ERRx
x = 4 to 0
xrDiagnosis of Channel x
0No failure
1 Over temperature, over load or short circuit
Data Sheet 37 Rev. 1.3, 2007-10-30
SPI Power Controller
SPOC - BTS5566G
Serial Peripheral Interface (SPI)
9.6 Register Overview
Name W/R Addr43210default
1)
1) The default values are set after reset.
OUT W/R 00BOUT4 OUT3 OUT2 OUT1 OUT0 00H
HWCR R 10BRST X SBM PWM CTL 00H
W10
BRST 0 0 PWM CTL 00H
DCR W/R 11B00 MUX 07
H
SPI Power Controller
SPOC - BTS5566G
Application Description
Data Sheet 38 Rev. 1.3, 2007-10-30
10 Application Description
Figure 23 Application Circuit Example
µC
VSS
SPI
VBB
Limp
Home
LHI
GND
OUT3
OUT2
OUT1
OUT0
OUT4
GND
VBB
LH I
VCC
V
bat
AD
2k Ω
2kΩ
2kΩ
2k Ω
5V
VDD
VDD
100nF
500 Ω
LH I
8k Ω
8k Ω
3. 3k Ω
1k Ω
1nF
GPIO
GPIO
SO
SCLK
SI
CS
IS
IN1
IN2
IN3
IN4
IN0
Circuit .emf
SPI
8k Ω
10nF. . 100nF
68nF
Schottky
27W
27W
27W
10W
10W
Data Sheet 39 Rev. 1.3, 2007-10-30
SPI Power Controller
SPOC - BTS5566G
Package Outlines SPOC - BTS5566G
11 Package Outlines SPOC - BTS5566G
Figure 24 PG-DSO-36-34 (Plastic Dual Small Outline Package)
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant with
government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e
Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
GPS01089
2) Does not include dambar protrusion of 0.05 max. per side
1) Does not include plastic or metal protrusion of 0.15 max. per side
1 18
36 19
0.65
0.33
0.2
2.45
2.65 MAX.
0.1
-0.2
-0.1
0.23
+0.09
0.35 x 45˚
-0.21)
7.6
10.3
0.7
±0.2
8˚ MAX.
±0.3
Index Marking
1)
12.8
-0.2
18 1
19 36
Index Marking
Ejector Mark
Bottom View
0.17
M
C A-B D 36x
±0.08
2)
C
D
A
B
You can find all of our packages, sorts of packing and others in our Infineon Internet Page
“Products”: http://www.infineon.com/products.Dimensions in mm
SPI Power Controller
SPOC - BTS5566G
Revision History
Data Sheet 40 Rev. 1.3, 2007-10-30
12 Revision History
Revision Date Changes
1.3 07-10-30 • Chapter 11 Package outline drawing changed
1.2 07-08-28 • 4.1 Conditions updated
• 4.1 and 6.4 : footnote change to : Specified RthJA value is according to Jedec JESD51-
2,-5,-7 at natural convection on FR4 2s2p board; The Product (Chip+Package) was
simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70µm Cu, 2
x 35µm Cu).
• 4.1.4 Conditions updated
• 4.1.28 Definition change
• 5.2 Reset Command : tCS(td) change to : tCS(td).
• 8.4.1 Kilis : updated values for Channel 2-3
• 8.4.3 New parameter : Current sense leakage / offset current
• Max Input Voltage value change to 40 Volts
1.1 07-03-05 • Product summary Green Product (ROHS compliant) and AEC Qualified added
• 4.1.12 Current through input pins min value change to -0.75mA
• 4.1.21 Current through limp home input pin min value change to -0.75mA
• Chapter 2 Test pin change to Vbb
• Chapter 6 Ron definition changed
• Chapter 7.2 (also even in case of Vdd = 0V) added.
• Basic Feature : Green Logo added
• Chapter 8.1 In case of high duty cyle ( off state of output < toff state_min) the VDS
might not be equal to VBB during the off state of the power Mosfet. The over load
monitoring signals might be set and latched in the error flags. See Application
Note “ Software Strategy for Diagnosis during PWM-Operation“ for more details
• Table 8.4.10 Off stateTime during PWM operation definition
• Chapter 11 68nF added between VBB and Gnd
• page 18: register read value added
• New template DIN A4 V1.2
Edition 2007-10-30
Published by
Infineon Technologies AG
81726 Munich, Germany
© Infineon Technologies AG 2007.
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics (“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values
stated herein and/or any information regarding the application of the device, Infineon Technologies hereby
disclaims any and all warranties and liabilities of any kind, including without limitation warranties of
non-infringement of intellectual property rights of any third party.
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For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
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Due to technical requirements components may contain dangerous substances. For information on the types in
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