2B
3
2
5
81
1OE VCC
1A
GND
DCU PACKAGE
(TOP VIEW)
1B 2OE
2A
46
7
PW PACKAGE
(TOP VIEW)
1
2
3
4
8
7
6
5
1OE
1A
1B
GND
VCC
2OE
2B
2A
SN74CB3Q3306A
www.ti.com
SCDS113E –DECEMBER 2002–REVISED JANUARY 2011
Dual FET Bus Switch 2.5-V/3.3-V Low-Voltage High-Bandwidth Bus Switch
Check for Samples: SN74CB3Q3306A
1FEATURES • Data and Control Inputs Provide Undershoot
Clamp Diodes
• High-Bandwidth Data Path (up to 500 MHz(1))• Low Power Consumption (ICC = 0.25 mA Typ)
• 5-V-Tolerant I/Os With Device Powered Up or
Powered Down • VCC Operating Range From 2.3 V to 3.6 V
• Low and Flat ON-State Resistance (ron) • Data I/Os Support 0- to 5-V Signaling Levels
Characteristics Over Operating Range (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, 5 V)
(ron = 4 ΩTyp) • Control Inputs Can Be Driven by TTL or
• Rail-to-Rail Switching on Data I/O Ports 5-V/3.3-V CMOS Outputs
– 0- to 5-V Switching With 3.3-V VCC • Ioff Supports Partial-Power-Down Mode
Operation
– 0- to 3.3-V Switching With 2.5-V VCC • Latch-Up Performance Exceeds 100 mA
• Bidirectional Data Flow With Near-Zero Per JESD 78, Class II
Propagation Delay • ESD Performance Tested Per JESD 22
• Low Input/Output Capacitance Minimizes
Loading and Signal Distortion – 2000-V Human-Body Model
(Cio(OFF) = 3.5 pF Typ) (A114-B, Class II)
• Fast Switching Frequency (f OE = 20 MHz Max) – 1000-V Charged-Device Model (C101)
• Supports Both Digital and Analog
(1) For additional information regarding the performance
characteristics of the CB3Q family, refer to the TI application Applications: USB Interface, Differential Signal
report, CBT-C, CB3T, and CB3Q Signal-Switch Families,Interface, Bus Isolation, Low-Distortion Signal
literature number SCDA008.Gating
ORDERING INFORMATION
TAPACKAGE(1) ORDERABLE PART NUMBER TOP-SIDE MARKING
Tube SN74CB3Q3306APW
TSSOP – PW BU306A
Tape and reel SN74CB3Q3306APWR
–40°C to 85°C SN74CB3Q3306ADCUR
US8-DCU Tape and reel GA6R(2)
74CB3Q3306ADCURE4
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(2) The last character designates assembly/test site.
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 2002–2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
1A
1OE
SW 1B
2A
2OE
SW 2B
2
1
5
7
3
6
SN74CB3Q3306A
SCDS113E –DECEMBER 2002–REVISED JANUARY 2011
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION/ORDERING INFORMATION
The SN74CB3Q3306A is a high-bandwidth FET bus switch utilizing a charge pump to elevate the gate voltage of
the pass transistor, providing a low and flat ON-state resistance (ron). The low and flat ON-state resistance allows
for minimal propagation delay and supports rail-to-rail switching on the data input/output (I/O) ports. The device
also features low data I/O capacitance to minimize capacitive loading and signal distortion on the data bus.
Specifically designed to support high-bandwidth applications, the SN74CB3Q3306A provides an optimized
interface solution ideally suited for broadband communications, networking, and data-intensive computing
systems.
The SN74CB3Q3306A is organized as two 1-bit switches with separate output-enable (1OE, 2OE) inputs. It can
be used as two 1-bit bus switches or as one 2-bit bus switch. When OE is low, the associated 1-bit bus switch is
ON and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE is high,
the associated 1-bit bus switch is OFF, and a high-impedance state exists between the A and B ports.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry prevents damaging
current backflow through the device when it is powered down. The device has isolation during power off.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Table 1. FUNCTION TABLE
(EACH BUS SWITCH)
INPUT INPUT/OUTPUT FUNCTION
OE A
L B A port = B port
H Z Disconnect
LOGIC DIAGRAM (POSITIVE LOGIC)
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A
EN(1)
B
(1) EN is the internal enable signal applied to the switch.
Charge
Pump
VCC
SN74CB3Q3306A
www.ti.com
SCDS113E –DECEMBER 2002–REVISED JANUARY 2011
SIMPLIFIED SCHEMATIC, EACH FET SWITCH (SW)
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT
VCC Supply voltage range –0.5 4.6 V
VIN Control input voltage range(2) (3) –0.5 7 V
VI/O Switch I/O voltage range(2) (3) (4) –0.5 7 V
IIK Control input clamp current VIN < 0 –50 mA
II/OK I/O port clamp current VI/O < 0 –50 mA
II/O ON-state switch current(5) ±64 mA
Continuous current through each VCC or ±100 mA
GND DCU TBD
qJA Package thermal impedance(6) °C/W
PW 88
Tstg Storage temperature range –65 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to ground, unless otherwise specified.
(3) The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(4) VIand VOare used to denote specific conditions for VI/O.
(5) IIand IOare used to denote specific conditions for II/O.
(6) The package thermal impedance is calculated in accordance with JESD 51-7.
RECOMMENDED OPERATING CONDITIONS(1)
MIN MAX UNIT
VCC Supply voltage 2.3 3.6 V
VCC = 2.3 V to 2.7 V 1.7 5.5
High-level control input
VIH V
voltage VCC = 2.7 V to 3.6 V 2 5.5
VCC = 2.3 V to 2.7 V 0 0.7
Low-level control input
VIL V
voltage VCC = 2.7 V to 3.6 V 0 0.8
VI/O Data input/output voltage 0 5.5 V
TAOperating free-air temperature –40 85 °C
(1) All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s) :SN74CB3Q3306A
SN74CB3Q3306A
SCDS113E –DECEMBER 2002–REVISED JANUARY 2011
www.ti.com
ELECTRICAL CHARACTERISTICS(1)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(2) MAX UNIT
VIK VCC = 3.6 V, II= –18 mA –1.8 V
IIN Control inputs VCC = 3.6 V, VIN = 0 to 5.5 V ±1 mA
VO= 0 to 5.5 V, Switch OFF,
IOZ (3) VCC = 3.6 V, ±1 mA
VI= 0, VIN = VCC or GND
Ioff VCC = 0, VO= 0 to 5.5 V, VI= 0 1 mA
II/O = 0,
ICC VCC = 3.6 V, VIN = VCC or GND 0.25 0.7 mA
Switch ON or OFF,
ΔICC (4) Control inputs VCC = 3.6 V, One input at 3 V, Other inputs at VCC or GND 25 mA
VCC = 3.6 V, A and B ports open,
Per control mA/
ICCD (5) 0.03 0.1
input MHz
Control input switching at 50% duty cycle
Cin Control inputs VCC = 3.3 V, VIN = 5.5 V, 3.3 V, or 0 2.5 3.5 pF
Switch OFF,
Cio(OFF) VCC = 3.3 V, VI/O = 5.5 V, 3.3 V, or 0 3.5 5 pF
VIN = VCC or GND,
Switch ON,
Cio(ON) VCC = 3.3 V, VI/O = 5.5 V, 3.3 V, or 0 8 10.5 pF
VIN = VCC or GND,
VI= 0, IO= 30 mA 4 8
VCC = 2.3 V,
TYP at VCC = 2.5 V VI= 1.7 V, IO= –15 mA 5 9
ron (6) Ω
VI= 0, IO= 30 mA 4 6
VCC = 3 V VI= 2.4 V, IO= –15 mA 5 8
(1) VIN and IIN refer to control inputs. VI, VO, II, and IOrefer to data pins.
(2) All typical values are at VCC = 3.3 V (unless otherwise noted), TA= 25°C.
(3) For I/O ports, the parameter IOZ includes the input leakage current.
(4) This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
(5) This parameter specifies the dynamic power-supply current associated with the operating frequency of a single control input (see
Figure 2).
(6) Measured by the voltage drop between the A and B terminals at the indicated current through the switch. ON-state resistance is
determined by the lower of the voltages of the two (A or B) terminals.
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
VCC = 2.5 V VCC = 3.3 V
FROM TO ± 0.2 V ± 0.3 V
PARAMETER UNIT
(INPUT) (OUTPUT) MIN MAX MIN MAX
fOE (1) OE A or B 10 20 MHz
tpd (2) A or B B or A 0.2 0.2 ns
ten OE A or B 1.5 6.5 1.5 5.5 ns
tdis OE A or B 1 6 1 5 ns
(1) Maximum switching frequency for control input (VO> VCC, VI= 5 V, RL≥1 MΩ, CL= 0)
(2) The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load
capacitance, when driven by an ideal voltage source (zero output impedance).
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Product Folder Link(s) :SN74CB3Q3306A
0
2
4
6
8
10
12
14
16
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
ron− ON-State Resistance −
VI − V
TYPICAL ron vs VI
Ω
VCC = 3.3 V
TA = 25°C
IO = −15 mA
0
2
4
6
8
10
12
0 2 4 6 8 10 12 14 16 18 20
OE Switching Frequency − MHz
TYPICAL ICC
vs
OE SWITCHING FREQUENCY
CC
I− mA
VCC = 3.3 V
TA = 25°C
A and B Ports Open
One OE Switching
SN74CB3Q3306A
www.ti.com
SCDS113E –DECEMBER 2002–REVISED JANUARY 2011
Figure 1. Typical ron vs VI
Figure 2. Typical ICC vs OE Switching Frequency
Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s) :SN74CB3Q3306A
VOH
VOL
CL
(see Note A)
TEST CIRCUIT
S1 2 × VCC
Open
GND
RL
RL
tPLH tPHL
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
VCC
0 V
VOH
VOL
0 V
VOL + V∆
VOH − V∆
0 V
Output
Control
(VIN)
VCC
VCC
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (tpd(s))VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd(s). The tpd propagation delay is the calculated RC time constant of the typical ON-state resistance
of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).
H. All parameters and waveforms are not applicable to all devices.
50 Ω
VG1
VCC
DUT
50 Ω
VIN
50 Ω
VG2 50 Ω
VI
TEST RL
S1 V∆
CL
2.5 V ± 0.2 V
3.3 V ± 0.3 V
VCC VI
tPHZ/tPZH
tPLZ/tPZL
tpd(s)
2.5 V ± 0.2 V
3.3 V ± 0.3 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
Open
Open
2 × VCC
2 × VCC
GND
GND
500 Ω
500 Ω
500 Ω
500 Ω
500 Ω
500 Ω
VCC or GND
VCC or GND
GND
GND
VCC
VCC
30 pF
50 pF
30 pF
50 pF
30 pF
50 pF
0.15 V
0.3 V
0.15 V
0.3 V
Output
Control
(VIN)
Input Generator
Input Generator
VCC/2 VCC/2
VCC/2 VCC/2
VCC/2 VCC/2 VCC/2
VCC/2
VO
SN74CB3Q3306A
SCDS113E –DECEMBER 2002–REVISED JANUARY 2011
www.ti.com
PARAMETER MEASUREMENT INFORMATION
Figure 3. Test Circuit and Voltage Waveforms
6Submit Documentation Feedback Copyright © 2002–2011, Texas Instruments Incorporated
Product Folder Link(s) :SN74CB3Q3306A
SN74CB3Q3306A
www.ti.com
SCDS113E –DECEMBER 2002–REVISED JANUARY 2011
REVISION HISTORY
Changes from Revision D (April 2005) to Revision E Page
• Added DCU package ordering information. .......................................................................................................................... 1
Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s) :SN74CB3Q3306A
PACKAGE OPTION ADDENDUM
www.ti.com 5-Mar-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
74CB3Q3306ADCURE4 ACTIVE US8 DCU 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
74CB3Q3306ADCURG4 ACTIVE US8 DCU 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
74CB3Q3306APWRE4 ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74CB3Q3306ADCUR ACTIVE US8 DCU 8 3000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM
SN74CB3Q3306APW ACTIVE TSSOP PW 8 150 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74CB3Q3306APWE4 ACTIVE TSSOP PW 8 150 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74CB3Q3306APWG4 ACTIVE TSSOP PW 8 150 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74CB3Q3306APWR ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74CB3Q3306APWRE4 ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74CB3Q3306APWRG3 PREVIEW TSSOP PW 8 2000 TBD Call TI Call TI
SN74CB3Q3306APWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
PACKAGE OPTION ADDENDUM
www.ti.com 5-Mar-2012
Addendum-Page 2
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74CB3Q3306ADCUR US8 DCU 8 3000 180.0 8.4 2.25 3.35 1.05 4.0 8.0 Q3
SN74CB3Q3306APWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1
SN74CB3Q3306APWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1
SN74CB3Q3306APWRG4 TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 15-Aug-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74CB3Q3306ADCUR US8 DCU 8 3000 202.0 201.0 28.0
SN74CB3Q3306APWR TSSOP PW 8 2000 367.0 367.0 35.0
SN74CB3Q3306APWR TSSOP PW 8 2000 364.0 364.0 27.0
SN74CB3Q3306APWRG4 TSSOP PW 8 2000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 15-Aug-2012
Pack Materials-Page 2
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