CMOS input and outputs Delays stable and precise 14pin DIP package (.150 high) Available in delays from 20 to 250ns 5 tapseach isolated and with 10 LPST@L fan-out capacity Fast rise time on all outputs design notes The "DIP Series Logic Delay Modules developed by Engineered Components Company have been designed to pro- vide precise tapped delays with required driving and pick-off cir- cuitry contained in a single 14-pin DIP package compatible with CMOS and LPST2L circuits. These logic delay modules are of hybrid construction utilizing the proven technologies of active integrated circuitry and of passive networks utilizing capacitive, inductive and resistive elements. The ICs utilized in these modules are burned-in to level B of MIL-STD-883 to ensure a high MTBF. The MTBF on these modules, when calculated per MIL- HDBK-217 for a 50C ground fixed environment, is in excess of 3 million hours. Module design includes compensation for propagation delays and incorporates internal termination at the output; no additional external components are needed to obtain the desired delay. &L very low profile CMOS COMPATIBLE Thinny DIP LOGIC DELAY MODULE The CMOSLDM is offered in twenty-eight (28) delays from 20ns to 250ns, with each module incorporating taps as shown in the part number table. Delay tolerances are maintained as shown in the accompanying part number table, when tested under the Test Conditions shown. Delay time is measured at the + 1.5 level on the leading edge. Rise time for all modules is Gns max- imum when measured from 0.75 to 2.4. Temperature coeffi- cient of delay is approximately +270 ppm/*C or 3ns, whichever is greater, over the operating temperature range of 40 ta +B5C, These modules accept either logic 1" or logic 'O"' inputs and reproduce the logic at the selected output tap without inversion. The delay modules are intended primarily for use with positive going pulses and are calibrated to the tolerances shown in the table on rising edge delay; where bast accuracy is desired in applications using falling edge timing, it is recommended that a special unit be calibrated for the specific application. Each module output has the capacity of driving up to 2 TAL loads, 10 LPST2L loads or greater than 50 CMOS DC loads. These DIP Series modules are packaged in a 14-pin DIP housing, molded of flame-proof Diallyl Phthalate per MIL-M-14, Type SDG-F, and are fully encapsulated in epoxy resin. Leads meet the solderability requirements of MIL-STD-202, Method 208. Corner standoffs on the housing provide positive standoff from the printed curcuit board to permit solder-fillet formation and flush cleaning of solder-flux residues for improved reliability. engineered components company 3580 Sacramento Drive, P. O. Box 8121, San Luis Obispo, CA 93403-8121 Phone: (805) 544-3800DESIGN NOTES (continued) OPERATING SPECIFICATIONS Marking consists of manufacturer's logo {EC2), part number, Wee supply voltage: . ee ee ee ee 4.5 to 5.5 DC terminal identification and date code of manufacture. All mark- Vee supply current: ing is applied by silk screen process using white epoxy paint ** Constant O" In ss. ee ees 7 te 13me typical in accordance with MIL-STD-130, to meet the permanency of Aner ; ' Constant 1" ime et ee - Tua typical identification required by MIL-STD-202, Method 215. Logic 1 input: BLOCK DIAGRAM IS SHOWN BELOW gs a ea ea i ee Lat yy Cane er eS ome eae eect car we ate 24V = lua max, Vee 20% 60% OUTPUT 14 12 10 68 a ? Logic 0 input: ee a a rire) Pecans se (cere ara Tin Po ata] Woltage se ee et ee te ee .BYV max. x | | | CHP ac ab ckea ieee eee 2s TUB max. | INPUT 5 DELAY LINE WITH | | DRIVER CMOS PICKOFF l Logic 1 Voltage out; . + +--+ eee es 3.84 min, | l Logic O Voltage out:. 6... 2 ee ee oY max, l od | Operating temperature range: ..... . -40 to +85C. | | Storage temperatura: 6 ee ee 55 to4+ 125C. Le ace ai os *Delays decrease or increase approximately 1% or Ins, whichever Fat is greater, for a respective increase or decrease of 5% in supply 1 4 6 az voltage. INPUT 40% 80% GROUND u ** 7ma typical through CMOSLDM-100T and 13ma typical for parts MECHANICAL DETAIL IS SHOWN BELOW CMOSLDM-125T and above. I 200 PART NUMBER TABLE \ 3 OUT @ DELAYS AND TOLERANCES {in ns} 400 @ CMOSLDM- T PART NO. Tap 1 Tap 2 Tap 3 Tap 4 | OUTPUT ee CMOSLDM-20T [ie +1 | 1741 | 18 +1 | 1921 | 2041 IN 2 4. CMOSLOM-22T 1621 |17.6 +1 19+1 (20.5 41 22 +1 , CMOSLOM-24T [16 41 a41 | 20 +1 2241 | 2441 | CMOSLDOM-26T 168+1 [18.6 +1 2121 63.541 26 +1 | 1 020 CMOSLOM-28T |16 +1 1941 22 41 2521] 28 +1 ; CMOSLOM-32T |16 +1 20 41 2441 28 =1 327 +1 150 iy MADE IN cl { CMOSLOM-35T 15 41 20 +1 26 41 30 +15) 35 +1.5 f CMOSLOM-39T 15 41 21 +1 2741.6] 33416] 3921.5 .130 =,020 CMOSLDM43T [1541 | 2241 | 2941.5] 36415) 4941.5 ere CMOSLOM-47T [15 +1 23 +1 3141.5] 39415) 47 41.5 o60 ale 020 DIA. TYP CMOSLOM-51T |15 41 2431 3341.5 | 42415) 51 +2 t = - 100 TYP 5 f CMOSLDM-55T 15 41 25 =1 38 +16] 45 +2 BE z2 TYP. | =, 1BO TYP. CMosLoM-58T |15+1 | 26-1 | 37+15| 48+2 | 59 42.5 CMOSLOM-63T 15 +1 27 +1 3941.6) 61 2 63 +2.5 | o oe CMOSLOM-67T |15 +1 27841.5| 4121.65] 4422 | 67 42.5 | CMOSLDOM-?71T 15 +1 29 +16) 4341.5] 87 2 71 2.65 400 CMOSLOM-75T |15 +1 3041.5] 45 +2 6042.5] 75 +25 | CMOSLOM-80T 16 +1 3241.5) 468 22 6442.5) 80 43 . . CMOSLOM-BBT |17 +1 3441.5 51 +2 68425] 85 +4 = CMOSLOM-90T |18 +1 | 3641.5] 5442 | 72425) 9049 CMOSLDM-S5T 18 1 3821.6) 57 +2 76425) 95 +3 CMOSLDOM-100T | 20 = 4021.5) 6042 BO +3 | 100 +3 CMOSLDM-125T | 25 +1 BO +2 75 +2.5)100 +3 | 128 +4 CMOSLDM-150T | 30 +1.5) 60 +2 90 +3 |120 +4 | 150 +5 CMOSLOM-175T }35 1.65) 7042.51105 +4 |140 +5 | 175 +5 CMOSLDM-200T |40 +1.5) 8043 | 120 +4 160 +5 | 200 +6 CMOSLOM-225T |45 +2 90+3 (135 +4 |180+6 | 225 +7 TEST CONDITIONS CMOSLDOM-250T |B0O +2 ]100 43 160 +5 |2700+6 | 250+8 1. All measurements are made at 25C. @ All modules can be operated with a minimum input pulse width of 2. Voc supply voltage is maintained at 5.0V DC. 40% of full delay and pulse period approaching square wave; 3. Allunits are tested using a CMOS positive input pulse and one since delay accuracies may be somewhat degraded, it is sug- CMOS load at the output being tested. gested that the module be evaluated under the intended specific 84. Input pulse width used is 5 to 10ns longer than full delay of Operating conditions. Special modules can be readily manufac- module under test; spacing between pulses (falling edge to tured to improve accuracies and/or provide customer specified rising edge) is three times the pulse width used. random delay times for specific applications. Catalog No. C/111585