SPICE Device Model Si4410BDY
Vishay Siliconix
N-Channel 30-V (D-S) MOSFET
CHARACTERISTICS
• N-Channel Vertical DMOS
• Macro Model (Model Subcircuit)
• Level 3 MOS
• Apply for both Linear and Switching Application
• Accurate over the −55 to 125°C Temperature Range
• Model the Gate Charge, Transient, and Diode Reverse Recovery
Characteristics
DESCRIPTION
The attached spice model describes the typical electrical
characteristics of the n-channel vertical DMOS. The subcircuit
mode is extracted and optimized over the −55 to 125°C temperature
ranges under the pulsed 0-to-10V gate drive. The saturated output
impedance is best fit at the gate bias near the threshold voltage.
A novel gate-to-drain feedback capacitance network is used to
model the gate charge characteristics while avoiding convergence
difficulties of the switched Cgd model. All model parameter values
are optimized to provide a best fit to the measured electrical data
and are not intended as an exact physical interpretation of the
device.
SUBCIRCUIT MODEL SCHEMATIC
This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate
data sheet of the same number for guaranteed specification limits.
Document Number: 72284 www.vishay.com
15-May-03 1
SPICE Device Model Si4410BDY
Vishay Siliconix
SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED)
Parameter Symbol Test Conditions
Simulated
Data
Measured
Data Unit
Static
Gate Threshold Voltage VGS(th) VDS = VGS, ID = 250µA 1.5 V
On-State Drain Currenta ID(on) VDS ≥ 5V, VGS = 10V 333 A
VGS = 10V, ID = 10A 0.013 0.011
Drain-Source On-State Resistancea r
DS(on)
VGS = 4.5V, ID = 5A 0.019 0.017
Ω
Forward Transconductancea g
fs V
DS = 15V, ID = 10A 22 25 S
Forward Voltagea V
SD I
S = 2.3A, VGS = 0 V 0.68 0.76 V
Dynamicb
Total Gate Charge Qg 13.6 13
Gate-Source Charge Qgs 5.5 5.5
Gate-Drain Charge Qgd
VDS = 15V, VGS = 5V, ID = 10A
3.7 3.7
nC
Turn-On Delay Time td(on) 11 10
Rise Time tr 6 10
Turn-Off Delay Time td(off) 26 40
Fall Time tf
VDD = 25V, RL = 25Ω
ID ≅ 1A, VGEN = 10V, RG = 6Ω
22 15
Source-Drain Reverse Recovery Time trr IF = 2.3A, di/dt = 100 A/µs 31 35
ns
Notes
a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%.
b. Guaranteed by design, not subject to production testing.
www.vishay.com Document Number: 72284
2 15-May-03
SPICE Device Model Si4410BDY
Vishay Siliconix
COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED)
Document Number: 72284 www.vishay.com
15-May-03 3
