UPD444012AGY-B85X-MJH(A) - RENESAS TECHNOLOGY

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MOS INTEGRATED CIRCUIT

PD444012A-X

4M-BIT CMOS STATIC RAM

256K-WORD BY 16-BIT

EXTENDED TEMPERATURE OPERATION

DATA SHEET

Document No. M14464EJ7V0DS00 (7th edition)

Date Published September 2006 NS CP (K)

Printed in Japan

1999

Description

The

PD444012A-X is a high speed, low power, 4,194,304 bits (262,144 words by 16 bits) CMOS static RAM.

The

PD444012A-X has two chip enable pins (/CE1, CE2) to extend the capacity.

The

PD444012A-X is packed in 48-pin PLASTIC TSOP (I) (Normal bent).

Features

• 262,144 words by 16 bits organization

• Fast access time: 50, 55, 70, 85, 100, 120 ns (MAX.)

• Byte data control: /LB (I/O1 - I/O8), /UB (I/O9 - I/O16)

• Low voltage operation

(B version: VCC = 2.7 to 3.6 V, C version: VCC = 2.2 to 3.6 V)

• Low VCC data retention: 1.0 V (MIN.)

• Operating ambient temperature: TA = –25 to +85°C

• Output Enable input for easy application

• Two Chip Enable inputs: /CE1, CE2

Part number Access time Operating supply Operating ambient Supply current

ns (MAX.) Voltage temperature At operating At standby At data retention

V °C mA (MAX.)

A (MAX.)

PD444012A-BxxX 50 Note 1, 55, 70, 85, 100 2.7 to 3.6 −25 to +85 40 Note 2 7 3

45 Note 3

50 Note 4

PD444012A-CxxX 70, 85, 100, 120 2.2 to 3.6 40

Notes 1. VCC ≥ 3.0 V

2. Cycle time ≥ 70 ns

3. Cycle time = 55 ns

4. Cycle time = 50 ns

Data Sheet M14464EJ7V0DS

PD444012A-X

Ordering Information

Part number Package Access time Operating Operating Remark

ns (MAX.) supply voltage temperature

V °C

PD444012AGY-B55X-MJH 48-pin PLASTIC TSOP (I) 55, 50 Note 2.7 to 3.6 −25 to +85 B version

PD444012AGY-B70X-MJH (12×18) (Normal bent) 70

PD444012AGY-B85X-MJH 85

PD444012AGY-B10X-MJH 100

PD444012AGY-C70X-MJH 70 2.2 to 3.6 C version

PD444012AGY-C85X-MJH 85

PD444012AGY-C10X-MJH 100

PD444012AGY-C12X-MJH 120

PD444012AGY-B55X-MJH-A 55, 50 Note 2.7 to 3.6 B version

PD444012AGY-B70X-MJH-A 70

PD444012AGY-B85X-MJH-A 85

PD444012AGY-B10X-MJH-A 100

PD444012AGY-C70X-MJH-A 70 2.2 to 3.6 C version

PD444012AGY-C85X-MJH-A 85

PD444012AGY-C10X-MJH-A 100

PD444012AGY-C12X-MJH-A 120

Note VCC ≥ 3.0 V

Remark Products with -A at the end of the part number are lead-free products.

Data Sheet M14464EJ7V0DS 3

PD444012A-X

Pin Configuration (Marking Side)

/xxx indicates active low signal.

48-pin PLASTIC TSOP (I) (12×18) (Normal bent)

[

PD444012AGY-BxxX-MJH ]

[

PD444012AGY-CxxX-MJH ]

[

PD444012AGY-BxxX-MJH-A ]

[

PD444012AGY-CxxX-MJH-A ]

A15

A14

A13

A12

A11

A10

/WE

CE2

/UB

/LB

A17

A16

GND

I/O16

I/O8

I/O15

I/O7

I/O14

I/O6

I/O13

I/O5

I/O12

I/O4

I/O11

I/O3

I/O10

I/O2

I/O9

I/O1

/OE

GND

/CE1

A0 - A17 : Address inputs

I/O1 - I/O16 : Data inputs / outputs

/CE1, CE2 : Chip Enable 1, 2

/WE : Write Enable

/OE : Output Enable

/LB, /UB : Byte data select

CC : Power supply

GND : Ground

NC : No Connection

Remark Refer to Package Drawing for the 1-pin index mark.

Data Sheet M14464EJ7V0DS

PD444012A-X

Block Diagram

Address buffer

Address

buffer

Row

decoder

Memory cell array

4,194,304 bits

Input data

controller

A17

I/O9 - I/O16

/CE1

/WE

/OE

CE2

/UB

/LB

Output data

controller

I/O1 - I/O8

GND

Sense amplifier /

Switching circuit

Column decoder

Truth Table

/CE1 CE2 /OE /WE /LB /UB Mode I/O Supply current

I/O1 - I/O8 I/O9 - I/O16

H × × × × × Not selected High impedance High impedance ISB

× L × × × ×

L H H H × × Output disable High impedance High impedance ICCA

L H L L Word read DOUT DOUT

L H Lower byte read DOUT High impedance

H L Upper byte read High impedance DOUT

× L L L Word write DIN DIN

L H Lower byte write DIN High impedance

H L Upper byte write High impedance DIN

× × × × H H Not selected High impedance High impedance ISB

Remark × : VIH or VIL

Data Sheet M14464EJ7V0DS 5

PD444012A-X

Electrical Specifications

Absolute Maximum Ratings

Parameter Symbol Condition Rating Unit

Supply voltage VCC –0.5 Note to +4.0 V

Input / Output voltage VT –0.5 Note to VCC + 0.4 (4.0 V MAX.) V

Operating ambient temperature TA –25 to +85 °C

Storage temperature Tstg –55 to +125 °C

Note –3.0 V (MIN.) (Pulse width : 30 ns)

Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause

permanent damage. The device is not meant to be operated under conditions outside the limits

described in the operational section of this specification. Exposure to Absolute Maximum Rating

conditions for extended periods may affect device reliability.

Recommended Operating Conditions

Parameter Symbol Condition

PD444012A-BxxX

PD444012A-CxxX Unit

MIN. MAX. MIN. MAX.

Supply voltage VCC 2.7 3.6 2.2 3.6 V

High level input voltage VIH 2.7 V ≤ VCC ≤ 3.6 V 2.4 VCC+0.4 2.4 VCC+0.4 V

2.2 V ≤ VCC < 2.7 V – – 2.0 VCC+0.3

Low level input voltage VIL –0.3

Note +0.5 –0.3

Note +0.3 V

Operating ambient temperature TA –25 +85 –25 +85 °C

Note –1.5 V (MIN.) (Pulse width: 30 ns)

Capacitance (TA = 25°C, f = 1 MHz)

Parameter Symbol Test condition MIN. TYP. MAX. Unit

Input capacitance CIN VIN = 0 V 8 pF

Input / Output capacitance CI/O VI/O = 0 V 10 pF

Remarks 1. VIN : Input voltage

I/O : Input / Output voltage

2. These parameters are not 100% tested.

Data Sheet M14464EJ7V0DS

PD444012A-X

DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)(1/2)

Parameter Symbol Test condition VCC ≥ 2.7 V Unit

PD444012A-BxxX

MIN. TYP. MAX.

Input leakage current ILI VIN = 0 V to VCC –1.0 +1.0

I/O leakage current ILO VI/O = 0 V to VCC, /CE1 = VIH or –1.0 +1.0

CE2 = VIL or /WE = VIL or /OE = VIH

Operating supply current ICCA1 /CE1 = VIL, CE2 = VIH, Cycle time = 50 ns – 50 mA

Minimum cycle time, Cycle time = 55 ns – 45

II/O = 0 mA Cycle time ≥ 70 ns – 40

ICCA2 /CE1 = VIL, CE2 = VIH, II/O = 0 mA, – 4

Cycle time = ∞

ICCA3 /CE1 ≤ 0.2 V, CE2 ≥ VCC – 0.2 V, – 6

Cycle time = 1

s, II/O = 0 mA, VIL ≤ 0.2 V,

VIH ≥ VCC – 0.2 V

Standby supply current ISB /CE1 = VIH or CE2 = VIL or /LB = /UB = VIH – 0.6 mA

ISB1 /CE1 ≥ VCC − 0.2 V, CE2 ≥ VCC − 0.2 V 0.5 7

ISB2 CE2 ≤ 0.2 V 0.5 7

ISB3 /LB = /UB ≥ VCC − 0.2 V, /CE1 ≤ 0.2 V, 0.5 7

CE2 ≥ VCC − 0.2 V

High level output voltage VOH IOH = –0.5 mA 2.4 V

Low level output voltage VOL IOL = 1.0 mA 0.4 V

Remarks 1. VIN : Input voltage

I/O : Input / Output voltage

2. These DC characteristics are in common regardless of product specification.

Data Sheet M14464EJ7V0DS 7

PD444012A-X

DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)(2/2)

Parameter Symbol Test condition VCC ≥ 2.2 V Unit

PD444012A-CxxX

MIN. TYP. MAX.

Input leakage current ILI VIN = 0 V to VCC –1.0 +1.0

I/O leakage current ILO VI/O = 0 V to VCC, /CE1 = VIH or –1.0 +1.0

CE2 = VIL or /WE = VIL or /OE = VIH

Operating supply current ICCA1 /CE1 = VIL, CE2 = VIH, Minimum cycle time, – 40 mA

II/O = 0 mA VCC ≤ 2.7 V – 25

ICCA2 /CE1 = VIL, CE2 = VIH, – 4

II/O = 0 mA, Cycle time = ∞ VCC ≤ 2.7 V – 2

ICCA3 /CE1 ≤ 0.2 V, CE2 ≥ VCC – 0.2 V, – 6

Cycle time = 1

s, II/O = 0 mA,

VIL ≤ 0.2 V, VIH ≥ VCC – 0.2 V VCC ≤ 2.7 V – 5

Standby supply current ISB /CE1 = VIH or CE2 = VIL or – 0.6 mA

/LB = /UB = VIH VCC ≤ 2.7 V – 0.6

ISB1 /CE1 ≥ VCC − 0.2 V, 0.5 7

CE2 ≥ VCC − 0.2 V VCC ≤ 2.7 V 0.4 6

ISB2 CE2 ≤ 0.2 V 0.5 7

VCC ≤ 2.7 V 0.4 6

ISB3 /LB = /UB ≥ VCC − 0.2 V, /CE1 ≤ 0.2 V, 0.5 7

CE2 ≥ VCC − 0.2 V VCC ≤ 2.7 V 0.4 6

High level output voltage VOH IOH = –0.5 mA

2.4 V

VCC ≤ 2.7 V 1.8

Low level output voltage VOL IOL = 1.0 mA 0.4 V

Remarks 1. VIN : Input voltage

I/O : Input / Output voltage

2. These DC characteristics are in common regardless of product classification.

Data Sheet M14464EJ7V0DS

PD444012A-X

AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)

AC Test Conditions

[

PD444012A-B55X,

PD444012A-B70X,

PD444012A-B85X,

PD444012A-B10X ]

Input Waveform (Rise and Fall Time ≤ 5 ns)

0.1

0.9

Test pointsV

/2 V

Output Waveform

Test pointsV

/2 V

Output Load

1TTL + 50 pF

[

PD444012A-C70X,

PD444012A-C85X,

PD444012A-C10X,

PD444012A-C12X ]

Input Waveform (Rise and Fall Time ≤ 5 ns)

0.1

0.9

Test pointsV

/2 V

Output Waveform

Test pointsV

/2 V

Output Load

1TTL + 30 pF

Data Sheet M14464EJ7V0DS 9

PD444012A-X

Read Cycle (1/2) (B version)

Parameter Symbol VCC ≥ 3.0 V VCC ≥ 2.7 V Unit Condition

PD444012A

-B55X -B55X -B70X -B85X -B10X

MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.

Read cycle time tRC 50 55 70 85 100 ns

Address access time tAA 50 55 70 85 100 ns Note 1

/CE1 access time tCO1 50 55 70 85 100 ns

CE2 access time tCO2 50 55 70 85 100 ns

/OE to output valid tOE 30 30 35 40 50 ns

/LB, /UB to output valid tBA 50 55 70 85 100 ns

Output hold from address change tOH 10 10 10 10 10 ns

/CE1 to output in low impedance tLZ1 10 10 10 10 10 ns Note 2

CE2 to output in low impedance tLZ2 10 10 10 10 10 ns

/OE to output in low impedance tOLZ 0 0 0 0 0 ns

/LB, /UB to output in low impedance tBLZ 10 10 10 10 10 ns

/CE1 to output in high impedance tHZ1 20 20 25 30 35 ns

CE2 to output in high impedance tHZ2 20 20 25 30 35 ns

/OE to output in high impedance tOHZ 20 20 25 30 35 ns

/LB, /UB to output in high impedance tBHZ 20 20 25 30 35 ns

Notes 1. The output load is 1TTL + 50 pF.

2. The output load is 1TTL + 5 pF.

Read Cycle (2/2) (C version)

Parameter Symbol VCC ≥ 2.2 V Unit Condition

PD444012A

-C70X -C85X -C10X -C12X

MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.

Read cycle time tRC 70 85 100 120 ns

Address access time tAA 70 85 100 120 ns Note 1

/CE1 access time tCO1 70 85 100 120 ns

CE2 access time tCO2 70 85 100 120 ns

/OE to output valid tOE 35 40 50 60 ns

/LB, /UB to output valid tBA 70 85 100 120 ns

Output hold from address change tOH 10 10 10 10 ns

/CE1 to output in low impedance tLZ1 10 10 10 10 ns Note 2

CE2 to output in low impedance tLZ2 10 10 10 10 ns

/OE to output in low impedance tOLZ 0 0 0 0 ns

/LB, /UB to output in low impedance tBLZ 10 10 10 10 ns

/CE1 to output in high impedance tHZ1 25 30 35 40 ns

CE2 to output in high impedance tHZ2 25 30 35 40 ns

/OE to output in high impedance tOHZ 25 30 35 40 ns

/LB, /UB to output in high impedance tBHZ 25 30 35 40 ns

Notes 1. The output load is 1TTL + 30 pF.

2. The output load is 1TTL + 5 pF.

Data Sheet M14464EJ7V0DS

PD444012A-X

Read Cycle Timing Chart

tHZ2

tRC

tOH

tHZ1

tBLZ

tBA

tLZ2

tCO2

tLZ1

tCO1

tBHZ

tAA

High impedance Data out

/LB, /UB (Input)

CE2 (Input)

/CE1 (Input)

Address (Input)

I/O (Output)

tOLZ

tOE tOHZ

/OE (Input)

Remark In read cycle, /WE should be fixed to high level.

Data Sheet M14464EJ7V0DS 11

PD444012A-X

Write Cycle (1/2) (B version)

Parameter Symbol VCC ≥ 3.0 V VCC ≥ 2.7 V Unit Condition

PD444012A

-B55X -B55X -B70X -B85X -B10X

MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.

Write cycle time tWC 50 55 70 85 100 ns

/CE1 to end of write tCW1 45 50 55 70 80 ns

CE2 to end of write tCW2 45 50 55 70 80 ns

/LB, /UB to end of write tBW 45 50 55 70 80 ns

Address valid to end of write tAW 45 50 55 70 80 ns

Address setup time tAS 0 0 0 0 0 ns

Write pulse width tWP 40 45 50 55 60 ns

Write recovery time tWR 0 0 0 0 0 ns

Data valid to end of write tDW 25 25 30 35 40 ns

Data hold time tDH 0 0 0 0 0 ns

/WE to output in high impedance tWHZ 20 20 25 30 35 ns Note

Output active from end of write tOW 5 5 5 5 5 ns

Note The output load is 1TTL + 5 pF.

Write Cycle (2/2) (C version)

Parameter Symbol VCC ≥ 2.2 V Unit Condition

PD444012A

-C70X -C85X -C10X -C12X

MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.

Write cycle time tWC 70 85 100 120 ns

/CE1 to end of write tCW1 55 70 80 100 ns

CE2 to end of write tCW2 55 70 80 100 ns

/LB, /UB to end of write tBW 55 70 80 100 ns

Address valid to end of write tAW 55 70 80 100 ns

Address setup time tAS 0 0 0 0 ns

Write pulse width tWP 50 55 60 85 ns

Write recovery time tWR 0 0 0 0 ns

Data valid to end of write tDW 30 35 40 60 ns

Data hold time tDH 0 0 0 0 ns

/WE to output in high impedance tWHZ 25 30 35 40 ns Note

Output active from end of write tOW 5 5 5 5 ns

Note The output load is 1TTL + 5 pF.

Data Sheet M14464EJ7V0DS

PD444012A-X

Write Cycle Timing Chart 1 (/WE Controlled)

CW1

WHZ

Indefinite data out High

impe-

dance

High

impe-

dance

Data in Indefinite data out

Address (Input)

/CE1 (Input)

/LB, /UB (Input)

I/O (Input / Output)

CE2 (Input)

CW2

/WE (Input)

Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated.

2. Do not input data to the I/O pins while they are in the output state.

Remarks 1. Write operation is done during the overlap time of a low level /CE1, /WE, /LB and/or /UB, and a

high level CE2.

2. If /CE1 changes to low level at the same time or after the change of /WE to low level, or if CE2

changes to high level at the same time or after the change of /WE to low level, the I/O pins will

remain high impedance state.

3. When /WE is at low level, the I/O pins are always high impedance. When /WE is at high level,

read operation is executed. Therefore /OE should be at high level to make the I/O pins high

impedance.

Data Sheet M14464EJ7V0DS 13

PD444012A-X

Write Cycle Timing Chart 2 (/CE1 Controlled)

CW1

Data in

High impedance

Address (Input)

/CE1 (Input)

/LB, /UB (Input)

I/O (Input) High

impedance

CE2 (Input)

CW2

/WE (Input)

Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated.

2. Do not input data to the I/O pins while they are in the output state.

Remark Write operation is done during the overlap time of a low level /CE1, /WE, /LB and/or /UB, and a high level

CE2.

Data Sheet M14464EJ7V0DS

PD444012A-X

Write Cycle Timing Chart 3 (CE2 Controlled)

CW2

Data in

High impedance

Address (Input)

CE2 (Input)

/LB, /UB (Input)

I/O (Input) High

impedance

/CE1 (Input)

CW1

/WE (Input)

Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated.

2. Do not input data to the I/O pins while they are in the output state.

Remark Write operation is done during the overlap time of a low level /CE1, /WE, /LB and/or /UB, and a high level

CE2.

Data Sheet M14464EJ7V0DS 15

PD444012A-X

Write Cycle Timing Chart 4 (/LB, /UB Controlled)

Data in

High impedance

Address (Input)

/LB, /UB (Input)

I/O (Input) High

impedance

CE2 (Input)

CW2

/WE (Input)

/CE1 (Input)

CW1

Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated.

2. Do not input data to the I/O pins while they are in the output state.

Remark Write operation is done during the overlap time of a low level /CE1, /WE, /LB and/or /UB, and a high level

CE2.

Data Sheet M14464EJ7V0DS

PD444012A-X

Low VCC Data Retention Characteristics (TA = –25 to +85°C)

Parameter Symbol Test Condition VCC ≥ 2.7 V VCC ≥ 2.2 V Unit

PD444012A

-B××X

-C××X

MIN. TYP. MAX. MIN. TYP. MAX.

Data retention VCCDR1 /CE1 ≥ VCC − 0.2 V, CE2 ≥ VCC − 0.2 V 1.0 3.6 1.0 3.6 V

supply voltage VCCDR2 CE2 ≤ 0.2 V 1.0 3.6 1.0 3.6

VCCDR3 /LB = /UB ≥ VCC − 0.2 V, 1.0 3.6 1.0 3.6

/CE1 ≤ 0.2 V, CE2 ≥ VCC − 0.2 V

Data retention ICCDR1 VCC = 1.5 V, /CE1 ≥ VCC − 0.2 V, 0.3 3.0 0.3 3.0

supply current CE2 ≥ VCC − 0.2 V

ICCDR2 VCC = 1.5 V, CE2 ≤ 0.2 V 0.3 3.0 0.3 3.0

ICCDR3 VCC = 1.5 V, /LB = /UB ≥ VCC − 0.2 V, 0.3 3.0 0.3 3.0

/CE1 ≤ 0.2 V, CE2 ≥ VCC − 0.2 V

Chip deselection tCDR 0 0 ns

to data retention

mode

Operation tR tRCNote tRCNote ns

recovery time

Note tRC : Read cycle time

Data Sheet M14464EJ7V0DS 17

PD444012A-X

Data Retention Timing Chart

(1) /CE1 Controlled

VIH (MIN.)

VCCDR (MIN.)

VIL (MAX.)

VCC

/CE1

/CE1 ≥ VCC – 0.2 V

GND

VCC (MIN.)Note

tCDR Data retention mode tR

Note B version : 2.7 V, C version : 2.2 V

Remark On the data retention mode by controlling /CE1, the input level of CE2 must be ≥ VCC − 0.2 V or ≤ 0.2 V.

The other pins (Address, I/O, /WE, /OE, /LB, /UB) can be in high impedance state.

(2) CE2 Controlled

(MIN.)

CCDR

(MIN.)

(MAX.)

CE2

CE2 ≤ 0.2 V

GND

(MIN.)

Note

CDR

Data retention mode t

Note B version : 2.7 V, C version : 2.2 V

Remark On the data retention mode by controlling CE2, The other pins (/CE1, Address, I/O, /WE, /OE, /LB, /UB)

can be in high impedance state.

Data Sheet M14464EJ7V0DS

PD444012A-X

(3) /LB, /UB Controlled

CDR

Data retention mode

(MIN.)

CCDR

(MIN.)

(MAX.)

/LB, /UB

/LB, /UB ≥ V

– 0.2 V

GND

(MIN.)

Note

Note B version : 2.7 V, C version : 2.2 V

Remark On the data retention mode by controlling /LB and /UB, the input level of /CE1 and CE2 must be

≥ VCC − 0.2 V or ≤ 0.2 V. The other pins (Address, I/O, /WE, /OE) can be in high impedance state.

Data Sheet M14464EJ7V0DS 19

PD444012A-X

Package Drawing

NOTES

48-PIN PLASTIC TSOP(I) (12x18)

ITEM MILLIMETERS

12.0±0.1

0.5 (T.P.)

0.1±0.05

0.45 MAX.

1.2 MAX.

16.4±0.1

0.145±0.05

0.10M

D 0.22±0.05

1. Each lead centerline is located within 0.10 mm of

its true position (T.P.) at maximum material condition.

2. "A" excludes mold flash. (Includes mold flash : 12.4 mm MAX.)

1.0±0.05G

L 0.5

0.10N

P 18.0±0.2

Q3°+5°

−3°

0.25R

S48GY-50-MJH1-1

S 0.60±0.15

J 0.8±0.2

detail of lead end

Data Sheet M14464EJ7V0DS

PD444012A-X

Recommended Soldering Conditions

Please consult with our sales offices for soldering conditions of the

PD444012A-X.

Types of Surface Mount Device

PD444012AGY-BxxX-MJH : 48-pin PLASTIC TSOP (I) (12×18) (Normal bent)

PD444012AGY-CxxX-MJH : 48-pin PLASTIC TSOP (I) (12×18) (Normal bent)

PD444012AGY-BxxX-MJH-A : 48-pin PLASTIC TSOP (I) (12×18) (Normal bent)

PD444012AGY-CxxX-MJH-A : 48-pin PLASTIC TSOP (I) (12×18) (Normal bent)

Quality Grade

• A quality grade of the products is “Standard”.

• Anti-radioactive design is not implemented in the products.

• Semiconductor devices have the possibility of unexpected defects by affection of cosmic ray that reach to the

ground and so forth.

<R>

Data Sheet M14464EJ7V0DS 21

PD444012A-X

Revision History

Edition/ Page Type of Location Description

Date This Previous revision (Previous edition → This edition)

edition edition

7th edition/ p.20 p.20 Addition Quality Grade Section of Quality Grade has been added.

Sep. 2006

Data Sheet M14464EJ7V0DS

PD444012A-X

[ MEMO ]

Data Sheet M14464EJ7V0DS 23

PD444012A-X

VOLTAGE APPLICATION WAVEFORM AT INPUT PIN

Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the

CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may

malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,

and also in the transition period when the input level passes through the area between VIL (MAX) and

VIH (MIN).

HANDLING OF UNUSED INPUT PINS

Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is

possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS

devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed

high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND

via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must

be judged separately for each device and according to related specifications governing the device.

PRECAUTION AGAINST ESD

A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and

ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as

much as possible, and quickly dissipate it when it has occurred. Environmental control must be

adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that

easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static

container, static shielding bag or conductive material. All test and measurement tools including work

benches and floors should be grounded. The operator should be grounded using a wrist strap.

Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for

PW boards with mounted semiconductor devices.

STATUS BEFORE INITIALIZATION

Power-on does not necessarily define the initial status of a MOS device. Immediately after the power

source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does

not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the

reset signal is received. A reset operation must be executed immediately after power-on for devices

with reset functions.

POWER ON/OFF SEQUENCE

In the case of a device that uses different power supplies for the internal operation and external

interface, as a rule, switch on the external power supply after switching on the internal power supply.

When switching the power supply off, as a rule, switch off the external power supply and then the

internal power supply. Use of the reverse power on/off sequences may result in the application of an

overvoltage to the internal elements of the device, causing malfunction and degradation of internal

elements due to the passage of an abnormal current.

The correct power on/off sequence must be judged separately for each device and according to related

specifications governing the device.

INPUT OF SIGNAL DURING POWER OFF STATE

Do not input signals or an I/O pull-up power supply while the device is not powered. The current

injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and

the abnormal current that passes in the device at this time may cause degradation of internal elements.

Input of signals during the power off state must be judged separately for each device and according to

related specifications governing the device.

NOTES FOR CMOS DEVICES

PD444012A-X

The information in this document is current as of September, 2006. The information is subject to

change without notice. For actual design-in, refer to the latest publications of NEC Electronics data

sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not

all products and/or types are available in every country. Please check with an NEC Electronics sales

representative for availability and additional information.

No part of this document may be copied or reproduced in any form or by any means without the prior

written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may

appear in this document.

NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual

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or any other liability arising from the use of such products. No license, express, implied or otherwise, is

granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.

Descriptions of circuits, software and other related information in this document are provided for illustrative

purposes in semiconductor product operation and application examples. The incorporation of these

circuits, software and information in the design of a customer's equipment shall be done under the full

responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by

customers or third parties arising from the use of these circuits, software and information.

While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,

customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To

minimize risks of damage to property or injury (including death) to persons arising from defects in NEC

Electronics products, customers must incorporate sufficient safety measures in their design, such as

redundancy, fire-containment and anti-failure features.

NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and

"Specific".

The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-

designated "quality assurance program" for a specific application. The recommended applications of an NEC

Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of

each NEC Electronics product before using it in a particular application.

"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio

and visual equipment, home electronic appliances, machine tools, personal electronic equipment

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"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster

systems, anti-crime systems, safety equipment and medical equipment (not specifically designed

for life support).

"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems and medical equipment for life support, etc.

The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC

Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications

not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to

determine NEC Electronics' willingness to support a given application.

(Note)

(1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its

majority-owned subsidiaries.

(2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as

defined above).

•

M8E 02. 11-1