CD4093BCMX - Fairchild Semiconductor

October 1987

Revised April 2002

CD4093BC Quad 2-Input NAND Schmitt Trigger

CD4093BC

Quad 2-Input NAND Schmitt Trigger

General Description

The CD4093B consists of four Schmitt-trigger circuits.

Eac h c i r cui t fu nc t io ns as a 2- i n put N AN D g a te wi t h Sc h mit t -

trigger acti o n on both in pu ts. T he g ate switche s at differe nt

points for positive and negative-going signals. The differ-

ence between the positive (VT+) and the negative voltage

(VT−) is defined as hysteresis voltage (VH).

All outputs have equal source and sink currents and con-

form to standard B-series output drive (see Static Electrical

Characteristics).

Features

■Wide supply voltage range: 3.0V to 15V

■Sch m itt-trigger on each input

with no external components

■Noise immunity greater than 50%

■Equal source and sink currents

■No limit on input rise and fall time

■Standard B-series output drive

■Hysteresis voltage (any input) TA = 25°C

Applications

• Wave and pulse shapers

• High-noise-environment systems

• Monostable multivibrators

• Astable multivibrators

• NAND logic

Ordering Code:

Devices also available in Tape and R eel. Speci fy by appending the s uffix let t er “X” to the ordering code.

Connection Diagram

Top View

Typical VDD = 5.0V VH = 1.5V

VDD = 10V VH = 2.2V

VDD = 15V VH = 2.7V

Guaranteed VH = 0.1 VDD

Order Number Package Number Package Description

CD4093BCM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

CD4093BCN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

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CD4093BC

Absolute Maximum Ratings(Note 1)

(Note 2) Recommended Operating

Conditions (Note 2)

Note 1: “Absolute Maximum Ratings” are those values beyond which the

safety of the device cannot be guaranteed; they are not meant to imply that

the devices should be operated at these limits. The table of “Recom-

mended Operating Conditions” and “Electrical Characteristics” provides

conditions for act ual devi c e operation.

Note 2: VSS = 0V unless otherwise specified.

DC Electrical Characteristi cs (Note 2)

Note 3: IOH and IOL are tes t ed one ou t put at a time.

DC Supply Voltage (VDD)−0.5 to +18 VDC

Input Voltage (VIN)−0.5 to VDD +0.5 VDC

Storage Temperature Range ( T S)−65°C to +150°C

Power Dissipation (PD)

Dual-In-Line 700 mW

Small Out lin e 500 mW

Lead Temperature (TL)

(Solder ing, 10 seco nds) 260°C

DC Supply Voltage (VDD) 3 to 15 VDC

Input Voltage (VIN)0 to V

DD VDC

Operating Temperature Rang e (TA)−55°C to +125°C

Symbol Parameter Conditions −55°C+25°C+125°CUnits

Min Max Min Typ Max Min Max

IDD Quiescent Device VDD = 5V 0.25 0.25 7.5 µACurrent VDD = 10V 0.5 0.5 15.0

VDD = 15V 1.0 1.0 30.0

VOL LOW Level VIN = VDD, |IO| < 1 µA

Output Voltage VDD = 5V 0.05 0 0.05 0.05 VVDD = 10V 0.05 0 0.05 0.05

VDD = 15V 0.05 0 0.05 0.05

VOH HIGH Level VIN = VSS, |IO| < 1 µA

Output Voltage VDD = 5V 4.95 4.95 5 4.95 VVDD = 10V 9.95 9.95 10 9.95

VDD = 15V 14.95 14.95 15 14.95

VT−Negative-Going Threshold |IO| < 1 µA

Voltage (Any Input) VDD = 5V, VO = 4.5V 1.3 2.25 1.5 1.8 2.25 1.5 2.3 VVDD = 10V, VO = 9V 2.85 4.5 3.0 4.1 4.5 3.0 4.65

VDD = 15V, VO = 13.5V 4.35 6.75 4 .5 6.3 6.75 4 .5 6.9

VT+Positive- Going Thr eshol d |IO| < 1 µA

Voltage (Any Input) VDD = 5V, VO = 0.5V 2.75 3.6 2.75 3.3 3.5 2.65 3.5 VVDD = 10V, VO = 1V 5.5 7.15 5.5 6.2 7.0 5.35 7.0

VDD = 15V, VO = 1.5V 8.25 10.65 8.25 9.0 10.5 8.1 10.5

VHHysteresis (VT+ − VT−)V

DD = 5V 0.5 2.35 0.5 1.5 2.0 0.35 2.0 V(Any Input) VDD = 10V 1.0 4.3 1.0 2.2 4.0 0.70 4.0

VDD = 15V 1.5 6.3 1.5 2.7 6.0 1.20 6.0

IOL LOW Level Output VIN = VDD

Current (Note 3) VDD = 5V, VO = 0.4V 0.64 0.51 0.88 0.36 mAVDD = 10V, VO = 0.5V 1.6 1.3 2.25 0.9

VDD = 15V, VO = 1.5V 4.2 3.4 8.8 2.4

IOH HIG H Level Output VIN = VSS

Current (Note 3) VDD = 5V, VO = 4.6V −0.64 0.51 −0.88 −0.36 mAVDD = 10V, VO = 9.5V −1.6 −1.3 −2.25 −0.9

VDD = 15V, VO = 13.5V −4.2 −3.4 −8.8 −2.4

IIN Input Current VDD = 15V, VIN = 0V −0.1 −10−5−0.1 −1.0 µA

VDD = 15V, VIN = 15V 0.1 10−50.1 1.0

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CD4093BC

AC Electrical Characteristics (Note 4)

TA = 25°C, CL = 50 pF, RL = 200k, Input tr, tf = 20 ns, unless otherwise specified

Note 4: AC Paramet ers are guaranteed by DC co rrelated te s tin g.

Symbol Parameter Conditions Min Typ Max Units

tPHL, tPLH Propagation Delay Time VDD = 5V 300 450 nsVDD = 10V 120 210

VDD = 15V 80 160

tTHL, tTLH Transition Time VDD = 5V 90 145 nsVDD = 10V 50 75

VDD = 15V 40 60

CIN Input Capacitance (Any Input) 5.0 7.5 pF

CPD Power Dissipation Capacitance (Per Gate) 24 pF

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CD4093BC

Typical Applications

Gat ed Oscillator

Assume t1 + t2 >> tPHL + tPLH then:

t0 = RC ln [VDD/VT−]

t1 = RC ln [(VDD − VT−)/(VDD − VT+)]

t2 = RC ln [VT+/VT−]

Gated One-Shot (a) Negative-Edge Triggered

(b) Positive-Edge Triggered

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CD4093BC

Typical Performance Characteristics

Typical Transfer

Characteristics

Guaranteed Hysteresis vs VDD

Guaranteed Trigger Threshold

Volt age vs V DD

Guaranteed Hysteresis vs VDD

Input and Output Characteristics

VNML = VIH(MIN) − VOL ≅ VIH(MIN) = VT+(MIN)

VNMH = VOH − VIL(MAX) ≅ VDD − VIL(MAX) = VDD − VT−(MAX)

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CD4093BC

AC Test Circui ts and Switchi ng Time Waveforms

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CD4093BC

Physical Dimensions inches (millimeters) unless otherwise noted

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

Package Number M14A

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CD4093BC Quad 2-Input NAND Schmitt Trigger

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Package Number N14A

Fairchild does not assu me any responsibility for use of any circuitry de scribed, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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