© Semiconductor Components Industries, LLC, 2006
October, 2006 − Rev. 7
1Publication Order Number:
MC33178/D
MC33178, MC33179
Low Power, Low Noise
Operational Amplifiers
The MC33178/9 series is a family of high quality monolithic
amplifiers employing Bipolar technology with innovative high
performance concepts for quality audio and data signal processing
applications. This device family incorporates the use of high
frequency PNP input transistors to produce amplifiers exhibiting low
input offset voltage, noise and distortion. In addition, the amplifier
provides high output current drive capability while consuming only
420 mA of drain current per amplifier. The NPN output stage used,
exhibits no deadband crossover distortion, large output voltage swing,
excellent phase and gain margins, low open−loop high frequency
output impedance, symmetrical source and sink AC frequency
performance.
The MC33178/9 family offers both dual and quad amplifier
versions in several package options.
Features
•600 W Output Drive Capability
•Large Output Voltage Swing
•Low Offset Voltage: 0.15 mV (Mean)
•Low T.C. of Input Offset Voltage: 2.0 mV/°C
•Low Total Harmonic Distortion: 0.0024%
(@ 1.0 kHz w/600 W Load)
•High Gain Bandwidth: 5.0 MHz
•High Slew Rate: 2.0 V/ms
•Dual Supply Operation: ±2.0 V to ±18 V
•ESD Clamps on the Inputs Increase Ruggedness without Affecting
Device Performance
•Pb−Free Packages are Available
Figure 1. Representative Schematic Diagram
(Each Amplifier)
VEE
VCC
Iref
Vin +
Vin −
Iref
CC
CM
VO
PDIP−8
P SUFFIX
CASE 626
SOIC−8
D SUFFIX
CASE 751
DUAL
QUAD
PDIP−14
P SUFFIX
CASE 646
SOIC−14
D SUFFIX
CASE 751A
1
8
1
8
1
14
14
1
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See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
ORDERING INFORMATION
See general marking information in the device marking
section on page 4 of this data sheet.
DEVICE MARKING INFORMATION
1
8
Micro8
DM SUFFIX
CASE 846A
1
14
TSSOP−14
DTB SUFFIX
CASE 948G
MC33178, MC33179
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2
MAXIMUM RATINGS
Rating Symbol Value Unit
Supply Voltage (VCC to VEE) VS+36 V
Input Differential Voltage Range VIDR Note 1 V
Input Voltage Range VIR Note 1 V
Output Short Circuit Duration (Note 2) tSC Indefinite sec
Maximum Junction Temperature TJ+150 °C
Storage Temperature Range Tstg −60 to +150 °C
Maximum Power Dissipation PDNote 2 mW
Operating Temperature Range TA−40 to +85 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Either or both input voltages should not exceed VCC or VEE.
2. Power dissipation must be considered to ensure maximum junction temperature (TJ) is not exceeded. (See power dissipation performance
characteristic, Figure 2.)
ORDERING INFORMATION
Device Package Shipping†
MC33178D SOIC−8
98 Units / Rail
MC33178DG SOIC−8
(Pb−Free)
MC33178DR2 SOIC−8
2500 / Tape & Reel
MC33178DR2G SOIC−8
(Pb−Free)
MC33178P PDIP−8
50 Units / Rail
MC33178PG PDIP−8
(Pb−Free)
MC33178DMR2 Micro8
4000 / Tape & Reel
MC33178DMR2G Micro8
(Pb−Free)
MC33179D SOIC−14
55 Units / Rail
MC33179DG SOIC−14
(Pb−Free)
MC33179DR2 SOIC−14
2500 / Tape & Reel
MC33179DR2G SOIC−14
(Pb−Free)
MC33179P PDIP−14
25 Units / Rail
MC33179PG PDIP−14
(Pb−Free)
MC33179DTBR2G TSSOP−14
(Pb−Free) 2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
MC33178, MC33179
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3
MARKING DIAGRAMS
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G= Pb−Free Package
PDIP−14
CASE 646
SOIC−14
CASE 751A
1
14
MC33179P
AWLYYWWG
PDIP−8
CASE 626
SOIC−8
CASE 751
1
8
MC33178P
AWL
YYWWG
PIN CONNECTIONS
CASE 626/751/846A
DUAL
CASE 646/751A/948G
QUAD
(Top View)
VEE
Inputs 1
Inputs 2
Output 2
Output 1 VCC
−
−
+
+
1
2
3
4
8
7
6
5
(Top View)
1
2
3
4
5
6
78
9
10
11
12
13
14
4
23
1
Inputs 1
Output 1
VCC
Inputs 2
Output 2
Output 4
Inputs 4
VEE
Inputs 3
Output 3
++
−−
++
−−
DUAL QUAD
33178
ALYW
G
1
8
MC33179DG
AWLYWW
1
14
Micro8
CASE 846A
3178
AYWG
G
1
8
TSSOP−14
CASE 948G
MC33
179
ALYWG
G
1
14
(Note: Microdot may be in either location)
MC33178, MC33179
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DC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = −15 V, TA = 25°C, unless otherwise noted.)
Characteristics Figure Symbol Min Typ Max Unit
Input Offset Voltage (RS = 50 W, VCM = 0 V, VO = 0 V)
(VCC = +2.5 V, VEE = −2.5 V to VCC = +15 V, VEE = −15 V)
TA = +25°C
TA = −40° to +85°C
3 |VIO|
−
−
0.15
−
3.0
4.0
mV
Average Temperature Coefficient of Input Offset Voltage
(RS = 50 W, VCM = 0 V, VO = 0 V)
TA = −40° to +85°C
3DVIO/DT
−2.0 −
mV/°C
Input Bias Current (VCM = 0 V, VO = 0 V)
TA = +25°C
TA = −40° to +85°C
4, 5 IIB
−
−
100
−
500
600
nA
Input Offset Current (VCM = 0 V, VO = 0 V)
TA = +25°C
TA = −40° to +85°C
|IIO|
−
−
5.0
−
50
60
nA
Common Mode Input Voltage Range
(DVIO = 5.0 mV, VO = 0 V)
6 VICR −13
−
−14
+14
−
+13
V
Large Signal Voltage Gain (VO = −10 V to +10 V, RL = 600 W)
TA = +25°C
TA = −40° to +85°C
7, 8 AVOL
50
25
200
−
−
−
kV/V
Output Voltage Swing (VID = ±1.0 V)
(VCC = +15 V, VEE = −15 V)
RL = 300 W
RL = 300 W
RL = 600 W
RL = 600 W
RL = 2.0 kW
RL = 2.0 kW
(VCC = +2.5 V, VEE = −2.5 V)
RL = 600 W
RL = 600 W
9, 10, 11
VO+
VO−
VO+
VO−
VO+
VO−
VO+
VO−
−
−
+12
−
+13
−
1.1
−
+12
−12
+13.6
−13
+14
−13.8
1.6
−1.6
−
−
−
−12
−
−13
−
−1.1
V
Common Mode Rejection (Vin = ±13 V) 12 CMR 80 110 −dB
Power Supply Rejection
VCC/VEE = +15 V/ −15 V, +5.0 V/ −15 V, +15 V/ −5.0 V
13 PSR
80 110 −
dB
Output Short Circuit Current (VID = ±1.0 V, Output to Ground)
Source (VCC = 2.5 V to 15 V)
Sink (VEE = −2.5 V to −15 V)
14, 15 ISC
+50
−50
+80
−100
−
−
mA
Power Supply Current (VO = 0 V)
(VCC = 2.5 V, VEE = −2.5 V to VCC = +15 V, VEE = −15 V)
MC33178 (Dual)
TA = +25°C
TA = −40° to +85°C
MC33179 (Quad)
TA = +25°C
TA = −40° to +85°C
16 ID
−
−
−
−
−
−
1.7
−
1.4
1.6
2.4
2.6
mA
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AC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = −15 V, TA = 25°C, unless otherwise noted.)
Characteristics Figure Symbol Min Typ Max Unit
Slew Rate
(Vin = −10 V to +10 V, RL = 2.0 kW, CL = 100 pF, AV = +1.0 V)
17, 32 SR
1.2 2.0 −
V/ms
Gain Bandwidth Product (f = 100 kHz) 18 GBW 2.5 5.0 −MHz
AC Voltage Gain (RL = 600 W, VO = 0 V, f = 20 kHz) 19, 20 AVO −50 −dB
Unity Gain Bandwidth (Open−Loop) (RL = 600 W, CL = 0 pF) BW −3.0 −MHz
Gain Margin (RL = 600 W, CL = 0 pF) 21, 23, 24 Am−15 −dB
Phase Margin (RL = 600 W, CL = 0 pF) 22, 23, 24 fm−60 −Deg
Channel Separation (f = 100 Hz to 20 kHz) 25 CS − −120 −dB
Power Bandwidth (VO = 20 Vpp, RL = 600 W, THD ≤ 1.0%) BWp−32 −kHz
Total Harmonic Distortion (RL = 600 W,, VO = 2.0 Vpp, AV = +1.0 V)
(f = 1.0 kHz)
(f = 10 kHz)
(f = 20 kHz)
26 THD
−
−
−
0.0024
0.014
0.024
−
−
−
%
Open Loop Output Impedance
(VO = 0 V, f = 3.0 MHz, AV = 10 V)
27 |ZO|
−150 −
W
Differential Input Resistance (VCM = 0 V) Rin −200 −kW
Differential Input Capacitance (VCM = 0 V) Cin −10 −pF
Equivalent Input Noise Voltage (RS = 100 W,)
f = 10 Hz
f = 1.0 kHz
28 en
−
−
8.0
7.5
−
−
nV/ Hz√
Equivalent Input Noise Current
f = 10 Hz
f = 1.0 kHz
29 in
−
−
0.33
0.15
−
−
pA/ Hz√
Figure 2. Maximum Power Dissipation
versus Temperature
Figure 3. Input Offset Voltage versus
Temperature for 3 Typical Units
P(MAX), MAXIMUM POWER DISSIPATION (mW)
D
TA, AMBIENT TEMPERATURE (°C)
−60 −40 −20 0 20 40 60 80 100 120 180160140
MC33178P/9P
MC33179D
MC33178D
V, INPUT OFFSET VOLTAGE (mV)
IO
TA, AMBIENT TEMPERATURE (°C)
−55 −25 0 25 50 75 100 125
Unit 1
Unit 2
Unit 3
VCC = +15 V
VEE = −15 V
RS = 10 W
VCM = 0 V
2400
2000
1600
1200
800
400
0
4.0
3.0
2.0
1.0
0
−1.0
−2.0
−3.0
−4.0
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6
VO, OUTPUT VOLTAGE (V )
pp
Figure 4. Input Bias Current
versus Common Mode Voltage
Figure 5. Input Bias Current
versus Temperature
Figure 6. Input Common Mode Voltage
Range versus Temperature
Figure 7. Open Loop Voltage Gain
versus Temperature
Figure 8. Voltage Gain and Phase
versus Frequency
Figure 9. Output Voltage Swing
versus Supply Voltage
I, INPUT BIAS CURRENT (nA)
IB
VCM, COMMON MODE VOLTAGE (V)
−15 −10 −5.0 0 5.0 10 15
VCC = +15 V
VEE = −15 V
TA = 25°C
TA, AMBIENT TEMPERATURE (°C)
−55 −25 0 25 50 75 100 125
VCC = +15 V
VEE = −15 V
VCM = 0 V
, INPUT COMMON MODE VOLTAGE RANGE (V)
ICR
TA, AMBIENT TEMPERATURE (°C)
−55 −25 0 25 50 75 100 125
VCC = +5.0 V to +18 V
VEE = −5.0 V to −18 V
DVIO = 5.0 mV
TA, AMBIENT TEMPERATURE (°C)
VOL, OPEN LOOP VOLTAGE GAIN (kV/V)
−55 −25 0 25 50 75 100 12
5
VCC = +15 V
VEE = −15 V
f = 10 Hz
DVO = 10 V to +10 V
RL = 600 W
f, FREQUENCY (Hz)
VOL
A , OPEN LOOP VOLTAGE GAIN (dB)
, EXCESS PHASE (DEGREES)
2 345678910 20
80
100
120
140
160
180
200
220
240
260
280
φ
1A) Phase (RL = 600 W)
2A) Phase (RL = 600 W, CL = 300 pF)
1B) Gain (RL = 600 W)
2B) Gain (RL = 600 W, CL = 300 pF)
VCC = +15 V
VEE = −15 V
VO = 0 V
TA = 25°C
2B
1A
2A
1B
VCC, |VEE|, SUPPLY VOLTAGE (V)
0 5.0 10 15 20
TA = 25°C
RL = 10 kW
RL = 600 W
I, INPUT BIAS CURRENT (nA)
IB
V
A
160
140
120
100
80
60
40
20
0
120
110
100
90
80
70
60
VCC
VCC −0.5 V
VCC −1.0 V
VCC −1.5 V
VCC −2.0 V
VEE +1.0 V
VEE +0.5 V
VEE
250
200
150
100
50
0
50
40
30
20
10
0
−10
−20
−30
−40
−50
40
35
30
25
20
15
10
5.0
0
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7
VO, OUTPUT VOLTAGE (V )
pp
Source
Sink VCC = +15 V
VEE = −15 V
VID = ±1.0 V
RL < 10 W
TA = −55° to +125°C
VCC = +15 V
VEE = −15 V
DVCC = ±1.5 V
−PSR
+PSR
−
+
DVO
ADM
PSR = 20 Log
VCC
VEE
DVO/ADM
DVCC
Figure 10. Output Saturation Voltage
versus Load Current
Figure 11. Output Voltage
versus Frequency
Figure 12. Common Mode Rejection
versus Frequency Over Temperature
Figure 13. Power Supply Rejection
versus Frequency Over Temperature
Figure 14. Output Short Circuit Current
versus Output Voltage
Figure 15. Output Short Circuit Current
versus Temperature
Vsat
IL, LOAD CURRENT (±mA)
0 5.0 10 15 20
VCC = +5.0 V to +18 V
VEE = −5.0 V to −18 V
TA = +125°C
TA = −55°C
Source
Sink
TA = −55°C
f, FREQUENCY (Hz)
1.0 k 10 k 100 k 1.0 M
VCC = +15 V
VEE = −15 V
RL = 600 W
AV = +1.0 V
THD = ≤1.0%
TA = 25°C
f, FREQUENCY (Hz)
CMR, COMMON MODE REJECTION (dB)
10 100 1.0 k 10 k 100 k 1.0 M
VCC = +15 V
VEE = −15 V
VCM = 0 V
DVCM = ±1.5 V
TA = −55° to +125°C
PSR, POWER SUPPLY REJECTION (dB)
f, FREQUENCY (Hz)
10 100 1.0 k 10 k 100 k 1.0 M
I, OUTPUT SHORT CIRCUIT CURRENT (mA)
SC
−15 −9.0 −3.0 0 3.0 9.0 15
Source
Sink
VCC = +15 V
VEE = −15 V
VID = ±1.0 V
I, OUTPUT SHORT CIRCUIT CURRENT (mA)
SC
TA, AMBIENT TEMPERATURE (°C)
−55 −25 0 25 50 75 100 125
, OUTPUT SATURATION VOLTAGE (V)
TA = +125°C
VO, OUTPUT VOLTAGE (V)
VCC
VCC −1.0 V
VCC −2.0 V
VEE +2.0 V
VEE +1.0 V
VEE
28
24
20
16
8.0
4.0
0
12
120
100
80
60
40
20
0
120
100
80
60
40
20
0
100
80
60
40
20
0
100
90
80
70
60
50
CMR = 20 Log
−
+
DVCM DVO
x ADM
ADM
DVCM
DVO
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8
2B
1A
1B 2A
1A) Phase VCC =18 V, VEE = −18 V
2A) Phase VCC 1.5 V, VEE = −1.5 V
1B) Gain VCC = 18 V, VEE = −18 V
2B) Gain VCC = 1.5 V, VEE = −1.5 V
TA = 25°C
RL = ∞
CL = 0 pF
TA = +125°C
TA = +25°C
TA = −55°C
I , SUPPLY CURRENT/AMPLIFIER ( A)
Figure 16. Supply Current versus Supply
Voltage with No Load
Figure 17. Normalized Slew Rate
versus Temperature
Figure 18. Gain Bandwidth Product
versus Temperature
Figure 19. Voltage Gain and Phase
versus Frequency
Figure 20. Voltage Gain and Phase
versus Frequency
Figure 21. Open Loop Gain Margin
versus Temperature
VCC, |VEE| , SUPPLY VOLTAGE (V)
CC μ
0 2.0 4.0 6.0 8.0 10 12 14 16 18
TA, AMBIENT TEMPERATURE (°C)
SR, SLEW RATE (NORMALIZED)
−55 −25 0 25 50 75 100 125
VCC = +15 V
VEE = −15 V
DVin = 20 Vpp
TA, AMBIENT TEMPERATURE (°C)
GBW, GAIN BANDWIDTH PRODUCT (MHz)
−55 −25 0 25 50 75 100 125
VCC = +15 V
VEE = −15 V
f = 100 kHz
RL = 600 W
CL = 0 pF
f, FREQUENCY (Hz)
A , VOLTAGE GAIN (dB)
V
, EXCESS PHASE (DEGREES)
100 k
φ
1.0 M 10 M 100 M
Gain
Phase
VCC = +15 V
VEE = −15 V
RL = 600 W
TA = 25°C
CL = 0 pF
f, FREQUENCY (Hz)
A, V
O
LTA
G
E
G
AIN (dB)
V
, PHASE (DEGREES)
100 k
φ
1.0 M 10 M 100 M
TA, AMBIENT TEMPERATURE (°C)
A , OPEN LOOP GAIN MARGIN (dB)
m
−55 −25 0 25 50 75 100 125
VCC = +15 V
VEE = −15 V
RL = 600 W
CL = 10 pF
CL = 100 pF
CL = 300 pF
625
500
375
250
125
0
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
0.75
10
8.0
6.0
4.0
2.0
0
50
40
30
20
10
0
−10
−20
−30
−40
−50
50
40
30
20
10
0
−10
−20
−30
−40
−50
15
12
9.0
6.0
3.0
0
VO
100 pF
600 W
−
+
DVin
80
100
120
140
160
180
200
220
240
260
280
80
100
120
140
160
180
200
220
240
260
280
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9
VCC = +15 V VO = 2.0 Vpp
VEE = −15 V TA = 25°C
RL = 600 WAV = 1000
AV = 100
AV = 10 AV = 1.0
Figure 22. Phase Margin
versus Temperature
Figure 23. Phase Margin and Gain Margin
versus Differential Source Resistance
Figure 24. Open Loop Gain Margin and Phase
Margin versus Output Load Capacitance
Figure 25. Channel Separation
versus Frequency
Figure 26. Total Harmonic Distortion
versus Frequency
Figure 27. Output Impedance
versus Frequency
φm
VCC = +15 V
VEE = −15 V
RL = 600 W
CL = 10 pF
CL = 100 pF
CL = 300 pF
TA, AMBIENT TEMPERATURE (°C)
−55 −25 0 25 50 75 100 125
, PHASE MARGIN (DEGREES)
RT, DIFFERENTIAL SOURCE RESISTANCE (W)
A, GAIN MARGIN (dB)
m
100 1.0 k 10 k 100 k
m
φ, PHASE MARGIN (DEGREES)
Gain Margin
Phase Margin
VCC = +15 V
VEE = −15 V
RT = R1+R2
VO = 0 V
TA = 25°C
A, OPEN LOOP GAIN MARGIN (dB)
m
m
CL, OUTPUT LOAD CAPACITANCE (pF)
φ
10 100 1.0 k
, PHASE MARGIN (DEGREES)
Phase Margin
Gain Margin
VCC = +15 V
VEE = −15 V
VO = 0 V
f, FREQUENCY (Hz)
CS, CHANNEL SEPARATION (dB)
100 1.0 k 10 k 100 k 1.0 M
Drive Channel
VCC = +15 V
CEE = −15 V
RL = 600 W
TA = 25°C
f, FREQUENCY (Hz)
THD, TOTAL HARMONIC DISTORTION (%)
10 100 1.0 k 10 k 100 k
f, FREQUENCY (Hz)
|Z|, OUTPUT IMPEDANCE ()
OΩ
1.0 k 10 k 100 k 1.0 M 10 M
1. AV = 1.0
2. AV = 10
3. AV = 100
4. AV = 1000
VCC = +15 V
VEE = −15 V
VO = 0 V
TA = 25°C
3
4
21
60
50
40
30
20
10
0
12
10
8.0
6.0
4.0
2.0
0
18
15
12
9.0
6.0
3.0
0
150
140
130
120
110
100
10
1.0
0.1
0.01
500
400
300
200
100
0
60
50
40
30
20
10
0
60
50
40
30
0
10
20
Vin
R2
R1
VO
−
+
VO
600 W
−
+
Vin
CL
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10
Figure 28. Input Referred Noise Voltage
versus Frequency
Figure 29. Input Referred Noise Current
versus Frequency
Figure 30. Percent Overshoot versus
Load Capacitance
Figure 31. Non−inverting Amplifier Slew Rate
Figure 32. Small Signal Transient Response Figure 33. Large Signal Transient Response
t, TIME (2.0 ms/DIV)
t, TIME (5.0 ms/DIV)
VCC = +15 V
VEE = −15 V
AV = +1.0
RL = 600 W
CL = 100 pF
TA = 25°C
t, TIME (2.0 ns/DIV)
VO
f, FREQUENCY (Hz)
10 100 1.0 k 10 k 10 k
e, INPUT REFERRED NOISE VOLTAGE ()
nnV/ Hz√
VCC = +15 V
VEE = −15 V
TA = 25°C
f, FREQUENCY (Hz)
i, INPUT REFERRED NOISE CURRENT ()
n
10 100 1.0 k 10 k 100 k
VCC = +15 V
VEE = −15 V
TA = 25°C
pA/ Hz√
CL, LOAD CAPACITANCE (pF)
PERCENT OVERSHOOT (%)
10 100 1.0 k 10 k
VCC = +15 V
VEE = −15 V
TA = 25°C
RL = 600 W
RL = 2.0 kW
VCC = +15 V
VEE = −15 V
AV = +1.0
RL = 600 W
CL = 100 pF
TA = 25°C
VCC = +15 V
VEE = −15 V
AV = +1.0
RL = 600 W
CL = 100 pF
TA = 25°C
, OUTPUT VOLTAGE (50 mV/DIV)
VO, OUTPUT VOLTAGE (5.0 V/DIV) VO, OUTPUT VOLTAGE (5.0 V/DIV)
20
18
16
14
12
10
8.0
6.0
4.0
2.0
0
0.5
0.4
0.3
0.2
0.1
0
100
90
80
70
60
50
40
30
20
10
0
Input Noise Voltage Test
Circuit
+
VO
−VO
Input Noise Current Test Circuit
RS
(RS = 10 kW)
+
−
MC33178, MC33179
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11
10 k
A1
To
Receiver +
−
1.0 mF
300
200 k
120 k
2.0 k A2 820
1N4678
Tip
Phone Line
Ring
A3
VR
From
Microphone −
−
+
+
10 k
10 k
10 k
VR
10 k
0.05 mF
Figure 34. Telephone Line Interface Circuit
APPLICATION INFORMATION
This unique device uses a boosted output stage to combine
a high output current with a drain current lower than similar
bipolar input op amps. Its 60° phase margin and 15 dB gain
margin ensure stability with up to 1000 pF of load
capacitance (see Figure 24). The ability to drive a minimum
600 W load makes it particularly suitable for telecom
applications. Note that in the sample circuit in Figure 34
both A2 and A3 are driving equivalent loads of
approximately 600 W.
The low input offset voltage and moderately high slew
rate and gain bandwidth product make it attractive for a
variety of other applications. For example, although it is not
single supply (the common mode input range does not
include ground), it is specified at +5.0 V with a typical
common mode rejection of 110 dB. This makes it an
excellent choice for use with digital circuits. The high
common mode rejection, which is stable over temperature,
coupled with a low noise figure and low distortion, is an
ideal op amp for audio circuits.
The output stage of the op amp is current limited and
therefore has a certain amount of protection in the event of
a short circuit. However, because of its high current output,
it is especially important not to allow the device to exceed
the maximum junction temperature, particularly with the
MC33179 (quad op amp). Shorting more than one amplifier
could easily exceed the junction temperature to the extent of
causing permanent damage.
Stability
As usual with most high frequency amplifiers, proper lead
dress, component placement, and PC board layout should be
exercised for optimum frequency performance. For
example, long unshielded input or output leads may result in
unwanted input/output coupling. In order to preserve the
relatively low input capacitance associated with these
amplifiers, resistors connected to the inputs should be
immediately adjacent to the input pin to minimize additional
stray input capacitance. This not only minimizes the input
pole frequency for optimum frequency response, but also
minimizes extraneous “pick up” at this node. Supplying
decoupling with adequate capacitance immediately adjacent
to the supply pin is also important, particularly over
temperature, since many types of decoupling capacitors
exhibit great impedance changes over temperature.
Additional stability problems can be caused by high load
capacitances and/or a high source resistance. Simple
compensation schemes can be used to alleviate these
effects.
MC33178, MC33179
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12
If a high source of resistance is used (R1 > 1.0 kW), a
compensation capacitor equal to or greater than the input
capacitance of the op amp (10 pF) placed across the
feedback resistor (see Figure 35) can be used to neutralize
that pole and prevent outer loop oscillation. Since the closed
loop transient response will be a function of that
capacitance, it is important to choose the optimum value for
that capacitor. This can be determined by the following
Equation:
(1)
CC+(1 )[R1ńR2])2 CL(ZOńR2)
where: ZO is the output impedance of the op amp.
For moderately high capacitive loads (500 pF < CL
< 1500 pF) the addition of a compensation resistor on the
order of 20 W between the output and the feedback loop will
help to decrease miller loop oscillation (see Figure 36). For
high capacitive loads (CL > 1500 pF), a combined
compensation scheme should be used (see Figure 37). Both
the compensation resistor and the compensation capacitor
affect the transient response and can be calculated for
optimum performance. The value of CC can be calculated
using Equation 1. The Equation to calculate RC is as follows:
(2)
RC+ZO R1ńR2
Figure 35. Compensation for
High Source Impedance
Figure 36. Compensation Circuit for
Moderate Capacitive Loads
Figure 37. Compensation Circuit for
High Capacitive Loads
R2
−
+
R1 ZL
CCR2
RC
CL
R1
−
+
R2
CC
RC
CL
R1
−
+
MC33178, MC33179
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13
PACKAGE DIMENSIONS
PDIP−8
P SUFFIX
CASE 626−05
ISSUE L
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
14
58
F
NOTE 2 −A−
−B−
−T−
SEATING
PLANE
H
J
G
DK
N
C
L
M
M
A
M
0.13 (0.005) B M
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A9.40 10.16 0.370 0.400
B6.10 6.60 0.240 0.260
C3.94 4.45 0.155 0.175
D0.38 0.51 0.015 0.020
F1.02 1.78 0.040 0.070
G2.54 BSC 0.100 BSC
H0.76 1.27 0.030 0.050
J0.20 0.30 0.008 0.012
K2.92 3.43 0.115 0.135
L7.62 BSC 0.300 BSC
M−−− 10 −−− 10
N0.76 1.01 0.030 0.040
__
MC33178, MC33179
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14
Micro8t
CASE 846A−02
ISSUE G
S
B
M
0.08 (0.003) A S
T
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED
0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. 846A−01 OBSOLETE, NEW STANDARD 846A−02.
b
e
PIN 1 ID
8 PL
0.038 (0.0015)
−T−
SEATING
PLANE
A
A1 cL
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
8X 8X
6X ǒmm
inchesǓ
SCALE 8:1
1.04
0.041
0.38
0.015
5.28
0.208
4.24
0.167
3.20
0.126
0.65
0.0256
DIM
A
MIN NOM MAX MIN
MILLIMETERS
−− −− 1.10 −−
INCHES
A1 0.05 0.08 0.15 0.002
b0.25 0.33 0.40 0.010
c0.13 0.18 0.23 0.005
D2.90 3.00 3.10 0.114
E2.90 3.00 3.10 0.114
e0.65 BSC
L0.40 0.55 0.70 0.016
−− 0.043
0.003 0.006
0.013 0.016
0.007 0.009
0.118 0.122
0.118 0.122
0.026 BSC
0.021 0.028
NOM MAX
4.75 4.90 5.05 0.187 0.193 0.199
HE
HE
DD
E
MC33178, MC33179
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15
SOIC−8 NB
CASE 751−07
ISSUE AH
SEATING
PLANE
1
4
58
N
J
X 45 _
K
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
BS
D
H
C
0.10 (0.004)
DIM
A
MIN MAX MIN MAX
INCHES
4.80 5.00 0.189 0.197
MILLIMETERS
B3.80 4.00 0.150 0.157
C1.35 1.75 0.053 0.069
D0.33 0.51 0.013 0.020
G1.27 BSC 0.050 BSC
H0.10 0.25 0.004 0.010
J0.19 0.25 0.007 0.010
K0.40 1.27 0.016 0.050
M0 8 0 8
N0.25 0.50 0.010 0.020
S5.80 6.20 0.228 0.244
−X−
−Y−
G
M
Y
M
0.25 (0.010)
−Z−
Y
M
0.25 (0.010) ZSXS
M
____
1.52
0.060
7.0
0.275
0.6
0.024
1.270
0.050
4.0
0.155
ǒmm
inchesǓ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
MC33178, MC33179
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16
PACKAGE DIMENSIONS
PDIP−14
CASE 646−06
ISSUE P
17
14 8
B
ADIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.715 0.770 18.16 19.56
B0.240 0.260 6.10 6.60
C0.145 0.185 3.69 4.69
D0.015 0.021 0.38 0.53
F0.040 0.070 1.02 1.78
G0.100 BSC 2.54 BSC
H0.052 0.095 1.32 2.41
J0.008 0.015 0.20 0.38
K0.115 0.135 2.92 3.43
L
M−−− 10 −−− 10
N0.015 0.039 0.38 1.01
__
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
F
HG D
K
C
SEATING
PLANE
N
−T−
14 PL
M
0.13 (0.005)
L
M
J0.290 0.310 7.37 7.87
MC33178, MC33179
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17
PACKAGE DIMENSIONS
SOIC−14
CASE 751A−03
ISSUE H
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
−A−
−B−
G
P7 PL
14 8
7
1
M
0.25 (0.010) B M
S
B
M
0.25 (0.010) A S
T
−T−
F
RX 45
SEATING
PLANE D14 PL K
C
J
M
_DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A8.55 8.75 0.337 0.344
B3.80 4.00 0.150 0.157
C1.35 1.75 0.054 0.068
D0.35 0.49 0.014 0.019
F0.40 1.25 0.016 0.049
G1.27 BSC 0.050 BSC
J0.19 0.25 0.008 0.009
K0.10 0.25 0.004 0.009
M0 7 0 7
P5.80 6.20 0.228 0.244
R0.25 0.50 0.010 0.019
__ __
7.04
14X
0.58
14X
1.52
1.27
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT*
7X
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
MC33178, MC33179
http://onsemi.com
18
PACKAGE DIMENSIONS
TSSOP−14
CASE 948G−01
ISSUE B
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A4.90 5.10 0.193 0.200
B4.30 4.50 0.169 0.177
C−−− 1.20 −−− 0.047
D0.05 0.15 0.002 0.006
F0.50 0.75 0.020 0.030
G0.65 BSC 0.026 BSC
H0.50 0.60 0.020 0.024
J0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L6.40 BSC 0.252 BSC
M0 8 0 8
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
____
S
U0.15 (0.006) T
2X L/2
S
U
M
0.10 (0.004) V S
T
L−U−
SEATING
PLANE
0.10 (0.004)
−T−
ÇÇÇ
ÇÇÇ
ÇÇÇ
SECTION N−N
DETAIL E
JJ1
K
K1
ÉÉÉ
ÉÉÉ
DETAIL E
F
M
−W−
0.25 (0.010)
8
14
7
1
PIN 1
IDENT.
H
G
A
D
C
B
S
U0.15 (0.006) T
−V−
14X REFK
N
N
7.06
14X
0.36 14X
1.26
0.65
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT*
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
MC33178, MC33179
http://onsemi.com
19
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
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