5962-85131073A - Intersil Corporation

FN3142.8

HI-506, HI-507, HI-508, HI-509

Single 16 and 8/Differential 8-Channel and

4-Channel CMOS Analog Multiplexers

The HI-506/HI-507 and HI-508/HI-509 monolithic CMOS

multiplexers each include an array of sixteen and eight

analog switches respectively, a digital decoder circuit for

channel selection, voltage reference for logic thresholds, and

an enable input for device selection when several

multiplexers are present. The Dielectric Isolation (DI)

process used in fabrication of these devices eliminates the

problem of latchup. DI also offers much lower substrate

leakage and parasitic capacitance than conventional junction

isolated CMOS (see Application Note AN520).

The switching threshold for e ach digital input is established by

an internal +5V reference, providi ng a guaran teed minimum

2.4V for logic “1” and maximum 0.8V for logic “0”. This allo ws

direct interface without pullup resistors to signals from most

logic families: CMOS, TTL, DTL and so me PMOS. For

protection against transient overvolt ag e, th e digit al inp ut s

include a series 200Ω resistor an d diode cla mp to each

supply.

The HI-506 is a single 16-channel, the HI-507 is an

8-channel differential, the HI-508 is a single 8- channel and

the HI-509 is a 4-channel differential multiplexer.

If input overvoltages are present, the HI-546/HI-547/HI-548/

HI-549 multiplexers are recommended.

Features

• Pb-Free Available (RoHS Compliant) (See Ordering Info)

• Low ON Resistance . . . . . . . . . . . . . . . . . . . . . . . . 180Ω

• Wide Analog Signal Range . . . . . . . . . . . . . . . . . . . . . ±15V

• TTL/CMOS Compatible

• Access Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250ns

• Maximum Power Supply . . . . . . . . . . . . . . . . . . . . . . 44V

• Break-Before-Make Switching

• No Latch-Up

• Replaces DG506A/DG506AA and DG5 07A/DG507AA

• Replaces DG508A/DG508AA and DG5 09A/DG509AA

• Pb-Free Available (RoHS Compliant)

Applications

• Data Acquisition Systems

• Precision Instrumentation

• Demultiplexing

• Selector Switch

Data Sheet October 30, 2007

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

2FN3142.8

October 30, 2007

Ordering Information

PART NUMBER PART MARKING TEMP.

RANGE (°C) PACKAGE PKG. DWG. #

HI1-0506-2 HI1-506-2 -55 to +125 28 Ld CERDIP F28.6

HI1-0506-5 HI1-506-5 0 to +75 28 Ld CERDIP F28.6

HI4P0506-5 HI4P 506-5 0 to +75 28 Ld PLCC N28.45

HI4P0506-5Z (Note 1) HI4P 506-5Z 0 to +75 28 Ld PLCC (Pb-free) N28.45

HI9P0506-5 HI9P506-5 0 to +75 28 Ld SOIC M28.3

HI9P0506-9 HI9P506-9 -40 to +85 28 Ld SOIC M28.3

HI9P0506-9Z (Note 1) HI9P506-9Z -40 to +85 28 Ld SOIC (Pb-free) M28.3

HI1-0507-2 HI1-507-2 -55 to +125 28 Ld CERDIP F28.6

HI3-0507-5 HI3-507-5 0 to +75 28 Ld PDIP E28.6

HI3-0507-5Z HI3-507-5Z 0 to +75 28 Ld PDIP (Note 3) (Pb-free) E28.6

HI1-0508-2 HI1-508-2 -55 to 125 16 Ld CERDIP F16.3

HI1-0508-5 HI1-508 0 to +75 16 Ld CERDIP F16.3

HI3-0508-5 HI3-508-5 0 to +75 16 Ld PDIP E16.3

HI3-0508-5Z (Note 1) HI3-508-5Z 0 to +75 16 Ld PDIP (Note 3) (Pb-free) E16.3

HI9P0508-5 HI9P508-5 0 to +75 16 Ld SOIC M16.15

HI9P0508-5Z (Notes 1, 2) HI9P508-5Z 0 to +75 16 Ld SOIC (Pb-free) M16.15

HI9P0508-9 HI9P508-9 -40 to +85 16 Ld SOIC M16.15

HI9P0508-9Z (Note 1) HI9P508-9Z -40 to +85 16 Ld SOIC (Pb-free) M16.15

HI1-0509-2 HI1-509-2 -55 to +125 16 Ld CERDIP F16.3

HI1-0509-4 HI1-509-4 -25 to +85 16 Ld CERDIP F16.3

HI1-0509-5 HI1-509-5 0 to +75 16 Ld CERDIP F16.3

HI3-0509-5 HI3-509-5 0 to +75 16 Ld PDIP E16.3

HI4P0509-5 HI4P 509-5 0 to +75 20 Ld PLCC N20.35

HI4P0509-5Z (Notes 1, 2) HI4P 509-5Z 0 to +75 20 Ld PLCC (Pb-free) N20.35

HI9P0509-5 HI9P 509-5 0 to +75 16 Ld SOIC M16.15

HI9P0509-5Z (Notes 1, 2) HI9P 509-5Z 0 to +75 16 Ld SOIC (Pb-free) M16.15

NOTES:

1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte

tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.

Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC

J STD-020.

2. Add “96” suffix for tape and reel. Please refer to TB347 for details on reel specifications.

3. Pb-free PDIPs can be used for through hole wave solder processing only . They are not intended for use in Reflow solder processing applications.

HI-506, HI-507, HI-508, HI-509

3FN3142.8

October 30, 2007

Pinouts HI-506 (CERDIP, SOIC)

TOP VIEW HI-506 (PLCC)

TOP VIEW

HI-507 (PDIP, CERDIP)

TOP VIEW HI-508 (PDIP, CERDIP, SOIC)

TOP VIEW

+VSUPPLY

IN 16

IN 15

IN 14

IN 13

IN 12

IN 11

IN 10

IN 9

GND

ADDRESS A3

OUT

IN 8

IN 7

IN 6

IN 5

IN 3

IN 1

ENABLE

ADDRESS A0

ADDRESS A1

ADDRESS A2

-VSUPPLY

IN 4

IN 2

IN 15

IN 14

IN 13

IN 12

IN 11

IN 10

IN 9

IN 16

+VSUPPLY

OUT

-VSUPPLY

IN 8

GND

ENABLE

IN 7

IN 6

IN 5

IN 4

IN 3

IN 2

IN 1

14 15 16 17 1812 13

3214282726

+VSUPPLY

OUT B

IN 8B

IN 7B

IN 6B

IN 5B

IN 4B

IN 3B

IN 2B

IN 1B

GND

OUT A

IN 8A

IN 7A

IN 6A

IN 5A

IN 3A

IN 1A

ENABLE

ADDRESS A0

ADDRESS A1

ADDRESS A2

-VSUPPLY

IN 4A

IN 2A

ENABLE

-VSUPPLY

IN 1

IN 2

IN 3

OUT

IN 4

GND

+VSUPPLY

IN 5

IN 6

IN 7

IN 8

HI-506, HI-507, HI-508, HI-509

4FN3142.8

October 30, 2007

HI-509 (PDIP, CERDIP, SOIC)

TOP VIEW HI-509 (PLCC)

TOP VIEW

Pinouts (Continued)

ENABLE

-VSUPPLY

IN 1A

IN 2A

IN 3A

OUT A

IN 4A

+VSUPPLY

IN 1B

IN 2B

IN 3B

IN 4B

OUT B

GND

-VSUPPLY

IN 1A

IN 2A

IN 3A

ENABLE

GND

IN 4A

OUT A

OUT B

IN 4B

+VSUPPLY

IN 1B

IN 2B

IN 3B

10 11 12 139

3212019

HI-506, HI-507, HI-508, HI-509

5FN3142.8

October 30, 2007

Truth Tables

HI-506

A3A2A1A0EN “ON” CHANNEL

XXXXL None

LLLLH 1

LLLHH 2

LLHLH 3

LLHHH 4

LHLLH 5

LHLHH 6

LHHLH 7

LHHHH 8

HLLLH 9

HLLHH 10

HLHLH 11

HLHHH 12

HHLLH 13

HHLHH 14

HHHLH 15

HHHHH 16

HI-507

A2A1A0EN “ON” CHANNEL

X X X L None

LLLH 1

LLHH 2

LHLH 3

LHHH 4

HLLH 5

HLHH 6

HHLH 7

HHHH 8

HI-508

A2A1A0EN “ON” CHANNEL

X X X L None

LLLH 1

LLHH 2

LHLH 3

LHHH 4

HLLH 5

HLHH 6

HHLH 7

HHHH 8

HI-509

A1A0EN “ON” CHANNEL PAIR

X X L None

LLH 1

LHH 2

HLH 3

HHH 4

HI-506, HI-507, HI-508, HI-509

6FN3142.8

October 30, 2007

Functional Diagrams

HI-506 HI-507

HI-508 HI-509

DECODER/

DRIVER

† † † †

OUT

IN 1

IN 2

IN 16

† DIGITAL

PROTECTION

A0A1A2A3

†

INPUT

LEVEL

SHIFT

REF

DECODER/

DRIVER

†††

OUT B

IN 8A

IN 1A

IN 1B

† DIGITAL

PROTECTION

A0A1A2

†

INPUT

LEVEL

SHIFT

REF

OUT A

IN 8B

DECODER/

DRIVER

†††

OUT

IN 1

IN 2

IN 8

† DIGITAL

PROTECTION

A0A1A2

†

INPUT

LEVEL

SHIFT

REF

DECODER/

DRIVER

† †

OUT B

IN 4A

IN 1A

IN 1B

† DIGITAL

PROTECTION

A0A1

†

INPUT

LEVEL

SHIFT

REF

OUT A

IN 4B

HI-506, HI-507, HI-508, HI-509

7FN3142.8

October 30, 2007

Schematic Diagrams ADDRESS DECODER

ADDRESS INPUT BUFFER LEVEL SHIFTER

TTL REFERENCE CIRCUIT MULTIPLEX SWITCH

A0 OR A0

TO N-CHANNEL

DEVICE OF

THE SWITCH

A1 OR A1

A2 OR A2

A3 OR A3

ENABLE

PP PP P P

V+

V-

TO P-CHANNEL

DEVICE OF

THE SWITCH

DELETE A3 OR A3 INPUT FOR HI-507, HI-508, HI-509

DELETE A2 OR A2 INPUT FOR HI-509

V+

200Ω

AIN

ALL N-CHANNEL BODIES TO V-

ALL P-CHANNEL BODIES TO V+

UNLESS OTHERWISE INDICATED

V-

V+

P6 P7 P8 P9 P10

N6 N7 N8 N9 N10

Q9P

Q10N

N13 N14

P15 Q1P

N15

Q5N

Q11P

6.8k

P16

16.8k

Q12N

Q6N

Q2P

V+

Q3P Q4P

N12

Q7P

V- GND

Q8N

FROM DECODE

V+

N18

N19

P17

N17

V-

P18

OUT

FROM DECODE

HI-506, HI-507, HI-508, HI-509

8FN3142.8

October 30, 2007

Absolute Maximum Ratings Thermal Information

V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+44V

V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+22V

V- to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25V

Digital Input Voltage (VEN, VA) . . . . . (V-) -4V to (V+) +4V or 20mA,

Whichever Occurs First

Analog Signal (VIN, VOUT, Note 5) . . . . . . . . . . (V-) -2V to (V+) +2V

Continuous Current, In or Out . . . . . . . . . . . . . . . . . . . . . . . . . 20mA

Peak Current, In or Out (Pulsed 1ms, 10% Duty Cycle Max) . 40mA

Operating Conditions

Temperature Ranges

HI-50X-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C

HI-50X-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-25°C to +85°C

HI-50X-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +75°C

HI-50X-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C

Typical Minimum Supply Voltage. . . . . . . . . . . . ±10V or Single 20V

Thermal Resistance (Typical, Note 4) θJA (°C/W) θJC (°C/W)

16 Ld CERDIP Package. . . . . . . . . . . . 85 32

16 Ld SOIC Package . . . . . . . . . . . . . . 115 N/A

16 Ld PDIP Package . . . . . . . . . . . . . . 100 N/A

20 Ld PLCC Package. . . . . . . . . . . . . . 80 N/A

28 Ld CERDIP Package. . . . . . . . . . . . 55 18

28 Ld PDIP Package . . . . . . . . . . . . . . 60 N/A

28 Ld SOIC Package . . . . . . . . . . . . . . 70 N/A

28 Ld PLCC Package. . . . . . . . . . . . . . 70 N/A

Maximum Junction Temperature

Ceramic Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+175°C

Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C

Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C

Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and

result in failures not covered by warranty.

NOTE:

4. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

5. Signals on IN or OUT exceeding V+ or V- are clamped by internal diodes. Limit resulting current to maximum current ratings. If an overvoltage

condition is anticipated (analog input exceeds either power supply voltage), the Intersil HI-546/HI-547/H I -548/HI-549 multiplexers are

recommended.

Electrical Specifications Supplies = +15V, -15V; VAH (Logic Level High) = 2.4V; VAL (Logic Level Low) = 0.8V,

Unless Otherwise Specified. For Test Conditions, Consult Test Circuits Section

PARAMETER TEST

CONDITIONS TEMP

(°C)

-2 -4, -5, -9

UNITS

MIN

(Note 11) TYP MAX MIN

(Note 11) TYP MAX

DYNAMIC CHARACTERISTICS

Access Time, tA25 - 250 500 - 250 - ns

Full - - 1000 - - 1000 ns

Break-Before-Make Delay, tOPEN 25 25 80 - 25 80 - ns

Enable Delay (ON), tON(EN) 25 - 250 500 - 250 - ns

Full - - 1000 - - 1000 ns

Enable Delay (OFF), tOFF(EN) 25 - 250 500 - 250 - ns

Full - - 1000 - - 1000 ns

Settling Time, tS

(HI-506 and HI-507) To 0.1% 25 - 1.2 - - 1.2 - μs

To 0.01% 25 - 2.4 - - 2.4 - μs

Settling Time, tS

(HI-508 and HI-509) To 0.1% 25 - 360 - - 360 - ns

To 0.01% 25 - 600 - - 600 - ns

Off Isolation Note 9 25 - 68 - - 68 - dB

Channel Input Capacitance, CS(OFF) 25 -10- -10-pF

Channel Output Capacitance, CD(OFF)

HI-506 25 -52- -52-pF

HI-507 25 -30- -30-pF

HI-508 25 -17- -17-pF

HI-509 25 -12- -12-pF

Digital Input Capacitance, CA25 - 6 - - 6 - pF

Input to Output Capacitance, CDS(OFF) 25 -0.08- -0.08-pF

DIGITAL INPUT CHARACTERISTICS

Input Low Threshold, VAL Full - - 0.8 - - 0.8 V

Input High Threshold, VAH Full 2.4 - - 2.4 - - V

HI-506, HI-507, HI-508, HI-509

9FN3142.8

October 30, 2007

Input Leakage Current

(High or Low), IANote 8 Full - - 1.0 - - 1.0 μA

ANALOG CHANNEL CHARACTERISTICS

Analog Signal Range, VIN Full -15 - +15 -15 - +15 V

On Resistance, rON Note 6 25 - 180 300 - 180 400 Ω

ΔrON, (Any Two Channels)25-5--5-%

Off Input Leakage Current, IS(OFF) Note 7 25 - 0.03 - - 0.03 - nA

Full - - 50 - - 50 nA

Off Output L eakage Current ,

ID(OFF) Note 7 25 - 0.3 - - 0.3 - nA

HI-506 Full - - 300 - - 300 nA

HI-507 Full - - 200 - - 200 nA

HI-508 Full - - 200 - - 200 nA

HI-509 Full - - 100 - - 100 nA

On Channel Leakage Curre nt, ID(ON) Note 7 25 - 0.3 - - 0.3 - nA

HI-506 Full - - 300 - - 300 nA

HI-507 Full - - 200 - - 200 nA

HI-508 Full - - 200 - - 200 nA

HI-509 Full - - 100 - - 100 nA

Differential Of f Output Leakage Current, IDIFF

(HI-507, HI-509 Only) Full - - 50 - - 50 nA

POWER SUPPLY CHARACTERISTICS

Current, I+

HI-506/HI-507 Note 10 Full - 1.5 3.0 - 1.5 3.0 mA

HI-508/HI-509 Note 10 Full - 1.5 2.4 - 1.5 2.4 mA

Current, I-

HI-506/HI-507 Note 10 Full - 0.4 1.0 - 0.4 1.0 mA

HI-508/HI-509 Note 10 Full - 0.4 1.0 - 0.4 1.0 mA

Power Dissipation, PD

HI-506/HI-507 Full - - 60 - - 60 mW

HI-508/HI-509 Full - - 51 - - 51 mW

NOTES:

6. VOUT = ±10V, IOUT = +1mA.

7. 10nA is the practical lower limit for high speed measurement in the production test environment.

8. Digital input leakage is primarily due to the clamp diodes (see Schematic). Typical leakage is less than 1nA at +25°C.

9. VEN = 0.8V, RL = 1k, CL = 15pF, VS = 7VRMS, f = 100kHz.

10. VEN, VA = 0V or 2.4V.

11. Parts are 100% tested at +25°C. Over-tempe rature limits established by characterization and are not production tested.

Electrical Specifications Supplies = +15V, -15V; VAH (Logic Level High) = 2.4V; VAL (Logic Level Low) = 0.8V,

Unless Otherwise Specified. For Test Conditions, Consult Test Circuits Section (Continued)

PARAMETER TEST

CONDITIONS TEMP

(°C)

-2 -4, -5, -9

UNITS

MIN

(Note 11) TYP MAX MIN

(Note 11) TYP MAX

HI-506, HI-507, HI-508, HI-509

10 FN3142.8

October 30, 2007

T est Circuits and W aveforms TA = +25 °C, VSUPPLY = ±15 V, VAH = 2.4V, V AL = 0.8V, Unless Otherwise S pecified

FIGURE 1A. TEST CIRCUIT

FIGURE 1B. ON RESISTANCE vs ANALOG INPUT VOLTAGE FIGURE 1C. NORMALIZED ON RESIST ANCE vs SUPPL Y

VOLTAGE

FIGURE 1. ON RESISTANCE

FIGURE 2A. LEAKAGE CURRENT vs TEMPERATURE FIGURE 2B. ID(OFF) TEST C I RCUIT (NOTE 12)

1mA

OUTIN

VIN rON = V2

1mA

400

300

200

100

-15

ANALOG INPUT (V)

ON RESISTANCE (Ω)

-10 -5 0 5 10 15

+125°C

+25°C

-55°C

2.2

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

NORMALIZED RESISTANCE

(REFERRED TO VALUE AT ±15V)

10 11 12 13 14 15

SUPPLY VOLTAGE (±V)

-55°C TO + 125°C

VIN = 0V

100nA

10nA

1nA

100pA

10pA

LEAKAGE CURRENT

25 50 75 100 125

TEMPERATURE (°C)

OFF OUTPUT

LEAKAGE CURRENT

ID(OFF)

ID(ON)

OFF INPUT

LEAKAGE CURRENT

IS(OFF)

+10V

±10V

0.8V

OUT

ID(OFF)

HI-506, HI-507, HI-508, HI-509

11 FN3142.8

October 30, 2007

FIGURE 2C. IS(OFF) TEST CIRCUIT (NOTE 12) FIGURE 2D. ID(ON) TEST CIRCUIT (NOTE 12)

FIGURE 2. LEAKAGE CURRENTS

NOTE:

12. Two measurements per channel: ±10V and +10V. (Two measurements per device for ID(OFF) ±10V and +10V)

FIGURE 3A. ON CHANNEL CURRENT vs VOLTAGE FIGURE 3B. TEST CIRCUIT

FIGURE 3. ON CHANNEL CURRENT

FIGURE 4A. SUPPLY CURRENT vs TOGGLE FREQUENCY FIGURE 4B. TEST CIRCUIT

FIGURE 4. DYNAMIC SUPPLY CURRENT

T est Circuits and W aveforms TA = +25 °C, VSUPPLY = ±15 V, VAH = 2.4V, V AL = 0.8V, Unless Otherwise S pecified (Continued)

+10V

±10V

0.8V

OUT

IS(OFF)

OUT

ID(ON)

+10V ±10V

2.4V

A0A1

0024 6810121416

VOLTAGE ACROSS SWITCH (±V)

SWITCH CURRENT (mA)

-55°C

+25°C

+125°C

±VIN

TOGGLE FREQUENCY (Hz)

SUPPLY CURRENT (mA)

10k 100k 1M 10M

VSUPPLY = ±15V

VSUPPLY = ±10V

±10V/±5V

+15V/+10V

V+

V-

IN 1

IN 2

IN 8/16

OUT

10 14

MΩpF

50Ω

3.5V GND

-15V/-10V

A-ISUPPLY

+ISUPPLY

+10V/+5V

HIGH = 3.5V

LOW = 0V

50% DUTY CYCLE

THRU

IN 7/15

HI-506†

†Similar connection for HI-507/

HI-508/HI-509

HI-506, HI-507, HI-508, HI-509

12 FN3142.8

October 30, 2007

FIGURE 5A. ACCESS TIME vs LOGIC LEVEL (HIGH) FIGURE 5B. TEST CIRCUIT

FIGURE 5C. MEASUREMENT POINTS FIGURE 5D. WAVEFORMS

FIGURE 5. ACCESS TIME

FIGURE 6A. TEST CIRCUIT

T est Circuits and W aveforms TA = +25 °C, VSUPPLY = ±15 V, VAH = 2.4V, V AL = 0.8V, Unless Otherwise S pecified (Continued)

600

400

200

ACCESS TIME (ns)

LOGIC LEVEL (HIGH) (V)

345 151413

±10V

+15V

V+

V-

IN 1

IN 2 THRU

IN 16

OUT

10 50

kΩpF

50Ω

3.5V GND

-15V

+10V

IN 7/15

HI-506†

†Similar connection for HI-507/

HI-508/HI-509

50%

3.5V

10%

+10V

OUTPUT

-10V

ADDRESS

DRIVE (VA)

200ns/DIV.

S1 ON

S16 ON

VA INPUT

2V/DIV.

OUTPUT

5V/DIV.

+15V

V+

V-

IN 1

IN 2 THRU

IN 8 /16

OUT

50pF

200Ω

VOUT

-15V

50Ω

3.5V

GND

+5V

IN 7/IN 15

HI-506†

†Similar connection for HI-507/HI-508/HI-509

HI-506, HI-507, HI-508, HI-509

13 FN3142.8

October 30, 2007

FIGURE 6B. MEASUREMENT POINTS FIGURE 6C. WAVEFORMS

FIGURE 6. BREAK-BEFORE-MAKE DELAY

FIGURE 7A. TEST CIRCUIT

FIGURE 7B. MEASUREMENT POINTS FIGURE 7C. WAVEFORMS

FIGURE 7. ENABLE DELAYS

T est Circuits and W aveforms TA = +25 °C, VSUPPLY = ±15 V, VAH = 2.4V, V AL = 0.8V, Unless Otherwise S pecified (Continued)

50% 50%

3.5V

OUTPUT

ADDRESS

DRIVE (VA)

tOPEN

S1 ON S16 ON

VA INPUT

2V/DIV.

OUTPUT

1V/DIV.

100ns/DIV.

+15V

V+

V-

IN 1

IN 2 THRU

IN 8 /16

OUT

50pF

200Ω

VOUT

-15V

VAGND

+10V

IN 7/IN 15

HI-506†

†Similar connection for HI-507/HI-508/HI-509

50Ω

3.5V

OUTPUT

tOFF(EN)

ENABLE DRIVE (VA)

10%

50%

90%

tON(EN)

DISABLED

OUTPUT

2V/DIV.

ENABLE

DRIVE

2V/DIV.

ENABLED

(S1 ON)

100ns/DIV

HI-506, HI-507, HI-508, HI-509

14 FN3142.8

October 30, 2007

Typical Performance Curves TA = 25°C, VSUPPLY = ±15V, V AH = 2. 4V, V AL = 0.8 V, Unless Otherwise Specified

FIGURE 8. LOGIC THRESHOLD vs POWER SUPPLY VOLTAGE FIGURE 9. OFF ISOLATION vs FREQUENCY

FIGURE 10A. HI-506/HI-507 FIGURE 10B. HI-508/HI-509

FIGURE 10. POWER SUPPLY CURRENT vs TEMPERATURE

10 12 14 16 18 20

POWER SUPPLY VOLTAGE (±V)

INPUT LOGIC THRESHOLD (V)

100

104

(VS), (VD) OFF ISOLATION (dB)

105106107

FREQUENCY (Hz)

VEN = 0V

CLOAD = 28pF

VS = 7VRMS

RL = 1k

RL = 10M

POWER SUPPLY CURRENT (mA)

-55

TEMPERATURE (°C)

-35 -15 -5 4525 65 85 105 125

VEN = 2.4V

VEN = 0V

-55

POWER SUPPLY CURRENT (mA)

TEMPERATURE (°C)

-35 -15 -5 25 45 65 85 105 125

EN = 5V

EN = 0V

HI-506, HI-507, HI-508, HI-509

15 FN3142.8

October 30, 2007

Die Characteristics

METALLIZATION:

Type: CuAl

Thickness: 16kÅ ±2kÅ

SUBSTRATE POTENTIAL (NOTE):

-VSUPPLY

PASSIVATION:

Type : Nitride/Silox

Nitride Thickness: 3.5kÅ ±1kÅ

Silox Thickness: 12kÅ ±2kÅ

WORST CASE CURRENT DENSITY:

1.4 x 105 A/cm2

TRANSISTOR COUNT:

421

PROCESS:

CMOS-DI

NOTE: The substrate appears resistive to the -VSUPPLY terminal, therefore it may be left floating (Insulating Die Mount) or it may be mounted on a

conductor at -VSUPPLY potential.

Metallization Mask Layout

HI-506 HI-507

IN 16

IN 15

IN 14

IN 13

IN 12

IN 11

IN 10

IN 9

GND

OUT

IN 8

IN 7

IN 6

IN 5

IN 3

IN 1

EN A0A1A2

-V

IN 4

IN 2

IN 8B

IN 7B

IN 6B

IN 5B

IN 4B

IN 3B

IN 2B

IN 1B

GND

OUT B

OUT A

IN 8A

IN 7A

IN 6A

IN 5A

IN 3A

IN 1A

EN A0A1A2

-V

IN 4A

IN 2A

HI-506, HI-507, HI-508, HI-509

16 FN3142.8

October 30, 2007

Die Characteristics

METALLIZATION:

Type: CuAl

Thickness: 16kÅ ±2kÅ

SUBSTRATE POTENTIAL (NOTE):

-VSUPPLY

PASSIVATION:

Type : Nitride/Silox

Nitride Thickness: 3.5kÅ ±1kÅ

Silox Thickness: 12kÅ ±2kÅ

WORST CASE CURRENT DENSITY:

1.4 x 105 A/cm2

TRANSISTOR COUNT:

234

PROCESS:

CMOS-DI

NOTE: The substrate appears resistive to the -VSUPPLY terminal, therefore it may be left floating (Insulating Die Mount) or it may be mounted on a

conductor at -VSUPPLY potential.

Metallization Mask Layout

HI-508 HI-509

+VSUP

GND

OUT IN 8

IN 7

IN 6

IN 5

IN 3

IN 1

EN A0A1A2

-VSUP

IN 4

IN 2

+VSUP

GND

OUT A IN 4B

IN 3B

IN 2B

IN 1B

IN 3A

IN 1A

EN A0A1

-VSUP

IN 4A

IN 2A

OUT B

HI-506, HI-507, HI-508, HI-509

17 FN3142.8

October 30, 2007

HI-506, HI-507, HI-508, HI-509

Dual-In-Line Plastic Packages (PDIP)

NOTES:

1. Controlling Dimensions: INCH. In case of conflict between English and

Metric dimensions, the inch dimensions control.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of

Publication No. 95.

4. Dimensions A, A1 and L are measured with the package seated in JE-

DEC seating plane gauge GS-3.

5. D, D1, and E1 dimensions do not include mold flash or protrusions.

Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).

6. E and are measured with the leads constrained to be perpendic-

ular to datum .

7. eB and eC are measured at the lead tips with the leads unconstrained.

eC must be zero or greater.

8. B1 maximum dimensions do not include dambar protrusions. Dambar

protrusions shall not exceed 0.010 inch (0.25mm).

9. N is the maximum number of terminal positions.

10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,

E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).

-C-

-B-

INDEX 12 3 N/2

AREA

SEATING

BASE

PLANE

-C-

B1 Be

-A-

0.010 (0.25) C AMBS

E16.3 (JEDEC MS-001-BB ISSUE D)

16 LEAD DUAL-IN-LINE PLASTIC PACKAGE

SYMBOL

INCHES MILLIMETERS

NOTESMIN MAX MIN MAX

A-0.210 -5.33 4

A1 0.015 -0.39 -4

A2 0.115 0.195 2.93 4.95 -

B0.014 0.022 0.356 0.558 -

B1 0.045 0.070 1.15 1.77 8, 10

C0.008 0.014 0.204 0.355 -

D0.735 0.775 18.66 19.68 5

D1 0.005 -0.13 -5

E0.300 0.325 7.62 8.25 6

E1 0.240 0.280 6.10 7.11 5

e 0.100 BSC 2.54 BSC -

eA0.300 BSC 7.62 BSC 6

eB-0.430 -10.92 7

L0.115 0.150 2.93 3.81 4

N16 169

Rev. 0 12/93

18 FN3142.8

October 30, 2007

HI-506, HI-507, HI-508, HI-509

Dual-In-Line Plastic Packages (PDIP)

NOTES:

1. Controlling Dimensions: INCH. In case of conflict between English and

Metric dimensions, the inch dimensions control.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of

Publication No. 95.

4. Dimensions A, A1 and L are measured with the package seated in

JEDEC seating plane gauge GS-3.

5. D, D1, and E1 dimensions do not include mold flash or protrusions.

Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).

6. E and are measured with the leads constrained to be perpendic-

ular to datum .

7. eB and eC are measured at the lead tips with the leads unconstrained.

eC must be zero or greater.

8. B1 maximum dimensions do not include dambar protrusions. Dambar

protrusions shall not exceed 0.010 inch (0.25mm).

9. N is the maximum number of terminal positions.

10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,

E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).

-C-

-B-

INDEX 12 3 N/2

AREA

SEATING

BASE

PLANE

-C-

B1 Be

-A-

0.010 (0.25) C AMBS

E28.6 (JEDEC MS-011-AB ISSUE B)

28 LEAD DUAL-IN-LINE PLASTIC PACKAGE

SYMBOL

INCHES MILLIMETERS

NOTESMIN MAX MIN MAX

A-0.250 -6.35 4

A1 0.015 -0.39 -4

A2 0.125 0.195 3.18 4.95 -

B0.014 0.022 0.356 0.558 -

B1 0.030 0.070 0.77 1.77 8

C0.008 0.015 0.204 0.381 -

D1.380 1.565 35.1 39.7 5

D1 0.005 -0.13 -5

E0.600 0.625 15.24 15.87 6

E1 0.485 0.580 12.32 14.73 5

e 0.100 BSC 2.54 BSC -

eA0.600 BSC 15.24 BSC 6

eB-0.700 -17.78 7

L0.115 0.200 2.93 5.08 4

N28 289

Rev. 1 12/00

19 FN3142.8

October 30, 2007

HI-506, HI-507, HI-508, HI-509

Ceramic Dual-In-Line Frit Seal Packages (CERDIP)

NOTES:

1. Index area: A notch or a pin one identification mark shall be locat-

ed adjacent to pin one and shall be located within the shaded

area shown. The manufacturer’s identification shall not be used

as a pin one identification mark.

2. The maximum limits of lead dimensions b and c or M shall be

measured at the centroid of the finished lead surfaces, when

solder dip or tin plate lead finish is applied.

3. Dimensions b1 and c1 apply to lead base metal only . Dimension

M applies to lead plating and finish thickness.

4. Corner leads (1, N, N/2, and N/2+1) may be configured with a

partial lead paddle. For this configuration dimension b3 replaces

dimension b2.

5. This dimension allows for off-center lid, meniscus, and glass

overrun.

6. Dimension Q shall be measured from the seating plane to the

base plane.

7. Measure dimension S1 at all four corners.

8. N is the maximum number of terminal positions.

9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.

10. Controlling dimension: INCH.

bbb C A - B

SEATING

BASE

PLANE

-D-

-A-

-C-

-B-

b2 b

(c)

(b)

SECTION A-A

BASE

LEAD FINISH

METAL

eA/2

ccc C A - B

SSaaa CA - B

F16.3 MIL-STD-1835 GDIP1-T16 (D-2, CONFIGURATION A)

16 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE

SYMBOL

INCHES MILLIMETERS

NOTESMIN MAX MIN MAX

A-0.200 -5.08 -

b0.014 0.026 0.36 0.66 2

b1 0.014 0.023 0.36 0.58 3

b2 0.045 0.065 1.14 1.65 -

b3 0.023 0.045 0.58 1.14 4

c0.008 0.018 0.20 0.46 2

c1 0.008 0.015 0.20 0.38 3

D-0.840 -21.34 5

E0.220 0.310 5.59 7.87 5

e 0.100 BSC 2.54 BSC -

eA 0.300 BSC 7.62 BSC -

eA/2 0.150 BSC 3.81 BSC -

L0.125 0.200 3.18 5.08 -

Q0.015 0.060 0.38 1.52 6

S1 0.005 -0.13 -7

α90o105o90o105o-

aaa - 0.015 -0.38 -

bbb - 0.030 -0.76 -

ccc - 0.010 -0.25 -

M-0.0015 -0.038 2, 3

N16 168

Rev. 0 4/94

20 FN3142.8

October 30, 2007

HI-506, HI-507, HI-508, HI-509

Ceramic Dual-In-Line Frit Seal Packages (CERDIP)

NOTES:

1. Index area: A notch or a pin one identification mark shall be locat-

ed adjacent to pin one and shall be located within the shaded

area shown. The manufacturer’s identification shall not be used

as a pin one identification mark.

2. The maximum limits of lead dimensions b and c or M shall be

measured at the centroid of the finished lead surfaces, when

solder dip or tin plate lead finish is applied.

3. Dimensions b1 and c1 apply to lead base metal only . Dimension

M applies to lead plating and finish thickness.

4. Corner leads (1, N, N/2, and N/2+1) may be configured with a

partial lead paddle. For this configuration dimension b3 replaces

dimension b2.

5. This dimension allows for off-center lid, meniscus, and glass

overrun.

6. Dimension Q shall be measured from the seating plane to the

base plane.

7. Measure dimension S1 at all four corners.

8. N is the maximum number of terminal positions.

9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.

10. Controlling dimension: INCH.

bbb C A - B

SEATING

BASE

PLANE

-D-

-A-

-C-

-B-

b2 b

(c)

(b)

SECTION A-A

BASE

LEAD FINISH

METAL

eA/2

ccc C A - B

SSaaa CA - B

F28.6 MIL-STD-1835 GDIP1-T28 (D-10, CONFIGURATION A)

28 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE

SYMBOL

INCHES MILLIMETERS

NOTESMIN MAX MIN MAX

A-0.232 -5.92 -

b0.014 0.026 0.36 0.66 2

b1 0.014 0.023 0.36 0.58 3

b2 0.045 0.065 1.14 1.65 -

b3 0.023 0.045 0.58 1.14 4

c0.008 0.018 0.20 0.46 2

c1 0.008 0.015 0.20 0.38 3

D-1.490 -37.85 5

E0.500 0.610 12.70 15.49 5

e 0.100 BSC 2.54 BSC -

eA 0.600 BSC 15.24 BSC -

eA/2 0.300 BSC 7.62 BSC -

L0.125 0.200 3.18 5.08 -

Q0.015 0.060 0.38 1.52 6

S1 0.005 -0.13 -7

α90o105o90o105o-

aaa - 0.015 -0.38 -

bbb - 0.030 -0.76 -

ccc - 0.010 -0.25 -

M-0.0015 -0.038 2, 3

N28 288

Rev. 0 4/94

21 FN3142.8

October 30, 2007

HI-506, HI-507, HI-508, HI-509

Small Outline Plastic Packages (SOIC)

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of

Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.

Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006

inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Interlead

flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual index

feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above

the seating plane, shall not exceed a maximum value of 0.61mm

(0.024 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions are

not necessarily exact.

INDEX

AREA E

123

-B-

0.25(0.010) C AMBS

-A-

-C-

SEATING PLANE

0.10(0.004)

h x 45°

H0.25(0.010) BM M

M16.15 (JEDEC MS-012-AC ISSUE C)

16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

SYMBOL

INCHES MILLIMETERS

NOTESMIN MAX MIN MAX

A 0.0532 0.0688 1.35 1.75 -

A1 0.0040 0.0098 0.10 0.25 -

B 0.013 0.020 0.33 0.51 9

C 0.0075 0.0098 0.19 0.25 -

D 0.3859 0.3937 9.80 10.00 3

E 0.1497 0.1574 3.80 4.00 4

e 0.050 BSC 1.27 BSC -

H 0.2284 0.2440 5.80 6.20 -

h 0.0099 0.0196 0.25 0.50 5

L 0.016 0.050 0.40 1.27 6

N16 167

α0° 8° 0° 8° -

Rev. 1 6/05

22 FN3142.8

October 30, 2007

HI-506, HI-507, HI-508, HI-509

Small Outline Plastic Packages (SOIC)

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2

of Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate

burrs. Mold flash, protrusion and gate burrs shall not exceed

0.15mm (0.006 inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. In-

terlead flash and protrusions shall not exceed 0.25mm (0.010

inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual

index feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater

above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch)

10. Controlling dimension: MILLIMETER. Converted inch dimen-

sions are not necessarily exact.

INDEX

AREA

123

-B-

0.25(0.010) C AMBS

-A-

-C-

SEATING PLANE

0.10(0.004)

h x 45o

H0.25(0.010) BM M

M28.3 (JEDEC MS-013-AE ISSUE C)

28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE

SYMBOL

INCHES MILLIMETERS

NOTESMIN MAX MIN MAX

A 0.0926 0.1043 2.35 2.65 -

A1 0.0040 0.0118 0.10 0.30 -

B 0.013 0.0200 0.33 0.51 9

C 0.0091 0.0125 0.23 0.32 -

D 0.6969 0.7125 17.70 18.10 3

E 0.2914 0.2992 7.40 7.60 4

e 0.05 BSC 1.27 BSC -

H 0.394 0.419 10.00 10.65 -

h 0.01 0.029 0.25 0.75 5

L 0.016 0.050 0.40 1.27 6

N28 287

α0o8o0o8o-

Rev. 0 12/93

23 FN3142.8

October 30, 2007

HI-506, HI-507, HI-508, HI-509

Plastic Leaded Chip Carrier Packages (PLCC)

ASEATING

PLANE

0.020 (0.51)

MIN

VIEW “A”

D2/E2

0.025 (0.64)

0.045 (1.14) R

0.042 (1.07)

0.056 (1.42)

0.050 (1.27) TP

EE1

0.042 (1.07)

0.048 (1.22)

PIN (1) IDENTIFIER

0.020 (0.51) MAX

3 PLCS 0.026 (0.66)

0.032 (0.81)

0.045 (1.14)

MIN

0.013 (0.33)

0.021 (0.53)

0.025 (0.64)

MIN

VIEW “A” TYP.

0.004 (0.10) C

-C-

D2/E2

NOTES:

1. Controlling dimension: INCH. Converted millimeter dimensions are

not necessarily exact.

2. Dimensions and tolerancing per ANSI Y14.5M-1982.

3. Dimensions D1 and E1 do not include mold protrusions. Allowable

mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1

and E1 include mold mismatch and are measured at the extreme

material condition at the body parting line.

4. To be measured at seating plane contact point.

5. Centerline to be determined where center leads exit plastic body.

6. “N” is the number of terminal positions.

-C-

N20.35 (JEDEC MS-018AA ISSUE A)

20 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE

SYMBOL

INCHES MILLIMETERS

NOTESMIN MAX MIN MAX

A0.165 0.180 4.20 4.57 -

A1 0.090 0.120 2.29 3.04 -

D0.385 0.395 9.78 10.03 -

D1 0.350 0.356 8.89 9.04 3

D2 0.141 0.169 3.59 4.29 4, 5

E0.385 0.395 9.78 10.03 -

E1 0.350 0.356 8.89 9.04 3

E2 0.141 0.169 3.59 4.29 4, 5

N20 206

Rev. 2 11/97

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No lice nse is gran t ed by i mpli catio n or other wise u nder an y p a tent or patent rights of Inter si l or i t s sub sidi ari es.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN3142.8

October 30, 2007

HI-506, HI-507, HI-508, HI-509

Plastic Leaded Chip Carrier Packages (PLCC)

NOTES:

1. Controlling dimension: INCH. Converted millimeter dimensions are

not necessarily exact.

2. Dimensions and tolerancing per ANSI Y14.5M-1982.

3. Dimensions D1 and E1 do not include mold protrusions. Allowable

mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1

and E1 include mold mismatch and are measured at the extreme

material condition at the body parting line.

4. To be measured at seating plane contact point.

5. Centerline to be determined where center leads exit plastic body.

6. “N” is the number of terminal positions.

-C-

ASEATING

PLANE

0.020 (0.51)

MIN

VIEW “A”

D2/E2

0.025 (0.64)

0.045 (1.14) R

0.042 (1.07)

0.056 (1.42)

0.050 (1.27) TP

EE1

0.042 (1.07)

0.048 (1.22)

PIN (1) IDENTIFIER

0.020 (0.51) MAX

3 PLCS 0.026 (0.66)

0.032 (0.81)

0.045 (1.14)

MIN

0.013 (0.33)

0.021 (0.53)

0.025 (0.64)

MIN

VIEW “A” TYP.

0.004 (0.10) C

-C-

D2/E2

N28.45 (JEDEC MS-018AB ISSUE A)

28 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE

SYMBOL

INCHES MILLIMETERS

NOTESMIN MAX MIN MAX

A0.165 0.180 4.20 4.57 -

A1 0.090 0.120 2.29 3.04 -

D0.485 0.495 12.32 12.57 -

D1 0.450 0.456 11.43 11.58 3

D2 0.191 0.219 4.86 5.56 4, 5

E0.485 0.495 12.32 12.57 -

E1 0.450 0.456 11.43 11.58 3

E2 0.191 0.219 4.86 5.56 4, 5

N28 286

Rev. 2 11/97