FSTD16450GX - Fairchild Semiconductor

January 2001

Revised August 2001

FSTD16450 Configurable 4-Bit to 20-Bit Bus Switch with Selectable Level Shifting

FSTD16450

Configurable 4-Bit to 20-Bit Bus Switch

with Selectable Level Shifting

General Description

The Fairchild Universal Bus Switch FSTD16450 provides

4-bit, 5-bit, 8 -bit, 1 0-bi t, 16- bit, 20 -bit of hig h-spee d C MOS

TTL-compatible bus switching. The low on resistance of

the switch all ows inputs to be conn ecte d to ou tpu ts wi tho ut

adding propagation delay or generating additional ground

bounce noise.

The FSTD16450 is designed to allow “customer” configura-

tion contr ol of the ena ble connection s. The device is orga-

nized as either a 4-bit, 5 -bit, 10-b it or 20-b it bus swit ch. 8-

bit and 16-bit configurations are also achievable (see Func-

tional Descr ipti on ). T he d evice' s bi t con figur atio n i s chos en

through select pin logic. (see Truth Table). When OEx is

LOW, Port Ax is connected to Port Bx. When OEx is HIGH,

the switch is OPEN.

Another key device feature is the addition of a level shifting

select pin, “S2”. When S2 is LOW, the de vice be ha ves as a

standard N-M OS swi tch . When S2 is HIGH, a diod e to VCC

is integrated into the circuit allowing for level shifting

between 5V inputs and 3.3V outputs.

Features

■4Ω switch connection between two ports

■Voltage level shifting

■Minimal propagation delay through the switch

■Low lCC

■Zero bounce in flow-through mode

■Control inputs compatible with TTL level

■Also packaged in plastic Fine-Pitch Ball Grid Array

(FBGA) (Prelimi nary)

Applications Note

Select pins S0, S1, S2 are intended to be used as static

user configurable control pins. The AC performance of

these pi ns has no t be en cha racterized o r t este d. Switching

of these select pins during system operation may tempo-

rarily disrupt output logic states and/or enable pin controls.

Ordering Code:

Devices also available in Tape and R eel. Spe ci fy by append ing the suffix let t er “X” to the ordering code.

Note 1: BGA package available in Tape and Reel only.

UHC is a trademark of Fairchild Semiconductor Corporation.

Order Number Package Number Package Description

FSTD16450GX

(Note 1) BGA54A

(Preliminary) 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

[Tape and Reel]

FSTD16450MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

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FSTD16450

Connection Diagrams

Pin Assi gn m en ts for TS SO P

Pin Assignments for FBGA

(Top Thru View)

Pin Descriptions

FBGA Pin Assignments

Pin Name Description

OE1, OE2Bus Switch Enables

1A, 2A Bus A

1B, 2B Bus B

S0, S1Bit Configuration Enables

S2Level Shifting Diode Enable

123456

A1A31A2OE1OE21B21B3

B1A51A41A11B11B41B5

C1A71A6GND OE51B61B7

D1A91A8GND VCC 1B81B9

E2A11A10 S0VCC 1B10 2B1

F2A32A2S1S22B22B3

G2A52A4VCC GND 2B42B5

H2A72A62A10 2B10 2B62B7

J2A92A8OE4OE

32B82B9

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FSTD16450

Logic Diagrams

20-Bit Configuration

(Configuration 1)

5-Bit Configuration

(Configuration 3)

10-Bit Configuration

(Configuration 2)

4-Bit Configuration

(Configuration 4)

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FSTD16450

Functional Description

The device can also be configured as an 8 and 16-bit device by grounding the unused pins in Configurations 2 and 1

respectively. The 8-bit configuration may also be achieved by tying two of the 4-bit enables from configuration together and

tying the remai n ing ena bl e pin (OE ) HIGH.

Truth Tables (X = VCC or GND)

(see Functional Description) Select Pin

S2Mode

L Std. NMOS Switch

H Level Shifting Diode Enabled

Configuration 1 S0 = S1 = L 20-Bit Configuration

Inputs Inputs/Outputs

OE1OE2OE3OE4OE5

LXXXX 1A

1-10 = 1B1-10, 2A1-10 = 2B1-10

HXXXX Z

Configuration 2 S0 = L, S1 = H 10-Bit Configuration

Inputs Inputs/Outputs

OE1OE2OE3OE4OE51A1-10 = 1B1-10 2A1-10 = 2B1-10

LXXLX 1A

X = 1BX2AX = 2BX

LXXHX 1A

X = 1BXZ

HXXLX Z 2A

X = 2BX

HXXHX Z Z

Configuration 3 S0 = H, S1 = L 5-Bit Configuration

Inputs Inputs/Outputs

OE1OE2OE3OE4OE51A1-5, 1B1-5 1A6-10, 1B6-10 2A1-5, 2B1-5 2A6-10, 2B6-10

LLLLX1A

x = 1Bx1Ay = 1By2Ax = 2Bx2Ay = 2By

LLLHX1A

x = 1Bx1Ay = 1By2Ax = 2BxZ

LLHLX1A

x = 1Bx1Ay = 1ByZ2A

y = 2By

LLHHX1A

x = 1Bx1Ay = 1ByZZ

LHLLX1A

x = 1BxZ2A

x = 2Bx2Ay = 2By

LHLHX1A

x = 1BxZ2A

x = 2BxZ

LHHLX1A

x = 1BxZZ2A

y = 2By

LHHHX1A

x = 1BxZZZ

HLLLX Z 1A

y = 1By2Ax = 2Bx2Ay = 2By

HLLHX Z 1A

y = 1By2Ax = 2BxZ

HLHLX Z 1A

y = 1ByZ2A

y = 2By

HLHHX Z 1A

y = 1ByZZ

HHLLX Z Z 2A

x = 2Bx2Ay = 2By

HHLHX Z Z 2A

x = 2BxZ

HHHLX Z Z Z 2A

y = 2By

HHHHX Z Z Z Z

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FSTD16450

Truth Tables (Continued)

Configuration 4 S0 = S1 = H 4-Bit Configuration

Inputs Inputs/Outputs

OE1OE2OE3OE4OE51A1-4, 1B1-4 1A5-8, 1B5-8 2A3-6, 2B3-6 2A7-10, 2B7-10 1A9-10, 2B9-10

2A1-2, 2B1-2

LLLLL1A

x = 1Bx1Ay = 1By2Ax = 2Bx2Ay = 2By1Az = 1Bz

2Az = 2Bz

LLLLH1A

x = 1Bx1Ay = 1By2Ax = 2Bx2Ay = 2ByZ

LLLHL1A

x = 1Bx1Ay = 1By2Ax = 2BxZ1Az = 1Bz

2Az = 2Bz

LLLHH1A

x = 1Bx1Ay = 1By2Ax = 2BxZZ

LLHLL1A

x = 1Bx1Ay = 1ByZ2A

y = 2By1Az = 1Bz

2Az = 2Bz

LLHLH1A

x = 1Bx1Ay = 1ByZ2A

y = 2ByZ

LLHHL1A

x = 1Bx1Ay = 1ByZZ

1Az = 1Bz

2Az = 2Bz

LLHHH1A

x = 1Bx1Ay = 1ByZZZ

LHLLL1A

x = 1BxZ2A

x = 2Bx2Ay = 2By1Az = 1Bz

2Az = 2Bz

LHLLH1A

x = 1BxZ2A

x = 2Bx2Ay = 2ByZ

LHLHL1A

x = 1BxZ2A

x = 2BxZ1Az = 1Bz

2Az = 2Bz

LHLHH1A

x = 1BxZ2A

x = 2BxZZ

LHHLL1A

x = 1BxZZ2A

y = 2By1Az = 1Bz

2Az = 2Bz

LHHLH1A

x = 1BxZZ2A

y = 2ByZ

LHHHL1A

x = 1BxZZZ

1Az = 1Bz

2Az = 2Bz

LHHHH1A

x = 1BxZZZZ

HLLLL Z 1A

y = 1By2Ax = 2Bx2Ay = 2By1Az = 1Bz

2Az = 2Bz

HLLLH Z 1A

y = 1By2Ax = 2Bx2Ay = 2ByZ

HLLHL Z 1A

y = 1By2Ax = 2BxZ1Az = 1Bz

2Az = 2Bz

HLLHH Z 1A

y = 1By2Ax = 2BxZZ

HLHLL Z 1A

y = 1ByZ2A

y = 2By1Az = 1Bz

2Az = 2Bz

HLHLH Z 1A

y = 1ByZ2A

y = 2ByZ

HLHHL Z 1A

y = 1ByZZ

1Az = 1Bz

2Az = 2Bz

HLHHH Z 1A

y = 1ByZZZ

HHLLL Z Z 2A

x = 2Bx2Ay = 2By1Az = 1Bz

2Az = 2Bz

HHLLH Z Z 2A

x = 2Bx2Ay = 2ByZ

HHLHL Z Z 2A

x = 2BxZ1Az = 1Bz

2Az = 2Bz

HHLHH Z Z 2A

x = 2BxZZ

HHHLL Z Z Z 2A

y = 2By1Az = 1Bz

2Az = 2Bz

HHHLH Z Z Z 2A

y = 2ByZ

HHHHL Z Z Z Z 1Az = 1Bz

2Az = 2Bz

HHHHH Z Z Z Z Z

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FSTD16450

Absolute Maximum Ratings(Note 2) Recommended Operating

Conditions (Note 5)

Note 2: The “Absolute Maximum Ratings” are thos e values bey ond which

the saf ety of the device cannot be gu aranteed. Th e device shoul d not be

operated at these limits. The parametric values defined in the Electrical

Characteristics tables are not guaranteed at the absolute maximum rating.

The “R ecomm ended Oper ating Co ndition s” table will def ine the condit ions

for actu al device operation.

Note 3: VS is the voltage observed/applied at either the A or B Ports across

the switch.

Note 4: The inpu t and outpu t negati ve voltag e ratings m ay be ex ceede d if

the input and output diode current ratings are observed.

Note 5: Unused control inputs must be held HIGH or LOW. They may not

float.

DC Electrical Characteristics

Note 6: Typ ical values ar e at VCC = 5.0V and TA = +25°C

Note 7: Measured by the v olt age drop between A and B pins at th e indica te d c urrent thro ugh the swit c h. On Res is t ance is de te rm ined by th e lower of the

voltages on the two (A or B) pi ns .

Supply Voltage (VCC)−0.5V to +7.0V

DC Switch Voltage (VS) (Note 3) −0.5V to +7.0V

DC Input Control Pin Voltag e

(VIN) (Note 4) −0.5V to +7.0V

DC Input Diode Current (lIK) VIN < 0V −50 mA

DC Output (IOUT) Current 128 mA

DC VCC/GND Current (ICC/IGND)+/− 100 mA

Storage Temperature Range (TSTG)−65°C to +150 °C

Power Supply Operating (VCC) 4.0V to 5.5V

Input Voltage (VIN)0V to 5.5V

Output Voltage (VOUT)0V to 5.5V

Free Air Operating Temperature (TA)-40 °C to +85 °C

Symbol Parameter VCC TA = −40 °C to +85 °CUnits Conditions

(V) Min Typ

(Note 6) Max

VIK Clamp Diode Voltage 4.5 −1.2 V IIN = −18 mA

VIH HIGH Level Input V oltag e 4.0-5.5 2.0 V IF S2 = HIGH 4.5V ≤ VCC ≤ 5.5V

VIL LOW Level Input Voltage 4.0-5.5 0.8 V IF S2 = HIGH 4.5V ≤ VCC ≤ 5.5V

VOH HIGH Level Output Voltage 4.5-5.5 See Figure 3 V S2 = VCC

IIInput Leakage Current 5.5 ±1.0 µA0 ≤ VIN ≤ 5.5V

010µAV

IN = 5.5 V

IOZ OFF-STA T E Leakag e Current 5.5 ±1.0 µA0 ≤ A, B ≤ VCC

RON Switch On Resistance 4.5 4 7 ΩVIN = 0V, IIN = 64 mA, S2 = 0V or VCC

(Note 7) 4.5 4 7 ΩVIN = 0V, IIN = 30 mA, S2 = 0V or VCC

4.5 8 12 ΩVIN = 2.4V, IIN = 15 mA, S2 = 0V

4.0 11 20 ΩVIN = 2.4V, IIN = 15 mA, S2 = 0V

4.5 35 50 ΩVIN = 2.4V, IIN = 15 mA, S2 = VCC

ICC Quiescent Supply Current

5.5

3µAS

2 = GND, VIN = VCC or GND, IOUT = 0

10 µAS

2 = VCC, OEx = VCC, VIN = VCC or GND, IOUT = 0

1.5 mA S2 = VCC, OEx = GND, VIN = VCC or GND, IOUT = 0

∆ ICC Increase in ICC per Input

5.5 2.5 mA One Input at 3.4V

Other Inputs at VCC or GND, S2 = 0V

4.0 mA One Input at 3.4V

Other Inputs at VCC or GND, S2 = VCC

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FSTD16450

AC Electrical Characteristics

Note 8: T his parameter is gu aranteed by de s ign but is not te s t ed. The bus switch con t ribut es no pro pagation delay ot her tha n t he RC dela y of the typica l On

Resistance of th e s w it c h and the 50pF load capacit ance, when driven by an ideal v oltage so urc e (zero out put impedance).

AC Electrical Characteristics: Translating Diode

Note 9: This parameter is guaranteed by design but is not tested. This bus switch contributes no propagation delay other than the RC delay of t he typical On

Resistance of th e s w it c h and the 50pF load capacit ance, when driven by an ideal v oltage so urc e (zero out put impedance).

Capacitance (Note 10)

Note 10: TA = +25°C, f = 1 MHz, Capacitance is characterized but not tested.

Symbol Parameter

TA = −40 °C to +85 °C,

Units

CL = 50pF, RU = RD = 500ΩConditions Figure

VCC = 4.5 – 5.5V VCC = 4.0V (S2 = 0V) Number

Min Max Min Max

tPHL, tPLH Propagation Delay Bus-to-Bus

(Note 8) 0.25 0.25 ns VI = OPEN Figures

1, 2

tPZH, tPZL Output Enable Time 1.5 6.5 7.0 ns VI = 7V for tPZL Figures

1, 2

VI = OPEN for tPZH

tPHZ, tPLZ Output Disable Time 1.5 6.7 7.2 ns VI = 7V for tPLZ Figures

1, 2

VI = OPEN for tPHZ

tPZH, tPZL Sel (S0, 1) to Output Enable Time 1.5 7.0 7.5 ns VI = 7V for tPZL Figures

1, 2

VI = OPEN for tPZH

tPHZ, tPLZ Sel (S0, 1) to Output Disable Time 1.5 7.5 7.7 ns V I = 7V for tPLZ Figures

1, 2

VI = OPEN for tPHZ

Symbol Parameter

TA = −40 °C to +85 °C,

Units

CL = 50pF, RU = RD = 500ΩConditions Figure

VCC = 4.5 – 5.5V (S2 = VCC)Number

Min Max

tPHL, tPLH Propagation Delay Bus-to-Bus (Note 9) 0.25 ns VI = OPEN Figures

1, 2

tPZH, tPZL Output Enable Time 1.5 10.0 ns VI = 7V for tPZL Figures

1, 2

VI = OPEN for tPZH

tPHZ, tPLZ Output Disable Time 1.5 9.0 ns VI = 7V for tPLZ Figures

1, 2

VI = OPEN for tPHZ

tPZH, tPZL Sel (S0, 1) to Output Enable Time 1.5 11.0 ns VI = 7V for tPZL Figures

1, 2

VI = OPEN for tPZH

tPHZ, tPLZ Sel (S0, 1) to Output Disable Time 1.5 10.0 ns VI = 7V for tPLZ Figures

1, 2

VI = OPEN for tPHZ

Symbol Parameter Typ Max Units Conditions

CIN Control Pin Input Capacitance 4 pF VCC = 5.0V, VIN = 0V

CI/O Input/Output Capacitance “OFF State”8pFV

CC, OE = 5.0V, VIN = 0V

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FSTD16450

AC Loading and Waveforms

Note: Input driven by 50Ω source terminated in 50Ω

Note: CL includes load and stray capacitance

Note: Input Frequency = 1.0 MHz, tW = 500 ns

FIGURE 1. AC Test Circuit

FIGURE 2. AC Waveforms

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FSTD16450

FIGURE 3.

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FSTD16450

Physical Dimensions inches (millimeters) unless otherwise noted

54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

Packag e Num b er BGA5 4A

Preliminary

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FSTD16450 Configurable 4-Bit to 20-Bit Bus Switch with Selectable Level Shifting

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

56-Lea d Th in S hri n k Small Ou tlin e Pack age (TSSOP ), JED EC MO-1 53, 6.1mm Wide

Package Number MTD56

Technology Description

The Fairchild Switch family derives fro m and embodies Fairchild’s proven switch t echnology used for several years in its

74LVX3L384 (FST3384) bus switch product.

Fairchild does not assume an y responsibility fo r use of any circuitry described, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life suppor t de vices o r syst ems are dev ic es or syste ms

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instruct ions fo r use pr ovi de d in the l abe ling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A crit ical componen t in any com ponen t of a life s uppor t

device or system whose failure to perform can be rea-

sonabl y e xpec ted to cause th e fa i lure of the l ife s upport

device or system, or to affect its safety or effectiveness.