1. Product profile
1.1 General description
200 W LDMOS power tran sistor for avionics applications a t frequencies from 1030 MHz to
1090 MHz.
1.2 Features and benefits
Typical pulsed RF performance at frequencies from 1030 MHz to 1090 MHz, a supply
voltage of 28 V and an IDq of 100 mA:
Output power = 200 W
Power gain = 20 dB
Efficiency = 65 %
Easy power control
Integrated ESD protection
Enhanced ruggedness
High efficiency
Excellent thermal stability
Designed for broadband operation (1030 MHz to 1090 MHz)
Internally matched for ease of use
Compliant to Directive 2002/95/EC, rega rd in g Re stri ctio n of Hazard ou s Sub stances
(RoHS)
1.3 Applications
Avionics transmitter applications in the 1030 MHz to 1090 MHz frequency range.
BLA6G1011-200R;
BLA6G1011L(S)-200RG
Power LDMOS transistor
Rev. 4 — 9 November 2011 Product data sheet
Table 1. Test information
Typical RF performance at Tcase = 25
C.
Test signal f VDS PLGpDtrtf
(MHz) (V) (W) (dB) (%) (ns) (ns)
Typical RF performance in a class-AB production test circuit for SOT502A
pulsed RF 1030 to 1090 28 200 20 65 10 6
Typical RF performance in a Gullwing application for SOT502C and SOT502D
pulsed RF 1030 to 1090 28 200 20 65 15 6
BLA6G1011-200R_L-200RG_LS-200RG All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 4 — 9 November 2011 2 of 13
NXP Semiconductors BLA6G1011(L)(S)-200R(G)
Power LDMOS transistor
2. Pinning information
[1] Connected to flange.
3. Ordering information
4. Limiting values
Table 2. Pinning
Pin Description Simplified outline Graphic symbol
BLA6G1011-200R (SOT502A)
1drain
2gate
3source [1]
BLA6G1011L-200RG (SOT502D)
1drain
2gate
3source [1]
BLA6G1011LS-200RG (SOT502C)
1drain
2gate
3source [1]
3
2
1
sym112
1
3
2
2
13
sym112
1
3
2
2
3
1
sym112
1
3
2
Table 3. Ordering information
Type number Package
Name Description Version
BLA6G1011-200R - flanged LDMOST ceramic package; 2 mounting
holes; 2 leads SOT502A
BLA6G1011L-200RG - eared flanged LDMOST ceramic package; 2
mounting holes; 2 leads SOT502D
BLA6G1011LS-200RG - earless flanged LDMOST ceramic package; 2 leads SOT502C
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VDS drain-source voltage - 65 V
VGS gate-source voltage 0.5 +13 V
BLA6G1011-200R_L-200RG_LS-200RG All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 4 — 9 November 2011 3 of 13
NXP Semiconductors BLA6G1011(L)(S)-200R(G)
Power LDMOS transistor
5. Thermal characteristics
6. Characteristics
IDdrain current - 49 A
Tstg storage temperature 65 +150 C
Tjjunction temperature - 225 C
Table 4. Limiting values …con tinued
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
Table 5. Thermal characteristics
Symbol Parameter Conditions Type Typ Unit
Zth(j-c) transient thermal impedance
from junction to case Tcase =25C;
tp= 50 s;
=2%
BLA6G1011-200R 0.085 K/W
BLA6G1011L-200RG 0.065 K/W
BLA6G1011LS-200RG 0.065 K/W
Table 6. DC characteristics
Tj = 25
C unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
V(BR)DSS drain-source breakdown
voltage VGS =0V; I
D=0.9mA 65 - - V
VGS(th) gate-source threshold voltage VDS =10 V; I
D= 270 mA 1.4 2.0 2.4 V
VGSq gate-source quiescent voltage VDS =28 V;
ID= 1620 mA 1.7 2.2 2.7 V
IDSS drain leakage current VGS =0V; V
DS =28V - - 4.2 A
IDSX drain cut-off current VGS =V
GS(th) +3.75 V;
VDS =10V 40 48 - A
IGSS gate leakage current VGS =11V; V
DS = 0 V - - 420 nA
gfs forward transconductance VDS =10V; I
D=9.45A 11 18 26 S
RDS(on) drain-source on-state
resistance VGS =V
GS(th) + 3.75 V;
ID=9.45A 0.012 0.07 0.093
Crs feedback capacitance VGS =0V; V
DS =28V;
f= 1MHz -3-pF
Table 7. RF characteristics
Test signal: Pulsed RF; tp = 50
s;
= 2 %; VDS =28V; I
Dq = 100 mA; Tcase = 25
C; unless
otherwise specified; in a class-AB production test circuit for straight leads.
Symbol Parameter Conditions Min Typ Max Unit
PLoutput power 200 - - W
Gppower gain PL = 200 W 18 20 - dB
RLin input return loss PL = 200 W - 10 8dB
Ddrain efficiency PL = 200 W 58 65 - %
trrise time PL = 200 W - 10 20 ns
tffall time PL = 200 W - 6 20 ns
BLA6G1011-200R_L-200RG_LS-200RG All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 4 — 9 November 2011 4 of 13
NXP Semiconductors BLA6G1011(L)(S)-200R(G)
Power LDMOS transistor
6.1 Ruggedness in class-AB operation
The BLA6G1011-200R, BLA6G1011L-200RG and BLA6G1011LS-200RG are enhanced
rugged devices and are capable of withstanding a load mismatch corr esponding to
VSWR = 10 : 1 through all phases under the following conditions: tp=50s; =2%;
VDS =28V; I
Dq =100mA; P
L= 200 W; f = 1030 MHz to 1090 MHz.
7. Application information
7.1 Impedance information
Table 8. Typical impedance
Typical values unless otherwise specified.
f ZSZL
MHz
BLA6G1011-200R
1030 0.57 j0.94 0.80 j0.68
1060 0.70 j1.13 0.84 j0.52
1090 0.80 j1.53 0.86 j0.35
BLA6G1011L-200RG and BLA6G1011LS-200RG
1030 0.69 j2.18 0.84 j0.59
1060 0.86 j2.36 0.85 j0.73
1090 1.12 j2.54 0.86 j0.87
Fig 1. Definition of transis tor imp e danc e
001aaf059
drain
Z
L
Z
S
gate
BLA6G1011-200R_L-200RG_LS-200RG All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 4 — 9 November 2011 5 of 13
NXP Semiconductors BLA6G1011(L)(S)-200R(G)
Power LDMOS transistor
7.2 RF performance
VDS = 28 V; tp = 50 s; = 2 %; IDq = 100 mA.
(1) f = 1030 MHz
(2) f = 1060 MHz
(3) f = 1090 MHz
VDS = 28 V; tp = 50 s; = 2 %; IDq = 100 mA.
(1) f = 1030 MHz
(2) f = 1060 MHz
(3) f = 1090 MHz
Fig 2. Output power as a function of input power;
typical valu e s Fig 3. Power gain as a function of load power;
typical values
Pi (W)
04312
001aak266
100
150
50
200
250
PL
(W)
0
(1)
(2)
(3)
PL (W)
0 250200100 15050
001aak267
16
18
14
20
22
Gp
(dB)
12
(1)
(2)
(3)
VDS = 28 V; tp = 50 s; = 2 %; IDq = 100 mA.
(1) f = 1030 MHz
(2) f = 1060 MHz
(3) f = 1090 MHz
PL = 200 W; VDS = 28 V; tp = 50 s; = 2 %;
IDq = 100 mA.
Fig 4. Drain efficiency as a func tio n of load power;
typical values Fig 5. Power gain, input return loss and drain
efficiency as function of frequency;
typical values
PL (W)
0 250200100 15050
001aak268
ηD
(%)
40
20
60
70
30
10
50
0
(1)
(2)
(3)
f (MHz)
1020 110010801040 1060
001aak269
10
15
5
20
25
Gp
RLin
(dB)
0
ηD
(%)
60
65
55
70
75
50
Gp
RLin
ηD
BLA6G1011-200R_L-200RG_LS-200RG All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 4 — 9 November 2011 6 of 13
NXP Semiconductors BLA6G1011(L)(S)-200R(G)
Power LDMOS transistor
7.3 Application circuit
Remark: For BLA6G1011-200R with straight leads
[1] American Technical Ceramics type 100A or capacitor of same quality.
[2] American Technical Ceramics type 100B or capacitor of same quality.
See Table 9 for list of components.
Fig 6. Component layout for class-AB application circuit
C4
C8
C5
001aak270
C3
C2
C1
R1
C6 C7
+
Table 9. List of components
See Figure 6.
Striplines are on a Rogers Duroid 6010 Printed-Circuit Board (PCB);
r = 6.15 F/m;
thickness = 0.64 mm
Component Description Value Remarks
C1, C6 multilayer ceramic chip capacitor 10 FTDK
C2 multilayer ceramic chip capacitor 68 pF [1]
C3 multilayer ceramic chip capacitor 1.5 pF [1]
C4 multilayer ceramic chip capacitor 3.9 pF [1]
C5, C8 multilayer ceramic chip capacitor 30 pF [2]
C7 electrolytic capacitor 470 F; 63 V
R1 SMD resistor 12 1206
BLA6G1011-200R_L-200RG_LS-200RG All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 4 — 9 November 2011 7 of 13
NXP Semiconductors BLA6G1011(L)(S)-200R(G)
Power LDMOS transistor
8. Package outline
Fig 7. Package outline SOT502A
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT502A 99-12-28
03-01-10
0 5 10 mm
scale
Flanged LDMOST ceramic package; 2 mounting holes; 2 leads SOT502A
p
L
AF
b
D
U2
H
Q
c
1
3
2
D1
E
A
C
q
U1
C
B
E1
M M
w2
UNIT A
mm
Db
12.83
12.57 0.15
0.08 20.02
19.61 9.53
9.25 19.94
18.92 9.91
9.65
4.72
3.43
cU2
0.25 0.5127.94
qw
2
w1
F
1.14
0.89
U1
34.16
33.91
L
5.33
4.32
p
3.38
3.12
Q
1.70
1.45
EE
1
9.50
9.30
inches 0.505
0.495 0.006
0.003 0.788
0.772
D1
19.96
19.66
0.786
0.774 0.375
0.364 0.785
0.745 0.390
0.380
0.186
0.135 0.01 0.021.100
0.045
0.035 1.345
1.335
0.210
0.170 0.133
0.123 0.067
0.057
0.374
0.366
H
DIMENSIONS (millimetre dimensions are derived from the original inch dimensions)
w1AB
M M M
BLA6G1011-200R_L-200RG_LS-200RG All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 4 — 9 November 2011 8 of 13
NXP Semiconductors BLA6G1011(L)(S)-200R(G)
Power LDMOS transistor
Fig 8. Package outline SOT502C
References
Outline
version
European
projection Issue date
IEC JEDEC JEITA
SOT502C
sot502c_po
11-03-23
11-05-02
inches
max
nom
min
0.185
0.135
0.505
0.495
0.788
0.772
0.786
0.774
0.375
0.365
0.375
0.365
0.536
0.519
0.048
0.031
0.815
0.805
Note
1. Millimeter dimensions are derived from the original inch dimensions.
Earless flanged LDMOST ceramic package; 2 leads SOT502C
0.006
0.004
0.045
0.035
0.008
0.002
0.39
0.38
0.01 0.01
Unit(1)
mm
max
nom
min
4.72
3.43
12.83
12.57
20.02
19.61
19.96
19.66
9.53
9.27
9.53
9.27
13.6
13.2
1.2
0.8
20.70
20.45
A
1
2
3
Dimensions
bc
0.16
0.10
DD
1EE
1
θF
1.14
0.89
HL
pQ
0.195
0.055
U1U2
9.91
9.65
v
0.25
w2
0.25
0 5 10 mm
scale
detail X
0.4 mm
gauge plane
Lp
b
H
U1
U2
B
A
w2B
vA
A
D
D1
F
c
E
E1
θ
Q
X
BLA6G1011-200R_L-200RG_LS-200RG All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 4 — 9 November 2011 9 of 13
NXP Semiconductors BLA6G1011(L)(S)-200R(G)
Power LDMOS transistor
Fig 9. Package outline SOT502D
References
Outline
version
European
projection Issue date
IEC JEDEC JEITA
SOT502D
sot502d_po
11-03-23
11-05-02
inches
max
nom
min
0.185
0.135
0.505
0.495
0.788
0.772
0.786
0.774
0.375
0.365
0.375
0.365
0.536
0.519
0.048
0.031
1.345
1.335
Note
1. Millimeter dimensions are derived from the original inch dimensions.
Eared flanged LDMOST ceramic package; 2 leads; 2 mounting holes SOT502D
0.006
0.004
0.045
0.035
0.008
0.002
0.39
0.38
0.01 0.01
Unit(1)
mm
max
nom
min
4.72
3.43
12.83
12.57
20.02
19.61
19.96
19.66
9.53
9.27
9.53
9.27
13.6
13.2
1.2
0.8
34.16
33.91
A
1
2
3
Dimensions
bc
0.16
0.10
DD
1EE
1
θF
1.14
0.89
HL
p
0.133
0.123
3.38
3.12
pQ
0.195
0.055
1.1
q
27.94
U1U2
9.91
9.65
w1
0.25
0.01
v
0.25
w2
0.25
0 5 10 mm
scale
detail X
0.4 mm
gauge plane
Lp
c
E
E1
θ
Q
X
A
D
D1
F
q
b
p
H
U1
U2
B
A
w2B
w1A
vA
B
BLA6G1011-200R_L-200RG_LS-200RG All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 4 — 9 November 2011 10 of 13
NXP Semiconductors BLA6G1011(L)(S)-200R(G)
Power LDMOS transistor
9. Handling information
10. Abbreviations
11. Revision history
CAUTION
This device is sensitive to ElectroStatic Discharge (ESD). Observe precautions for handling
electrostatic sensitive devices.
Such precautions are described in the ANSI/ESD S20.20, IEC/ST 61340-5, JESD625-A or
equivalent standards.
Table 10. Abbreviations
Acronym Description
LDMOS Laterally Diffused Metal-Oxide Semiconductor
LDMOST Laterally Diffused Metal-Oxide Semiconductor Transistor
RF Radio Frequency
SMD Surface Mounted Device
VSWR Voltage Standing-Wave Ratio
Table 11. Revision history
Document ID Release date Data sheet status Change notice Supersedes
BLA6G1011-200R_L-200RG_LS-200RG V.4 20111109 Product data sheet BLA6G1011-200R v.3
Modifications: This document now also describes the products BLA6G1011L-200RG
and BLA6G1011LS-200RG.
BLA6G1011-200R v.3 20100714 Product data sheet - -
BLA6G1011-200R_L-200RG_LS-200RG All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 4 — 9 November 2011 11 o f 13
NXP Semiconductors BLA6G1011(L)(S)-200R(G)
Power LDMOS transistor
12. Legal information
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[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
12.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
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representations or warranties as to the accuracy or completeness of
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Short data sheet — A short dat a sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
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full data sheet shall pre vail.
Product specificatio nThe information and data provided in a Product
data sheet shall define the specification of the product as agreed be tween
NXP Semiconductors and its customer, unless NXP Semiconductors and
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Applications — Applications that are described herein for any of these
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Customers are responsible for the design and ope ration of their applications
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NXP Semiconductors does not accept any liability rela ted to any default,
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Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
the quality and reliability of the device.
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products are sold subject to the general terms and conditions of commercial
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Document status[1][2] Product status[3] Definition
Objective [short] data sheet D evelopment This document contain s data from the objective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] dat a sheet Production This document contains the product specification.
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Product data sheet Rev. 4 — 9 November 2011 12 of 13
NXP Semiconductors BLA6G1011(L)(S)-200R(G)
Power LDMOS transistor
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Notice: All refe renced brands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
13. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors BLA6G1011(L)(S)-200R(G)
Power LDMOS transistor
© NXP B.V. 2011. All rights reserved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 9 November 2011
Document identifier : BLA6G10 11- 2 00 R_ L-200RG_LS-200RG
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
14. Contents
1 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 General description . . . . . . . . . . . . . . . . . . . . . 1
1.2 Features and benefits. . . . . . . . . . . . . . . . . . . . 1
1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 Pinning information. . . . . . . . . . . . . . . . . . . . . . 2
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2
5 Thermal characteristics . . . . . . . . . . . . . . . . . . 3
6 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 3
6.1 Ruggedness in class-AB operation . . . . . . . . . 4
7 Application information. . . . . . . . . . . . . . . . . . . 4
7.1 Impedance information. . . . . . . . . . . . . . . . . . . 4
7.2 RF performance . . . . . . . . . . . . . . . . . . . . . . . . 5
7.3 Application circuit . . . . . . . . . . . . . . . . . . . . . . . 6
8 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 7
9 Handling information. . . . . . . . . . . . . . . . . . . . 10
10 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 10
11 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 10
12 Legal information. . . . . . . . . . . . . . . . . . . . . . . 11
12.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 11
12.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
12.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 11
12.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 12
13 Contact information. . . . . . . . . . . . . . . . . . . . . 12
14 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13