2014-2019 Microchip Technology Inc. DS20005287B-page 1
MCP3918
Features:
• One 24-Bit Resolution Delta-Sigma A/D Converter
• 93.5 dB SINAD, -107 dBc Total Harmonic
Distortion (THD) (up to 35th harmonic),
112 dB Spurious-Free Dynamic Range (SFDR)
• Flexible Serial Interface that Includes Both SPI
and a Simple 2-Wire Interface Ideal for Polyphase
Shunt Energy Meters
• Advanced Security Features:
- 16-Bit Cyclic Redundancy Check (CRC)
Checksum on All Communications for Secure
Data Transfers
- 16-Bit CRC Checksum and Interrupt Alert for
Register Map Configuration
- Register Map Lock with 8-Bit Secure Key
• 2.7V-3.6V AVDD, DVDD
• Programmable Data Rate, Up to 125 ksps:
- 4 MHz Maximum Sampling Frequency
- 16 MHz Maximum Master Clock
• Oversampling Ratio, Up to 4096
• Ultra Low-Power Shutdown Mode with < 10 µA
• Low-Drift 1.2V Internal Voltage Reference:
9 ppm/°C
• Differential Voltage Reference Input Pins
• High-Gain Programmable Gain Amplifier (PGA)
(up to 32 V/V)
• Phase Delay Compensation with 1 µs Time
Resolution
• Separate Data Ready Pin for Easy
Synchronization
• Individual 24-Bit Digital Offset and Gain Error
Correction
• High-Speed 20 MHz SPI Interface with Mode 0,0
and 1,1 Compatibility
• Continuous Read/Write Modes for Minimum
Communication with Dedicated 16-/32-Bit Modes
• Available in 20-Lead QFN and SSOP Packages
• Extended Temperature Range: -40°C to +125°C
(all specifications are valid down to -45°C)
Description:
The MCP3918 is a 3V single-channel Analog Front End
(AFE), containing one Delta-Sigma Analog-to-Digital
Converter (ADC), one Programmable Gain Amplifier
(PGA), phase delay compensation block, low-drift
internal voltage reference, digital offset and Gain Error
Calibration registers, and high-speed 20 MHz SPI
compatible serial interface.
The MCP3918 ADC is fully configurable with features
such as: 16-/24-bit resolution, Oversampling Ratio
(OSR) from 32 to 4096, gain from 1x to 32x, independent
shutdown and Reset, dithering and auto-zeroing.
Communication is largely simplified with 8-bit com-
mands, including various continuous Read/Write modes
and 16-/24-/32-bit data formats that can be accessed by
the Direct Memory Access (DMA) of an 8, 16 or 32-bit
MCU, and with the separate Data Ready pin that can
directly be connected to an Interrupt Request (IRQ) input
of an MCU.
The MCP3918 includes advanced security features to
secure the communications and the configuration set-
tings, such as a CRC-16 checksum on both serial data
outputs and on the register map static configuration. It
also includes a register map lock through an 8-bit
password to avoid the processing of any unwanted
WRITE commands.
For polyphase shunt-based energy meters, the
MCP3918 2-wire serial interface greatly reduces sys-
tem cost, requiring only a single bidirectional isolator
per phase.
The MCP3918 is capable of interfacing a variety of volt-
age and current sensors, including shunts, Current
Transformers (CTs), Rogowski coils and Hall effect
sensors.
Applications:
• Single-Phase and Polyphase Energy Meters
• Energy Metering and Power Measurement
• Automotive
• Portable Instrumentation
• Medical and Power Monitoring
• Audio/Voice Recognition
• Isolator Sensor Application
3V Single-Channel Analog Front End
MCP3918
DS20005287B-page 2 2014-2019 Microchip Technology Inc.
Package Type
Functional Block Diagram
OSC1/CLKI/GAIN0
1
2
3
4
20
19
18
17
16
15
14
13
5
6
7
8
OSC2/MODE
SDI/OSR1
RESET/OSR0
DVDD
AVDD
CH0+
CH0-
NC
12
9
DGND
MDAT0
NC
DR/GAIN1
NC
AGND
SDO
11
10
REFIN+/OUT
REFIN-
CS/BOOST
SCK/MCLK
SDO
2
NC
NC
CH0+ SCK/MCLK
CS/BOOST
REFIN+/OUT
OSC2/MODE
REFIN-
DGND
NC
OSC1/CLKI/
GAIN0
AVDD
DVDD
RESET/
OSR0
SDI/OSR1
CH0- EP
20
1
19 18 17
3
4
14
13
12
11
6789
21
5
10
15
16
AGND
MDAT0
DR/GAIN1
MCP3918
4x4QFN*
MCP3918
SSOP
* Includes Exposed Thermal Pad (EP); see Ta b l e 3 - 1 .
CH0+
CH0-
Single-Channel '6ADC
ANALOG DIGITAL
-
+
PGA '6
Modulator
AMCLK
DMCLK/DRCLK
DATA_CH0
<23:0>
REFIN+/OUT
REFIN-
AVDD
AGND DGND
DVDD
MOD<3:0>
POR
AVDD
Monitoring
Vref+Vref-
VREFEXT
Voltage
Reference
VREF
+
-
POR
DVDD
Monitoring
SDO
SDI/OSR1
SCK
Xtal Oscillator
MCLK
OSC1/CLKI/GAIN0
OSC2/MODE
DR/GAIN1
RESET/OSR0
Digital
Interfaces
(SPI & 2-wire)
Clock
Generation
Modulator
Output Block
MDAT0
DMCLK OSR<2:0>
PRE<1:0>
EN_MDAT
CS/BOOST
+
OFFCAL_CH0
<23:0>
GAINCAL_CH0
<23:0>
X
SINC3+
SINC1
Phase
Shifter
Φ
PHASE <11:0>
MOD <3:0>
2014-2019 Microchip Technology Inc. DS20005287B-page 3
MCP3918
1.0 ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
VDD ..................................................................... -0.3V to 4.0V
Digital inputs and outputs w.r.t. AGND................ --0.3V to 4.0V
Analog input w.r.t. AGND ..................................... ....-2V to +2V
VREF input w.r.t. AGND .............................. -0.6V to VDD + 0.6V
Storage temperature .....................................-65°C to +150°C
Ambient temp. with power applied ................-65°C to +125°C
Soldering temperature of leads (10 seconds) ............. +300°C
ESD on the analog inputs (HBM, MM) ................4.0 kV, 200V
ESD on all other pins (HBM, MM).......................4.0 kV, 200V
† Notice: Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at those or any other
conditions, above those indicated in the operational
listings of this specification, is not implied. Exposure to
maximum rating conditions for extended periods may
affect device reliability.
1.1 Electrical Specifications
TABLE 1-1: ANALOG SPECIFICATIONS
Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD =DV
DD =3V; MCLK=4MHz;
PRE[1:0] = 00; OSR = 256; GAIN = 1; VREFEXT = 0; CLKEXT = 1; DITHER[1:0] = 11; BOOST[1:0] = 10; VCM =0V;
TA= -40°C to +125°C (Note 1); VIN =1.2V
PP = -0.5 dBFS @ 50/60 Hz on all channels.
Characteristic Sym. Min. Typ. Max. Units Conditions
ADC Performance
Resolution
(No Missing Codes)
24 — — bits OSR = 256 or greater
Sampling Frequency fS(DMCLK) — 1 4 MHz For maximum condition,
BOOST[1:0] = 11
Output Data Rate fD(DRCLK) — 4 125 ksps For maximum condition,
BOOST[1:0] = 11, OSR = 32
Analog Input Absolute
Voltage on CH0+/- pins
CH0+/- -1 — +1 V All analog input channels
measured to AGND
Analog Input
Leakage Current
IIN — ±1 — nA RESET[0] = 1,
MCLK running continuously
Differential Input
Voltage Range
(CH0+ -CH0-) -600/GAIN — +600/GAIN mV VREF = 1.2V, proportional to VREF
Offset Error VOS -1 0.2 1 mV Note 5
Offset Error Drift — 0.5 — µV/°C
Gain Error GE -4 — +4 % Note 5
Note 1: All specifications are valid down to -45°C.
2: This specification implies that the ADC output is valid over this entire differential range and that there is no
distortion or instability across this input range. Dynamic performance specified at -0.5 dB below the maximum
signal range, VIN =1.2V
PP =424mV
RMS, VREF = 1.2V @ 50/60 Hz. See Section 4.0 “Terminology and
Formulas” for definition. This parameter is established by characterization and not 100% tested.
3: For these operating currents, the following Configuration bit settings apply: SHUTDOWN[0] = 0,
RESET[0] = 0, VREFEXT = 0, CLKEXT = 0.
4: For these operating currents, the following Configuration bit settings apply: SHUTDOWN[0] = 1,
VREFEXT = 1, CLKEXT = 1.
5: Applies to all gains. Offset and gain errors depend on the PGA gain setting. See Section 2.0 “Typical
Performance Curves” for typical performance.
6: Outside this range, the ADC accuracy is not specified. An extended input range of ±2V can be applied
continuously to the part with no damage.
7: For proper operation and for optimizing the ADC accuracy, AMCLK should be limited to the maximum
frequency defined in Table 5-2 , as a function of the BOOST and PGA setting chosen. MCLK can take larger
values as long as the prescaler settings (PRE[1:0]) limit AMCLK = MCLK/PRESCALE within the defined
range in Tab l e 5-2.
MCP3918
DS20005287B-page 4 2014-2019 Microchip Technology Inc.
Gain Error Drift — 1 — ppm/°C
Integral Nonlinearity INL — 5 — ppm
Measurement Error ME — 0.1 — % Measured with a 10,000:1
dynamic range (from 600 mVPeak
to 6 µVPeak), AVDD =DV
DD =3V,
measurement points averaging
time: 20 seconds
Differential Input
Impedance
ZIN 232 — — kG = 1, proportional to 1/AMCLK
142 — — kG = 2, proportional to 1/AMCLK
72 — — kG = 4, proportional to 1/AMCLK
38 — — kG = 8, proportional to 1/AMCLK
36 — — kG = 16, proportional to 1/AMCLK
33 — — kG = 32, proportional to 1/AMCLK
Signal-to-Noise and
Distortion Ratio (Note 2)
SINAD 92 93.5 — dB
Total Harmonic
Distortion (Note 2)
THD — -107 -103 dBc Includes the first 35 harmonics
Signal-to-Noise Ratio (Note 2)SNR 92 94 — dB
Spurious-Free Dynamic
Range (Note 2)
SFDR — 112 — dBFS
AC Power Supply
Rejection
AC PSRR — -73 — dB AVDD =DV
DD =3V+0.6 V
PP
,
50/60 Hz, 100/120 Hz
DC Power Supply
Rejection
DC PSRR — -73 — dB AVDD =DV
DD = 2.7V to 3.6V
DC Common-mode
Rejection
DC CMRR — -105 — dB VCM from -1V to +1V
TABLE 1-1: ANALOG SPECIFICATIONS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD =DV
DD =3V; MCLK=4MHz;
PRE[1:0] = 00; OSR = 256; GAIN = 1; VREFEXT = 0; CLKEXT = 1; DITHER[1:0] = 11; BOOST[1:0] = 10; VCM =0V;
TA= -40°C to +125°C (Note 1); VIN =1.2V
PP = -0.5 dBFS @ 50/60 Hz on all channels.
Characteristic Sym. Min. Typ. Max. Units Conditions
Note 1: All specifications are valid down to -45°C.
2: This specification implies that the ADC output is valid over this entire differential range and that there is no
distortion or instability across this input range. Dynamic performance specified at -0.5 dB below the maximum
signal range, VIN =1.2V
PP =424mV
RMS, VREF = 1.2V @ 50/60 Hz. See Section 4.0 “Terminology and
Formulas” for definition. This parameter is established by characterization and not 100% tested.
3: For these operating currents, the following Configuration bit settings apply: SHUTDOWN[0] = 0,
RESET[0] = 0, VREFEXT = 0, CLKEXT = 0.
4: For these operating currents, the following Configuration bit settings apply: SHUTDOWN[0] = 1,
VREFEXT = 1, CLKEXT = 1.
5: Applies to all gains. Offset and gain errors depend on the PGA gain setting. See Section 2.0 “Typical
Performance Curves” for typical performance.
6: Outside this range, the ADC accuracy is not specified. An extended input range of ±2V can be applied
continuously to the part with no damage.
7: For proper operation and for optimizing the ADC accuracy, AMCLK should be limited to the maximum
frequency defined in Table 5-2 , as a function of the BOOST and PGA setting chosen. MCLK can take larger
values as long as the prescaler settings (PRE[1:0]) limit AMCLK = MCLK/PRESCALE within the defined
range in Tab l e 5-2.
2014-2019 Microchip Technology Inc. DS20005287B-page 5
MCP3918
Internal Voltage Reference
To l e r a nc e V REF 1.176 1.2 1.224 V VREFEXT = 0, TA=+25°C only
Temperature Coefficient TCVREF —9—ppm/°CT
A= -40°C to +125°C,
VREFEXT = 0
Output Impedance ZOUTVREF —0.6— kVREFEXT = 0
Internal Voltage Reference
Operating Current
AIDDVREF — 54 — µA VREFEXT = 0,
SHUTDOWN[0] = 1
Voltage Reference Input
Input Capacitance — — 10 pF
Differential Input Voltage
Range (VREF+ –V
REF-)
VREF 1.1 — 1.3 V VREFEXT = 1
Absolute Voltage
on REFIN+ Pin
VREF+
V
REF
-+1.1 — V
REF
-+1.3
V VREFEXT = 1
Absolute Voltage
on REFIN- Pin
VREF- -0.1 — +0.1 V REFIN- should be connected to
AGND when VREFEXT = 0
Master Clock Input
Master Clock Input
Frequency Range
fMCLK — 20 MHz CLKEXT = 1 (Note 7)
Crystal Oscillator Operating
Frequency Range
fXTAL 1 — 20 MHz CLKEXT = 0 (Note 7)
Analog Master Clock AMCLK — — 16 MHz Note 7
Crystal Oscillator
Operating Current
DIDDXTAL — 80 — µA CLKEXT = 0
Power Supply
Operating Voltage, Analog AVDD 2.7 — 3.6 V
Operating Voltage, Digital DVDD 2.7 — 3.6 V
TABLE 1-1: ANALOG SPECIFICATIONS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD =DV
DD =3V; MCLK=4MHz;
PRE[1:0] = 00; OSR = 256; GAIN = 1; VREFEXT = 0; CLKEXT = 1; DITHER[1:0] = 11; BOOST[1:0] = 10; VCM =0V;
TA= -40°C to +125°C (Note 1); VIN =1.2V
PP = -0.5 dBFS @ 50/60 Hz on all channels.
Characteristic Sym. Min. Typ. Max. Units Conditions
Note 1: All specifications are valid down to -45°C.
2: This specification implies that the ADC output is valid over this entire differential range and that there is no
distortion or instability across this input range. Dynamic performance specified at -0.5 dB below the maximum
signal range, VIN =1.2V
PP =424mV
RMS, VREF = 1.2V @ 50/60 Hz. See Section 4.0 “Terminology and
Formulas” for definition. This parameter is established by characterization and not 100% tested.
3: For these operating currents, the following Configuration bit settings apply: SHUTDOWN[0] = 0,
RESET[0] = 0, VREFEXT = 0, CLKEXT = 0.
4: For these operating currents, the following Configuration bit settings apply: SHUTDOWN[0] = 1,
VREFEXT = 1, CLKEXT = 1.
5: Applies to all gains. Offset and gain errors depend on the PGA gain setting. See Section 2.0 “Typical
Performance Curves” for typical performance.
6: Outside this range, the ADC accuracy is not specified. An extended input range of ±2V can be applied
continuously to the part with no damage.
7: For proper operation and for optimizing the ADC accuracy, AMCLK should be limited to the maximum
frequency defined in Table 5-2 , as a function of the BOOST and PGA setting chosen. MCLK can take larger
values as long as the prescaler settings (PRE[1:0]) limit AMCLK = MCLK/PRESCALE within the defined
range in Tab l e 5-2.
MCP3918
DS20005287B-page 6 2014-2019 Microchip Technology Inc.
1.2 Serial Interface Characteristics
Operating Current, Analog
(Note 3)
IDD,A — 0.8 1 mA BOOST[1:0] = 00
—11.2mABOOST[1:0]=01
— 1.3 1.7 mA BOOST[1:0] = 10
— 2.2 2.9 mA BOOST[1:0] = 11
Operating Current, Digital IDD,D — 0.2 0.3 mA MCLK = 4 MHz,
proportional to MCLK
—0.7— mAMCLK=16MHz,
proportional to MCLK
Shutdown Current, Analog IDDS,A —— 1 µAAV
DD pin only (Note 4)
Shutdown Current, Digital IDDS,D —— 2 µADV
DD pin only (Note 4)
Pull-Down Current on OSC2
Pin (External Clock mode)
IOSC2 — 35 — µA CLKEXT = 1
TABLE 1-2: SERIAL DC CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, all parameters apply at DVDD = 2.7 to 3.6 V,
TA= -40°C to +125°C (Note 1), CLOAD = 30 pF, applies to all digital I/Os.
Characteristic Sym. Min. Typ. Max. Units Conditions
High-Level Input Voltage VIH 0.7 DVDD — — V Schmitt triggered
Low-Level Input Voltage VIL ——0.3 DV
DD V Schmitt triggered
Input Leakage Current ILI ——±1µACS=DV
DD, VIN =D
GND to DVDD
Output Leakage Current ILO ——±1µACS=DV
DD, VOUT =D
GND or DVDD
Hysteresis of Schmitt
Triggered Inputs
VHYS —300— mVDV
DD = 3.3V only (Note 3)
Low-Level Output Voltage VOL — — 0.4V V IOL =+1.7mA, DV
DD =3.3V
Note 1: All specifications are valid down to -45°C.
2: This parameter is periodically sampled and not 100% tested.
3: This parameter is established by characterization and not production tested.
TABLE 1-1: ANALOG SPECIFICATIONS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD =DV
DD =3V; MCLK=4MHz;
PRE[1:0] = 00; OSR = 256; GAIN = 1; VREFEXT = 0; CLKEXT = 1; DITHER[1:0] = 11; BOOST[1:0] = 10; VCM =0V;
TA= -40°C to +125°C (Note 1); VIN =1.2V
PP = -0.5 dBFS @ 50/60 Hz on all channels.
Characteristic Sym. Min. Typ. Max. Units Conditions
Note 1: All specifications are valid down to -45°C.
2: This specification implies that the ADC output is valid over this entire differential range and that there is no
distortion or instability across this input range. Dynamic performance specified at -0.5 dB below the maximum
signal range, VIN =1.2V
PP =424mV
RMS, VREF = 1.2V @ 50/60 Hz. See Section 4.0 “Terminology and
Formulas” for definition. This parameter is established by characterization and not 100% tested.
3: For these operating currents, the following Configuration bit settings apply: SHUTDOWN[0] = 0,
RESET[0] = 0, VREFEXT = 0, CLKEXT = 0.
4: For these operating currents, the following Configuration bit settings apply: SHUTDOWN[0] = 1,
VREFEXT = 1, CLKEXT = 1.
5: Applies to all gains. Offset and gain errors depend on the PGA gain setting. See Section 2.0 “Typical
Performance Curves” for typical performance.
6: Outside this range, the ADC accuracy is not specified. An extended input range of ±2V can be applied
continuously to the part with no damage.
7: For proper operation and for optimizing the ADC accuracy, AMCLK should be limited to the maximum
frequency defined in Table 5-2 , as a function of the BOOST and PGA setting chosen. MCLK can take larger
values as long as the prescaler settings (PRE[1:0]) limit AMCLK = MCLK/PRESCALE within the defined
range in Tab l e 5-2.
2014-2019 Microchip Technology Inc. DS20005287B-page 7
MCP3918
High-Level Output Voltage VOH DVDD –0.5 — — V I
OH =-1.7mA, DV
DD =3.3V
Internal Capacitance
(All Inputs and Outputs)
CINT ——7 pFT
A= +25°C, SCK = 1.0 MHz,
DVDD =3.3V (Note 2)
TABLE 1-3: SERIAL AC CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, all parameters apply at DVDD = 2.7 to 3.6 V,
TA= -40°C to +125°C (Note 1), GAIN = 1, CLOAD =30pF.
Characteristic Sym Min Typ Max Units Conditions
Serial Clock Frequency fSCK —— 20MHz
CS Setup Time tCSS 25 — — ns
CS Hold Time tCSH 50 — — ns
CS Disable Time tCSD 50 — — ns
Data Setup Time tSU 5— —ns
Data Hold Time tHD 10 — — ns
Serial Clock High Time tHI 20 — — ns
Serial Clock Low Time tLO 20 — — ns
Serial Clock Delay Time tCLD 50 — — ns
Serial Clock Enable Time tCLE 50 — — ns
Output Valid from SCK Low tDO — — 25 ns
Output Hold Time tHO 0— —ns
Output Disable Time tDIS — — 25 ns
Reset Pulse Width (RESET)t
MCLR 100 — — ns
Data Transfer Time to DR
(Data Ready)
tDODR — — 25 ns Note 2
Modulator Mode Entry to
Modulator Data Present
tMODSU —— 100ns
Data Ready Pulse Low Time tDRP — 1/(2 x DMCLK) — µs
2-Wire Mode Enable Time tMODE — — 50 ns
2-Wire Mode
Watchdog Timer
tWATCH 3.5 — 35 µs
Note 1: All specifications are valid down to -45°C.
2: This parameter is established by characterization and not production tested.
TABLE 1-2: SERIAL DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, all parameters apply at DVDD = 2.7 to 3.6 V,
TA= -40°C to +125°C (Note 1), CLOAD = 30 pF, applies to all digital I/Os.
Characteristic Sym. Min. Typ. Max. Units Conditions
Note 1: All specifications are valid down to -45°C.
2: This parameter is periodically sampled and not 100% tested.
3: This parameter is established by characterization and not production tested.
TABLE 1-4: TEMPERATURE SPECIFICATIONS
Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD = 2.7 to 3.6V, DVDD = 2.7 to 3.6V.
Parameters Sym. Min. Typ. Max. Units Conditions
Temperature Ranges
Operating Temperature Range TA-40 — +125 °C Note 1, Note 2
Note 1: The internal junction temperature (TJ) must not exceed the absolute maximum specification of +150°C.
2: All specifications are valid down to -45°C.
MCP3918
DS20005287B-page 8 2014-2019 Microchip Technology Inc.
FIGURE 1-1: Serial Output Timing Diagram.
FIGURE 1-2: Serial Input Timing Diagram.
Storage Temperature Range TA-65 — +150 °C
Thermal Package Resistances
Thermal Resistance, 20-Lead QFN JA —46.2 — °C/W
Thermal Resistance, 20-Lead SSOP JA —87.3 — °C/W
TABLE 1-4: TEMPERATURE SPECIFICATIONS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD = 2.7 to 3.6V, DVDD = 2.7 to 3.6V.
Parameters Sym. Min. Typ. Max. Units Conditions
Note 1: The internal junction temperature (TJ) must not exceed the absolute maximum specification of +150°C.
2: All specifications are valid down to -45°C.
tCSH
tDIS
tHI tLO
fSCK
CS
SCK
SDO MSB Out LSB Out
SDI
Mode 1,1
Mode 0,0
tHO
tDO
DON’T CARE
CS
SCK
SDI LSB InMSB In
Mode 1,1
Mode 0,0
tCSS
tSU tHD
tCSD
tCSH
tCLD
tCLE
SDO High-Z
tHI tLO
fSCK
2014-2019 Microchip Technology Inc. DS20005287B-page 9
MCP3918
FIGURE 1-3: Data Ready Pulse/Sampling Timing Diagram.
FIGURE 1-4: Timing Waveforms.
FIGURE 1-5: Entering 2-Wire Interface Mode Timing Diagram.
DR
SCK
tDRP
SDO
1/fD
tDODR
CS
VIH
Waveform for tDIS
High-Z
90%
10%
tDIS
SDO
SCK
SDO
tDO
Timing Waveform for tDO
High-Z
AVDD, DVDD
OSC2/MODE
SCK/MCLK
SDO
SPI
Mode
2-Wire
Mode
tMODE
0
0
0
MCP3918
DS20005287B-page 10 2014-2019 Microchip Technology Inc.
NOTES:
2014-2019 Microchip Technology Inc. DS20005287B-page 11
MCP3918
2.0 TYPICAL PERFORMANCE CURVES
Note: Unless otherwise indicated, AVDD =3V; DV
DD =3V; T
A= +25°C; MCLK = 4 MHz; PRESCALE = 1;
OSR = 256; GAIN = 1; Dithering = Maximum; VIN = -0.5 dBFS @ 60 Hz on all channels; VREFEXT = 0;
CLKEXT = 1; BOOST[1:0] = 10.
FIGURE 2-1: Spectral Response.
FIGURE 2-2: Spectral Response.
FIGURE 2-3: Spectral Response.
FIGURE 2-4: Spectral Response.
FIGURE 2-5: Measurement Error
with 1-Point Calibration.
FIGURE 2-6: Measurement Error
with 2-Point Calibration.
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
-
140
-120
-100
-80
-60
-40
-20
0
Amplitude (dB)
Vin = -0.5 dBFS @ 60 Hz
fD= 3.9 ksps
OSR = 256
Dithering = Off
16 ksamples FFT
-180
-160
140
0 500 1000 1500 2000
Frequency (Hz)
20
0Vin = -60 dBFS @ 60 Hz
-40
-
20
B
)
f
D= 3.9 ksps
OSR = 256
Dithering = Off
-80
-60
de (d
B
16 ksamples FFT
-120
-100
mplitu
-
160
-140
A
-180
-
160
0
500
1000
1500
2000
0
500
1000
1500
2000
Frequency (Hz)
-
140
-120
-100
-80
-60
-40
-20
0
Amplitude (dB)
Vin = -0.5 dBFS @ 60 Hz
fD= 3.9 ksps
OSR = 256
Dithering = Maximum
16 ksamples FFT
-180
-160
140
0 500 1000 1500 2000
Frequency (Hz)
0
-40
-20
0
)
Vin = -60 dBFS @ 60 Hz
fD= 3.9 ksps
OSR = 256
-80
-60
d
e (dB
)
Dithering = Maximum
16 ksamples FFT
-120
-100
m
plitu
d
-160
-140
A
m
-180
0 500 1000 1500 2000
Frequency (Hz)
-1.0%
-0.5%
0.0%
0.5%
1.0%
0.01 0.1 1 10 100 1000
Measurement Error (%)
Current Channel Input Amplitude (mVPeak)
% Error Channel 0,1
-1.0%
-0.5%
0.0%
0.5%
1.0%
0.01 0.1 1 10 100 1000
Measurement Error (%)
Current Channel Input Amplitude (mVPeak)
% Error Channel 0,1
MCP3918
DS20005287B-page 12 2014-2019 Microchip Technology Inc.
Note: Unless otherwise indicated, AVDD =3V; DV
DD =3V; T
A= +25°C; MCLK = 4 MHz; PRESCALE = 1;
OSR = 256; GAIN = 1; Dithering = Maximum; VIN = -0.5 dBFS @ 60 Hz on all channels; VREFEXT = 0;
CLKEXT = 1; BOOST[1:0] = 10.
FIGURE 2-7: THD Repeatability
Histogram.
FIGURE 2-8: Spurious-Free Dynamic
Range Repeatability Histogram.
FIGURE 2-9: SINAD Repeatability
Histogram.
FIGURE 2-10: Output Noise Histogram.
FIGURE 2-11: THD vs.OSR.
FIGURE 2-12: SINAD vs. OSR.
e
rrenc
e
f
Occu
e
ncy o
f
F
requ
e
-108.2 -107.8 -107.4 -107.0 -106.6 -106.2
F
Total Harmonic Distortion (
dBc)
Total Harmonic Distortion (
-
dBc)
q
uency of Occurrence
111.7 112.3 112.9 113.5 114.1 114.7 115.3 115.9
Fre
q
Spurious Free Dynamic Range (dBFS)
e
u
rrenc
e
o
f Occ
u
ency
o
Frequ
93.3 93.4 93.5 93.6 93.7 93.8
Signal to Noise and Distortion (dB)
Signal to Noise and Distortion (dB)
u
ency of Occurrence
Standar deviation = 78 LSB
Noise = 7.4ȝVrms
16 ksamples
448
481
514
548
581
614
647
680
714
747
780
813
846
880
913
946
979
1,012
1,046
1,079
1,112
Freq
u
Output Noise (LSB)
-120
-115
-110
-105
-100
-95
-90
al Harmonic Distortion
(dBc)
Dithering=Maximum
Dithering=Medium
Dithering=Minimum
Dithering=Off
-130
-125
32 64 128 256 512 1024 2048 4096
Tot
Oversampling Ratio (OSR)
110
95
100
105
nd
d
B)
85
90
95
N
oise a
R
atio (
d
75
80
85
al-to-
N
o
rtion
R
Dithering
=
Maximu
65
70
Sign
Dist
o
Dithering Maximu
m
Dithering=Medium
60
32 64 128 256 512 1024 2048 4096
Oversampling Ratio (OSR)
Oversampling Ratio (OSR)
2014-2019 Microchip Technology Inc. DS20005287B-page 13
MCP3918
Note: Unless otherwise indicated, AVDD =3V; DV
DD =3V; T
A= +25°C; MCLK = 4 MHz; PRESCALE = 1;
OSR = 256; GAIN = 1; Dithering = Maximum; VIN = -0.5 dBFS @ 60 Hz on all channels; VREFEXT = 0;
CLKEXT = 1; BOOST[1:0] = 10.
FIGURE 2-13: SNR vs.OSR.
FIGURE 2-14: SFDR vs. OSR.
FIGURE 2-15: THD vs. MCLK.
FIGURE 2-16: SINAD vs. MCLK.
FIGURE 2-17: SNR vs. MCLK.
FIGURE 2-18: SFDR vs. MCLK.
110
95
100
105
(
dB)
85
90
95
Ratio
(
75
80
85
-
Noise
Dithering
=
Maximum
65
70
75
nal-to
-
Dithering Maximum
Dithering=Medium
Dithering=Minimum
Dithering=Off
60
32 64 128 256 512 1024 2048 4096
Sig
O li R ti (OSR)
O
versamp
li
ng
R
a
ti
o
(OSR)
120
110
115
n
amic
)
100
105
110
e
e Dy
n
(
dBFS
)
95
100
o
us Fr
e
R
ange
(
Ditherin
g
=Maximum
85
90
Spuri
o
R
g
Dithering=Medium
Dithering=Minimum
Dithering
=
Off
80
32 64 128 256 512 1024 2048 4096
O li R ti (OSR)
Dithering Off
O
versamp
li
ng
R
a
ti
o
(OSR)
100
-95
-90
-85
-80
-75
-70
-65
-60
a
l Harmonic Distortion
(dB)
Boost = 00
Boost = 01
Boost = 10
Boost = 11
-110
-105
-
100
2 4 6 8 10 12 14 16 18 20
Tot
a
MCLK Frequency (MHz)
100
90
95
e
and
80
85
o
-Nois
e
t
ortion
dB)
75
80
g
nal-t
o
Dis
t
(
65
70
Si
g
Boost = 00
Boost = 01
60
2 4 6 8 10 12 14 16 18
Boost = 10
MCLK Frequency (MHz)
100
90
95
t
io
80
85
ise Ra
t
)
75
80
-to-No
(dB
)
65
70
Signal
Boost = 00
Boost = 01
Boost = 10
60
2 4 6 8 1012141618
Boost = 10
Boost = 11
MCLK Frequency (MHz)
120
110
amic
90
100
e
e Dyn
ge
F
S)
80
90
o
us Fr
e
Ran
(dB
F
70
80
Spuri
o
Boost = 00
Boost = 01
Boost = 10
60
2
4
6
8
10
12
14
16
18
20
Boost = 11
2
4
6
8
10
12
14
16
18
20
MCLK Frequency (MHz)
MCP3918
DS20005287B-page 14 2014-2019 Microchip Technology Inc.
Note: Unless otherwise indicated, AVDD =3V; DV
DD =3V; T
A= +25°C; MCLK = 4 MHz; PRESCALE = 1;
OSR = 256; GAIN = 1; Dithering = Maximum; VIN = -0.5 dBFS @ 60 Hz on all channels; VREFEXT = 0;
CLKEXT = 1; BOOST[1:0] = 10.
FIGURE 2-19: THD vs. GAIN.
FIGURE 2-20: SINAD vs. GAIN.
FIGURE 2-21: SNR vs. GAIN.
FIGURE 2-22: SFDR vs. GAIN.
FIGURE 2-23: THD vs. Input Signal
Amplitude.
FIGURE 2-24: SINAD vs. Input Signal
Amplitude.
-140
-120
-100
-80
-60
-40
-20
0
12481632
Total Harmonic Distortion (dB)
Gain (V/V)
OSR = 32
OSR = 64
OSR = 128
OSR = 256
OSR = 512
OSR = 1024
OSR = 2048
OSR = 4096
0
20
40
60
80
100
120
12481632
Signal-to-Noise and Distortion
Ratio (dB)
Gain (V/V)
OSR = 32
OSR = 64
OSR = 128
OSR = 256
OSR = 512
OSR = 1024
OSR = 2048
OSR = 4096
0
20
40
60
80
100
120
12481632
Signal-to-Noise Ratio (dB)
Gain (V/V)
OSR = 32
OSR = 64
OSR = 128
OSR = 256
OSR = 512
OSR = 1024
OSR = 2048
OSR = 4096
0
20
40
60
80
100
120
140
12481632
Spurious-Free Dynamic Range
(dBFS)
Gain (V/V)
OSR = 32
OSR = 64
OSR = 128
OSR = 256
OSR = 512
OSR = 1024
OSR = 2048
OSR = 4096
-120
-100
-80
-60
-40
-20
0.001 0.01 0.1 1 10 100 1000
Total Harmonic Distortion (dB)
Input Signal Amplitude (mVPK)
GAIN = 1x
GAIN = 2x
GAIN = 4x
GAIN = 8x
GAIN = 16x
GAIN = 32x
-20
0
20
40
60
80
100
0.001 0.01 0.1 1 10 100 1000
Signal-to-Noise and Distortion
Ratio (dB)
Input Signal Amplitude (mVPK)
GAIN = 1x
GAIN = 2x
GAIN = 4x
GAIN = 8x
GAIN = 16x
GAIN = 32x
2014-2019 Microchip Technology Inc. DS20005287B-page 15
MCP3918
Note: Unless otherwise indicated, AVDD =3V; DV
DD =3V; T
A= +25°C; MCLK = 4 MHz; PRESCALE = 1;
OSR = 256; GAIN = 1; Dithering = Maximum; VIN = -0.5 dBFS @ 60 Hz on all channels; VREFEXT = 0;
CLKEXT = 1; BOOST[1:0] = 10.
FIGURE 2-25: SNR vs. Input Signal
Amplitude.
FIGURE 2-26: SFDR vs. Input Signal
Amplitude.
FIGURE 2-27: SINAD vs. Input Frequency.
FIGURE 2-28: THD vs. Temperature.
FIGURE 2-29: SINAD vs. Temperature.
FIGURE 2-30: SNR vs. Temperature.
-20
0
20
40
60
80
100
0.001 0.01 0.1 1 10 100 1000
Signal-to-Noise Ratio (dB)
Input Signal Amplitude (mVPK)
GAIN = 1x
GAIN = 2x
GAIN = 4x
GAIN = 8x
GAIN = 16x
GAIN = 32x
0
20
40
60
80
100
120
140
0.001 0.01 0.1 1 10 100 1000
Spurious-Free Dynamic Range
(dBFS)
Input Signal Amplitude (mVPK)
GAIN = 1x
GAIN = 2x
GAIN = 4x
GAIN = 8x
GAIN = 16x
GAIN = 32x
0
20
40
60
80
100
120
10 100 1000 10000 100000
Signal-to-Noise and Distortion
Ratio (dB)
Signal Frequency (Hz)
OSR = 32
OSR = 64
OSR = 128
OSR = 256
OSR = 512
OSR = 1024
OSR = 2048
OSR = 4096
-120
-100
-80
-60
-40
-20
0
-50 -25 0 25 50 75 100 125
Total Harmonic Distortion (dB)
Temperature (°C)
GAIN = 1x
GAIN = 2x
GAIN = 4x
GAIN = 8x
GAIN = 16x
GAIN = 32x
0
10
20
30
40
50
60
70
80
90
100
-50 -25 0 25 50 75 100 125
Signal-to-Noise and Distortion
Ratio (dB)
Temperature (°C)
GAIN = 1x
GAIN = 2x
GAIN = 4x
GAIN = 8x
GAIN = 16x
GAIN = 32x
0
10
20
30
40
50
60
70
80
90
100
-50 -25 0 25 50 75 100 125
Signal-to-Noise Ratio (dB)
Temperature (°C)
GAIN = 1x
GAIN = 2x
GAIN = 4x
GAIN = 8x
GAIN = 16x
GAIN = 32x
MCP3918
DS20005287B-page 16 2014-2019 Microchip Technology Inc.
Note: Unless otherwise indicated, AVDD =3V; DV
DD =3V; T
A= +25°C; MCLK = 4 MHz; PRESCALE = 1;
OSR = 256; GAIN = 1; Dithering = Maximum; VIN = -0.5 dBFS @ 60 Hz on all channels; VREFEXT = 0;
CLKEXT = 1; BOOST[1:0] = 10.
FIGURE 2-31: SFDR vs. Temperature.
FIGURE 2-32: Offset vs. Temperature vs.
Gain.
FIGURE 2-33: Gain Error vs. Temperature
vs. Gain.
FIGURE 2-34: Internal Voltage Reference
vs. Temperature.
FIGURE 2-35: Internal Voltage Reference
vs. Supply Voltage.
FIGURE 2-36: Integral Nonlinearity
(Dithering Maximum).
0
20
40
60
80
100
120
-50 -25 0 25 50 75 100 125
Spurious-Free Dynamic Range
(dBFS)
Temperature (°C)
GAIN = 1x
GAIN = 2x
GAIN = 4x
GAIN = 8x
GAIN = 16x
GAIN = 32x
-1000
-800
-600
-400
-200
0
200
400
600
800
1000
-40 -20 0 20 40 60 80 100 120
Offset (µV)
Temperature (°C)
GAIN = 1x
GAIN = 2x
GAIN = 4x
GAIN = 8x
GAIN = 16x
GAIN = 32x
-5
-3
-1
1
3
5
7
9
-40 -20 0 20 40 60 80 100 120
Gain Error (%)
Temperature (°C)
GAIN = 1x
GAIN = 2x
GAIN = 4x
GAIN = 8x
GAIN = 16x
GAIN = 32x
1.197
1.198
1.199
1.2
-40 -20 0 20 40 60 80 100 120 140
Internal Voltage Reference (V)
Temperature (°C)
1.1961
1.1962
1.1963
1.1964
1.1965
1.1966
1.1967
1.1968
1.1969
2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6
Internal Voltage Reference (V)
AVDD (V)
-10
-8
-6
-4
-2
0
2
4
6
8
10
-0.6 -0.4 -0.2 0.0 0.2 0.4 0.6
Integral Non-Linearity Error
(ppm)
Input Voltage (V)
2014-2019 Microchip Technology Inc. DS20005287B-page 17
MCP3918
Note: Unless otherwise indicated, AVDD =3V; DV
DD =3V; T
A= +25°C; MCLK = 4 MHz; PRESCALE = 1;
OSR = 256; GAIN = 1; Dithering = Maximum; VIN = -0.5 dBFS @ 60 Hz on all channels; VREFEXT = 0;
CLKEXT = 1; BOOST[1:0] = 10.
FIGURE 2-37: Integral Nonlinearity
(Dithering Off).
FIGURE 2-38: Operating Current vs. MCLK
Frequency vs. Boost, VDD =3.0V.
-10
-8
-6
-4
-2
0
2
4
6
8
10
-0.6 -0.4 -0.2 0.0 0.2 0.4 0.6
Integral Non-Linearity Error
(ppm)
Input Voltage (V)
0
0.25
0.5
0.75
1
1.25
1.5
1.75
2
2.25
2.5
2.75
3
2468101214161820
I
DD
(mA)
MCLK Frequency (MHz)
AI
DD
Boost = 0.5
AI
DD
Boost = 0.66
AI
DD
Boost = 1
DI
DD
AI
DD
Boost = 2
MCP3918
DS20005287B-page 18 2014-2019 Microchip Technology Inc.
NOTES:
2014-2019 Microchip Technology Inc. DS20005287B-page 19
MCP3918
3.0 PIN DESCRIPTION
The description of the pins is listed in Ta b l e 3 - 1 .
TABLE 3-1: SIX-CHANNEL MCP3918 PIN FUNCTION TABLE
MCP3918
SSOP
MCP3918
QFN Symbol Function
1 18 RESET/OSR0 Master Reset Logic Input Pin or OSR0 Logic Input Pin
219 DV
DD Digital Power Supply Pin
320 AV
DD Analog Power Supply Pin
4 1 CH0+ Noninverting Analog Input Pin for Channel 0
5 2 CH0- Inverting Analog Input Pin for Channel 0
6 3 NC Not Connected
7 4 NC Not Connected
85 A
GND Analog Ground Pin, Return Path for Internal Analog Circuitry
9 6 REFIN+/OUT Noninverting Voltage Reference Input and Internal Reference
Output Pin
10 7 REFIN- Inverting Voltage Reference Input Pin
11 8 DGND Digital Ground Pin, Return Path for Internal Digital Circuitry
12 9 NC Not Connected
13 10 MDAT0 Modulator Data Output Pin for Channel 0
14 11 DR/GAIN1 Data Ready Signal Output Pin or GAIN1 Logic Input Pin
15 12 OSC1/CLKI/GAIN0 Oscillator Crystal Connection Pin or External Clock Input Pin or
GAIN0 Logic Input Pin
16 13 OSC2/MODE Oscillator Crystal Connection Input Pin or Serial Interface Mode
Logic Input Pin
17 14 CS/BOOST Serial Interface Chip Select Input Pin or BOOST Logic Input Pin
18 15 SCK/MCLK Serial Interface Clock Pin or Master Clock Input Pin
19 16 SDO Serial Interface Data Input Pin
20 17 SDI/OSR1 Serial Interface Data Input Pin or OSR1 Logic Input Pin
— 21 EP Exposed Thermal Pad
MCP3918
DS20005287B-page 20 2014-2019 Microchip Technology Inc.
3.1 Master Reset/OSR0 Logic Input
(RESET/OSR0)
In SPI mode, this pin is active-low and places the entire
chip in a Reset state when active.
When RESET is logic low, all registers are reset to their
default value, no communication can take place and no
clock is distributed inside the part, except in the input
structure if MCLK is applied (if MCLK is Idle, then no clock
is distributed). This state is equivalent to a Power-on
Reset (POR) state.
Since the default state of the ADC is on, the analog
power consumption when RESET is logic low is equiv-
alent to when RESET is logic high. Only the digital
power consumption is largely reduced because this
current consumption is essentially dynamic and is
reduced drastically when there is no clock running.
If MCLK is applied when RESET is logic low, all the
analog biases are enabled during a Reset, so that the
part is fully operational just after a RESET rising edge.
If MCLK is not applied, there is a time after a Hard
Reset when the conversion may not accurately
correspond to the start-up of the input structure.
This input is Schmitt triggered.
In 2-Wire Interface mode, this is the OSR0 logic select
pin (see Section 7.0 “2-Wire Serial Interface
Description” for the logic input table for OSR0 and
OSR1). The pin state is latched when the mode
changes to 2-Wire Interface mode and is relatched at
each Watchdog Timer Reset.
3.2 Digital VDD (DVDD)
DVDD is the power supply voltage for the digital circuitry
within the MCP3918. For optimal performance, it is rec-
ommended to connect appropriate bypass capacitors
(typically a 10 µF in parallel with a 0.1 µF ceramic).
DVDD should be maintained between 2.7V and 3.6V for
specified operation.
3.3 Analog Power Supply (AVDD)
AVDD is the power supply voltage for the analog circuitry
within the MCP3918. It is recommended to connect
appropriate bypass capacitors (typically a 10 µF in par-
allel with a 0.1 µF ceramic). AVDD should be maintained
between 2.7V and 3.6V for specified operation.
3.4 ADC Differential Analog Inputs
(CH0+/CH0-)
The CH0+/- pins are the fully differential analog voltage
inputs for the Delta-Sigma ADC.
The linear and specified region of the channels is
dependent on the PGA gain. This region corresponds
to a differential voltage range of ±600 mV/GAIN with
VREF =1.2V.
The maximum absolute voltage, with respect to AGND,
for each CH0+/- input pin is ±1V with no distortion and
±2V with no breaking after continuous voltage. This
maximum absolute voltage is not proportional to the
VREF voltage.
3.5 Analog Ground (AGND)
AGND is the ground reference voltage for the analog
circuitry within the MCP3918. For optimal performance,
it is recommended to connect it to the same ground node
voltage as DGND, preferably with a star connection.
If an analog ground plane is available, it is recom-
mended that these pins be tied to this plane of the
Printed Circuit Board (PCB). This plane should also
reference all other analog circuitry in the system.
3.6 Noninverting Reference Input,
Internal Reference Output
(REFIN+/OUT)
This pin is the noninverting side of the differential
voltage reference input for the ADC or the internal
voltage reference output.
When VREFEXT = 1, an external voltage reference
source can be used and the internal voltage reference
is disabled. When using an external differential voltage
reference, it should be connected to its VREF+ pin.
When using an external single-ended reference, it
should be connected to this pin.
When VREFEXT = 0, the internal voltage reference is
enabled and connected to this pin through a switch.
This voltage reference has minimal drive capability, and
thus needs proper buffering and bypass capacitances
(a 0.1 µF ceramic capacitor is sufficient in most cases)
if used as a voltage source.
If the voltage reference is only used as an internal
VREF
, adding bypass capacitance on REFIN+/OUT is
not necessary for keeping ADC accuracy, but a minimal
0.1 µF ceramic capacitance can be connected to avoid
EMI/EMC susceptibility issues due to the antenna,
created by the REFIN+/OUT pin, if left floating.
2014-2019 Microchip Technology Inc. DS20005287B-page 21
MCP3918
3.7 Inverting Reference Input (REFIN-)
This pin is the inverting side of the differential voltage
reference input for the ADC. When using an external
differential voltage reference, it should be connected to
its VREF- pin. When using an external single-ended
voltage reference, or when VREFEXT = 0 (default) and
using the internal voltage reference, the pin should be
directly connected to AGND.
3.8 Digital Ground Connection (DGND)
DGND is the ground reference voltage for the digital
circuitry within the MCP3918. For optimal performance,
it is recommended to connect it to the same ground node
voltage as AGND, preferably with a star connection.
If a digital ground plane is available, it is recommended
that this pin be tied to this plane of the PCB. This plane
should also reference all other digital circuitry in the
system.
3.9 Modulator Output (MDAT0)
MDAT0 is the output pin for the modulator serial bit
streams of the ADC. This pin is high-impedance when
the EN_MDAT bit is logic low. When the EN_MDAT bit is
enabled, the modulator bit stream of the ADC is present
on the pin and updated at the AMCLK frequency (see
Section 5.3.5 “Modulator Output Block” for a com-
plete description of the modulator output). This pin can
be directly connected to an MCU or a DSP when a
specific digital filtering is needed. When the MDAT0 out-
put pin is enabled, the DR output is disabled. In 2-Wire
Interface mode, this pin is automatically inactive; its state
is high-impedance during the 2-Wire mode (therefore,
this pin can be left grounded in applications using exclu-
sively the 2-Wire Interface mode; this configuration
improves the EMI/EMC susceptibility of the device).
3.10 Data Ready Output/GAIN1 Logic
Input (DR/GAIN1)
In SPI mode, the Data Ready pin indicates if a new
conversion result is ready to be read. The default state
of this pin is logic high when DR_HIZ = 1 and is
high-impedance when DR_HIZ = 0 (default). After each
conversion is finished, a logic low pulse will take place
on the Data Ready pin to indicate the conversion result
is ready as an interrupt. This pulse is synchronous with
the master clock, and has a defined and constant width.
The Data Ready pin is independent from the SPI inter-
face and acts like an interrupt output. The Data Ready
pin state is not latched, and the pulse width (and
period) are both determined by the MCLK frequency,
oversampling rate and internal clock prescale settings.
The data ready pulse width is equal to half a DMCLK
period and the frequency of the pulses is equal to
DRCLK (see Figure 1-3).
In 2-Wire Interface mode, this is the GAIN1 logic select
pin. See Section 7.0 “2-Wire Serial Interface
Description” for the logic input table for GAIN0 and
GAIN1. The pin state is latched when the mode
changes to 2-Wire Interface mode and is relatched at
each Watchdog Timer Reset.
3.11 Crystal Oscillator/Master Clock
Input/GAIN0 Logic Input
(OSC1/CLKI/GAIN0)
In SPI mode, OSC1/CLKI and OSC2 provide the
master clock for the device. When CLKEXT = 0, a res-
onant crystal or clock source with a similar sinusoidal
waveform must be placed across the OSC1 and OSC2
pins to ensure proper operation.
The typical clock frequency specified is 4 MHz. For
proper operation and in order to optimize ADC accuracy,
AMCLK should be limited to the maximum frequency
defined in Table 5-2 for the function of the BOOST and
PGA settings chosen. MCLK can take larger values as
long as the prescaler settings (PRE[1:0]) limit
AMCLK = MCLK/PRESCALE in the defined range in
Table 5-2. Appropriate load capacitance should be
connected to these pins for proper operation.
In 2-Wire Interface mode, this is the GAIN0 logic
select pin. See Section 7.0 “2-Wire Serial Interface
Description” for the logic input table for GAIN0 and
GAIN1. The pin state is latched when the mode changes
to 2-Wire Interface mode and is relatched at each
Watchdog Timer Reset.
Note: This pin should not be left floating when the
DR_HIZ bit is low; a 100 k pull-up resistor
connected to DVDD is recommended.
Note: When CLKEXT = 1, the crystal oscillator is
disabled. OSC1 becomes the master
clock input, CLKI, a direct path for an
external clock source. One example
would be a clock source generated by an
MCU.
MCP3918
DS20005287B-page 22 2014-2019 Microchip Technology Inc.
3.12 Crystal Oscillator Output/
Interface MODE Logic Input
(OSC2/MODE)
When CLKEXT = 0 (default), a resonant crystal or clock
source with a similar sinusoidal waveform must be
placed across the OSC1 and OSC2 pins to ensure
proper operation. Appropriate load capacitance should
be connected to these pins for proper operation.
When CLKEXT = 1 (default condition at POR), this pin
is the MODE selection pin for the digital interface.
When MODE is logic low, the SPI interface is selected
(see Section 6.0 “SPI Serial Interface Description”).
When MODE is logic high, the 2-Wire interface mode is
selected (see Section 7.0 “2-Wire Serial Interface
Description”). The MODE input is latched after a
POR, a Master Reset and/or a Watchdog Timer Reset.
3.13 Chip Select/ Boost Logic Input
(CS/BOOST)
In SPI mode, this pin is the SPI chip select that enables
serial communication. When this pin is logic high, no
communication can take place. A chip select falling
edge initiates serial communication and a chip select
rising edge terminates the communication. No commu-
nication can take place, even when CS is logic low, if
RESET is also logic low.
This input is Schmitt triggered.
In the 2-Wire Interface mode, this is the BOOST logic
select pin. See Section 7.0 “2-Wire Serial Interface
Description” for the logic input table for BOOST. The
pin state is latched when the mode changes to 2-Wire
Interface mode and is relatched at each Watchdog
Timer Reset.
3.14 Serial Data Clock/
Master Clock Input (SCK/MCLK)
In SPI mode, this is the serial clock pin for SPI commu-
nication. Data are clocked into the device on the rising
edge of SCK. Data are clocked out of the device on the
falling edge of SCK.
The MCP3918 SPI interface is compatible with SPI
Mode 0,0 and 1,1. SPI modes can be changed during
a CS high time.
The maximum clock speed specified is 20 MHz. SCK
and MCLK are two different and asynchronous clocks;
SCK is only required when a communication happens,
while MCLK is continuously required when the part is
converting analog inputs.
This input is Schmitt triggered.
In the 2-Wire Interface mode, this pin is defining the
Master Clock (MCLK) of the device and the Serial
Clock (SCK) for the interface, simultaneously. In this
mode, the clock has to be provided continuously to
ensure proper operation. See Section 7.0 “2-Wire
Serial Interface Description” for more information
and timing diagrams of the 2-wire interface protocol.
3.15 Serial Data Output (SDO)
This is the SPI data output pin. Data are clocked out of
the device on the falling edge of SCK.
This pin remains in a high-impedance state during the
command byte. It also stays high-impedance during the
entire communication for WRITE commands and when
the CS pin is logic high or when the RESET pin is logic
low. This pin is active only when a READ command is
processed. The interface is half-duplex (inputs and
outputs do not happen at the same time).
In the 2-Wire Interface mode, this pin is the only digital
output pin and sends synchronous frames at each data
ready with data bits clocked out on the falling edge of
SCK.
3.16 Serial Data/OSR1 Logic Input
(SDI/OSR1)
In SPI mode, this is the SPI data input pin. Data are
clocked into the device on the rising edge of SCK.
When CS is logic low, this pin is used to communicate
with 8-bit commands, followed by data bytes that can
be 16, 24 or 32-bit wide. The interface is half-duplex
(inputs and outputs do not happen at the same time).
Each communication starts with a chip select falling
edge, followed by an 8-bit command word entered
through the SDI pin. Each command is either a READ or
a WRITE command. Toggling SDI during a READ
command has no effect.
This input is Schmitt triggered.
In 2-Wire Interface mode, this is the OSR1 logic select
pin. See Section 7.0 “2-Wire Serial Interface Descrip-
tion” for the logic input table for OSR0 and OSR1. The
pin state is latched when the mode changes to 2-Wire
Interface mode and is relatched at each Watchdog Timer
Reset.
3.17 Exposed Pad (EP)
Exposed Thermal Pad. This pin must be connected to
AGND for optimal accuracy and thermal performance.
This pad can also be left floating if necessary. Connecting
it to AGND is preferable for the lowest noise performance
and best thermal behavior.
2014-2019 Microchip Technology Inc. DS20005287B-page 23
MCP3918
4.0 TERMINOLOGY AND
FORMULAS
This section defines the terms and formulas used
throughout this data sheet. The following terms are
defined:
•MCLK – Master Clock
•AMCLK – Analog Master Clock
•DMCLK – Digital Master Clock
•DRCLK – Data Rate Clock
•OSR – Oversampling Ratio
•Offset Error
•Gain Error
•Integral Nonlinearity Error
•Signal-to-Noise Ratio (SNR)
•Signal-to-Noise and Distortion Ratio (SINAD)
•Total Harmonic Distortion (THD)
•Spurious-Free Dynamic Range (SFDR)
•MCP3918 Delta-Sigma Architecture
•Idle Tones
•Dithering
•PSRR
•CMRR
•ADC Reset Mode
•Hard Reset Mode (RESET = 0)
•ADC Shutdown Mode
•Full Shutdown Mode
4.1 MCLK – Master Clock
This is the fastest clock present on the device. This is
the frequency of the crystal placed at the OSC1/OSC2
inputs when CLKEXT = 0 or the frequency of the clock
input at the OSC1/CLKI inputs when CLKEXT = 1. In
the 2-Wire mode, this is the frequency present at the
SCK input pin. See Figure 4-1.
4.2 AMCLK – Analog Master Clock
AMCLK is the clock frequency that is present on the
analog portion of the device after prescaling has
occurred via the PRE[1:0] bits in the CONFIG0 register
(see Equation 4-1). The analog portion includes the
PGA and one Delta-Sigma modulator.
EQUATION 4-1:
FIGURE 4-1: Clock Sub-Circuitry.
4.3 DMCLK – Digital Master Clock
This is the clock frequency that is present on the digital
portion of the device after prescaling and division by four
(Equation 4-2). This is also the sampling frequency,
which is the rate at which the modulator outputs are
refreshed. Each period of this clock corresponds to one
sample and one modulator output. See Figure 4-1.
EQUATION 4-2:
4.4 DRCLK – Data Rate Clock
This is the output data rate (i.e., the rate at which the
ADC outputs new data). Each new datum is signaled by
a data ready pulse on the Data Ready pin.
This data rate is dependent on the OSR and the
prescaler with the formula in Equation 4-3.
EQUATION 4-3:
TABLE 4-1: MCP3918 OVERSAMPLING
RATIO SETTINGS
CONFIG0 Analog Master Clock
Prescale
PRE[1:0]
00 AMCLK = MCLK/1 (default)
01 AMCLK = MCLK/2
10 AMCLK = MCLK/4
11 AMCLK = MCLK/8
AMCLK MCLK
PRESCALE
-------------------------------
=
Xtal Oscillator
MCLK
OSC1
OSC2 Multiplexer
OUT
0
1
1/PRESCALE 1/4 1/OSR
AMCLK DMCLK DRCLK
Clock Divider Clock Divider Clock Divider
OSR[2:0]PRE[1:0]CLKEXT
Multiplexer
OUT
0
1
MODE
SCK
DMCLK AMCLK
4
---------------------MCLK
4PRESCALE
----------------------------------------==
DRCLK DMCLK
OSR
---------------------- AMCLK
4OSR
--------------------- MCLK
4 OSR PRESCALE
-----------------------------------------------------------===
MCP3918
DS20005287B-page 24 2014-2019 Microchip Technology Inc.
Since this is the output data rate, and because the
decimation filter is a SINC (or notch) filter, there is a
notch in the filter transfer function at each integer
multiple of this rate.
Table 4-2 describes the various combinations of OSR
and PRESCALE, and their associated AMCLK,
DMCLK and DRCLK rates.
TABLE 4-2: DEVICE DATA RATES IN FUNCTION OF MCLK, OSR AND PRESCALE,
MCLK = 4 MHz
PRE[1:0] OSR[2:0] OSR AMCLK DMCLK DRCLK DRCLK
(ksps) SINAD (dB)(1)ENOB from
SINAD (bits)(1)
1 11114096 MCLK/8 MCLK/32 MCLK/131072 0.035 102.5 16.7
1 11102048 MCLK/8 MCLK/32 MCLK/65536 0.061 100 16.3
1 11011024 MCLK/8 MCLK/32 MCLK/32768 0.122 97 15.8
1 1100 512 MCLK/8 MCLK/32 MCLK/16384 0.244 96 15.6
1 1011 256 MCLK/8 MCLK/32 MCLK/8192 0.488 95 15.5
1 1010 128 MCLK/8 MCLK/32 MCLK/4096 0.976 90 14.7
1 1001 64 MCLK/8 MCLK/32 MCLK/2048 1.95 83 13.5
1 1000 32 MCLK/8 MCLK/32 MCLK/1024 3.9 70 11.3
1 01114096 MCLK/4 MCLK/16 MCLK/65536 0.061 102.5 16.7
1 01102048 MCLK/4 MCLK/16 MCLK/32768 0.122 100 16.3
1 01011024 MCLK/4 MCLK/16 MCLK/16384 0.244 97 15.8
1 0100 512 MCLK/4 MCLK/16 MCLK/8192 0.488 96 15.6
1 0011 256 MCLK/4 MCLK/16 MCLK/4096 0.976 95 15.5
1 0010 128 MCLK/4 MCLK/16 MCLK/2048 1.95 90 14.7
1 0001 64 MCLK/4 MCLK/16 MCLK/1024 3.9 83 13.5
1 0000 32 MCLK/4 MCLK/16 MCLK/512 7.8125 70 11.3
0 11114096 MCLK/2 MCLK/8 MCLK/32768 0.122 102.5 16.7
0 11102048 MCLK/2 MCLK/8 MCLK/16384 0.244 100 16.3
0 11011024 MCLK/2 MCLK/8 MCLK/8192 0.488 97 15.8
0 1100 512 MCLK/2 MCLK/8 MCLK/4096 0.976 96 15.6
0 1011 256 MCLK/2 MCLK/8 MCLK/2048 1.95 95 15.5
0 1010 128 MCLK/2 MCLK/8 MCLK/1024 3.9 90 14.7
0 1001 64 MCLK/2 MCLK/8 MCLK/512 7.8125 83 13.5
0 1000 32 MCLK/2 MCLK/8 MCLK/256 15.625 70 11.3
0 01114096 MCLK MCLK/4 MCLK/16384 0.244 102.5 16.7
0 01102048 MCLK MCLK/4 MCLK/8192 0.488 100 16.3
0 01011024 MCLK MCLK/4 MCLK/4096 0.976 97 15.8
0 0100 512 MCLK MCLK/4 MCLK/2048 1.95 96 15.6
0 0011 256 MCLK MCLK/4 MCLK/1024 3.9 95 15.5
0 0010 128 MCLK MCLK/4 MCLK/512 7.8125 90 14.7
0 0001 64 MCLK MCLK/4 MCLK/256 15.625 83 13.5
0 0000 32 MCLK MCLK/4 MCLK/128 31.25 70 11.3
Note 1: For OSR = 32 and 64, DITHER = None. For OSR = 128 and higher, DITHER = Maximum. The SINAD
values are given for GAIN = 1.
2014-2019 Microchip Technology Inc. DS20005287B-page 25
MCP3918
4.5 OSR – Oversampling Ratio
This is the ratio of the sampling frequency to the output
data rate: OSR = DMCLK/DRCLK. The default OSR
is 256, with MCLK = 4 MHz, PRESCALE = 1,
AMCLK = 4 MHz, fS = 1 MHz and fD = 3.90625 ksps. The
bits in Table 4-3, available in the CONFIG0 register, are
used to change the Oversampling Ratio (OSR).
4.6 Offset Error
This is the error induced by the ADC when the inputs
are shorted together (VIN = 0V). The specification
incorporates both PGA and ADC offset contributions.
This error varies with PGA and OSR settings. The
offset is different on each channel and varies from chip-
to-chip. The offset is specified in µV. The offset error
can be digitally compensated independently on each
channel through the OFFCAL_CH0 register, with a
24-bit Calibration Word.
The offset on the MCP3918 has a low-temperature
coefficient.
4.7 Gain Error
This is the error induced by the ADC on the slope of the
transfer function. It is the deviation expressed in %
compared to the ideal transfer function defined in
Equation 5-3. The specification incorporates both PGA
and ADC gain error contributions, but not the VREF
contribution (it is measured with an external VREF).
This error varies with PGA and OSR settings. The gain
error can be digitally compensated independently on
each channel through the GAINCAL_CH0 register with
a 24-bit Calibration Word.
The gain error on the MCP3918 has a low-temperature
coefficient.
4.8 Integral Nonlinearity Error
Integral nonlinearity error is the maximum deviation of
an ADC transition point from the corresponding point of
an ideal transfer function, with the offset and gain
errors removed, or with the end points equal to zero.
It is the maximum remaining error after calibration of
offset and gain errors for a DC input signal.
4.9 Signal-to-Noise Ratio (SNR)
For the MCP3918 ADC, the Signal-to-Noise Ratio is a
ratio of the output fundamental signal power to noise
power (not including the harmonics of the signal), when
the input is a sine wave at a predetermined frequency
(see Equation 4-4). It is measured in dB. Usually, only
the maximum Signal-to-Noise Ratio is specified. The
SNR figure depends mainly on the OSR and DITHER
settings of the device.
EQUATION 4-4: SIGNAL-TO-NOISE RATIO
4.10 Signal-to-Noise and Distortion
Ratio (SINAD)
The most important Figure of Merit for the analog per-
formance of the ADC present on the MCP3918 is the
Signal-to-Noise and Distortion (SINAD) specification.
The Signal-to-Noise and Distortion Ratio is similar to the
Signal-to-Noise Ratio, with the exception that you must
include the harmonics power in the noise power calcula-
tion (see Equation 4-5). The SINAD specification
depends mainly on the OSR and DITHER settings.
EQUATION 4-5: SINAD EQUATION
The calculated combination of SNR and THD per the
following formula also yields SINAD (see Equation 4-6).
EQUATION 4-6: SINAD, THD AND SNR
RELATIONSHIP
TABLE 4-3: MCP3918 OVERSAMPLING
RATIO SETTINGS
CONFIG0 Oversampling Ratio
(OSR)
OSR[2:0]
000 32
001 64
010 128
011 256 (Default)
100 512
101 1024
110 2048
111 4096
SNR dB 10 SignalPower
NoisePower
----------------------------------
log=
SINAD dB 10 SignalPower
Noise HarmonicsPower+
---------------------------------------------------------------------
log=
SINAD dB 10 10
SNR
10
-----------
10
THD–
10
----------------
+log=
MCP3918
DS20005287B-page 26 2014-2019 Microchip Technology Inc.
4.11 Total Harmonic Distortion (THD)
The Total Harmonic Distortion is the ratio of the output
harmonics power to the fundamental signal power for a
sine wave input and is defined in Equation 4-7.
EQUATION 4-7:
The THD calculation includes the first 35 harmonics for
the MCP3918 specifications. The THD is usually only
measured with respect to the first ten harmonics. THD
is sometimes expressed as percentage. Equation 4-8
converts the THD in percentage.
EQUATION 4-8:
This specification depends mainly on the DITHER
setting.
4.12 Spurious-Free Dynamic Range
(SFDR)
SFDR is the ratio between the output power of the
fundamental and the highest spur in the frequency
spectrum (see Equation 4-9). The spur frequency is not
necessarily a harmonic of the fundamental, even
though this is usually the case. This figure represents
the dynamic range of the ADC when a full-scale signal
is used at the input. This specification depends mainly
on the DITHER setting.
EQUATION 4-9:
4.13 MCP3918 Delta-Sigma
Architecture
The MCP3918 incorporates one Delta-Sigma ADC with
a multibit architecture. A Delta-Sigma ADC is an over-
sampling converter that incorporates a built-in modulator,
which digitizes the quantity of charges integrated by the
modulator loop (see Figure 5-1). The quantizer is the
block that performs the Analog-to-Digital conversion. The
quantizer is typically 1-bit, or a simple comparator, which
helps maintain the linearity performance of the ADC (the
DAC structure is, in this case, inherently linear).
Multibit quantizers help lower the quantization error
(the error fed back in the loop can be very large with
1-bit quantizers) without changing the order of the
modulator or the OSR, which leads to better SNR
figures. However, typically, the linearity of such archi-
tectures is more difficult to achieve since the DAC
linearity is as difficult to attain and its linearity limits the
THD of such ADC.
The 5-level quantizer present in MCP3918 is a Flash
ADC composed of four comparators, arranged with
equally spaced thresholds and a thermometer coding.
For improved THD figures, the MCP3918 also includes
proprietary 5-level DAC architecture that is inherently
linear.
4.14 Idle Tones
A Delta-Sigma converter is an integrating converter. It
also has a finite quantization step (LSB) which can be
detected by its quantizer. A DC input voltage that is
below the quantization step should only provide an all
zeros result, since the input is not large enough to be
detected. As an integrating device, any Delta-Sigma
ADC will show Idle tones. This means that the output will
have spurs in the frequency content that depend on the
ratio between the quantization step voltage and the input
voltage. These spurs are the result of the integrated sub-
quantization step inputs that will eventually cross the
quantization steps after a long enough integration. This
will induce an AC frequency at the output of the ADC and
can be shown in the ADC output spectrum.
These Idle tones are residues that are inherent to the
quantization process and to the fact that the converter
is integrating at all times without being reset. They are
residues of the finite resolution of the conversion
process. They are very difficult to attenuate and they
are heavily signal-dependent. They can degrade the
SFDR and THD of the converter, even for DC inputs.
They can be localized in the baseband of the converter
and are thus difficult to filter from the actual input signal.
For power metering applications, Idle tones can be very
disturbing, because energy can be detected even at
the 50 or 60 Hz frequency, depending on the DC offset
of the ADC, while no power is really present at the
inputs. The only practical way to suppress or attenuate
the Idle tones phenomenon is to apply dithering to the
ADC. The amplitudes of the Idle tones are a function of
the order of the modulator, the OSR and the number of
levels in the quantizer of the modulator. A higher order,
a higher OSR or a higher number of levels for the
quantizer will attenuate the amplitudes of the Idle
tones.
THD dB 10 HarmonicsPower
FundamentalPower
-----------------------------------------------------
log=
THD % 100 10
THD dB
20
------------------------
=
SFDR dB 10 FundamentalPower
HighestSpurPower
-----------------------------------------------------
log=
2014-2019 Microchip Technology Inc. DS20005287B-page 27
MCP3918
4.15 Dithering
In order to suppress or attenuate the Idle tones present
in any Delta-Sigma ADC, dithering can be applied to
the ADC. Dithering is the process of adding an error to
the ADC feedback loop in order to “decorrelate” the
outputs and “break” the Idle tone’s behavior. Usually a
random or pseudorandom generator adds an analog or
digital error to the feedback loop of the Delta-Sigma
ADC in order to ensure that no tonal behavior can hap-
pen at its outputs. This error is filtered by the feedback
loop and typically has a zero average value, so that the
converter’s static transfer function is not disturbed by
the dithering process. However, the dithering process
slightly increases the noise floor (it adds noise to the
part) while reducing its tonal behavior and thus improv-
ing SFDR and THD. The dithering process scrambles
the Idle tones into baseband white noise and ensures
that dynamic specs (SNR, SINAD, THD, SFDR) are
less signal-dependent. The MCP3918 incorporates a
proprietary dithering algorithm on the ADC in order to
remove Idle tones and improve THD, which is crucial
for power metering applications.
4.16 PSRR
This is the ratio between a change in the power supply
voltage and the ADC output codes. It measures the
influence of the power supply voltage on the ADC
outputs.
The PSRR specification can be DC (the power supply
takes multiple DC values) or AC (the power supply is a
sine wave at a certain frequency with a certain
Common-mode). In AC, the amplitude of the sine wave
represents the change in the power supply; it is defined
in Equation 4-10.
EQUATION 4-10:
Where VOUT is the equivalent input voltage that the output
code translates to, with the ADC transfer function.
In the MCP3918 specification, AVDD varies from 2.7V to
3.6V, and for AC PSRR, a 50/60 Hz sine wave centered
around 3.0V is chosen with a maximum amplitude of
300 mV. The PSRR specification is measured with
AVDD = DVDD.
4.17 CMRR
CMRR is the ratio between a change in the
Common-mode input voltage and the ADC output
codes. It measures the influence of the Common-mode
input voltage on the ADC outputs.
The CMRR specification can be DC (the Common-mode
input voltage takes multiple DC values) or AC (the
Common-mode input voltage is a sine wave at a certain
frequency with a certain Common-mode). In AC, the
amplitude of the sine wave represents the change in the
power supply; it is defined in Equation 4-11.
EQUATION 4-11:
Where VCM = (CH0+ + CH0-)/2 is the Common-mode
input voltage and VOUT is the equivalent input voltage
that the output code translates to, with the ADC transfer
function. In the MCP3918 specification, VCM varies
from -1V to +1V.
4.18 ADC Reset Mode
ADC Reset mode (also called Soft Reset mode) can
only be entered in SPI mode by setting the RESET[0]
bit high in the CONFIG1 register. This mode is defined
as the condition where the converter is active, but its
output is forced to ‘0’.
The registers are not affected in this Reset mode and
retain their state, except for the data registers of the
corresponding channel, which are reset to ‘0’.
The ADC can immediately output meaningful codes
after leaving the Reset mode (and after the SINC filter
settling time). This mode is both entered and exited
through bit settings in the CONFIG1 register.
The Configuration registers are not modified by the Soft
Reset mode. While in Reset mode, no data ready pulse
will be generated by the ADC.
When the ADC exits ADC Reset mode, any phase
delay present before Reset was entered will still be
present.
However, when the ADC is in Soft Reset mode, the
input structure is still clocking, if MCLK is applied, in
order to properly bias the inputs so that no leakage
current is observed. If MCLK is not applied, large
analog input leakage currents can be observed for
highly negative input voltages (typically, below -0.6V,
referred to as AGND).
PSRR dB 20
VOUT
AVDD
-------------------
log=
CMRR dB 20
VOUT
VCM
-----------------
log=
MCP3918
DS20005287B-page 28 2014-2019 Microchip Technology Inc.
4.19 Hard Reset Mode (RESET = 0)
This mode is only available during a POR or when the
RESET pin is pulled low in SPI mode. The RESET pin
logic low state places the device in Hard Reset mode.
In this mode, all internal registers are reset to their
default state. In the 2-Wire Interface mode, the RESET
pin functionality is not available and the user must use
a Watchdog Timer Reset to be able to fully reset the
part (see Section 7.4 “Watchdog Timer Reset,
Resetting the Part When in 2-Wire Mode”).
The DC biases for the analog blocks are still active (i.e.,
the MCP3918 is ready to convert). However, this pin
clears all conversion data in the ADC. The comparators’
outputs of the ADC are forced to their Reset state
(‘0011’). The SINC filter, as well as its double-output buf-
fers, are all reset. See serial timing for minimum pulse
low time in Section 1.0 “Electrical Characteristics”.
During a Hard Reset, no communication with the part is
possible. The digital interface is maintained in a Reset
state.
During this state, the clock, MCLK, can be applied to
the part in order to properly bias the input structures of
all channels. If not applied, large analog input leakage
currents can be observed for highly negative input
signals, and after removing the Hard Reset state, a
certain start-up time is necessary to properly bias the
input structure. During this delay, the ADC conversions
can be inaccurate.
4.20 ADC Shutdown Mode
ADC Shutdown mode is defined as a state where the
converters and their biases are off, consuming only
leakage current. When the Shutdown bit is reset to ‘0’,
the analog biases will be enabled, as well as the clock
and the digital circuitry. The ADC will give a data ready
after the SINC filter settling time has occurred. How-
ever, since the analog biases are not completely settled
at the beginning of the conversion, the sampling may
not be accurate for about 1 ms (corresponding to the
settling time of the biasing under worst-case condi-
tions). In order to ensure accuracy, the data ready
pulse within the delay of 1 ms + settling time of the
SINC filter should be discarded.
The Configuration registers are not modified by the
Shutdown mode. This mode is only available in SPI
mode through programming the SHUTDOWN[1:0] bits
in the CONFIG1 register.
The output data are flushed to all zeros while in ADC
Shutdown mode. While in ADC Shutdown mode, no
data ready pulse will be generated by the ADC.
When the ADC exits ADC Shutdown mode, any phase
delay present before shutdown was entered will still be
present.
If the ADC is in Shutdown mode, the clock is not
distributed to the input structure or to the digital core for
low-power operation. This can potentially cause high
analog input leakage currents at the analog inputs if the
input voltage is highly negative (typically below -0.6V,
referred to as AGND). Once the ADC is back to normal
operation, the clock is automatically distributed again.
4.21 Full Shutdown Mode
The lowest power consumption can be achieved when
SHUTDOWN[0] = 1, VREFEXT
=
CLKEXT
=
1
. This
mode is called Full Shutdown mode and no analog
circuitry is enabled. In this mode, both AVDD and DVDD
POR monitoring are also disabled and no clock is prop-
agated throughout the chip. The ADC is in Shutdown
mode and the internal voltage reference is disabled.
This mode can only be entered during SPI mode.
The clock is no longer distributed to the input structure
either. This can potentially cause high analog input
leakage currents at the analog inputs if the input
voltage is highly negative (typically below -0.6V,
referred to as AGND).
The only circuit that remains active is the SPI interface,
but this circuit does not induce any static power
consumption. If SCK is Idle, the only current consump-
tion comes from the leakage currents induced by the
transistors and is less than 5 µA on each power supply.
This mode can be used to power down the chip
completely and to avoid power consumption when
there are no data to convert at the analog inputs. Any
SCK or MCLK edge occurring while in this mode will
induce dynamic power consumption.
Once any of the SHUTDOWN, CLKEXT and VREFEXT
bits returns to ‘0’, the two POR monitoring blocks are
operational, and AVDD and DVDD monitoring can take
place.
2014-2019 Microchip Technology Inc. DS20005287B-page 29
MCP3918
4.22 Measurement Error
The measurement error specification is typically used
in power metering applications. This specification is a
measurement of the linearity of the active energy of a
given power meter across its dynamic range.
For this measurement, the goal is to measure the
active energy of one phase when the voltage Root
Mean Square (RMS) value is fixed, and the current
RMS value is sweeping across the dynamic range
specified by the meter. The measurement error is the
nonlinearity error of the energy power across the cur-
rent dynamic range. It is expressed in percent (%).
Equation 4-12 shows the formula that calculates the
measurement error:
EQUATION 4-12:
In the present device, the calculation of the active
energy is done externally as a post-processing step that
typically happens in the microcontroller, considering, for
example, one ADC as current channel and the other
MCP3918 ADC as voltage channel. The voltage channel
is fed with a full-scale sine wave at 600 mV peak and is
configured with GAIN = 1 and DITHER = Maximum. To
obtain the active energy measurement error graphs, the
current channel is fed with sine waves with amplitudes
that vary from 600 mV peak to 60 µV peak, representing
a 10,000:1 dynamic range. The offset is removed on
both current and voltage channels, and the channels are
multiplied together to give instantaneous power. The
active energy is calculated by multiplying the current and
voltage channel, and averaging the results of this power
during 20 seconds to extract the active energy. The
sampling frequency is chosen as a multiple integer of
line frequency (coherent sampling). Therefore, the
calculation does not take into account any residue
coming from bad synchronization.
The measurement error is a function of IRMS and varies
with the OSR, averaging time and MCLK frequency,
and is tightly coupled with the noise and linearity
_specifications. The measurement error is a function of
the linearity and THD of the ADC, while the standard
deviation of the measurement error is a function of the
noise specification of the ADC. Overall, the low THD
specification enables low measurement error on a very
large dynamic range (e.g., 10,000:1). A low noise and
high SNR specification enables the decrease of the
measurement time, and therefore, of the calibration time
to obtain a reliable measurement error specification.
Figure 2-5 shows the typical measurement error curves
obtained with the samples acquired by the MCP3918,
using the default settings with 1-point and 2-point cali-
bration. These calibrations are detailed in Section 8.6
“Energy Measurement Error Considerations”.
Measurement Error IRMS
Measured Active Energy Active Energy present at inputs–
Active Energy present at inputs
-------------------------------------------------------------------------------------------------------------------------------------------- 1 0 0 %
=
MCP3918
DS20005287B-page 30 2014-2019 Microchip Technology Inc.
NOTES:
2014-2019 Microchip Technology Inc. DS20005287B-page 31
MCP3918
5.0 DEVICE OVERVIEW
5.1 Analog Inputs (CH0+/-)
The MCP3918 analog inputs can be connected directly
to current and voltage transducers (such as shunts,
Current Transformers or Rogowski coils). Each input
pin is protected by specialized ESD structures that
allow bipolar ±2V continuous voltage, with respect to
AGND, to be present at their inputs without the risk of
permanent damage.
The ADC has fully differential voltage inputs for better
noise performance. The absolute voltage at each pin,
relative to AGND, should be maintained in the ±1V
range during operation in order to ensure the specified
ADC accuracy. The Common-mode signals should be
adapted to respect both the previous conditions and
the differential input voltage range. For best
performance, the Common-mode signals should be
maintained to AGND.
5.2 Programmable Gain Amplifiers
(PGA)
The Programmable Gain Amplifier (PGA) resides at the
front end of the Delta-Sigma ADC. It has two functions:
translate the Common-mode voltage of the input from
AGND to an internal level between AGND and AVDD, and
amplify the input differential signal. The translation of
the Common-mode voltage does not change the differ-
ential signal, but recenters the Common-mode so that
the input signal can be properly amplified.
The PGA block can be used to amplify very low signals,
but the differential input range of the Delta-Sigma
modulator must not be exceeded. The PGA of the ADC
is controlled by the PGA_CH0[2:0] bits in the GAIN
register. Ta b l e 5 - 1 displays the gain settings for the PGA.
5.3 Delta-Sigma Modulator
5.3.1 ARCHITECTURE
The ADC includes a proprietary second-order modulator
with a multibit 5-level DAC architecture (see Figure 5-1).
The quantizer is a Flash ADC composed of four compar-
ators with equally spaced thresholds and a thermometer
output coding. The proprietary five-level architecture
ensures minimum quantization noise at the outputs of
the modulators, without disturbing linearity or inducing
additional distortion. The sampling frequency is DMCLK
(typically 1 MHz with MCLK = 4 MHz), so the modulators
are refreshed at a DMCLK rate.
Figure 5-1 represents a simplified block diagram of the
Delta-Sigma ADC present on the MCP3918.
FIGURE 5-1: Simplified Delta-Sigma ADC
Block Diagram.
Note: If the analog inputs are held to a potential
of -0.6 to -1V for extended periods of time,
MCLK must be present inside the device in
order to avoid large leakage currents at the
analog inputs. This is true even during
Hard Reset mode or during the Soft Reset
of the ADC. However, during the Shutdown
mode of the ADC or during the POR state,
the clock is not distributed inside the circuit.
During these states, it is recommended to
keep the analog input voltages above -0.6V,
referred to as AGND, in order to avoid high
analog input leakage currents.
TABLE 5-1: PGA CONFIGURATION
SETTING
GAIN Register
PGA_CH0[2:0]
Gain
(V/V)
Gain
(dB) VIN Range (V)
000 10±0.6
001 26±0.3
010 412±0.15
011 818±0.075
10016 24 ±0.0375
10132 30 ±0.01875
Note: The two undefined settings are G = 1. This
table is defined with VREF =1.2V.
Second-
Order
Integrator
Loop
Filter Quantizer
DAC
Differential
Voltage Input
Output
Bitstream
5-Level
Flash ADC
MCP3918 Delta-Sigma Modulator
MCP3918
DS20005287B-page 32 2014-2019 Microchip Technology Inc.
5.3.2 MODULATOR INPUT RANGE AND
SATURATION POINT
For a specified voltage reference value of 1.2V, the
modulator specified differential input range is ±600 mV.
The input range is proportional to VREF and scales
according to the VREF voltage. This range ensures the
stability of the modulator over amplitude and frequency.
Outside of this range, the modulator is still functional;
however, its stability is no longer ensured, and there-
fore, it is not recommended to exceed this limit. The
saturation point for the modulator is VREF/1.5, since the
transfer function of the ADC includes a gain of 1.5 by
default (independent from the PGA setting). See
Section 5.5 “ADC Output Coding”.
5.3.3 BOOST SETTINGS
The Delta-Sigma modulator includes a programmable
biasing circuit in order to further adjust the power
consumption to the sampling speed applied through
the MCLK. This can be programmed through the
BOOST[1:0] bits, which are applied to all channels
simultaneously.
The maximum achievable Analog Master Clock
(AMCLK) speed, the maximum sampling frequency
(DMCLK) and the maximum achievable data rate
(DRCLK) highly depend on the BOOST[1:0] and
PGA_CH0[2:0] bits settings. Ta b l e 5 - 2 specifies the
maximum AMCLK possible to keep optimal accuracy
with respect to the BOOST[1:0] and PGA_CH0[2:0]
settings.
TABLE 5-2: MAXIMUM AMCLK LIMITS AS A FUNCTION OF BOOST AND PGA GAIN
Conditions VDD = 3.0V to 3.6V,
TA from -40°C to +125°C
VDD = 2.7V to 3.6V,
TA from -40°C to +125°C
Boost Gain
Maximum AMCLK (MHz)
(SINAD within -3 dB
from its maximum)
Maximum AMCLK (MHz)
(SINAD within -5 dB
from its maximum)
Maximum AMCLK (MHz)
(SINAD within -3 dB
from its maximum)
Maximum AMCLK (MHz)
(SINAD within -5 dB
from its maximum)
0.5x 1 4 4 4 4
0.66x 1 6.4 7.3 6.4 7.3
1x 1 11.4 11.4 10.6 10.6
2x 1 16 16 16 16
0.5x 2 4 4 4 4
0.66x 2 6.4 7.3 6.4 7.3
1x 2 11.4 11.4 10.6 10.6
2x 2 16 16 13.3 14.5
0.5x 4 2.9 2.9 2.9 2.9
0.66x 4 6.4 6.4 6.4 6.4
1x 4 10.7 10.7 9.4 10.7
2x 4 16 16 16 16
0.5x 8 2.9 4 2.9 4
0.66x 8 7.3 8 6.4 7.3
1x 8 11.4 12.3 8 8.9
2x 8 16 16 10 11.4
0.5x 16 2.9 2.9 2.9 2.9
0.66x 16 6.4 7.3 6.4 7.3
1x 16 11.4 11.4 9.4 10.6
2x 16 13.3 16 8.9 11.4
0.5x 32 2.9 2.9 2.9 2.9
0.66x 32 7.3 7.3 7.3 7.3
1x 32 10.6 12.3 9.4 10,6
2x 32 13.3 16 10 11.4
2014-2019 Microchip Technology Inc. DS20005287B-page 33
MCP3918
5.3.4 DITHER SETTINGS
The modulator includes a dithering algorithm that can be
enabled through the DITHER[1:0] bits in the CONFIG0
register. This dithering process improves THD and
SFDR (for high OSR settings), while slightly increasing
the noise floor of the ADC. For power metering applica-
tions and applications that are distortion-sensitive, it is
recommended to keep DITHER at maximum settings for
best THD and SFDR performance. In the case of power
metering applications, THD and SFDR are critical
specifications. Optimizing SNR (noise floor) is not
problematic due to the large averaging factor at the out-
put of the ADC. Therefore, even for low OSR settings,
the dithering algorithm will show a positive impact on the
performance of the application.
5.3.5 MODULATOR OUTPUT BLOCK
If the user wishes to use the modulator output of the
device, the EN_MDAT bit in the STATUSCOM register
must be set to enable.
When the EN_MDAT bit is enabled, the modulator
output is present at the MDAT0 output pin as soon as
the command is placed. Additionally, the corresponding
SINC filter is disabled in order to consume less current.
The corresponding data ready pulse is not present
either at the DR output pin. When the EN_MDAT bit is
cleared, the SINC filter is back to normal operation and
the MDAT0 output is high-impedance. The Data Ready
output pin is then placed in high-impedance, regardless
of the DR_HIZ setting, so that the user can tie this pin
to an external supply or ground for lower noise
behavior.
Since the Delta-Sigma modulator has a five-level
output given by the state of the four comparators with
thermometer coding, its output can be represented on
four bits, each bit giving the state of the corresponding
comparator (see Tabl e 5 - 3). These bits are present in
the MOD register and are updated at the DMCLK rate.
In order to output the result of the comparator on a
separate pin (MDAT0), this comparator output bit has
been arranged to be serially output at the AMCLK rate
(see Figure 5-2).
This 1-bit serial bit stream is the same that would be
produced by a 1-bit DAC modulator with a sampling
frequency of AMCLK. The modulator can either be
considered as a five-level output at DMCLK rate or a
1-bit output at AMCLK rate. These two representations
are interchangeable. The MDAT0 output can therefore
be used in any application that requires 1-bit modulator
outputs. Such applications will often integrate and filter
the 1-bit output with SINC or more complex decimation
filters computed by an MCU or a DSP.
FIGURE 5-2: MDAT0 Serial Output with
Respect to the Modulator Output Code.
Since the Reset and shutdown SPI commands are
asynchronous, the MDAT0 pin is resynchronized with
DMCLK after each time the part goes out of Reset and
shutdown.
This means that after a Soft Reset or a shutdown, the
first output of MDAT0 is always ‘0011’ after the first
DMCLK rising edge.
The MDAT0 output pin is high-impedance if the RESET
pin is low and in 2-Wire Interface mode.
TABLE 5-3: DELTA-SIGMA MODULATOR
CODING
COMP[3:0]
Code
Modulator
Output Code
MDAT Serial
Stream
1111 +2 1111
0111 +1 0111
0011 00011
0001 -1 0001
0000 -2 0000
DMCLK
MDAT+2
MDAT+1
MDAT+0
MDAT-1
MDAT-2
COMP
AMCLK
[3] COMP
[2] COMP
[1] COMP
[0]
MCP3918
DS20005287B-page 34 2014-2019 Microchip Technology Inc.
5.4 SINC3 + SINC1 Filter
The decimation filter present in the MCP3918 is a
cascade of two SINC filters (SINC3 + SINC1): a
third-order SINC filter with a decimation ratio of OSR3,
followed by a first-order SINC filter with a decimation
ratio of OSR1 (moving average of OSR1 values).
Figure 5-3 represents the decimation filter architecture.
FIGURE 5-3: MCP3918 Decimation Filter Block Diagram.
Equation 5-1 calculates the filter z-domain transfer
function.
EQUATION 5-1: SINC FILTER TRANSFER
FUNCTION
Equation 5-2 calculates the settling time of the ADC as
a function of DMCLK periods.
EQUATION 5-2:
The SINC1 filter following the SINC3 filter is only enabled
for the high OSR settings. This SINC1 filter provides
additional rejection at a low cost with little modification to
the -3 dB bandwidth. The resolution (number of signifi-
cant bits) of the digital filter is 24-bit maximum for any
OSR and data format choice. The resolution depends
only on the OSR[2:0] settings in the CONFIG0 register
per Ta b l e 5 - 4 . Once the OSR is chosen, the resolution is
fixed and the output code respects the data format
defined by the WIDTH_DATA[1:0] setting in the
STATUSCOM register (see Section 5.5 “ADC Output
Coding”).
Modulator
Output
SINC
3
SINC
1
Decimation
Filter Output
OSR
3
OSR
1
416 (WIDTH = 0)
24 (WIDTH = 1)
Decimation Filter
OSR
1
=1
Hz
1z
- OSR3
–
3
OSR31z
1–
–
3
----------------------------------------------
1z
- OSR1OSR3
–
OSR11z
- OSR3
–
---------------------------------------------------------
=
Where z EXP 2
jf
in
DMCLK
=
SettlingTime DMCLKperiods3OSR
3
OSR11–OSR3
+=
2014-2019 Microchip Technology Inc. DS20005287B-page 35
MCP3918
The gain of the transfer function of this filter is one at
each multiple of DMCLK (typically 1 MHz), so a proper
anti-aliasing filter must be placed at the inputs. This will
attenuate the frequency content around DMCLK and
keep the desired accuracy over the baseband of the
converter. This anti-aliasing filter can be a simple,
first-order RC network, with a sufficiently low time
constant to generate high rejection at the DMCLK
frequency.
Any unsettled data are automatically discarded to avoid
data corruption. Each data ready pulse corresponds to
fully settled data at the output of the decimation filter.
The first data available at the output of the decimation
filter are present after the complete settling time of the
filter (see Table 5-4). After the first data have been
processed, the delay between two data ready pulses is
one DRCLK period. The data stream from input to
output is delayed by an amount equal to the settling
time of the filter (which is the group delay of the filter).
The resolution achievable, the -3 dB bandwidth and the
settling time at the output of the decimation filter (the
output of the ADC) are dependent on the OSR of each
SINC filter and are summarized in Tabl e 5-4.
FIGURE 5-4: SINC Filter Frequency
Response, OSR = 256, MCLK = 4 MHz,
PRE[1:0] = 00.
FIGURE 5-5: SINC Filter Frequency
Response, OSR = 4096 (in pink), OSR = 512 (in
blue), MCLK = 4 MHz, PRE[1:0] = 00.
TABLE 5-4: OVERSAMPLING RATIO AND SINC FILTER SETTLING TIME
OSR[2:0] OSR3OSR1Total OSR Resolution in Bits
(No Missing Code) Settling Time -3 dB Bandwidth
000 32 1 32 17 96/DMCLK 0.26 * DRCLK
001 64 1 64 20 192/DMCLK 0.26 * DRCLK
010 128 1 128 23 384/DMCLK 0.26 * DRCLK
011 256 1 256 24 768/DMCLK 0.26 * DRCLK
100 512 1 512 24 1536/DMCLK 0.26 * DRCLK
101 512 2 1024 24 2048/DMCLK 0.37 * DRCLK
110 512 4 2048 24 3072/DMCLK 0.42 * DRCLK
111 512 8 4096 24 5120/DMCLK 0.43 * DRCLK
-80
-60
-40
-20
0
a
gnitude (dB)
-120
-100
1 10 100 1000 10000 100000
M
a
Input Frequency (Hz)
-100
-80
-60
-40
-20
0
gnitude (dB)
-160
-140
-120
1 100 10000 1000000
Ma
Input Frequency (Hz)
MCP3918
DS20005287B-page 36 2014-2019 Microchip Technology Inc.
5.5 ADC Output Coding
The second-order modulator, SINC3 + SINC1 filter,
PGA, VREF and the analog input structure all work
together to produce the device transfer function for the
Analog-to-Digital conversion (see Equation 5-3).
The output data are calculated on 24-bit (23-bit plus
sign) and coded in two’s complement format, MSB first.
The output format can then be modified by the
WIDTH_DATA[1:0] settings in the STATUSCOM
register to allow 16, 24 or 32-bit format compatibility
(see Section 9.5 “STATUSCOM Register – Status
and Communication Register” for more information).
In case of positive saturation (CH0+ – CH0- > VREF/1.5),
the output code is locked to 7FFFFF for 24-bit mode. In
case of negative saturation (CH0+ – CH0- < -VREF/1.5),
the output code is locked to 800000 for 24-bit mode.
Equation 5-3 is only true for DC inputs. For AC inputs,
this transfer function needs to be multiplied by the
transfer function of the SINC3 + SINC1 filter (see
Equations 5-1 and 5-3).
EQUATION 5-3:
For data formats other than the default 24-bit format,
Equation 5-3 should be multiplied by a scaling factor,
depending on the data format used (defined by
WIDTH_DATA[1:0]). The data format and the associated
scaling factors are given in Figure 5-6.
FIGURE 5-6: Output Data Formats.
For 24-Bit Mode, WIDTH_DATA[1:0] = 01 (Default)
DATA_CH0 CHn+ CHn-
–
VREF+ VREF-
–
-------------------------------------
8388608
G
1.5
=
DATA
<7>
WIDTH_DATA[1:0] = 11
32-Bit with Sign Extension DATA
[23] DATA
[23:16]
31 0
DATA
[15:8] DATA
[7:0]
WIDTH_DATA[1:0] = 10
32-Bit with Zeros Padded 0x00
31 0
DATA
[23:16] DATA
[7:0]
DATA
[15:8]
WIDTH_DATA[1:0] = 01
24-Bit DATA
[23:16] DATA
[15:8] DATA
[7:0]
23 0
WIDTH_DATA[1:0] = 00
16-Bit DATA
[15:8]
15 0
DATA
[23:16]
Rounded
Unformatted ADC Data DATA
[23:16] DATA
[15:8] DATA
[7:0]
23 0
x1/256
x1
x256
x1
Scaling
Factor
2014-2019 Microchip Technology Inc. DS20005287B-page 37
MCP3918
The ADC resolution is a function of the OSR
(Section 5.4 “SINC3 + SINC1 Filter”). The resolution is
the same for all channels. No matter what the resolution
is, the ADC output data are always calculated in 24-bit
words, with added zeros at the end if the OSR is not
large enough to produce 24-bit resolution (left
justification).
TABLE 5-5: OSR = 256 (AND HIGHER) OUTPUT CODE EXAMPLES
ADC Output Code (MSB First) Hexadecimal Decimal,
24-Bit Resolution
0111 1111 1111 1111 1111 1111 0x7FFFFF + 8,388,607
0111 1111 1111 1111 1111 1110 0x7FFFFE + 8,388,606
0000 0000 0000 0000 0000 0000 0x000000 0
1111 1111 1111 1111 1111 1111 0xFFFFFF – 1
1000 0000 0000 0000 0000 0001 0x800001 – 8,388,607
1000 0000 0000 0000 0000 0000 0x800000 – 8,388,608
TABLE 5-6: OSR = 128 OUTPUT CODE EXAMPLES
ADC Output Code (MSB First) Hexadecimal Decimal,
23-Bit Resolution
0111 1111 1111 1111 1111 11100x7FFFFE + 4,194,303
0111 1111 1111 1110 1111 11000x7FFFFC + 4,194,302
0000 0000 0000 0000 0000 0000 0x000000 0
1111 1111 1111 1111 1111 11100xFFFFFE – 1
1000 0000 0000 0000 0000 00100x800002 – 4,194,303
1000 0000 0000 0000 0000 00000x800000 – 4,194,304
TABLE 5-7: OSR = 64 OUTPUT CODE EXAMPLES
ADC Output Code (MSB First) Hexadecimal Decimal,
20-Bit Resolution
0111 1111 1111 1111 1111 0 0 0 0 0x7FFFF0 + 524, 287
0111 1111 1111 1111 1110 0 0 0 0 0x7FFFE0 + 524, 286
0000 0000 0000 0000 0000 0 0 0 0 0x000000 0
1111 1111 1111 1111 1111 0 0 0 0 0xFFFFF0 – 1
1000 0000 0000 0000 0001 0 0 0 0 0x800010 – 524,287
1000 0000 0000 0000 0000 0 0 0 0 0x800000 – 524, 288
TABLE 5-8: OSR = 32 OUTPUT CODE EXAMPLES
ADC Output Code (MSB First) Hexadecimal Decimal,
17-Bit Resolution
0111 1111 1111 1111 1000 0000 0x7FFF80 + 65, 535
0111 1111 1111 1111 0000 0000 0x7FFF00 + 65, 534
0000 0000 0000 0000 0000 0000 0x000000 0
1111 1111 1111 1111 1000 0000 0xFFFF80 – 1
1000 0000 0000 0000 1000 0000 0x800080 – 65,535
1000 0000 0000 0000 0000 0000 0x800000 – 65, 536
MCP3918
DS20005287B-page 38 2014-2019 Microchip Technology Inc.
5.6 Voltage Reference
5.6.1 INTERNAL VOLTAGE REFERENCE
The MCP3918 contains an internal voltage reference
source specially designed to minimize drift over tempera-
ture. In order to enable the internal voltage reference, the
VREFEXT bit in the CONFIG1 register must be set to ‘0’
(Default mode). This internal VREF supplies reference
voltage to all channels. The typical value of this voltage
reference is 1.2V, ±2%. The internal reference has a very
low typical temperature coefficient of ±7 ppm/°C, allowing
the output to have minimal variation with respect to
temperature, since they are proportional to (1/VREF).
The noise of the internal voltage reference is low
enough not to significantly degrade the SNR of the
ADC if compared to a precision external low noise
voltage reference. The output pin for the internal
voltage reference is REFIN+/OUT.
If the voltage reference is only used as an internal
VREF
, adding bypass capacitance on REFIN+/OUT is
not necessary for keeping ADC accuracy, but a minimal
0.1 µF ceramic capacitance can be connected to avoid
EMI/EMC susceptibility issues due to the antenna,
created by the REFIN+/OUT pin, if left floating.
The bypass capacitors also help in applications where
the voltage reference output is connected to other cir-
cuits. In this case, additional buffering may be needed,
since the output drive capability of this output is low.
Adding too much capacitance on the REFIN+/OUT pin
may slightly degrade the THD performance of the ADC.
5.6.2 DIFFERENTIAL EXTERNAL
VOLTAGE INPUTS
When the VREFEXT bit is set to ‘1’, the two reference
pins (REFIN+/OUT, REFIN-) become a differential volt-
age reference input. The voltage at the REFIN+/OUT is
noted VREF+ and the voltage at the REFIN- pin is noted
VREF-. The differential voltage input value is given by
Equation 5-4.
EQUATION 5-4:
The specified VREF range is from 1.1V to 1.3V. The
REFIN- pin voltage (VREF-) should be limited to ±0.1V,
with respect to AGND. Typically, for single-ended refer-
ence applications, the REFIN- pin should be directly
connected to AGND, with its own separate track, to
avoid any spike due to switching noise.
5.6.3 TEMPERATURE COMPENSATION
(VREFCAL[7:0])
The internal voltage reference consists of a proprietary
circuit and algorithm to compensate for first-order and
second-order temperature coefficients. The compensa-
tion enables very low-temperature coefficients (typically
9 ppm/°C) on the entire range of temperatures, from
-40°C to +125°C. This temperature coefficient varies
from part to part.
This temperature coefficient can be adjusted on each part
through the VREFCAL[7:0] bits present in the CONFIG0
register (bits 7 to 0). These register settings are only for
advanced users. The VREFCAL[7:0] bits should not be
modified unless the user wants to calibrate the tempera-
ture coefficient of the whole system or application. The
default value of this register is set to 0x50. The default
value (0x50) was chosen to optimize the standard devia-
tion of the tempco across process variation. The value
can be slightly improved to around 7 ppm/°C if the
VREFCAL[7:0] bits are written at 0x42, but this setting
degrades the standard deviation of the VREF tempco.
The typical variation of the temperature coefficient of the
internal voltage reference, with respect to the VREFCAL
register code, is given by Figure 5-6. Modifying the value
stored in the VREFCAL[7:0] bits may also vary the voltage
reference, in addition to the temperature coefficient.
FIGURE 5-7: VREF Tempco vs. VREFCAL
Trim Code Chart.
5.6.4 VOLTAGE REFERENCE BUFFER
The MCP3918 ADC includes a voltage reference buffer
tied to the REFIN+/OUT pin, which allows the device to
properly charge the internal capacitors with the voltage
reference signals, even in the case of an external
voltage reference connection with weak load regulation
specifications. This ensures that the correct amount of
current is sourced to each channel to guarantee their
accuracy specifications, and diminishes the constraints
on the voltage reference load regulation.
VREF =V
REF+–V
REF-
0
10
20
30
40
50
60
0 64 128 192 256
V
REF
Drift (ppm)
V
REFCAL
Register Trim Code (Decimal)
2014-2019 Microchip Technology Inc. DS20005287B-page 39
MCP3918
5.7 Power-on Reset
The MCP3918 contains an internal POR circuit that
monitors both analog and digital supply voltages during
operation. The typical threshold for a power-up event
detection is 2.0V, ±5% and a typical start-up time (tPOR)
of 50 µs. The POR circuit has a built-in hysteresis for
improved transient spike immunity that has a typical
value of 200 mV. Proper decoupling capacitors (0.1 µF
ceramic and 10 µF) should be mounted as close as
possible to the AVDD and DVDD pins, providing
additional transient immunity.
Figure 5-8 illustrates the different conditions at a
power-up and a power-down event under typical condi-
tions. All internal DC biases are settled at least 1 ms
after a system POR, under worst-case conditions. In
order to ensure proper accuracy, any data ready pulse
occurring within 1 ms, plus the SINC filter settling time
after system Reset, should be ignored. After POR, data
ready pulses are present at the pin with all the default
conditions in the Configuration registers.
Both AVDD and DVDD are monitored, so either power
supply can sequence first.
FIGURE 5-8: Power-on Reset Operation.
Note: In order to ensure a proper power-up
sequence, the ramp rate of DVDD should
not exceed 3V/µs when coming out of the
POR state.
Additionally, the user should try to lower
the DVDD residual voltage, as close to 0V
as possible, when the device is kept in a
POR state (below DVDD POR threshold)
for a long time to ensure a proper power-
up sequence. The user can verify if the
power-up sequence has been correctly
performed by reading the default state of
all the registers in the register map right
after powering up the device. If one or
more of the registers do not show the
proper default settings when being read, a
new power-up cycle should be launched
to recover from this condition.
POR
State Power-up Normal POR
State
Biases are
unsettled.
Conversions
started here may
not be accurate
Biases are settled.
Conversions started
here are accurate.
Analog Biases
Settling Time
SINC Filter
Settling
Time
Voltage
(AVDD, DVDD)
Time
POR Threshold
Up (2.0V typical)
(1.8V typical)
tPOR
Operation
Any data read pulse occurring
during this time can yield
inaccurate output data. It is
recommended to discard them.
MCP3918
DS20005287B-page 40 2014-2019 Microchip Technology Inc.
5.8 Hard Reset Effect on Delta-Sigma
Modulator/SINC Filter
In SPI mode, when the RESET pin is logic low, the ADC
will be in Reset and the output code is 0x0000h. The
RESET pin performs a Hard Reset (DC biases are still
on, part is ready to convert) and clears all charges con-
tained in the Delta-Sigma modulator. The comparator’s
output is ‘0011’ for the ADC.
The SINC filter is reset, as well as its double-output
buffers. This pin is independent of the serial interface.
It brings all the registers to the default state. When
RESET is logic low, any write with the SPI interface will
be disabled and will have no effect. All output pins
(SDO, DR) are high-impedance.
If MCLK is applied, the input structure is enabled and is
properly biasing the substrate of the input transistors.
In this case, the leakage current on the analog inputs is
low if the analog input voltages are kept between -1V
and +1V.
If MCLK is not applied when in Reset mode, the
leakage can be high if the analog inputs are below
-0.6V, as referred to AGND.
5.9 Phase Delay Block
The MCP3918 incorporates a phase delay generator,
which ensures the ADC (CH0) converts the inputs after
a fixed delay as determined by the PHASE register
setting.
The PHASE register contains a 12-bit bank that
represents a group delay of the ADC channel (in addition
to the settling time of the SINC filter), expressed in
DMCLK periods, with an offset of OSR/2 periods. It is
coded with an 11-bit plus sign, MSB first, two’s comple-
ment code. This code indicates how many DMCLK
periods are induced as a delay (see Equation 5-5).
EQUATION 5-5:
The timing resolution of the phase delay is 1/DMCLK or
1 µs in the default configuration with MCLK = 4 MHz.
Given the definition of DMCLK, the phase delay is
affected by a change in the prescaler settings
(PRE[1:0]) and the MCLK frequency. The data ready
signal is affected by the phase delay settings.
5.9.1 PHASE DELAY LIMITS
The limits of the phase delays are determined by the
OSR settings: the phase delays can only go from 0 to
+(OSR-1) DMCLK periods when taking the last Reset
as a reference (same definition as MCP391X, but not
showing an odd channel reference here since there is
only one channel).
If larger delays are needed, they can be implemented
externally to the chip with an MCU. A FIFO in the MCU
can save incoming data from the ADC channel for a
number N of DRCLK clocks. In this case, DRCLK
would represent the coarse timing resolution and
DMCLK, the fine timing resolution. The total delay will
then be equal to:
EQUATION 5-6:
The Phase Delay register can be programmed once
with the OSR = 4096 setting and will automatically
adjust the OSR afterwards without the need to change
the value of the PHASE register.
•OSR = 4096: The delay can go from 0 to +4095.
PHASE[11] is the sign bit. Phase[10] is the MSB
and PHASE[0] the LSB.
•OSR = 2048: The delay can go from 0 to +2047.
PHASE[10] is the sign bit. Phase[9] is the MSB
and PHASE[0] the LSB.
•OSR = 1024: The delay can go from 0 to +1023.
PHASE[9] is the sign bit. Phase[8] is the MSB and
PHASE[0] the LSB.
•OSR = 512: The delay can go from 0 to +511
PHASE[8] is the sign bit. Phase[7] is the MSB and
PHASE[0] the LSB.
•OSR = 256: The delay can go from 0 to +255.
PHASE[7] is the sign bit. Phase[6] is the MSB and
PHASE[0] the LSB.
•OSR = 128: The delay can go from 0 to +127.
PHASE[6] is the sign bit. Phase[5] is the MSB and
PHASE[0] the LSB.
•OSR = 64: The delay can go from 0 to +63.
PHASE[5] is the sign bit. Phase[4] is the MSB and
PHASE[0] the LSB.
•OSR = 32: The delay can go from 0 to +31.
PHASE[4] is the sign bit. Phase[3] is the MSB and
PHASE[0] the LSB.
Total Delay
PHASE<11:0> Decimal Code OSR
2
-----------+
DMCLK
--------------------------------------------------------------------------------------------=
Note: Rewriting the PHASE register with the
same value automatically resets and
restarts the ADC.
Total Delay = N/DRCLK + OSR/2/DMCLK
2014-2019 Microchip Technology Inc. DS20005287B-page 41
MCP3918
5.10 Data Ready Status Bit
In addition to the DR pin indicator, the MCP3918 device
includes a separate data ready status bit. The ADC
channel is associated with the corresponding
DRSTATUS bit that can be read at all times in the
STATUSCOM register. This status bit can be used to
synchronize the data retrieval in case the DR pin is not
connected (see Section 6.8 “ADC Channel Latching
and Synchronization”).
The DRSTATUS bit is not writable; writing on it has no
effect. It has a default value of ‘1’, which indicates that
the data of the corresponding ADC are not ready. This
means that the ADC Output register has not been
updated since the last reading (or since the last Reset).
The DRSTATUS bit takes the ‘0’ state once the ADC
channel register is updated (which happens at a DRCLK
rate). A simple read of the STATUSCOM register clears
the DRSTATUS bit to its default value (‘1’).
5.11 Crystal Oscillator
The MCP3918 includes a Pierce-type crystal oscillator
with very high stability and ensures very low tempco and
jitter for the clock generation. This oscillator can handle
crystal frequencies up to 20 MHz, provided that proper
load capacitances and quartz quality factor are used.
The crystal oscillator is enabled when CLKEXT = 0 in the
CONFIG1 register, therefore, it cannot be enabled
during the 2-Wire Interface mode; it is only selectable in
the SPI Mode.
For a proper start-up, the load capacitors of the crystal
should be connected between OSC1 and DGND and
between OSC2 and DGND. They should also respect
Equation 5-7.
EQUATION 5-7:
When CLKEXT = 1, the crystal oscillator is bypassed
by a digital buffer to allow direct clock input for an
external clock (see Figure 4-1). In this case, OSC2
becomes the MODE select input pin for the Interface
mode. When MODE = 0, the digital interface stays in
SPI mode; when MODE = 1, the digital interface
toggles to the 2-Wire mode. A pull-down current forces
the MODE to be logic low (SPI mode) by default if the
OSC2 pin is floating.
For proper operation, the external clock should not be
higher than 20 MHz before prescaling (MCLK < 20 MHz).
TABLE 5-9: PHASE VALUES WITH
MCLK = 4 MHz, OSR = 4096,
PRE[1:0] = 00
PHASE[11:0] Hex Delay
011111111111 0x7FF 4095 µs
011111111110 0x7FE 4094 µs
000000000001 0x001 2049 µs
000000000000 0x000 2048 µs
111111111111 0xFFF 2047 µs
100000000001 0x801 1 µs
100000000000 0x800 0 µs
Note: In addition to the conditions defining the
maximum MCLK input frequency range, the
AMCLK frequency should be maintained
inferior to the maximum limits, defined in
Ta b l e 5 - 2 , to ensure the accuracy of the
ADC. If these limits are exceeded, it is
recommended to choose either a larger
OSR or a larger prescaler value, so that
AMCLK can respect these limits.
RM1.6 106
1
fCLOAD
-------------------------
2
<
Where:
f = Crystal frequency in MHz
CLOAD = Load capacitance in pF, including
parasitics from the PCB
RM= Motional resistance of the quartz in ohms
MCP3918
DS20005287B-page 42 2014-2019 Microchip Technology Inc.
5.12 Digital System Offset and Gain
Errors
The MCP3918 incorporates two sets of additional
registers to perform system digital offset and gain error
calibration, which will modify the output result of the
channel if calibration is enabled. The gain and offset
calibrations can be enabled or disabled through two
Configuration bits (EN_OFFCAL and EN_GAINCAL).
When both calibrations are enabled, the output of the
ADC is modified per Equation 5-8. These calibrations
are not effective in 2-Wire Interface mode.
EQUATION 5-8: DIGITAL OFFSET AND GAIN ERROR CALIBRATION REGISTERS CALCULATIONS
5.12.1 DIGITAL OFFSET ERROR
CALIBRATION
The OFFCAL_CH0 register is a 23-bit plus sign two’s
complement register, whose LSB value is the same as
the channel ADC data. This register is then added, bit-
by-bit, to the ADC output codes if the EN_OFFCAL bit
is enabled. Enabling the EN_OFFCAL bit does not
create a pipeline delay; the offset addition is instanta-
neous. For low OSR values, only the significant digits
are added to the output (up to the resolution of the
ADC; for example, at OSR = 32, only the first 17 bits are
added).
The offset is not added when the corresponding chan-
nel is in Reset or Shutdown mode. The corresponding
input voltage offset value added by each LSB in these
24-bit registers is:
EQUATION 5-9:
This register is a “Don’t Care” if EN_OFFCAL = 0
(offset calibration disabled), but its value is not cleared
by the EN_OFFCAL bit.
5.12.2 DIGITAL GAIN ERROR
CALIBRATION
This register is a signed 24-bit, MSB first register coded
with a range of -1x to +(1 – 2-23)x (from 0x800000 to
0x7FFFFF). The gain calibration adds 1x to this register
and multiplies it to the output code of the channel, bit-by-
bit, after offset calibration. Thus, the gain calibration
ranges from 0x to 1.9999999x (from 0x80000 to
0x7FFFFF). The LSB corresponds to a 2-23 increment in
the multiplier.
Enabling EN_GAINCAL creates a pipeline delay of
24 DMCLK periods on all channels. All data ready
pulses are delayed by 24 DMCLK periods, starting from
the data ready pulse following the command enabling
the EN_GAINCAL bit. The gain calibration is effective
on the next data ready pulse following the command
enabling the EN_GAINCAL bit.
The digital gain calibration does not function when the
corresponding channel is in Reset or Shutdown mode.
The gain multiplier value for an LSB in this 24-bit
register is:
EQUATION 5-10:
This register is a “Don’t Care” if EN_GAINCAL = 0
(offset calibration disabled), but its value is not cleared
by the EN_GAINCAL bit.
The output data are kept to either 7FFF or 8000 (16-bit
mode), or 7FFFFF or 800000 (24-bit mode) if the
output results are out of bounds after all calibrations are
performed.
DATA_CH0 post cal–DATA_CH0 pre cal–OFFCAL_CH0+1 GAINCAL_CH0+
=
OFFSET(1LSB) = VREF/(PGA_CHn x 1.5 x 8388608)
GAIN (1LSB) = 1/8388608
2014-2019 Microchip Technology Inc. DS20005287B-page 43
MCP3918
6.0 SPI SERIAL INTERFACE
DESCRIPTION
6.1 Overview
The MCP3918 device includes a four-wire (CS, SCK,
SDI, SDO) digital serial interface that is compatible with
SPI Modes 0,0 and 1,1. Data are clocked out of the
MCP3918 on the falling edge of SCK and data are
clocked into the MCP3918 on the rising edge of SCK. In
these modes, the SCK clock can Idle either high (1,1) or
low (0,0). The digital interface is asynchronous with the
MCLK clock that controls the ADC sampling and digital
filtering. All the digital input pins are Schmitt triggered to
avoid system noise perturbations on the communications.
Each independent SPI communication starts with a CS
falling edge and stops with the CS rising edge. When
CS is logic high, SDO is in high-impedance, there are
transitions on SCK and SDI has no effect. Changing
from an SPI Mode 1,1 to an SPI Mode 0,0 and vice
versa is possible, and can be done while the CS pin is
logic high. Any CS rising edge clears the communication
and resets the SPI digital interface.
Additional control pins (RESET, DR) are also provided
on separate pins for advanced communication
features. The Data Ready pin (DR) outputs pulses
when new ADC channel data are available for reading,
which can be used as an interrupt for an MCU. The
Master Reset pin (RESET) acts like a Hard Reset and
can reset the part to its default power-up configuration
(equivalent to a POR state).
The MCP3918 interface has a simple command struc-
ture. Every command is either a READ command from a
register or a WRITE command to a register. The
MCP3918 device includes nine registers defined in the
register map in Ta b l e 9 - 1. The register map is fully
compatible with the MCP391X family to allow easy porting
of MCU code from one design to another inside the
MCP391X family. The first byte (8-bit wide) transmitted is
always the control byte that defines the address of the
register and the type of command (READ or WRITE). It is
followed by the register itself, which can be in a 16, 24 or
32-bit format, depending on the multiple format settings
defined in the STATUSCOM register. The MCP3918 is
compatible with multiple formats that help reduce over-
head in the data handling for most MCUs and processors
available on the market (8, 16 or 32-bit MCUs) and
improve MCU code compaction and efficiency.
The MCP3918 digital interface is capable of handling
various continuous Read and Write modes, which allow
the device to perform ADC data streaming or full
register map writing within only one communication
(and therefore, with only one unique control byte). The
internal registers can be grouped together with various
configurations through the READ[1:0] and WRITE bits.
The internal address counter of the serial interface can
be automatically incremented with no additional control
byte needed in order to loop through the various groups
of registers within the register map. The groups are
defined in Tabl e 9 - 2 .
The MCP3918 device also includes advanced security
features. These features secure each communication,
to avoid processing unwanted WRITE commands in
order to change the desired configuration, and to alert
the user in case of a change in the desired configuration.
Each SPI read communication can be secured through
a selectable CRC-16 checksum provided on the SDO
pin at the end of every communication sequence. This
CRC-16 computation is compatible with the DMA CRC
hardware of the PIC24 and PIC32 MCUs, resulting in
no additional overhead for added security.
In order to secure the entire configuration of the device,
the MCP3918 includes an 8-bit lock code (LOCK[7:0]),
which blocks all WRITE commands to the full register map
if the value of the LOCK[7:0] is not equal to a defined
password (0xA5). The user can protect its configuration
by changing the LOCK[7:0] value to 0x00 after the full pro-
gramming, so that no unwanted WRITE command will
result in a change in the configuration (because the
LOCK[7:0] bits are different from the 0xA5 password).
An additional CRC-16 calculation is also running
continuously in the background to ensure the integrity of
the full register map. All writable registers of the register
map (except for the MOD register) are processed
through a CRC-16 calculation engine and give a
CRC-16 checksum that depends on the configuration.
This checksum is readable on the LOCK/CRC register
and updated at all times. If a change in this checksum
occurs, a selectable interrupt can give a flag on the DR
pin (the DR pin becomes logic low) to warn the user that
the configuration is corrupted.
6.2 Control Byte
The control byte of the MCP3918 contains two device
Address bits (A[6:5]), five register Address bits (A[4:0])
and a Read/Write bit (R/W). The first byte transmitted
to the MCP3918 in any communication is always the
control byte. During the control byte transfer, the SDO
pin is always in a high-impedance state. The MCP3918
interface is device-addressable (through A[6:5]), so
that multiple chips can be present on the same SPI bus
with no data bus contention, even if they use the same
CS pin and a provided half-duplex SPI interface with a
different address identifier. This functionality enables,
for example, a serial EEPROM, such as 24AAXXX/
24LCXXX or 24FCXXX. Moreover, it enables the
MCP3918 to share all the SPI pins and to consume
less I/O pins in the application processor, since all
these serial EEPROM circuits use A[6:5] = 00.
FIGURE 6-1: Control Byte.
A[6] A[5] A[4] A[3] A[2] A[1] A[0] R/W
Device
Address
Register Address Read/
Write
MCP3918
DS20005287B-page 44 2014-2019 Microchip Technology Inc.
The default device address bits are A[6:5] = 01
(contact the Microchip factory for other available
device address bits). For more information, see the
Product Identification System section. The register
map is defined in Ta bl e 9 - 1 .
6.3 Reading from the Device
The first register read on the SDO pin is the one defined
by the address (A[4:0]) given in the control byte. After
this first register is fully transmitted, if the CS pin is
maintained logic low, the communication continues
without an additional control byte and the SDO pin
transmits another register with the address automatically
incremented.
Four different Read mode configurations can be defined
through the READ[1:0] bits in the STATUSCOM register
for the address increment (see Section 6.5 “Continu-
ous Communications, Looping on Register Sets”
and Table 9-2). The data on SDO are clocked out of the
MCP3918 on the falling edge of SCK. The reading
format for each register is defined in Section 5.5 “ADC
Output Coding”.
FIGURE 6-2: Read on a Single Register with 24-Bit Format (WIDTH_DATA[1:0] = 01,
SPI Mode 1,1).
FIGURE 6-3: Read on a Single Register with 24-Bit Format (WIDTH_DATA[1:0] = 01,
SPI Mode 0,0).
Read Communication (SPI Mode 1,1)
Don’t careDon’t care
A[6]
DATA[22]
SCK
SDI
SDO
A[5]
A[4]
A[3]
A[2]
A[1]
A[0]
CS
DATA[21]
DATA[20]
DATA[19]
DATA[18]
DATA[17]
DATA[16]
DATA[15]
DATA[14]
DATA[13]
DATA[12]
DATA[11]
DATA[10]
DATA[9]
DATA[8]
DATA[7]
DATA[6]
DATA[5]
DATA[4]
DATA[3]
DATA[2]
DATA[1]
DATA[0]
High-Z High-Z
Device latches SDI on rising edge Device latches SDO on falling edge
R/W
DATA[23]
Read Communication (SPI Mode 0,0)
Don’t careDon’t care
Don’t care
A[6]
DATA[22]
SCK
SDI
SDO
A[5]
A[4]
A[3]
A[2]
A[1]
A[0]
R/W
CS
DATA[23]
DATA[21]
DATA[20]
DATA[19]
DATA[18]
DATA[17]
DATA[16]
DATA[15]
DATA[14]
DATA[13]
DATA[12]
DATA[11]
DATA[10]
DATA[9]
DATA[8]
DATA[7]
DATA[6]
DATA[5]
DATA[4]
DATA[3]
DATA[2]
DATA[1]
DATA[0]
High-Z High-Z
Device latches SDI on rising edge Device latches SDO on falling edge
2014-2019 Microchip Technology Inc. DS20005287B-page 45
MCP3918
6.4 Writing to the Device
The first register written from the SDI pin to the device
is the one defined by the address (A[4:0]) given in the
control byte. After this first register is fully transmitted,
if the CS pin is maintained logic low, the communication
continues without an additional control byte and the
SDI pin transmits another register with the address
automatically incremented.
Two different Write mode configurations for the address
increment can be defined through the WRITE bit in the
STATUSCOM register (see Section 6.5 “Continuous
Communications, Looping on Register Sets” and
Table 9-2). The SDO pin stays in a high-impedance state
during a write communication. The data on SDI are
clocked into the MCP3918 on the rising edge of SCK.
The writing format for each register is defined in
Section 5.5 “ADC Output Coding”. A write on an
undefined or nonwritable address, such as the ADC
Channel register address, will have no effect nor will it
increment the address counter.
FIGURE 6-4: Write to a Single Register with 24-Bit Format (WIDTH_CRC = 0, SPI Mode 1,1).
FIGURE 6-5: Write to a Single Register with 24-Bit Format (WIDTH_CRC = 0, SPI Mode 0,0).
Write Communication (SPI Mode 1,1)
Don’t care
A[6]
SCK
SDI
SDO
A[5]
A[4]
A[3]
A[2]
A[1]
A[0]
CS
High-Z
Device latches SDI on rising edge
R/W
DATA[22]
DATA[21]
DATA[20]
DATA[19]
DATA[18]
DATA[17]
DATA[16]
DATA[15]
DATA[14]
DATA[13]
DATA[12]
DATA[11]
DATA[10]
DATA[9]
DATA[8]
DATA[7]
DATA[6]
DATA[5]
DATA[4]
DATA[3]
DATA[2]
DATA[1]
DATA[23]
Don’t
care
DATA[0]
Write Communication (SPI Mode 0,0)
Don’t care
A[6]
SCK
SDI
SDO
A[5]
A[4]
A[3]
A[2]
A[1]
A[0]
R/W
CS
High-Z
Device latches SDI on rising edge
Don’t care
DATA[22]
DATA[23]
DATA[21]
DATA[20]
DATA[19]
DATA[18]
DATA[17]
DATA[16]
DATA[15]
DATA[14]
DATA[13]
DATA[12]
DATA[11]
DATA[10]
DATA[9]
DATA[8]
DATA[7]
DATA[6]
DATA[5]
DATA[4]
DATA[3]
DATA[2]
DATA[1]
DATA[0]
MCP3918
DS20005287B-page 46 2014-2019 Microchip Technology Inc.
6.5 Continuous Communications,
Looping on Register Sets
The MCP3918 digital interface can process communi-
cations in Continuous mode, without having to enter an
SPI command between each read or write to a register.
This feature allows the user to reduce communication
overhead to the strict minimum, which diminishes EMI
emissions and reduces switching noise in the system.
The registers can be grouped into multiple sets for
continuous communications. The grouping of the
registers in the different sets is defined by the
READ[1:0] and WRITE bits that control the internal SPI
Communication Address Pointer. For a graphical
representation of the register map sets in the function of
the READ[1:0] and WRITE bits, please see Table 9-2.
In the case of a continuous communication, there is
only one control byte on SDI to start the communication
after a CS pin falling edge. The part stays within the
same communication loop until the CS pin returns logic
high. The SPI internal Register Address Pointer starts
by transmitting/receiving the address defined in the
control byte. After this first transmission/reception, the
SPI internal Register Address Pointer automatically
increments to the next available address in the register
set for each transmission/reception. When it reaches
the last address in the set, the communication
sequence is finished. The Address Pointer loops auto-
matically back to the first address of the defined set and
restarts a new sequence with auto-increment (see
Table 6-6). The undefined or unused addresses are
automatically jumped by the Address Pointer (they are
not considered to be part of the register map by the
Address Pointer). This internal Address Pointer
automatic selection allows the following functionality:
• Read one ADC channel data continuously
• Continuously read the entire register map
• Continuously read or write each separate register
• Continuously read or write all Configuration
registers
FIGURE 6-6: Continuous Communication Sequences.
Don’t care
Continuous Read Communication (24-bit format)
Don’t care
SCK
SDI
SDO
CS
High-Z
8x
CONTROL
BYTE
24x
ADDR ... ADDR + n
Starts Read Sequence
at Address ADDR
Complete Read Sequence
ADDR + 1
24x ... 24x 24x
ADDR ...
Complete Read Sequence
ADDR + 1
24x ... 24x
ADDR + n
Continuous Write Communication (24-bit format)
Don’t care
SCK
SDI
SDO
CS
High-Z
8x
CONTROL
BYTE
24x
ADDR ... ADDR + n
Starts Write Sequence
at Address ADDR
Complete Write Sequence
ADDR + 1
24x ... 24x 24x
ADDR ...
Complete Write Sequence
ADDR + 1
24x ... 24x
ADDR + n
ADDR
ADDR + 1
...
ADDR + n
Complete
Read
Sequence
Rollover
ADDRESS SET
ADDR
ADDR + 1
...
ADDR + n
Complete
Write
Sequence
Rollover
ADDRESS SET
2014-2019 Microchip Technology Inc. DS20005287B-page 47
MCP3918
6.5.1 CONTINUOUS READ
The STATUSCOM register contains the loop settings for
the internal Register Address Pointer (READ[1:0] bits and
WRITE bit). For the Continuous Read modes, the
address selection can take the four following values:
No SDI data coming after the control byte are considered
during a continuous read communication. The following
figures represent a typical continuous read communi-
cation with the default settings (READ[1:0] = 10,
WIDTH_DATA[1:0] = 01) for SPI Mode 0,0 (Figure 6-7)
and SPI Mode 1,1 (Figure 6-8).
In SPI Mode (1,1), the SDO pin stays in the last state
(LSB of previous data) after a complete reading, which
also allows seamless Continuous Read mode (see
Figure 6-8).
FIGURE 6-7: Typical Continuous Read Communication (WIDTH_DATA[1:0] = 01, SPI Mode 0,0).
FIGURE 6-8: Typical Continuous Read Communication (WIDTH_DATA[1:0] = 01, SPI Mode 1,1).
TABLE 6-1: ADDRESS SELECTION IN
CONTINUOUS READ
READ[1:0]
Register Address Set Grouping
for Continuous Read
Communications
00 Static (no incrementation)
01 Groups
10 Types (default)
11 Full Register Map
Note: For continuous reading of ADC data in
SPI Mode 0,0 (see Figure 6-7), once the
data have been completely read after a
data ready pulse, the SDO pin will take the
MSB value of the previous data at the end
of the reading (falling edge of the last SCK
clock). If SCK stays Idle at logic low (by
definition of Mode 0,0), the SDO pin will
be updated at the falling edge of the next
data ready pulse (synchronously with the
DR pin falling edge with an output timing
of tDODR) with the new MSB of the data
corresponding to the data ready pulse.
This mechanism allows the MCP3918 to
continuously read ADC data outputs
seamlessly, even in SPI Mode (0,0).
Don’t Care
SCK
SDI
SDO
CS
High-Z
8x
0x01
24x
Starts Read Sequence at
Address 00000
24x
Don’t Care
DR
Complete Read Sequence on
New ADC Output Channel
Complete Read Sequence on
the ADC Output Channel
DATA_CH0
Stays at
DATA_CH[0]
DATA_CH0
Don’t Care
SCK
SDI
SDO
CS
High-Z
8x
0x01
24x
Starts Read Sequence at
Address 00000
24x
Don’t Care
DR
DATA_CH0 DATA_CH0
DATA_CH0
[23]
New Data
DATA_CH0
[23]
Old Data
MCP3918
DS20005287B-page 48 2014-2019 Microchip Technology Inc.
6.5.2 CONTINUOUS WRITE
The STATUSCOM register contains the write loop
settings for the internal Register Address Pointer
(WRITE). For the Continuous Write modes, the
address selection can take the two following values.
SDO is always in a high-impedance state during a
continuous write communication. Writing to a nonwritable
address (such as addresses: 0x00 to 0x07 or any of the
unused register’s addresses) has no effect and does not
increment the Address Pointer. In this case, the user
needs to stop the communication and restart a commu-
nication with a control byte pointing to a writable address
(0x08 to 0x1F).
6.6 Situations that Reset and Restart
Active ADC
Immediately after the following actions, the active ADC
(the ones not in Soft Reset or Shutdown modes) is
reset and automatically restarted in order to provide
proper operation:
1. Change in PHASE register.
2. Overwrite of the same PHASE register value.
3. Change in the OSR[2:0] bits setting.
4. Change in the PRE[1:0] bits setting.
5. Change in the CLKEXT bit setting.
6. Change in the VREFEXT bit setting.
After these temporary Resets, the ADC goes back to
normal operation, with no need for an additional
command. Each ADC Data Output register is cleared
during this process. The PHASE register can be used
to serially soft reset the ADC, without using the RESET
bit in the CONFIG1 register, if the same value is written
in the PHASE register.
6.7 Data Ready Pin (DR)
To communicate when channel data are ready for
transmission, the data ready signal is available on the
Data Ready (DR) pin at the end of a conversion. The
DR pin outputs an active-low pulse with a pulse width
equal to half a DMCLK clock period. After a data ready
pulse falling edge has occurred, the ADC output data
are updated within the tDODR timing and can then be
read through SPI communication.
The first data ready pulse after a Hard or Soft Reset is
located after the settling time of the SINC filter (see
Table 5-4), plus the phase delay of the corresponding
channel (see Section 5.11 “Crystal Oscillator”).
Each subsequent pulse is then periodic and the period
is equal to a DRCLK clock period (see Equation 4-3
and Figure 1-3). The data ready pulse is always
synchronous with the internal DRCLK clock.
The DR pin can be used as an interrupt pin when
connected to an MCU or DSP, which will synchronize
the readings of the ADC data outputs. When not
active-low, this pin can be either in high-impedance
(when DR_HIZ = 0) or in a defined logic high state
(when DR_HIZ = 1). This is controlled through the
STATUSCOM register. This allows multiple devices to
share the same DR pin (with a pull-up resistor con-
nected between DR and DVDD). If only the MCP3918
device is connected on the interrupt bus, the DR pin
does not require a pull-up resistor, and therefore, it is
recommended to use the DR_HIZ = 1 configuration for
such applications.
The CS pin has no effect over the DR pin, which means
that even if the CS pin is logic high, the data ready
pulses coming from the active ADC channels will still
be provided; the DR pin behavior is independent from
the SPI interface. While the RESET pin is logic low, the
DR pin is not active. The DR pin is latched in the logic
low state when the interrupt flag on the CRCREG is
present to signal that the desired register configuration
has been corrupted (see Section 6.11 “Detecting
Configuration Change through CRC-16 Checksum
on Register Map and its Associated Interrupt
Flag”).
TABLE 6-2: ADDRESS SELECTION IN
CONTINUOUS WRITE
WRITE Register Address Set Grouping for
Continuous Write Communications
0Static (no incrementation)
1Types (default)
Note: When the LOCK[7:0] bits are different from
0xA5, all the addresses, except for 0x1F,
become nonwritable (see Section 6.10
“Locking/Unlocking Register Map Write
Access”).
2014-2019 Microchip Technology Inc. DS20005287B-page 49
MCP3918
6.8 ADC Channel Latching and
Synchronization
The ADC Data Output register (address 0x00) has a
double-buffer output structure. The two sets of latches
in series are triggered by the data ready signal and an
internal signal indicating the beginning of a read
communication sequence (read start).
The first set of latches holds the ADC Channel Data
Output register when the data are ready. This behavior
is synchronous with the MCLK clock.
The second set of latches ensures that, when reading
starts on an ADC output, the corresponding data are
latched, so that no data corruption can occur within a
read. This behavior is synchronous with the SCK clock.
If an ADC read has started, in order to read the follow-
ing ADC output, the current reading needs to be fully
completed (all bits must be read on the SDO pin from
the ADC Output Data registers).
Since the double-output buffer structure is triggered
with two events that depend on two asynchronous
clocks (data ready pulse with MCLK and read start with
SCK), it is recommended to implement one of the three
following methods on the MCU or the processor in
order to synchronize the reading of the channels:
1. Use the DR pin pulses as an interrupt: Once
a falling edge occurs on the DR pin, the data are
available for reading on the ADC Output
registers after the tDODR timing. If this timing is
not respected, data corruption can occur.
2. Use a timer clocked with MCLK as a synchro-
nization event: Since the data ready pulse is
synchronous with MCLK, the user can calculate
the position of the data ready pulse depending
on the PHASE, the OSR[2:0] and the PRE[1:0]
bits setting. Again, the tDODR timing needs to be
added to this calculation, to avoid data
corruption.
3. Poll the DRSTATUS bit in the STATUSCOM
register: This method consists of continuously
reading the STATUSCOM register and waiting
for the DRSTATUS bit to be equal to ‘0’. When
this event happens, the user can start a new
communication to read the desired ADC data. In
this case, no additional timing is required.
The first method is the preferred one, as it can be used
without adding additional MCU code space, but
requires connecting the DR pin to an I/O pin of the
MCU. The two last methods require more MCU code
space and execution time, but they allow synchronizing
the reading of the channels without connecting the DR
pin, which saves one I/O pin on the MCU.
6.9 Securing Read Communications
through CRC-16 Checksum
Since power/energy metering systems can generate or
receive large EMI/EMC interferences and large tran-
sient spikes, it is helpful to secure SPI communications
as much as possible to maintain data integrity and
desired configurations during the lifetime of the
application.
The communication data on the SDO pin can be
secured through the insertion of a Cyclic Redundancy
Check (CRC) checksum at the end of each continuous
reading sequence. The CRC checksum on the commu-
nications can be enabled or disabled through the
EN_CRCCOM bit in the STATUSCOM register. The
CRC message ensures the integrity of the read
sequence bits transmitted on the SDO pin and the CRC
checksum is inserted in between each read sequence
(see Figure 6-10).
MCP3918
DS20005287B-page 50 2014-2019 Microchip Technology Inc.
FIGURE 6-9: Continuous Read Sequences with and without CRC Checksum Enabled.
The CRC checksum in the MCP3918 device uses the
16-bit CRC-16 ANSI polynomial, as defined in the
IEEE 802.3 standard: x16 + x15 + x2 + 1. This polynomial
can also be noted as 0x8005. CRC-16 detects all single
and double-bit errors, all errors with an odd number of
bits, all burst errors of length 16 or less and most errors
for longer bursts. This allows an excellent coverage of the
SPI communication errors that can happen in the system
and heavily reduces the risk of a miscommunication,
even under noisy environments.
The CRC-16 format displayed on the SDO pin depends
on the WIDTH_DATA[1] bit in the STATUSCOM register
(see Figure 6-10). It can be either 16-bit or 32-bit format
to be compatible with both 16-bit and 32-bit MCUs. The
CRCREG[15:0] bits, calculated by the MCP3918 device,
are not dependent on the format (the device always
calculates only a 16-bit CRC checksum). It is recom-
mended to keep WIDTH_DATA[1] = WIDTH_CRC when
the CRC checksum is enabled. If a 32-bit MCU is used
in the application, it is recommended to use 32-bit
formats (WIDTH_DATA[1] = WIDTH_CRC = 1) only.
FIGURE 6-10: CRC Checksum Format.
The CRC computed by the MCP3918 device is fully
compatible with the CRC hardware contained in the Direct
Memory Access (DMA) peripheral of the PIC24 and
PIC32 MCU product lines. The CRC message that should
be considered in the PIC® device DMA is the concatena-
tion of the read sequence and its associated checksum.
When the DMA CRC hardware computes this extended
message, the resulting checksum should be 0x0000. Any
other result indicates that a miscommunication has
happened and that the current communication sequence
should be stopped and restarted.
Continuous READ communication without CRC checksum (EN_CRCCOM=0)
Don’t care
SCK
SDI
SDO
CS
Hi-Z
8x
CONTROL
BYTE
16x/24x/32x
Depending on
data format
ADDR ... ADDR + n
Starts read sequence
at address ADDR
Complete READ sequence
ADDR + 1
16x/24x/32x
Depending on
data format
...
16x/24x/32x
Depending on
data format
16x/24x/32x
Depending on
data format
ADDR ...
Complete READ sequence
ADDR + 1
16x/24x/32x
Depending on
data format
...
16x/24x/32x
Depending on
data format
ADDR + n
Don’t care
ADDR
ADDR + 1
...
ADDR + n
Complete
READ
sequence
Roll-over
ADDRESS SET
Continuous READ communication with CRC checksum (EN_CRCCOM=1)
Don’t care
SCK
SDI
SDO
CS
Hi-Z
8x
CONTROL
BYTE
16x/24x/32x
Depending on
data format
ADDR ... ADDR + n
Starts read sequence
at address ADDR
Complete READ sequence = Message for CRC Calculation
ADDR + 1
16x/24x/32x
Depending on
data format
...
16x/24x/32x
Depending on
data format
16x/24x/32x
Depending on
data format
ADDR ...
New Message
ADDR + 1
16x/24x/32x
Depending on
data format
...
16x/24x/32x
Depending on
data format
ADDR + n
Don’t care
ADDR
ADDR + 1
...
ADDR + n
Complete
READ
sequence
Roll-over
ADDRESS SET
CRC Checksum CRC Checksum
16x or 32x
Depending on
CRC format
16x or 32x
Depending on
CRC format
CRC Checksum (not part of register map)
New ChecksumChecksum
High Z
High Z
WIDTH_DATA[1] = 0
16-Bit Format CRCCOM
[15:8] CRCCOM
[7:0]
15 0
WIDTH_DATA[1] = 1
32-Bit Format CRCCOM
[15:8] CRCCOM
[7:0]
31 0
0x00 0x00
Note: The CRC will be generated only at the end
of the selected address set, before the
rollover of the Address Pointer occurs
(see Figure 6-10).
2014-2019 Microchip Technology Inc. DS20005287B-page 51
MCP3918
6.10 Locking/Unlocking Register Map
Write Access
The MCP3918 digital interface includes an advanced
security feature that allows locking or unlocking the
register map write access. This feature prevents the
miscommunications that can corrupt the desired config-
uration of the device, especially an SPI read becoming
an SPI write because of the noisy environment.
The last register address of the register map
(0x1F: LOCK/CRC) contains the LOCK[7:0] bits. If
these bits are equal to the password value (which is
equal to the default value of 0xA5), the register map
write access is not locked. Any write can take place and
communications are not protected.
When the LOCK[7:0] bits are different from 0xA5, the
register map write access is locked. The register map,
and therefore, the full device configuration are write-
protected. Any write to an address other than 0x1F will
yield no result. All the register addresses, except for
0x1F, become read-only. In this case, if the user wants
to change the configuration, the LOCK[7:0] bits have to
be reprogrammed back to 0xA5 before sending the
desired WRITE command.
The LOCK[7:0] bits are located in the last register, so
that the user can program the whole register map,
starting from 0x09 to 0x1E, within one continuous write
sequence, and then lock the configuration at the end of
the sequence with writing all zeros, for example, in the
0x1F address.
6.11 Detecting Configuration Change
through CRC-16 Checksum on
Register Map and its Associated
Interrupt Flag
In order to prevent internal corruption of the register and
to provide additional security on the register map config-
uration, the MCP3918 device includes an automatic and
continuous CRC checksum calculation on the full regis-
ter map Configuration bits. This calculation is not the
same as the communication CRC checksum described
in Section 6.9 “Securing Read Communications
through CRC-16 Checksum”. This calculation takes
the full register map as the CRC message and outputs a
checksum on the CRCREG[15:0] bits located in the
LOCK/CRC register (address 0x1F).
Since this feature is intended to protect the configura-
tion of the device, this calculation is run continuously
only when the register map is locked (LOCK[7:0] bits
are different from 0xA5; see Section 6.10 “Locking/
Unlocking Register Map Write Access”). If the
register map is unlocked, the CRCREG[15:0] bits are
cleared and no CRC is calculated.
The calculation is fully completed in ten DMCLK
periods and refreshed every ten DMCLK periods
continuously. The CRCREG[15:0] bits are reset when a
POR or a Hard Reset occurs. All the bits contained in
the defined registers, from addresses 0x09 to 0x1F, are
processed by the CRC engine to give the
CRCREG[15:0] bits. The DRSTATUS bit is set to ‘1’
(default) and the CRCREG[15:0] bits are set to ‘0’
(default) for this calculation engine, as they could vary
during the calculation.
An interrupt flag can be enabled through the EN_INT
bit in the STATUSCOM register and provided on the DR
pin when the configuration has changed without a
WRITE command being processed. This interrupt is a
logic low state. This interrupt is cleared when the
register map is unlocked (since the CRC calculation is
not processed anymore).
At power-up, the interrupt is not present and the register
map is unlocked. As soon as the user finishes writing its
configuration, the user needs to lock the register map
(writing 0x00, for example, in the LOCK bits) to be able
to use the interrupt flag. The CRCREG[15:0] bits will be
calculated for the first time in 10 DMCLK periods. This
first value will then be the reference checksum value and
will be latched internally, until a Hard Reset, a POR or an
unlocking of the register map happens. The
CRCREG[15:0] bits will then be calculated continuously
and checked against the reference checksum. If the
CRCREG[15:0] bits are different from the reference, the
interrupt sends a flag by setting the DR pin to a logic low
state until it is cleared.
6.12 Interface Mode Selection
(SPI or 2-Wire)
The MCP3918 includes two different digital interfaces:
a standard 4-wire half-duplex SPI interface (see
Section 6.0 “SPI Serial Interface Description”) and
a 2-wire interface dedicated for digitally isolated
applications (see Section 7.0 “2-Wire Serial Interface
Description”).
The selection between these two interfaces is possible
only when the CLKEXT bit is high (CLKEXT = 1). This
is the case by default at POR. When the CLKEXT = 1
condition is true, the OSC2/MODE pin becomes the
selection input pin for the Interface mode.
When OSC2/MODE is logic low during the CLKEXT = 1
condition, the SPI interface is selected. When the
OSC2/MODE pin is logic high, the 2-Wire Interface
mode is selected (see Figure 1-5 for the 2-Wire mode
selection timing diagram).
If the OSC2/MODE pin is left floating while CLKEXT = 1,
an internal pull-down (35 µA typical current) automatically
selects the SPI mode as the default interface.
The mode selection is not combinatorial; it is latched at
each POR, Hard Reset and Watchdog Timer Reset. In
other words, to change from one interface mode to
another, the user needs to create one of these three
Resets and change the OSC2/MODE logic input state
before exiting the applied Reset.
MCP3918
DS20005287B-page 52 2014-2019 Microchip Technology Inc.
NOTES:
2014-2019 Microchip Technology Inc. DS20005287B-page 53
MCP3918
7.0 2-WIRE SERIAL INTERFACE
DESCRIPTION
7.1 Overview
The 2-Wire Interface mode is designed for applications
that require galvanic isolation. It allows a minimum
number of digital isolator channels, specifically one
bidirectional or two unidirectional channels, to be
connected to the MCP3918 when interfacing through
an isolation barrier. This functionality reduces the total
system cost in an isolated application system, such as
a polyphase shunt-based energy meter. It is recom-
mended to use the MCP3918 with the 2-Wire mode for
digitally isolated applications and with the SPI mode for
other applications where galvanic isolation is not
required.
The principle of this 2-Wire interface is simple: it has a
Serial Clock Input pin (SCK/MCLK) and a Serial Data
Output pin (SDO), and it automatically sends output
data in packets (frames) at a DRCLK data rate (every
time new data are available on the ADC output). It has
no serial input pin to diminish the number of isolated
channels. At the same time, the Serial Clock pin, SCK,
also becomes the Master Clock (MCLK) input pin of the
device, and the part becomes fully synchronous with
SCK = MCLK. The system then becomes fully synchro-
nous and can be driven by only one master clock for
multiple phases, which ensures proper synchronization
and constant phase angle between phases, which is
important for an energy metering application.
The SDO pin becomes the only output of the device
and is fully synchronous with the serial/master clock.
The SDO pin is never in high-impedance in this mode,
and is by default, at logic low when not transmitting
data. The SDO pin Idles logic low in this mode because
most of the digital isolator devices consume less
current in a logic low state than in a logic high state.
This effectively reduces the total power consumption of
a system with digital isolation devices.
When the part has entered 2-Wire mode, the logic pins,
RESET, SDI, CS, OSC1 and DR, become logic input
pins for the configuration of the device (respectively,
OSR0/OSR1/BOOST/GAIN0/GAIN1). These pins need
to have well-defined logic states for low-power applica-
tions. These pins define the only settings that can be
modified in 2-Wire mode.
The MDAT0 pin is always disabled and kept in a
high-impedance state during the 2-Wire Interface
mode. This pin can be grounded for applications using
exclusively the 2-Wire Interface mode so that the EMI/
EMC susceptibility of the part is improved.
FIGURE 7-1: MCP3918 2-Wire Interface Typical Application Schematic.
SDO
GAIN1
SCK/MCLK
OSR0
BOOST
CH0+
CH0-
MCP3918
ANALOG DIGITAL
SINC3
-
+
PGA '6
Modulator
MOD<3:0>
Isolator
Isolator
2-wire
Interface
OSR1
To SPI Ports
Of an MCU
GAIN0
Logic inputs
connected
to DVDD or
DGND
Main MCU/
CPU Board
Isolation
Barrier
MCP3918
DS20005287B-page 54 2014-2019 Microchip Technology Inc.
7.2 2-Wire Mode Configuration
Settings
When the user wants to exclusively use the 2-Wire
Interface mode in digitally isolated applications, the
OSC2 pin should always be in a logic high state, start-
ing from the power-up of the part. Otherwise, the user
can change the interface mode by toggling the OSC2/
MODE pin within a POR, a Hard Reset or a Watchdog
Timer Reset; the mode is latched when exiting one of
these three types of Reset. When the part has entered
2-Wire mode, the entire part configuration keeps its
default settings (see Section 9.0 “MCP3918 Internal
Registers” for the default settings of all internal
registers), except for the configuration of the Gain in
Channel 0, the OSR and the BOOST settings.
In 2-Wire mode, the input pins, OSR0/OSR1/BOOST/
GAIN0/GAIN1, are latched on the OSC2/MODE rising
edge and should typically be directly connected to
DVDD or DGND, depending on the desired configura-
tion. These pins define the only configurable settings in
2-Wire mode. If more settings are required by the
application, it is recommended to use the SPI mode.
The following tables describe the configuration options
for these five pins.
7.2.1 OSR1/OSR0
OSR Setting Logic Pins. These inputs are Schmitt
triggered.
7.2.2 BOOST
Current BOOST setting logic pin. This input is Schmitt
triggered.
7.2.3 GAIN1/GAIN0
PGA GAIN setting logic pins. These inputs are Schmitt
triggered.
7.3 2-Wire Communication Protocol
In 2-Wire mode, the SCK/MCLK pin needs to be
clocked continuously at all times for proper operation.
Any change in the clock frequency will lead to
degraded THD/SFDR specifications. The part obeys
the same timing specifications in both SPI and 2-Wire
Interface mode for the SCK/SDO pins. The MCLK max-
imum input frequency is 10 MHz in 2-Wire mode, since
the converter still respects Ta b l e 5 - 2 for maximum
AMCLK frequency (provided the part has entered
2-Wire mode at power-up). Since the MCLK is divided
internally, the part accepts a wide range of duty cycles
for the SCK input, provided the serial interface timings
are respected.
In 2-Wire Interface mode, communication uses framed
data sets on the SDO to output data at a fixed data rate,
synchronously with SCK, and using only one output
pin. The frame is different depending on the device and
the Oversampling Ratio (OSR) selected. When in
OSR = 64 mode, the MCP3918 frame contains the
sync bytes (16-bit), one channel of 16-bit ADC data and
a 16-bit CRC. For OSR = 128 and higher, each frame
is a group of 7 bytes (56 bits), clocked by the Serial
Clock, SCK. Each frame is composed of a sync word
(2 bytes), 24-bit data output word (3 bytes) and CRC.
The sync word comes first, followed by the Channel 0
ADC output (DATA_CH0[23:0]) and the 16-bit CRC.
See Figures 7-1 and 7-2.
As a verification feature, the sync word contains all
settings coming from the five logic input pins available
(OSR0/1, GAIN0/1, BOOST) in order to provide the
user with the information about this configuration. It
also provides information about the count of the frame
through bits, CNT0/1, which is useful when the SDO is
multiplexed at the output of the digital isolators (see
next paragraph). The sync word also contains an addi-
tional sync byte (fixed at 0xA5 value) for additional
security in synchronization and communication.
TABLE 7-1: OSR SETTINGS
OSR1 OSR0 OSR
0064
01128
10256
11512
TABLE 7-2: CURRENT BOOST SETTINGS
BOOST PIN BOOST
00.5x
11x
TABLE 7-3: CHANNEL 0 GAIN SETTINGS
GAIN1 GAIN0 CH0 PGA GAIN
00 1
01 8
10 16
11 32
2014-2019 Microchip Technology Inc. DS20005287B-page 55
MCP3918
FIGURE 7-2: Frame Word.
These four frames can be used to multiplex SDO at the
output of the digital isolators. In this case, up to four
channels (typically three phases and one neutral for
energy metering applications) can be multiplexed. The
output data of each individual MCP3918 device can be
attributed to a different frame (FRAME0, 1, 2 or 3) and
retrieved on a single SDO line, after the digital isolators,
provided that the isolators have a chip enable or a multi-
plexing feature. The frame counter can then be used to
retrieve the information about which the MCP3918 part
is actually being read. After the four frames have been
transmitted, the SDO pin Idles logic low to reduce digital
isolator power consumption until the next data are
available. Figure 7-3 displays the timing diagram for the
2-Wire Interface mode, showing all OSR possibilities.
Note that the first set of frames is sent only when the first
data are ready, which means that the settling time of the
SINC filter will be elapsed before sending the first set of
frames, as represented in Figure 7-3.
FIGURE 7-3: MCP3918 2-Wire Communication Protocol.
CRCCOM[15:0]
0
DATA_CH0[23:0]
Sync Word (2 Bytes)
SDO Output Frame (7 Bytes, 56x Clocks per Frame)
OSR0
OSR1
G1
G0
BOOST
CNT1
CNT0
0
1
1
0
1
0
0
1
Channel 0 ADC Data (3 Bytes)
SDO
SCK/
MCLK
CRCCOM[15:0]
CRCCOM on Entire Frame (2 Bytes)
DATA_CH0[15:0]
0
Sync Word (2 Bytes)
SDO Output Frame (6 Bytes, 48x Clocks per Frame)
OSR0
OSR1
G1
G0
BOOST
CNT1
CNT0
0
1
1
0
1
0
0
1
Channel 0 ADC Data (2 Bytes)
SDO
SCK/
MCLK
FRAME CLOCKING FOR OSR > 64
FRAME CLOCKING FOR OSR = 64
CRCCOM on Entire Frame (2 Bytes)
TABLE 7-4: FRAME COUNTER SETTINGS
CNT1 CNT0 Frame Number
00FRAME0
01FRAME1
10FRAME2
11FRAME3
SDO
(OSR=64)
00
Internal data ready (Data is
unsettled). No frame is transmitted Data Ready.
New data is available
OSC2/
MODE
256x
clocks
256x
clocks
256x
clocks
SCK/MCLK
256x
clocks
256x
clocks
256x
clocks
256x
clocks
256x
clocks
256x
clocks
256x
clocks
256x
clocks
256x
clocks
256x
clocks
256x
clocks
256x
clocks
256x
clocks
256x
clocks
256x
clocks
256x
clocks
256x
clocks
256x
clocks
256x
clocks
256x
clocks
256x
clocks
256x
clocks
DATA=D1 DATA=D2 DATA=D3 DATA=D4DATA=0 DATA=D5 DATA=D6 DATA=D7 DATA=D8 DATA=D9 DATA=D10 DATA=D11 DATA=D12 DATA=D13 DATA=D14 DATA=D15 DATA=D16 DATA=D17 DATA=D18 DATA=D19 DATA=D20 DATA=D21 DATA=D22
FRAME0
FRAME1
FRAME2
FRAME3
FRAME0
FRAME1
FRAME2
FRAME3
FRAME0
FRAME1
FRAME2
FRAME3
0
DATA=D1 DATA=D2 DATA=D3 DATA=D4 DATA=D5 DATA=D6 DATA=D7 DATA=D8 DATA=D9 DATA=D10
0
DATA=D1 DATA=D2 DATA=D3 DATA=D4
0
DATA=D1
00
0
0 0
0000
00000
0000
2-Wire Mode
Hi-Z
Hi-Z
Hi-Z
Hi-Z
SDO
(OSR=128)
SDO
(OSR=256)
SDO
(OSR=512)
0
0
0
0
FRAME0
FRAME1
FRAME2
FRAME3
FRAME0
FRAME1
FRAME2
FRAME3
FRAME0
FRAME1
FRAME2
FRAME3
FRAME0
FRAME1
FRAME2
FRAME3
FRAME0
FRAME1
FRAME2
FRAME3
FRAME0
FRAME1
FRAME2
FRAME3
FRAME0
FRAME1
FRAME2
FRAME3
FRAME0
FRAME1
FRAME2
FRAME3
FRAME0
FRAME1
FRAME2
FRAME3
FRAME0
FRAME1
FRAME2
FRAME3
FRAME0
FRAME1
FRAME2
FRAME3
FRAME0
FRAME1
FRAME2
FRAME3
FRAME0
FRAME1
FRAME2
FRAME3
FRAME0
FRAME1
FRAME2
FRAME3
FRAME0
FRAME1
FRAME2
FRAME3
FRAME0
FRAME1
FRAME2
FRAME3
FRAME0
FRAME1
FRAME2
FRAME3
FRAME0
FRAME1
FRAME2
FRAME3
FRAME0
FRAME1
FRAME2
FRAME3
FRAME0
FRAME1
FRAME2
FRAME3
FRAME0
FRAME1
FRAME2
FRAME3
FRAME0
FRAME1
FRAME2
FRAME3
FRAME0
FRAME1
FRAME2
FRAME3
FRAME0
FRAME1
FRAME2
FRAME3
FRAME0
FRAME1
FRAME2
FRAME3
FRAME0
FRAME1
FRAME2
FRAME3
FRAME0
FRAME1
FRAME2
FRAME3
FRAME0
FRAME1
FRAME2
FRAME3
FRAME0
FRAME1
FRAME2
FRAME3
FRAME0
FRAME1
FRAME2
FRAME3
FRAME0
FRAME1
FRAME2
FRAME3
FRAME0
FRAME1
FRAME2
FRAME3
FRAME0
FRAME1
FRAME2
FRAME3
FRAME0
FRAME1
FRAME2
FRAME3
MCP3918
DS20005287B-page 56 2014-2019 Microchip Technology Inc.
7.4 Watchdog Timer Reset, Resetting
the Part When in 2-Wire Mode
When the part has entered 2-Wire mode, the Hard
Reset mode functionality is not available because the
RESET pin becomes the logic input for OSR0. If the
user wants to execute a full Reset of the part without
doing a POR, the 2-Wire mode incorporates an internal
Watchdog Timer that automatically performs a full
Reset of the part, provided that the timer has elapsed.
The Watchdog Timer starts synchronously with each
rising edge of SCK/MCLK. If the SCK logic high state is
maintained for a time that is larger than tWATCH, the
Watchdog Timer circuit forces the full Reset of the chip,
which then returns to its default configuration with the
ADC being reset. If the SCK logic high state is main-
tained for a time shorter than tWATCH and then SCK/
MCLK toggles to logic low, the internal timer is cleared,
waiting for another rising edge to restart.
The Watchdog Timer functionality induces a restriction
in the usable range of frequencies on SCK/MCLK. In
order to avoid intermittent Resets in all cases, the
minimum SCK/MCLK frequency in 2-Wire Interface
mode is equal to the inverse of the minimum tWATCH
time (1/(2 x 3.6 µs) = 138.9 kHz, if the duty cycle of the
SCK/MCLK is 50%).
The Watchdog Timer starts only on the rising edge of
SCK/MCLK, not on the falling edge. Maintaining SCK/
MCLK at a logic low state for large periods of time does
not create any Watchdog Timer Resets. A Watchdog
Timer Reset is created only when the SCK/MCLK state
is maintained logic high during a long enough period of
time.
This Watchdog Timer period permits exiting the 2-Wire
Interface mode, if desired, by toggling the OSC2/
MODE pin to logic low before creating the Watchdog
Timer Reset and maintaining it logic low until the Reset
occurs.
2014-2019 Microchip Technology Inc. DS20005287B-page 57
MCP3918
8.0 BASIC APPLICATION
CONFIGURATION
One of the main applications for the MCP3918 is
energy/power measurement in systems where the
ADC sampling the current needs to be isolated from the
rest of the design. Figure 8-1 can be used as a starting
point for MCP3918 applications.
For power measurements, since MCP3918 is a 1-channel
ADC, it is recommended to use it for current samples
acquisition and to use the MCU ADC for voltage samples
acquisition.
The isolator used between the MCU and ADC needs to
be fast enough to support the high-speed clock
between the MCU and ADC, and the data coming from
the ADC to MCU.
This is typically the case in a polyphase shunt-based
power/energy metering or monitoring application. In
this case, each phase needs to be isolated from the
rest of the design, and since the sensor is not providing
this isolation, the isolation needs to be provided at the
output of the analog front end.
The MCP3918 device is built to work seamlessly with a
large variety of two-channel unidirectional digital isolators
(optocouplers, capacitive or inductive integrated digital
isolators with or without embedded power supplies).
FIGURE 8-1: MCP3918 Three-Phase Shunt Energy Meter – Typical Application Schematic for
Each Phase.
8.1 Power Supply Design
To power the isolated ADC, an isolated DC/DC
Converter that can be embedded with the isolated data
communication channels (as in Figure 8-1) or other
structures that provide isolated power supplies (e.g.,
flyback converter) can be used.
For single-phase designs, where isolation between the
ADC and MCU is not required, the SPI connection is
also available. This SPI interface could also be used
with isolators, but this would require four isolators
instead of two (for the 2-Wire mode), and therefore, this
configuration is not preferred.
8.2 Power Supply and Bypassing
The MCP3918 device was designed to measure positive
and negative voltages that might be generated by a
current-sensing device. This current-sensing device,
with a Common-mode voltage close to 0V, is referred to
as AGND, which is a shunt or Current Transformer (CT)
with burden resistors attached to ground.
The high performance and good flexibility that character-
ize this ADC enable it to be used in other applications, as
long as the absolute voltage on each pin, referred to as
AGND, stays in the -1V to +1V range.
3910A_SDO
A_GNDD
A_GNDA
A_GNDA
10
R76
0.1 μF
C52
10
R100 0.1 μF
C43
10
R86
A_GNDA
A_GNDA
A_GNDA
0.1 μF
C46
A_3.3DA_3.3A
A_GNDD
DR/GAIN1 14
DGND 11
AGND
8
CH0-
5
DVDD
2
OSC1/CLKI 15
SCK/MCLK 18
MDAT1 12
MDAT0 13
NC
6
NC
7
RFIN/OUT+
9
RFIN-
10
RESET/OSR0
1
AVDD
3
CH0+
4CS/BOOST 17
OSC2/MODE 16
SDO 19
SDI /OSR1 20
U3
MCP3918A1T/ISS
J24
J25
A_3.3D
1k
R80
A_GNDD
J26
J27
J28
HIGH LOW
HIGH LOW
LOW
LOW
HIGH
HIGH
GAIN1
GAIN0
BOOST
OSR1
OSR0
HIGH LOW
1k
R79
3910A_CLKIN
10
R87
3910A_SDO
A_GNDD
A_3.3D
3910A_CLKIN 3910_CLKIN_MCU_A
PHASE A
A_3.3D
A_3.3D
A_3.3A
A_GNDA
VBT1-S5-S5
-VIN
1
+VIN
2
+VOUT
5
-VOUT
4
DCDC
U7
4.7 μF
C63
MCP1754-3.3V
VIN
3
GND
1
VOUT
2
U18
A_GNDD
0.1 μF
C57 4.7 μF
C22
5V
L2
GND
3.3D
GND
0.1 μF
0603
C68
3.3D
GND
0.1 μF
0603
C60
A_3.3D
A_GNDD
NT3
3910A_SDO_MCU/RC3
VDD1
1
VOA
2
VIB
3
GND1 4
VDD2
8
VIA
7
VOB
6
GND2
5
FOD8012
U21
A_GNDA
A_GNDA
A_GNDAA_GNDA
A_GNDA
0.1 μF
C5
1k
R5
1k
R4
0.1 μF
C1
LINE_SHUNT1
LINE_SHUNT2
Via_1.6x1
CP1
Via_1.6x1
CP2
DNP
R3
DNP
R6
FB2
FB3
3 2 1
3 2 1
3 2 1
3 2 1
3 2 1
MCP3918
DS20005287B-page 58 2014-2019 Microchip Technology Inc.
In any system, the analog ICs (such as references or
operational amplifiers) are always connected to the
analog ground plane. The MCP3918 should also be
considered as a sensitive analog component and
should be connected to the analog ground plane. The
ADC features two pairs of pins: AGND and AVDD, DGND
and DVDD. For best performance, it is recommended to
keep the two pairs connected to two different networks
(Figure 8-2). This way, the design will feature two
ground traces and two power supplies (Figure 8-3).
This means the analog circuitry (including MCP3918)
and the digital circuitry (MCU) should have separate
power supplies and return paths to the external ground
reference, as described in Figure 8-2.
An example of a typical power supply circuit, with different
lines for analog and digital power, is shown in Figure 8-3.
A possible split example is shown in Figure 8-4, where
the ground star connection can be done at the bottom
of the device with the exposed pad. The split between
analog and digital can be done under the device, and
AVDD and DVDD can be connected together with lines
coming under the ground plane. Another possibility,
sometimes easier to implement in terms of PCB layout,
is to consider the MCP3918 as an analog component,
and therefore, to connect both AVDD and DVDD
together, and AGND and DGND together with a star
connection. In this scheme, the decoupling capacitors
may be larger, due to the ripple on the digital power
supply (caused by the digital filters and the SPI
interface of the MCP3918), now causing glitches on the
analog power supply.
FIGURE 8-2: All Analog and Digital
Return Paths Need to Stay Separate with Proper
Bypass Capacitors.
FIGURE 8-3: Power Supply with Separate Lines for Analog and Digital Sections.
V
A
V
D
“Star” Point
I
A
I
D
I
D
I
A
D
-
= A
-
=
0.1 μF0.1 μFC
AV
DD
DV
DD
A
GND
D
GND
MCP39XX
MCU
Note: The “Net Tie” Object NT2 represents the start ground connection.
2014-2019 Microchip Technology Inc. DS20005287B-page 59
MCP3918
FIGURE 8-4: Separation of Analog and
Digital Circuits on Layout.
Figure 7-5 shows a more detailed example with a direct
connection to a high-voltage line (e.g., a two-wire 120V
or 220V system). A current-sensing shunt is used for
current measurement on the high/line side that also
supplies the ground for the system. This is necessary
as the shunt is directly connected to the channel input
pins of the MCP3918. To reduce sensitivity to external
influences, such as EMI, these two wires should form a
twisted pair, as noted in Figure 8-5. The power supply
and MCU are separated on the right side of the PCB,
surrounded by the digital ground plane. The MCP3918
is kept on the left side, surrounded by the analog
ground plane. There are two separate power supplies
going to the digital section of the system and the analog
section, including the MCP3918. With this placement,
there are two separate current supply paths and
current return paths: IA and ID.
FIGURE 8-5: Connection Diagram.
The ferrite bead between the digital and analog ground
planes helps keep high-frequency noise from entering
the device. This ferrite bead is recommended to be low
resistance; most often it is a THT component. Ferrite
beads are typically placed on the shunt inputs and into
the power supply circuit for additional protection.
8.3 SPI Interface Digital Crosstalk
The MCP3918 incorporates a high-speed, 20 MHz SPI
digital interface. This interface can induce a crosstalk if
it is running at its full speed without any precautions.
The crosstalk is caused by the switching noise created
by the digital SPI signals (also called ground bouncing).
This crosstalk would negatively impact the SNR in this
case. The noise is attenuated if a proper separation
between the analog and digital power supplies is put in
place (see Section 8.2 “Power Supply and Bypass-
ing”). In order to further remove the influence of the
SPI communication on measurement accuracy, it is
recommended to add series resistors on the SPI lines
to reduce the current spikes caused by the digital
switching noise (see Figure 8-1 where these resistors
have been implemented). The resistors also help to
keep the level of electromagnetic emissions low. The
measurement graphs provided in this data sheet have
been performed with 100series resistors connected
on each SPI I/O pin. Measurement accuracy distur-
bances have not been observed, even at the full speed
of 20 MHz interfacing. The crosstalk performance is
dependent on the package choice due to the difference
in the pin arrangement (dual in-line or quad) and is
improved in the 20-lead QFN package.
MCU
Power Supply
Circuitry
LINE
NEUTRAL
Twisted
Pair
I
A
I
D
I
D
I
A
“Star” Point
V
A
V
D
Analog Ground Plane Digital Ground Plane
MCP3918
SHUNT
MCP3918
DS20005287B-page 60 2014-2019 Microchip Technology Inc.
8.4 Sampling Speed and Bandwidth
If ADC power consumption is not a concern in the
design, the boost settings can be increased for best
performance so that the OSR is always kept at the
maximum settings to improve the SINAD performance
(see Table 7-1). If the MCU cannot generate a clock
fast enough, it is possible to tap the OSC1/OSC2 pins
of the MCP3918 crystal oscillator directly to the crystal
of the microcontroller. When the sampling frequency is
enlarged, the phase resolution is improved, and with
the OSR increased, the phase compensation range
can be kept in the same range as the default settings.
8.5 Differential Inputs Anti-Aliasing
Filter
Due to the nature of the ADC used in the MCP3918
(oversampling converter), each differential input of the
ADC channels requires an anti-aliasing filter so that the
oversampling frequency (DMCLK) is largely attenuated
and does not generate any disturbances on the ADC
accuracy. This anti-aliasing filter also needs to have a
gain close to the one in the signal bandwidth of interest.
Typically, for 50/60 Hz measurement and default
settings (DMCLK = 1 MHz), a simple RC filter with 1 k
and 100 nF can be used. The anti-aliasing filter used
for the measurement graphs is a first-order RC filter
with 1 kand 15 nF. The typical schematic for connect-
ing a Current Transformer to the ADC is shown in
Figure 8-6. If wires are involved, twisting them is also
recommended.
FIGURE 8-6: First-Order Anti-Aliasing
Filter for CT-Based Designs.
The di/dt current sensors, such as Rogowski coils, can
be an alternative to Current Transformers. Since these
sensing elements are highly sensitive to high-
frequency electromagnetic fields, using a second-order
anti-aliasing filter is recommended to increase the
attenuation of potential perturbing RF signals.
FIGURE 8-7: Second-Order Anti-Aliasing
Filter for Rogowski Coil-Based Designs.
The filter presented in Figure 8-7 is an anti-aliasing
filter. The di/dt integrator can be created in firmware as
a first-order low-pass filter with corner frequency much
lower than the input signal.
The MCP3918 is highly recommended in applications
using di/dt as current sensors because of the extremely
low noise floor at low frequencies. In such applications,
a Low-Pass Filter (LPF) with a cutoff frequency much
lower than the signal frequency (50/60 Hz for metering)
is used to compensate for the 90-degree shift and for
the 20 db/decade attenuation induced by the di/dt
sensor. Because of this filter, the SNR will be
decreased, since the signal will be attenuated by a few
orders of magnitude, while the low-frequency noise will
not be attenuated. Usually, a high-order High-Pass
Filter (HPF) is used to attenuate the low-frequency
noise in order to prevent a dramatic degradation of the
SNR, which can be very important in other parts. A
high-order filter will also consume a significant portion of
the computation power of the MCU. When using the
MCP3918, such a high-order HPF is not required since
this part has a low noise floor at low frequencies. A
first-order HPF is enough to achieve very good accuracy.
TABLE 8-1: SAMPLING SPEED vs.
MCLK AND OSR, ADC
PRESCALE 1:1
MCLK
(MHz) Boost OSR
Sampling
Speed
(ksps)
16 0b11 1024 3.91
14 0b11 1024 3.42
12 0b11 1024 2.93
10 0b10 1024 2.44
80b10 512 3.91
60b01 512 2.93
40b01 256 3.91
2014-2019 Microchip Technology Inc. DS20005287B-page 61
MCP3918
8.6 Energy Measurement Error
Considerations
The measurement error is a typical representation of the
nonlinearity of the ADC (see Section 4.0 “Terminology
and Formulas” for the definition of measurement error).
The measurement error is dependent on the THD and
on the noise floor of the ADC. The measurement error
specification on the MCP3918 can be improved by
increasing the OSR (to get a better SINAD and THD
performance), and to some extent, the BOOST settings
(if the bandwidth of the measurements is too limited by
the bandwidth of the amplifiers in the Sigma-Delta ADC).
In most of the energy metering AC applications,
High-Pass Filters are used to cancel the offset on each
ADC channel (current and voltage channels), and there-
fore, a single-point calibration is necessary to calibrate
the system for active energy measurement. This calibra-
tion is a system gain calibration, and the user can utilize
the EN_GAINCAL bit and the GAINCAL_CH0 register to
perform this digital calibration. After such calibration,
typical measurement error curves, like the ones in
Figure 2-7, can be generated by sweeping the current
channel amplitude and measuring the energy at the out-
puts (the energy calculations here are being realized
off-chip). The error is measured using a gain of 1x, as it
is commonly used in most CT-based applications.
At low signal amplitude values (typically 1000:1
dynamic range and higher), the crosstalk between
channels, mainly caused by the PCB, becomes a sig-
nificant part of the perturbation as the measurement
error increases. The 1-point measurement error curves
in Figure 2-5 have been performed with a full-scale
sine wave on all the inputs that are not measured,
which means that these channels induce a maximum
amount of crosstalk on the measurement error curve.
In order to avoid such behavior, a 2-point calibration
can be put in place in the calculation section.
This 2-point calibration can be a simple linear inter-
polation between two calibration points (one at high
amplitudes, one at low amplitudes at each end of the
dynamic range) and helps to significantly lower the
effect of crosstalk between channels. A 2-point calibra-
tion is very effective in maintaining the measurement
error close to zero on the whole dynamic range, since
the nonlinearity and distortion of the MCP3918 is very
low. Figure 2-6 shows the measurement error curves
obtained with the same ADC data taken for Figure 2-5,
but where a 2-point calibration has been applied. The
difference is significant only at the low end of the
dynamic range, where all the perturbing factors are a
bigger part of the ADC output signals. These curves
show extremely tight measurement error across the full
dynamic range (here, typically 10,000:1), which is
required in high-accuracy class meters.
MCP3918
DS20005287B-page 62 2014-2019 Microchip Technology Inc.
NOTES:
2014-2019 Microchip Technology Inc. DS20005287B-page 63
MCP3918
9.0 MCP3918 INTERNAL
REGISTERS
The addresses associated with the internal registers
are listed in Table 9-1. This section also describes the
registers in detail. All registers are 24-bit long registers,
which can be addressed and read separately.
The format of the data register (0x00) can be changed
through the WIDTH_CRC and WIDTH_DATA[1:0] bits
in the STATUSCOM register. The READ[1:0] and
WRITE bits define the groups and types of registers for
continuous read/write communication or looping on
address sets, as shown in Tab l e 9-2.
TABLE 9-1: MCP3918 REGISTER MAP
Address Name Bits R/W Description
0x00 CHANNEL0 24 R Channel 0 ADC Data[23:0], MSB First
0x01 Unused 24 U Unused
0x02 Unused 24 U Unused
0x03 Unused 24 U Unused
0x04 Unused 24 U Unused
0x05 Unused 24 U Unused
0x06 Unused 24 U Unused
0x07 Unused 24 U Unused
0x08 MOD 24 R/W Delta-Sigma Modulators Output Value
0x09 PHASE 24 U Phase Delay Configuration Register
0x0A Unused 24 U Unused
0x0B GAIN 24 R/W Gain Configuration Register
0x0C STATUSCOM 24 R/W Status and Communication Register
0x0D CONFIG0 24 R/W Configuration Register
0x0E CONFIG1 24 R/W Configuration Register
0x0F OFFCAL_CH0 24 R/W Offset Correction Register – Channel 0
0x10 GAINCAL_CH0 24 R/W Gain Correction Register – Channel 0
0x11 Unused 24 U Unused
0x12 Unused 24 U Unused
0x13 Unused 24 U Unused
0x14 Unused 24 U Unused
0x15 Unused 24 U Unused
0x16 Unused 24 U Unused
0x17 Unused 24 U Unused
0x18 Unused 24 U Unused
0x19 Unused 24 U Unused
0x1A Unused 24 U Unused
0x1B Unused 24 U Unused
0x1C Unused 24 U Unused
0x1D Unused 24 U Unused
0x1E Unused 24 U Unused
0x1F LOCK/CRC 24 R/W Security Register (Password and CRC-16 on Register Map)
MCP3918
DS20005287B-page 64 2014-2019 Microchip Technology Inc.
TABLE 9-2: REGISTER MAP GROUPING FOR ALL CONTINUOUS READ/WRITE MODES
Function Address
READ[1:0] WRITE
= 11 = 10 = 01 = 00 = 1= 0
CHANNEL 0 0x00
LOOP ENTIRE REGISTER MAP
TYPE GROUP Static Not Writable
MOD 0x08
TYPE
GROUP Static
TYPE
Static
GAIN 0x0B Static Static
STATUSCOM 0x0C
GROUP
Static Static
CONFIG0 0x0D Static Static
CONFIG1 0x0E Static Static
OFFCAL_CH0 0x0F GROUP Static Static
GAINCAL_CH0 0x10 Static Static
LOCKCRC 0x1F GROUP Static Static
2014-2019 Microchip Technology Inc. DS20005287B-page 65
MCP3918
9.1 CHANNEL Register –
ADC Channel Data
Output Register
The ADC Channel Data Output register always
contains the most recent A/D conversion data. This
register is read-only. This register is latched when an
ADC read communication occurs. When a data ready
event occurs during a read communication, the most
current ADC data are also latched to avoid data
corruption issues. The three bytes of each channel are
updated synchronously at a DRCLK rate. They can be
accessed separately, if needed, but are refreshed
synchronously.
Name Bits Address Cof.
CHANNEL0 24 0x00 R
REGISTER 9-1: CHANNEL REGISTER
R-0 (MSB) R-0 R-0 R-0 R-0 R-0 R-0 R-0
DATA_CH0[23:16]
bit 23 bit 16
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
DATA_CH0[15:8]
bit 15 bit 8
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
DATA_CH0[7:0]
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 23-0 DATA_CH0: Output Code from ADC bits
These data are post-calibration if the EN_OFFCAL or EN_GAINCAL bits are enabled. These data can
be formatted in 16-/24-/32-bit modes, depending on the WIDTH_DATA[1:0] settings (see Section 5.5
“ADC Output Coding”).
MCP3918
DS20005287B-page 66 2014-2019 Microchip Technology Inc.
9.2 MOD Register – Modulators
Output Register
The MOD register contains the most recent modulator
data output and is updated at a DMCLK rate. The
default value corresponds to an equivalent input of 0V
on the ADC. Each bit in this register corresponds to one
comparator output on one of the channels. This register
should not be written to ensure ADC accuracy.
Name Bits Address Cof.
MOD 24 0x08 R/W
REGISTER 9-2: MOD REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 23 bit 16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-1 R/W-1
— — — — COMP3_CH0 COMP2_CH0 COMP1_CH0 COMP0_CH0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 23-4 Unimplemented: Read as ‘0’
bit 3-0 COMPn_CH0: Comparator Outputs from ADC bits
2014-2019 Microchip Technology Inc. DS20005287B-page 67
MCP3918
9.3 PHASE Register – Phase
Configuration Register
Any write to this register automatically resets and
restarts the active ADC.
Name Bits Address Cof.
PHASE 24 0x0A R/W
REGISTER 9-3: PHASE REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 23 bit 16
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — — PHASE[11:8]
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PHASE[7:0]
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 23-12 Unimplemented: Read as ‘0’
bit 11-0 PHASE[11:0]: Conversion Start Delay bits
Delay = (PHASE[11:0] decimal code + OSR/2)/DMCLK.
MCP3918
DS20005287B-page 68 2014-2019 Microchip Technology Inc.
9.4 GAIN Register – PGA Gain
Configuration Register
Name Bits Address Cof.
GAIN 24 0x0B R/W
REGISTER 9-4: GAIN REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 23 bit 16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — — — — PGA_CH0[2:0]
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 23-3 Unimplemented: Read as ‘0’
bit 2-0 PGA_CH0[2:0]: PGA Setting bits
111 = Reserved (Gain = 1)
110 = Reserved (Gain = 1)
101 = Gain is 32
100 = Gain is 16
011 = Gain is 8
010 = Gain is 4
001 = Gain is 2
000 = Gain is 1 (default)
2014-2019 Microchip Technology Inc. DS20005287B-page 69
MCP3918
9.5 STATUSCOM Register – Status
and Communication Register
Name Bits Address Cof.
STATUSCOM 24 0x0C R/W
REGISTER 9-5: STATUSCOM REGISTER
R/W-1 R/W-0 R/W-1 R/W-0 U-0 R/W-0 R/W-0 R/W-1
READ[1:0] WRITE DR_HIZ — WIDTH_ CRC WIDTH_ DATA[1:0]
bit 23 bit 16
R/W-0 R/W-0 r-0 r-0 R/W-0 U-0 U-0 U-0
EN_CRCCOM EN_INT — — EN_MDAT — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R-1
— — — — — — — DRSTATUS[0]
bit 7 bit 0
Legend: r = Reserved bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 23-22 READ[1:0]: Address Counter Increment Setting for Read Communication bits
11 = Address counter auto-increments, loops on the entire register map
10 = Address counter auto-increments, loops on register TYPES (DEFAULT)
01 = Address counter auto-increments, loops on register GROUPS
00 = Address not incremented, continually reads the same single register address
bit 21 WRITE: Address Counter Increment Setting for Write Communication bit
1 = Address counter loops on writable part of the register map (default)
0 = Address not incremented, continually writes to the same single register address
bit 20 DR_HIZ: Data Ready Pin Inactive State Control bit
1 = The DR pin state is a logic high when data are NOT ready
0 = The DR pin state is high-impedance when data are NOT ready (default)
bit 19 Unimplemented: Read as ‘0’
bit 18 WIDTH_CRC: CRC-16 Format on Communications bit
1 = 32-bit (CRC-16 code is followed by sixteen zeros); this coding is compatible with CRC implementation
in most 32-bit MCUs (including PIC32 MCUs)
0 = 16-bit (default)
bit 17-16 WIDTH_DATA[1:0]: ADC Data Format Settings for ADC bits
(see Section 5.5 “ADC Output Coding”)
11 = 32-bit with sign extension
10 = 32-bit with zeros padding
01 = 24-bit (default)
00 = 16-bit (with rounding)
bit 15 EN_CRCCOM: CRC-16 Checksum on Serial Communications Enable bit
1 = CRC-16 checksum is provided at the end of each communication sequence (therefore, each com-
munication is longer); the CRC-16 message is the complete communication sequence (see
Section 6.9 “Securing Read Communications through CRC-16 Checksum” for more details)
0 = Disabled (default)
MCP3918
DS20005287B-page 70 2014-2019 Microchip Technology Inc.
bit 14 EN_INT: CRCREG Interrupt Function Enable bit
1 = The interrupt flag for the CRCREG checksum verification is enabled. The Data Ready pin (DR)
will become logic low and stays logic low if a CRCREG checksum error happens. This interrupt is
cleared if the LOCK[7:0] value is made equal to the PASSWORD value (0xA5).
0 = The interrupt flag for the CRCREG checksum verification is disabled. The CRCREG[15:0] bits are
still calculated properly and can still be read in this mode.
bit 13-12 Reserved: Bits should be kept equal to ‘0’ at all times
bit 11 EN_MDAT: Enable Modulator Output bit
1 = MDAT0 output is enabled
0 = MDAT0 output is disabled (default)
bit 10-1 Unimplemented: Read as ‘0’
bit 0 DRSTATUS: Data Ready Status bit
DRSTATUS = 1– Channel CH0 data are not ready (default)
DRSTATUS = 0– Channel CH0 data are ready. The status bit is set back to ‘1’ after reading the
STATUSCOM register. The status bit is not set back to ‘1’ by the read of the corresponding channel
ADC data.
REGISTER 9-5: STATUSCOM REGISTER (CONTINUED)
2014-2019 Microchip Technology Inc. DS20005287B-page 71
MCP3918
9.6 CONFIG0 Register –
Configuration Register 0
Name Bits Address Cof.
CONFIG0 24 0x0D R/W
REGISTER 9-6: CONFIG0 REGISTER
R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0
EN_OFFCAL EN_GAINCAL DITHER[1:0] BOOST[1:0] PRE[1:0]
bit 23 bit 16
R/W-0 R/W-1 R/W-1 U-0 U-0 U-0 U-0 U-0
OSR[2:0] — — — — —
bit 15 bit 8
R/W-0 R/W-1 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0
VREFCAL[7:0]
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 23 EN_OFFCAL: 24-Bit Digital Offset Error Calibration on All Channels Enable bit
1 = Enabled; this mode does not add any group delay to the ADC data
0 = Disabled (default)
bit 22 EN_GAINCAL: 24-Bit Digital Gain Error Calibration on All Channels Enable/Disable bit
1 = Enabled; this mode adds a group delay on all channels of 24 DMCLK periods, all data ready pulses
are delayed by 24 clock periods compared to the mode with EN_GAINCAL = 0
0 = Disabled (default)
bit 21-20 DITHER[1:0]: Dithering Circuit for Idle Tones Cancellation and Improved THD on All Channels Control bits
11 = Dithering on, Strength = Maximum (default)
10 = Dithering on, Strength = Medium
01 = Dithering on, Strength = Minimum
00 = Dithering is turned off
bit 19-18 BOOST[1:0]: Bias Current Selection for the ADC bits
(impacts achievable maximum sampling speed, see Ta b l e 5 - 2 )
11 = All channels have current x 2
10 = All channels have current x 1 (default)
01 = All channels have current x 0.66
00 = All channels have current x 0.5
bit 17-16 PRE[1:0]: Analog Master Clock (AMCLK) Prescaler Value bits
11 = AMCLK = MCLK/8
10 = AMCLK = MCLK/4
01 = AMCLK = MCLK/2
00 = AMCLK = MCLK (default)
MCP3918
DS20005287B-page 72 2014-2019 Microchip Technology Inc.
bit 15-13 OSR[2:0]: Oversampling Ratio for Delta-Sigma A/D Conversion bits (all channels, fD/fS)
111 = 4096 (fD= 244 sps for MCLK = 4 MHz, fS=AMCLK=1MHz)
110 = 2048 (fD= 488 sps for MCLK = 4 MHz, fS=AMCLK=1MHz)
101 = 1024 (fD= 976 sps for MCLK = 4 MHz, fS=AMCLK=1MHz)
100 = 512 (fD= 1.953 ksps for MCLK = 4 MHz, fS=AMCLK=1MHz)
011 = 256 (fD= 3.90625 ksps for MCLK = 4 MHz, fS= AMCLK = 1 MHz) (Default)
010 = 128 (fD= 7.8125 ksps for MCLK = 4 MHz, fS= AMCLK = 1 MHz)
001 = 64 (fD= 15.625 ksps for MCLK = 4 MHz, fS=AMCLK=1MHz)
000 = 32 (fD= 31.25 ksps for MCLK = 4 MHz, fS= AMCLK = 1 MHz)
bit 12-8 Unimplemented: Read as ‘0’
bit 7-0 VREFCAL[7:0]: Internal Voltage Temperature Coefficient VREFCAL[7:0] Value bits
See Section 5.6.3 “Temperature Compensation (VREFCAL[7:0])” for complete description.
REGISTER 9-6: CONFIG0 REGISTER (CONTINUED)
2014-2019 Microchip Technology Inc. DS20005287B-page 73
MCP3918
9.7 CONFIG1 Register –
Configuration Register 1
Name Bits Address Cof.
CONFIG1 24 0x0E R/W
REGISTER 9-7: CONFIG1 REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
— — — — — — — RESET[0]
bit 23 bit 16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
— — — — — — — SHUTDOWN[0]
bit 15 bit 8
R/W-0 R/W-1 U-0 U-0 U-0 U-0 U-0 U-0
VREFEXT CLKEXT — — — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 23-17 Unimplemented: Read as ‘0’
bit 16 RESET[0]: ADC Soft Reset Mode Setting bit
1 = ADC channel is in Soft Reset mode
0 = ADC channel is not in Soft Reset mode
bit 15-9 Unimplemented: Read as ‘0’
bit 8 SHUTDOWN[0]: ADC Shutdown Mode Setting bit
1 = ADC channel is in Shutdown mode
0 = ADC channel is not in Shutdown mode
bit 7 VREFEXT: Internal Voltage Reference Selection bit
1 = Internal Voltage Reference Disabled: An external reference voltage needs to be applied across the
REFIN+/- pins; the analog power consumption (AIDD) is slightly diminished in this mode since the
internal voltage reference is placed in Shutdown mode
0 = Internal Voltage Reference Enabled: For optimal accuracy, the REFIN+/OUT pin needs proper
decoupling capacitors; REFIN- pin should be connected to AGND when in this mode
bit 6 CLKEXT: Internal Clock Selection bit
1 = MCLK is generated externally and should be provided on the OSC1 pin; the crystal oscillator is
disabled and consumes no current (default)
0 = Crystal oscillator is enabled; a crystal must be placed between OSC1 and OSC2 with proper decoupling
capacitors, the digital power consumption (DIDD) is increased in this mode due to the oscillator
bit 5-0 Unimplemented: Read as ‘0’
MCP3918
DS20005287B-page 74 2014-2019 Microchip Technology Inc.
9.8 OFFCAL_CH0 and GAINCAL_CH0
Registers – Digital Offset and Gain
Error Calibration Registers
Name Bits Address Cof.
OFFCAL_CH0 24 0x0F R/W
GAINCAL_CH0 24 0x10 R/W
REGISTER 9-8: OFFCAL_CHn REGISTERS
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
OFFCAL_CH0[23:16]
bit 23 bit 16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
OFFCAL_CH0[15:8]
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
OFFCAL_CH0[7:0]
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 23-0 OFFCAL_CH0[23:0]: Corresponding Channel CH0 Digital Offset Calibration Value bits
This register is simply added to the output code of the channel, bit-by-bit. This register is a 24-bit two’s
complement MSB first coding register. CH0 Output Code = OFFCAL_CH0 + ADC CH0 Output Code.
This register is a Don’t Care if EN_OFFCAL = 0 (offset calibration disabled), but its value is not cleared
by the EN_OFFCAL bit.
2014-2019 Microchip Technology Inc. DS20005287B-page 75
MCP3918
REGISTER 9-9: GAINCAL_CHn REGISTERS
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
GAINCAL_CH0[23:16]
bit 23 bit 16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
GAINCAL_CH0[15:8]
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
GAINCAL_CH0[7:0]
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 23-0 GAINCAL_CH0[23:0]: Corresponding Channel CH0 Digital Gain Error Calibration Value bits
This register is a 24-bit MSB first format with a range of -1x to +0.9999999x (from 0x800000 to
0x7FFFFF). The gain calibration adds 1x to this register and multiplies it to the output code of the
channel, bit-by-bit, after offset calibration. The range of the gain calibration is thus from 0x to
1.9999999x (from 0x800000 to 0x7FFFFF). The LSB corresponds to a 2-23 increment in the multiplier.
ADC Output Code = (GAINCAL_CH0 + 1) * ADC CH0 Output Code. This register is a Don’t Care if
EN_GAINCAL = 0 (gain calibration disabled), but its value is not cleared by the EN_GAINCAL bit.
MCP3918
DS20005287B-page 76 2014-2019 Microchip Technology Inc.
9.9 SECURITY Register – Password
and CRC-16 on Register Map
Name Bits Address Cof.
LOCK/CRC 24 0x1F R/W
REGISTER 9-10: LOCK/CRC REGISTER
R/W-1 R/W-0 R/W-1 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1
LOCK[7:0]
bit 23 bit 16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CRCREG[15:8]
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CRCREG[7:0]
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 23-16 LOCK[7:0]: Lock Code for Writable Part of Register Map bits
LOCK[7:0] = PASSWORD = 0xA5 (default value): The entire register map is writable. The
CRCREG[15:0] bits and the CRC interrupt are cleared. No CRC-16 checksum on register map is
calculated.
LOCK[7:0] Bits are Different from 0xA5: The only writable register is the LOCK/CRC register. All other
registers will appear as undefined while in this mode. The CRCREG checksum is calculated
continuously and can generate interrupts if the CRC interrupt EN_INT bit has been enabled. If a write
to a register needs to be performed, the user needs to unlock the register map beforehand by writing
0xA5 to the LOCK[7:0] bits.
bit 15-0 CRCREG[15:0]: CRC-16 Checksum Calculated with Writable Part of Register Map as a Message bits
This is a read-only 16-bit code. This checksum is continuously recalculated and updated every
10 DMCLK periods. It is reset to its default value (0x0000) when LOCK[7:0] = 0xA5.
2014-2019 Microchip Technology Inc. DS20005287B-page 77
MCP3918
10.0 PACKAGING INFORMATION
10.1 Package Marking Information
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
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PIN 1
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3918
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A1
E/ML
915256
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XXXXXXXXXXX
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DS20005287B-page 78 2014-2019 Microchip Technology Inc.
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DS20005287B-page 82 2014-2019 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
MCP3918
DS20005287B-page 84 2014-2019 Microchip Technology Inc.
NOTES:
2014-2019 Microchip Technology Inc. DS20005287B-page 85
MCP3918
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Device: MCP3918A1: One Channel Analog Font End Converter
Address Options: XX A6 A5
A0 = 0 0
A1* = 0 1
A2 = 1 0
A3 = 1 1
* Default option. Contact Microchip factory for other
address options
Tape and Reel: T = Tape and Reel
Temperature Range: E = -40°C to +125°C
Package: ML = 20-Lead Plastic Quad Flat, No Lead Package –
4x4x0.9 mm Body (QFN)
SS = 20-Lead Plastic Shrink Small Outline – 5.30 mm
Body (SSOP)
Examples:
a) MCP3918A1-E/ML: Address Option A1,
Extended Temperature,
20-Lead QFN Package
b) MCP3918A1T-E/ML: Address Option A1,
Tape and Reel,
Extended Temperature,
20-Lead QFN Package
a) MCP3918A1-E/SS: Address Option A1,
Extended Temperature,
20-Lead SSOP Package
b) MCP3918A1T-E/SS: Address Option A1,
Tape and Reel,
Extended Temperature,
20-Lead SSOP package
PART NO. X
Temperature
Range
Device
/XX
Package
X
Tape and
Reel
XX
Address
Options
MCP3918
DS20005287B-page 86 2014-2019 Microchip Technology Inc.
NOTES:
2014-2019 Microchip Technology Inc. DS20005287B-page 87
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate, AVR,
AVR logo, AVR Freaks, BitCloud, chipKIT, chipKIT logo,
CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo,
JukeBlox, KeeLoq, Kleer, LANCheck, LINK MD, maXStylus,
maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB,
OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip
Designer, QTouch, SAM-BA, SpyNIC, SST, SST Logo,
SuperFlash, tinyAVR, UNI/O, and XMEGA are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
and other countries.
ClockWorks, The Embedded Control Solutions Company,
EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS,
mTouch, Precision Edge, and Quiet-Wire are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, BodyCom, CodeGuard,
CryptoAuthentication, CryptoAutomotive, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, INICnet, Inter-Chip Connectivity,
JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi,
motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB,
MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation,
PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon,
QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O,
SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2019, Microchip Technology Incorporated, All Rights
Reserved.
ISBN: 978-1-5224-4260-8
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITY MANAGEMENT S
YSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
DS20005287B-page 88 2014-2019 Microchip Technology Inc.
AMERICAS
Corporate Office
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Tel: 480-792-7200
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Technical Support:
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Web Address:
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ASIA/PACIFIC
Australia - Sydney
Tel: 61-2-9868-6733
China - Beijing
Tel: 86-10-8569-7000
China - Chengdu
Tel: 86-28-8665-5511
China - Chongqing
Tel: 86-23-8980-9588
China - Dongguan
Tel: 86-769-8702-9880
China - Guangzhou
Tel: 86-20-8755-8029
China - Hangzhou
Tel: 86-571-8792-8115
China - Hong Kong SAR
Tel: 852-2943-5100
China - Nanjing
Tel: 86-25-8473-2460
China - Qingdao
Tel: 86-532-8502-7355
China - Shanghai
Tel: 86-21-3326-8000
China - Shenyang
Tel: 86-24-2334-2829
China - Shenzhen
Tel: 86-755-8864-2200
China - Suzhou
Tel: 86-186-6233-1526
China - Wuhan
Tel: 86-27-5980-5300
China - Xian
Tel: 86-29-8833-7252
China - Xiamen
Tel: 86-592-2388138
China - Zhuhai
Tel: 86-756-3210040
ASIA/PACIFIC
India - Bangalore
Tel: 91-80-3090-4444
India - New Delhi
Tel: 91-11-4160-8631
India - Pune
Tel: 91-20-4121-0141
Japan - Osaka
Tel: 81-6-6152-7160
Japan - Tokyo
Tel: 81-3-6880- 3770
Korea - Daegu
Tel: 82-53-744-4301
Korea - Seoul
Tel: 82-2-554-7200
Malaysia - Kuala Lumpur
Tel: 60-3-7651-7906
Malaysia - Penang
Tel: 60-4-227-8870
Philippines - Manila
Tel: 63-2-634-9065
Singapore
Tel: 65-6334-8870
Taiwan - Hsin Chu
Tel: 886-3-577-8366
Taiwan - Kaohsiung
Tel: 886-7-213-7830
Taiwan - Taipei
Tel: 886-2-2508-8600
Thailand - Bangkok
Tel: 66-2-694-1351
Vietnam - Ho Chi Minh
Tel: 84-28-5448-2100
EUROPE
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
Finland - Espoo
Tel: 358-9-4520-820
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Germany - Garching
Tel: 49-8931-9700
Germany - Haan
Tel: 49-2129-3766400
Germany - Heilbronn
Tel: 49-7131-67-3636
Germany - Karlsruhe
Tel: 49-721-625370
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Germany - Rosenheim
Tel: 49-8031-354-560
Israel - Ra’anana
Tel: 972-9-744-7705
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Italy - Padova
Tel: 39-049-7625286
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Norway - Trondheim
Tel: 47-7288-4388
Poland - Warsaw
Tel: 48-22-3325737
Romania - Bucharest
Tel: 40-21-407-87-50
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
Sweden - Gothenberg
Tel: 46-31-704-60-40
Sweden - Stockholm
Tel: 46-8-5090-4654
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
Worldwide Sales and Service
08/15/18
