MP7529B
1
Rev. 2.00
FEATURES
•Very Low Total Harmonic Distortion
•Low Glitch Energy
•Fast Settling Time
•Four Quadrant Multiplication
•On-Chip Latches for Both DACs
•4.5 V to 5.5 V Operation
•Low Power Consumption
•TTL/5V CMOS Compatible
•Latch-Up Free
•15 V Operation: MP7529A
5 V CMOS
Dual Buffered Multiplying 8-Bit
Digital-to-Analog Converter
BENEFITS
•Quiet Operation in Audio Applications
•Easy Interface to Microprocessors
GENERAL DESCRIPTION
The MP7529B is a dual 8-bit Digital-to-Analog Converter
featuring excellent DAC to DAC matching, tracking and
specifically optimized for applications requiring low total
harmonic distortion. The MP7529B is manufactured using
advanced thin film resistors on a double metal CMOS process.
The MP7529B incorporates a unique bit decoding technique
yielding lower glitch energy, higher speed and excellent
accuracy over temperature and time.
Data is transferred to either of the two D/A Converter latches
via a common 8-bit TTL/5 V CMOS compatible input port. The
control input DAC A/DAC B determines which D/A is to be
loaded.
The device operates from a 4.5 V to 5.5 V power supply , and
is TTL-compatible over this range. Power dissipation is only 10
mW. Both DACs offer excellent four quadrant multiplication
characteristics, and include separate reference inputs and
feedback resistors. An improved latch-up resistant design
eliminates the need for external protective Schottky diodes in
most applications.
SIMPLIFIED BLOCK AND TIMING DIAGRAM
DGND
LA TCH A
LATCH B
DAC A
DAC B
D
E
Q
D
E
Q
DB7-DB0
OUT
DB7-DB0
AGND
VDD VREFA
RFBA
IOUTA
RFBB
IOUTB
VREFB
DAC A/DAC B
CS
WR
DAC A/DAC B
CS
WR
MP7529B
2
Rev. 2.00
ORDERING INFORMATION
Package
Type Temperature
Range Part No.
Plastic Dip
Plastic Dip
MP7529BJN
MP7529BKN
–40 to +85°C+1
+1/2
+1
+1
+5
+3
SOIC MP7529BJS +1+1+5
SOIC MP7529BKS +1/2 +1+3
–40 to +85°C
–40 to +85°C
–40 to +85°C
MP7529BJP
PLCC MP7529BKP
–40 to +85°C
PLCC –40 to +85°C+1+1+5
+
1/2 +1+3
INL
(LSB) Gain Error
(LSB)
DNL
(LSB)
PIN CONFIGURATIONS
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
AGND
DGND
(MSB) DB7
DB6
DB5
DB4
DB0 (LSB)
DB1
DB2
DB3
20 Pin PDIP (0.300”)
N20
RFBA
VREFA
RFBB
VREFB
VDD
201
1110
2
3
4
5
6
715
14
13
12
17
16
8
9
19
18
20 Pin SOIC (Jedec, 0.300”)
S20
IOUTA
IOUTB
3 2 1 20 19
9 10111213
4
5
6
7
8
18
17
16
15
14
AGND
DGND
(MSB) DB7
DB6
DB5DB4 DB3 DB2 DB1
DB0
(LSB)
IOUTB
IOUTA
20 Pin PLCC
P20
RFBA
VREFA VREFB
VDD
RFBB
See
Pin Out
at Left
See Packaging Section for Package Dimensions
DAC A/DAC B CS
WR DAC A/DAC B
CS
WR
PIN OUT DEFINITIONS
PIN NO. NAME DESCRIPTION
1 AGND Analog Ground
2I
OUTA Current Output of DAC A
3R
FBA Internal Feedback Resistor of DAC A
4V
REFA Reference Input Voltage of DAC A
5 DGND Digital Ground
6 DACA/ DAC selection control
DACB
7 DB7 Data Input Bit 7 (MSB)
8 DB6 Data Input Bit 6
9 DB5 Data Input Bit 5
10 DB4 Data Input Bit 4
PIN NO. NAME DESCRIPTION
11 DB3 Data Input Bit 3
12 DB2 Data Input Bit 2
13 DB1 Data Input Bit 1
14 DB0 Data Input Bit 0 (LSB)
15 CS Chip Select (Active Low)
16 WR Write Enable (Active Low)
17 VDD Power Supply
18 VREFB Reference Input Voltage of DAC B
19 RFBB Internal Feedback Resistor of DAC B
20 IOUTB Current Output of DAC B
MP7529B
3
Rev. 2.00
25°CTmin to Tmax
ELECTRICAL CHARACTERISTICS
(VDD = 4.5 V to 5.5 V, Nominal VDD = 5 V, VREF = 10 V unless otherwise noted)
Parameter Symbol Min Typ Max Min Max Units T est Conditions/Comments
STATIC PERFORMANCE1
Resolution (All Grades) N 8 8 Bits
Integral Non-Linearity INL LSB End Point Linearity Spec.
(Relative Accuracy)
J+
1+1
K+
1/2 +1/2
Differential Non-Linearity DNL LSB All grades monotonic over full
J+
1+1 temperature range.
K+
1+1
Gain Error GE LSB Using Internal RFB
J+4+5
K+
2+3
Gain Temperature Coefficient2TCGE +15 +15 ppm/°C∆Gain/∆Temperature
Power Supply Rejection Ratio PSRR +100 +200 ppm/% |∆Gain/∆VDD|, ∆VDD = + 5%
VDD = 4.75 V, +5%, & 5.25 V +5%
Output Leakage Current ILKG +50 +200 nA
DYNAMIC PERFORMANCE2
Harmonic Distortion THD –95 dB VIN = 6VRMS @ 1 KHz
Digital Crosstalk Q 30 nVs
AC Feedthrough FTdB
VREFA to IOUTA FTA –70 –65 dB
VREFB to IOUTB FTB –70 –65 dB
Channel-to-Channel Isolation CCI dB
VREFA to IOUTB CCIBA –77 dB
VREFB to IOUTA CCIAB –77 dB
Glitch Energy Egl 10 nVs All zeros to all ones Input Change.
Current Settling Time tS200 250 ns To 1/2 LSB,RL=100Ω, CEXT=13pF
Propagation Delay tPD 100 150 ns From 50% of digital input to 90%
of final analog output current
RL=100Ω, CEXT=13pF
REFERENCE INPUT
Input Resistance RIN 8 15 8 15 kΩ
Input Resistance Matching +1+1%
DIGITAL INPUTS3
Logical “1” Voltage VIH 2.4 2.4 V
Logical “0” Voltage VIL 0.8 0.8 V
Input Leakage Current ILKG +1+10 µA
Input Capacitance2
Data CIN 10 10 pF
Control CIN 15 15 pF
MP7529B
4
Rev. 2.00
ELECTRICAL CHARACTERISTICS (CONT’D)
25°CTmin to Tmax
Parameter Symbol Min Typ Max Min Max Units T est Conditions/Comments
ANALOG OUTPUTS2
Output Capacitance COUTA/B 120 120 pF DAC inputs all 1’s
COUTA/B 50 50 pF DAC inputs all 0’s
POWER SUPPLY
Supply Current IDD 1 1 mA All digital inputs = 0 V or 5 V
2 2 mA All digital inputs = VIL or VIH
TIMING SPECIFICATIONS4
Chip Select to Write Set-Up Time tCS 60 80 ns
Chip Select to Write Hold Time tCH 15 20 ns
DAC Select to Write Set-Up Time tAS 60 80 ns
DAC Select to Write Hold Time tAH 15 20 ns
Data Valid to Write Set-Up Time tDS 60 80 ns
Data Valid to Write Hold Time tDH 00ns
Write Pulse Width5tWR 60 80 ns
NOTES:
Specifications are subject to change without notice
1Full Scale Range (FSR) is 10V for unipolar mode.
2Guaranteed but not production tested.
3Digital input levels should not go below GND or exceed the positive supply voltage, otherwise damage may occur.
4See timing diagram.
5tWR = 40ns minimum if tDH > 15ns (@T = 25°C)
ABSOLUTE MAXIMUM RATINGS (TA = +25°C unless otherwise noted)1, 2, 3
VDD to GND 0 to +7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AGND to DGND +1 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(Functionality Guaranteed +0.5 V)
Digital Input Voltage to GND GND –0.5 to VDD +0.5 V. . . .
IOUTA, IOUTB to GND GND –0.5 to VDD +0.5 V. . . . . . . . . . .
VREFA, VREFB to GND +25 V. . . . . . . . . . . . . . . . . . . . . . . . . . .
VRFBA, VRFBB to GND +25 V. . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage Temperature –65°C to +150°C. . . . . . . . . . . . . . . . .
Lead Temperature (Soldering, 10 seconds) +300°C. . . . . .
Package Power Dissipation Rating to 75°C
PDIP, SOIC, PLCC 900mW. . . . . . . . . . . . . . . . . . . . . . . .
Derates above 75°C 12mW/°C. . . . . . . . . . . . . . . . . . . . .
NOTES:
1Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
2Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps
(HP5082-2835) from input pin to the supplies.
All inputs have protection diodes
which will protect the device from short
transients outside the supplies of less than 100mA for less than 100µs.
3GND refers to AGND and DGND.
MP7529B
5
Rev. 2.00
DIGITAL INTERFACE
The digital inputs are designed to be both TTL and 5 V CMOS
compatible. All logic inputs are static protected MOS gates with
typical input currents of less than 10nA.
The control input DAC A/DAC B selects which DAC can ac-
cept data from the input port. Inputs CS and WR control the op-
erating mode of the selected DAC (
Table 1.
). When CS and WR
are both low the selected DAC is in the write mode. The input
data latches of the selected DAC are transparent and its analog
output responds to activity on DB0-DB7 (Write mode). The se-
lected DAC latch retains the data which was present on
DB0-DB7 just prior to CS or WR assuming a high state. Both
analog outputs remain at the values corresponding to the data in
their respective latches (Hold mode).
VALID
CS
DAC A/
DAC B
WR
NOTE:
Figure 1. Write Cycle Timing Diagram
DB7-DB0
VALID DAC A/
DAC B CS WR DAC A DAC B
L
H
X
X
L
L
H
X
L
L
X
H
WRITE
HOLD
HOLD
HOLD
HOLD
WRITE
HOLD
HOLD
L = Low State H = High State X = Don’t Care
Table 1. DAC’s Mode Selection
1. T iming measured from (VIH + VIL) /2
tCS tCH
tAS tAH
tWR
tDS tDH
MICROPROCESSOR INTERFACE
DAC A
DAC B
DB0
DB7
ADDRESS
DECODE
LOGIC
A0-A15
φ2
D0–D7
A+1***
A**
MP7529B*
CPU
6800
*Analog circuitry has been omitted for clarity
**A = Decoded 7529B DAC A Address
***A + 1 = Decoded 752B9 DAC B Address
Figure 2. MP7529B Dual DAC to 6800
CPU Interface
DAC A
DAC B
DB0
DB7
A8-A15
AD0–AD7
ADDRESS
DECODE
LOGIC
A+1***
A**
MP7529B*
CPU
8085
Figure 3. MP7529B Dual DAC to 8085
CPU Interface
LATCH
8212
ALE
NOTE:
8085 instruction shld (store H & L direct) can update
both DACS with data from H and L registers
*Analog circuitry has been omitted for clarity
**A = Decoded 7529B DAC A Address
***A + 1 = Decoded 7529B DAC B Address
VMA
Address Bus
Data Bus
Address Bus
ADDR/Data Bus
DAC A/DAC B
CS
WR
DAC A/DAC B
CS
WRWR
MP7529B
6
Rev. 2.00
PERFORMANCE CHARACTERISTICS
Graph 1. Relative Accuracy vs. Digital Code
APPLICATION NOTES
Refer to Section 8 for Applications Information
MP7529B
7
Rev. 2.00
SYMBOL MIN MAX MIN MAX
A 0.097 0.104 2.464 2.642
A10.0050 0.0115 0.127 0.292
B 0.014 0.019 0.356 0.483
C 0.0091 0.0125 0.231 0.318
D 0.500 0.510 12.70 12.95
E 0.292 0.299 7.42 7.59
e 0.050 BSC 1.27 BSC
H 0.400 0.410 10.16 10.41
h 0.010 0.016 0.254 0.406
L 0.016 0.035 0.406 0.889
α0°8°0°8°
INCHES MILLIMETERS
e
20 11
20 LEAD SMALL OUTLINE
(300 MIL JEDEC SOIC)
S20
10
D
E H
B
A
L
C
A1
Seating
Plane α
h x 45°
MP7529B
8
Rev. 2.00
A 0.165 0.180 4.19 4.57
A10.100 0.110 2.54 2.79
A20.148 0.156 3.76 3.96
B 0.013 0.021 0.330 0.533
C 0.008 0.012 0.203 0.305
D 0.385 0.395 9.78 10.03
D1 (1) 0.350 0.354 8.89 8.99
D20.290 0.330 7.37 8.38
D30.200 Ref 5.08 Ref.
e10.050 BSC 1.27 BSC
20 LEAD PLASTIC LEADED CHIP CARRIER
(PLCC)
P20
SYMBOL MIN MAX MIN MAX
INCHES MILLIMETERS
1
D
D1
D2
B
e1
A
A1
C
D D1
Seating
Plane
D3
Note: (1) Dimension D1 does not include mold protrusion.
Allowed mold protrusion is 0.254 mm/0.010 in.
A2
MP7529B
9
Rev. 2.00
20 LEAD PLASTIC DUAL-IN-LINE
(300 MIL PDIP)
N20
20
1
11
10
D
eB
1
A
1
E
1
α
C
E
A
L
B
Q
1
Seating
Plane
SYMBOL MIN MAX MIN MAX
INCHES
A –– 0.200 –– 5.08
A10.015 –– 0.38 ––
B 0.014 0.023 0.356 0.584
B1 (1) 0.038 0.065 0.965 1.65
C 0.008 0.015 0.203 0.381
D 0.945 1.060 24.0 26.92
E 0.295 0.325 7.49 8.26
E10.220 0.310 5.59 7.87
e 0.100 BSC 2.54 BSC
L 0.115 0.150 2.92 3.81
α0°15°0°15°
Q10.055 0.070 1.40 1.78
S 0.040 0.080 1.02 2.03
MILLIMETERS
S
Note: (1) The minimum limit for dimensions B1 may be 0.023”
(0.58 mm) for all four corner leads only.
MP7529B
10
Rev. 2.00
Notes
MP7529B
11
Rev. 2.00
Notes
MP7529B
12
Rev. 2.00
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to im-
prove design, performance or reliability . EXAR Corporation assumes no responsibility for the use of any circuits de-
scribed herein, conveys no license under any patent or other right, and makes no representation that the circuits are
free of patent infringement. Charts and schedules contains here in are only for illustration purposes and may vary
depending upon a user’s specific application. While the information in this publication has been carefully checked;
no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly
affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation
receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the
user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circum-
stances.
Copyright EXAR Corporation
Datasheet April 1995
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
