PE35400
Document Category: Product Specification
UltraCMOS® Divide-by-4 Prescaler, 3–13.5 GHz
©2015, Peregrine Semiconductor Corporation. All rights reserved. • Headquarters: 9380 Carroll Park Drive, San Diego, CA, 92121
Product Specification DOC-64872-2 – (10/2015)
www.psemi.com
Features
• High frequency support up to 13.5 GHz
• Low SSB phase noise of –135 dBc/Hz @
3.025 GHz output frequency
• Low supply current of 16 mA
• Bare die
Applications
• Wireless communication
• Test and measurement
• Phased array radar
Product Description
The PE35400 is a high-performance UltraCMOS® prescaler with a fixed divide ratio of 4. It supports an operating
frequency range from 3–13.5 GHz. It operates on a single voltage supply with a frequency-selecting bias resistor
and draws a low current of 16 mA. The PE35400 is available in bare die.
The PE35400 is manufactured on Peregrine’s UltraCMOS process, a patented variation of silicon-on-insulator
(SOI) technology on a sapphire substrate, offering the performance of GaAs with the economy and integration of
conventional CMOS.
Figure 1 • PE35400 Functional Diagram
DQ
Q
DQ
Q
PE35400
Divide-by-4 Prescaler
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Absolute Maximum Ratings
Exceeding absolute maximum ratings listed in Table 1 may cause permanent damage. Operation should be
restricted to the limits in Table 2. Operation between operating range maximum and absolute maximum for
extended periods may reduce reliability.
ESD Precautions
When handling this UltraCMOS device, observe the same precautions as with any other ESD-sensitive devices.
Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to
avoid exceeding the rating specified in Table 1.
Latch-up Immunity
Unlike conventional CMOS devices, UltraCMOS devices are immune to latch-up.
Recommended Operating Conditions
Table 2 lists the recommending operating conditions for the PE35400. Devices should not be operated outside
the recommended operating conditions listed below.
Table 1 • Absolute Maximum Ratings for PE35400
Parameter/Condition Min Max Unit
Supply voltage, VDD –0.3 3.3 V
Input power, 50Ω+14 dBm
Storage temperature range –65 +150 °C
ESD voltage HBM, all pins(*) 250 V
Note: * Human body model (MIL-STD 883 Method 3015).
Table 2 • Recommended Operating Conditions for PE35400
Parameter Min Typ Max Unit
Supply voltage, VDD 2.65 2.8 2.95 V
Input power, 50Ω, based on optimal RBIAS (see Figure 3), PIN +7 dBm
Operating temperature range –40 +85 °C
PE35400
Divide-by-4 Prescaler
DOC-64872-2 – (10/2015) Page 3
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Electrical Specifications
Table 3 provides the PE35400 key electrical specifications @ +25 °C, VDD = 2.8V (ZS = ZL = 50Ω), unless
otherwise specified.
Table 3 • PE35400 Electrical Specifications(*)
Parameter Condition Min Typ Max Unit
Operating frequency, FIN 3.0 GHz 13.5 GHz As shown
Input power sensitivity
FIN = 3–4.5 GHz –5 > –7 dBm
FIN = >4.5–11.5 GHz –15 > –20 dBm
FIN = >11.5–13.5 GHz –1 > –7 dBm
Output power 0.75–3.375 GHz output frequency range 0 5 dBm
Reverse leakage FIN = 3–13.5 GHz, PIN = 0 dBm –45 dBm
SSB phase noise 3.025 GHz output frequency @ 100 kHz offset, PIN = 0 dBm –135 dBc/Hz
Supply current, IDD FIN = 8 GHz 16 mA
Note: * All values in Min/Max columns are guaranteed by design characterization.
PE35400
Divide-by-4 Prescaler
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Device Functional Considerations
The PE35400 divides a 3.0–13.5 GHz input signal by four, producing a 750 MHz to 3.375 GHz output signal. In
order for the prescaler to work properly, several conditions need to be adhered to. It is crucial that VBYPS and VDD
are supplied with bypass capacitors to ground. In addition, the output signal RFOUT needs to be AC coupled via
an external capacitor, as shown in Figure 2. The input frequency range is selected by the value of RBIAS
according to Figure 3. The ground pattern on the board should be made as wide as possible to minimize ground
impedance.
Figure 2 • Circuit Block Diagram for PE35400(*)
Note: * For optimal performance, the following bond wire configuration is recommended. VBYPS: 2 bond wires per pad. RFIN: 1 bond wire. GND: 3
bond wires per pad. RFOUT
: 2 bond wires. VDD: 2 bond wires. RBIAS: 1 bond wire.
RBIAS RBIAS
10 pF
10 pF
6.8 pF
50Ω
50Ω
0.01 μF
0.01 μF
10 pF
VBYPS
GND
Transmission
Line Transmission
Line
Die ID
VDD
RFIN RFOUT
GND
VDD
VBYPS
PE35400
Divide-by-4 Prescaler
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Typical Performance Data
Figure 3 through Figure 11 show the typical performance data @ +25 °C, VDD = 2.8V (ZS = ZL = 50Ω), based on
optimal RBIAS as shown in Figure 3, unless otherwise specified.
Figure 3 • Frequency vs RBIAS
0
2
4
6
8
10
12
14
16
5.6 8.2 12 18 27 39 56
Lower Freq Limit (P
IN
= 0 dBm) Upper Freq Limit (P
IN
= 0 dBm)
Optimal Level Lower Freq Limit (P
IN
= -7 dBm)
Upper Freq Limit (P
IN
= -7 dBm)
RBIAS (kΩ)
Input Frequency (GHz)
PE35400
Divide-by-4 Prescaler
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Figure 4 • Input Power Sensitivity
-25
-20
-15
-10
-5
0
5
10
123456789101112131415
Input Power (dBm)
Input Frequency (GHz)
Min PIN Max PIN
RBIAS = 56 kΩ
Recommended input power
operating region
RBIAS = 5.6 kΩ
4.5 GHz 11.5 GHz
Figure 5 • Input Power Sensitivity vs Temperature
-25
-20
-15
-10
-5
0
5
10
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Input Power (dBm)
Input Frequency (GHz)
Min PIN -40 °C Min PIN +25 °C Min PIN +85 °C
Max PIN -40 °C Max PIN +25 °C Max PIN +85 °C
RBIAS = 56 kΩ RBIAS = 5.6 kΩ
4.5 GHz 11.5 GHz
PE35400
Divide-by-4 Prescaler
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Figure 6 • Output Power vs VDD
RBIAS Max
= 56 kΩ
RBIAS Min
= 5.6 kΩ
0
1
2
3
4
5
6
7
8
9
10
2 3 4 5 6 7 8 9 10 11 12 13 14
Ouput Power (dBm)
Input Frequency (GHz)
Output power @ 2.65V Output power @ 2.8V Output power @ 2.95V
214
Figure 7 • Output Power vs Temperature
RBIAS Max
= 56 kΩ
RBIAS Min
= 5.6 kΩ
0
1
2
3
4
5
6
7
8
9
10
2 3 4 6 7 8 9 10 11 12 13 14
Output power @ -40 °C Output power @ +25 °C Output power @ +85 °C
Output Power (dBm)
Input Frequency (GHz)
214
PE35400
Divide-by-4 Prescaler
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Figure 8 • SSB Phase Noise @ 3.025 GHz Output Frequency, PIN = 0 dBm
-160
-155
-150
-145
-140
-135
-130
-125
1.E+05 1.E+06 1.E+07
Phase Noise (dBc/Hz)
Offset Frequency (Hz)
SSB Phase Noise @ 3.025 GHz Output Frequency
Figure 9 • Output Harmonics, PIN = 0 dBm
PE35400
Divide-by-4 Prescaler
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Figure 10 • IDD vs RBIAS
10
11
12
13
14
15
16
17
18
19
20
5.6 8.2 12 18 27 39 56
IDD (mA)
RBIAS (kΩ)
Supply Current
Figure 11 • Reverse Leakage, PIN = 0 dBm
-70
-60
-50
-40
-30
-20
2 3 4 5 6 7 8 9 10 11 12 13 14
Power Level (dBm)
Input Frequency (GHz)
Reverse Leakage
PE35400
Divide-by-4 Prescaler
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Pad Configuration
This section provides pad information for the
PE35400. Figure 12 shows the pad configuration of
this device. Table 4 provides a description for each
pad.
Figure 12 • Pad Configuration (Top View)
VBYPS
1
2
34
5
6
7
8
RBIAS
VBYPS
GND
Die ID GND
VDD
RFIN RFOUT
Table 4 • Pad Descriptions for PE35400
Pad No. Pad
Name Description
1VBYPS Prescaler supply bypass
2VBYPS Prescaler supply bypass
3RFIN RF input
4 GND Ground
5RFOUT RF output
6VDD Supply voltage
7RBIAS Frequency selecting bias resistor
8 GND Ground
PE35400
Divide-by-4 Prescaler
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Die Mechanical Specifications
This section provides the die mechanical specifications for the PE35400.
Table 5 • Mechanical Specifications for PE35400
Parameter Min Typ Max Unit Condition
Die size, singulated (x,y) 866 × 716 886 × 736 916 × 766 µm Including excess sapphire, max
tolerance = –20/+30 µm
Wafer thickness 180 200 220 µm
Wafer size 150 mm
Table 6 • Pad Coordinates for PE35400(*)
Pad
No.
Pad
Name
Pad Center (µm) Pad Opening
Size (µm)
XYXY
1VBYPS –303 198 160 180
2VBPYS –303 –3 160 180
3RFIN –303 –208 100 100
4 GND 68 –243 290 130
5RFOUT 333 –193 100 190
6VDD 31840130190
7RBIAS 318 243 130 130
8 GND 14 243 290 130
Note: * All pad locations originate from the die center and refer to the
center of the pad.
Figure 13 • Pad Layout for PE35400(1)(2)
Notes:
1) Drawings are not drawn to scale.
2) Singulated die size shown, pad side up.
VBYPS
1
2
34
5
6
7
8
RBIAS
VBYPS
GND
Die ID GND
VDD
RFIN RFOUT
736 μm (−20 / +30 μm)
886 μm (−20 / +30 μm)
PE35400
Divide-by-4 Prescaler
Page 12 DOC-64872-2 – (10/2015)
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Waffle Pack Information
Figure 14 provides the waffle pack information for the PE35400.
Figure 14 • 2 × 2 Inch Waffle Pack for PE35400(1)(2)(3)
Notes:
1) Drawings are not drawn to scale.
2) Die in pocket shown pad side up.
3) Die will be oriented in the same direction in and within all waffle packs. Unless otherwise stated, die will be oriented such that the top left corner
of die will be in-line with the "notched" corner of the die plate base and corner. The die base cover label will be affixed on the die base cover
such that the top of the label indicates the top of the die within the waffle pack.
Pad 1
Die ID
Notch
Pocket Closeup
PE35400 Divide-by-4 Prescaler
Product Specification www.psemi.com DOC-64872-2 – (10/2015)
Document Categories
Advance Information
The product is in a formative or design stage. The datasheet contains
design target specifications for product development. Specifications
and features may change in any manner without notice.
Preliminary Specification
The datasheet contains preliminary data. Additional data may be added
at a later date. Peregrine reserves the right to change specifications at
any time without notice in order to supply the best possible product.
Product Specification
The datasheet contains final data. In the event Peregrine decides to
change the specifications, Peregrine will notify customers of the
intended changes by issuing a CNF (Customer Notification Form).
Product Brief
This document contains a shortened version of the datasheet. For the
full datasheet, contact sales@psemi.com.
Not Recommended for New Designs (NRND)
This product is in production but is not recommended for new designs.
End of Life (EOL)
This product is currently going through the EOL process. It has a
specific last-time buy date.
Obsolete
This product is discontinued. Orders are no longer accepted for this
product.
Sales Contact
For additional information, contact Sales at sales@psemi.com.
Disclaimers
The information in this document is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be
entirely at the user’s own risk. No patent rights or licenses to any circuits described in this document are implied or granted to any third party.
Peregrine’s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to
support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death
might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in
such applications.
Patent Statement
Peregrine products are protected under one or more of the following U.S. patents: patents.psemi.com
Copyright and Trademark
©2015, Peregrine Semiconductor Corporation. All rights reserved. The Peregrine name, logo, UTSi and UltraCMOS are registered trademarks and
HaRP, MultiSwitch and DuNE are trademarks of Peregrine Semiconductor Corp.
Ordering Information
Table 7 lists the available ordering code for the PE35400 as well as available shipping method.
Table 7 • Order Code for PE35400
Order Codes Description Packaging Shipping Method
PE35400A–G PE35400 die Die in 2 × 2 inch waffle pack 100 die/waffle pack