19-4011; Rev 0; 9/91 General Description The MAX501/MAX502 are 12-bit, 4-quadrant, voltage- output, multiplying digital-to-analog converters (DACs) with an output amplifier. Thin-film resistors, laser trimmed at the wafer level, maintain accuracy over the full operating temperature range. The MAX501/MAX502 have buffered latches that are easily interfaced with microprocessors. Data is trans- ferred into the input register in either a right-justified 8+4-bit format (MAX501) or with a 12-bit-wide data path (MAX502). In the MAX501, an LDAC signal transfers data from the input register to the DAC register. In the MAX502, the input registers are controlied by standard CHIP SELECT (CS) and WRITE (WR) signals. For stand- alone operation, the CS and WR inputs are grounded, making all latches transparent. All logic inputs are level triggered and compatible with TTL and +5V CMOS logic levels. The internally compensated, low-input offset-voltage output amplifier provides an output voltage from +10V to -10V while sourcing and sinking up to 5mA. Applications Digital Attenuators Programmable-Gain Amplifiers Servo Controls Digital to 4mA-to-20mA Converters Automatic Test Equipment Programmable Power Supplies MAAILSVI Voltage-Output, 12-Bit Multiplying DACs Features @ 12-Bit Voltage Output DAC @ +10V and 5mA Output Drive @ Monotonic Over Temperature @ Four Range-Scaling Resistors @ 8+4 (MAX501) and 12-Bit (MAX502) Interface @ 24-Pin DIP and Wide SO Packages Ordering Information PART TEMP. RANGE PACKAGE LsBs) MAXSOIACNG =: 0 to +70C.-24 Narrow Plastic DIP 1/2 MAX501BCNG 0C to +70C 24 Narrow Plastic DIP +3/4 MAXSO1IACWG = 0C to +70C.-24 Wide SO 1/2 MAXS0IBCWG = 0C to+70C 24 Wide SO +3/4 MAX501BC/D 0C to+70C__ Dice +3/4 MAXSOIAENG -40C to +85C 924 Narrow Plastic DIP +1/2 MAXSO1IBENG -40C to +85C 24 Narrow Plastic DIP +3/4 MAXS501AEWG -40C to +85C +24 Wide SO +1/2 MAXSOIBEWG -40C to +85C 24 Wide SO +3/4 MAXSO1IAMRG -55C to +125C 24 Narrow CERDIP** = +1/2 MAXSO1BMAG -55C to +125C 24 Narrow CERDIP** +3/4 Ordering Information continued on last page. Contact factory for dice specifications. * Contact factory for availability and processing to MIL-STD-883. ZOSXVW/LOSXVIA ______sM#FFunctional Diagram Pin Configurations TOP VIEW Voo RA RB RC REB WwW 20 jai [22 [23 | 24 Vour C4] [24] AFB on 2] (23) RC p10 (34 [22] RB 7 ps C4] MAKI [21] RA VREFH 12-BIT DAC 1 pe(e} MAX502 = [728] Vo MAXIM Your o7 [6 | 18) Vss MAX502 18 D6 (74 r18} AGNO 2-BIT AGND D5 [a] (17) VREF 1D VR CONTROL LOGIC ba [a | [76] CS DATA LATCH 03 Gat FS] wa 4p = Vs5 o2 Ci 14] 00 DGND [72] 73] Dt aT {2 liz [ie [i pal DO..Df! DBDGND CS WR DIP/SO MAXS501 on last page MVIAAISVI Maxim Integrated Products 9-5 /VIA AL/WI is a registered trademark of Maxim Integrated Products.MAX501/MAX502 Voltage-Output, 12-Bit Multiplying DACs ABSOLUTE MAXIMUM RATINGS Vpp to DGND Vss to DGND VREF to AGND RFB to AGND RA to AGND RB to AGND RC to AGND Vout to AGND (Note 1) Vop to AGND AGND to DGND Seer eee eee e eee e eens -0.3V, Voo Note 1: Vout may be shorted to AGND, Vpp, or Vss if the power dissipation of the package is not exceeded. -0.3V, +17V Digital Input Voltage to DGND ...........005 -0.3V, Vpo +0.3V, -17V Continuous Power Dissipation (any package) t25V TOF7EOS Cece cc cece cece cece ence ee eees 650mW +25V derate above +75G .... cece ce eee eee 10mMW/C +25V Operating Temperature Ranges: +25V MAX501_C__, MAX502_C__ .... wee eee 0C to +70C +25V MAX501_E_, MAX502_E_ ......... ~40C to +85C Vpop +0.3V, Vss -0.3V MAX501_M_, MAX502_M_ ......... -55C to +125C -0.3V, +17V Storage Temperature Range .......... -65C to +150C Lead Temperature (soldering, 10sec) ........... +300C Stresses beyond those under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS Dual Supply (Vop = +11.4V to +15.75V, Vgs = -11.4V to -15.75V, VREF = +10V, AGND = DGND = OV, Ri = 2kQ, CL = 100pF, all grades, Ta = Tain to Tmax, unless otherwise noted.) (Note 2) PARAMETER [| symeot | CONDITIONS | MIN TYP MAX [UNITS STATIC PERFORMANCE Resolution N 12 Bits Ta = 428C MAX501/502A +12 Relative Accuracy INL MAXSO1/5028 +34 LSB Ta = TMI to Tmax MAX501/502A 43/4 MAX501/502B #1 Differential Nonlinearity DNL +1 LSB Ta = +25C HH Zero-Code Offset Error Ta = Twin to Tax MAX501/502_C/E +2 mV MAX501/502_M +3 Offset Temperature Coefficient ates +5 UEPC RFB, Vout connected +3 Gain Error Ae or Be connected to Vour, +4% | LSB RA, VouT connected, VREF = 2.5V +6 Gain Temperature Coefficient Aten +1 ppm/?C Reference Input Resistance RFB 8 12 16 kQ Ratio Matching RA to RB to RC match 05 | % 9-6 SULA XI sviVoltage-Output, 12-Bit Multiplying DACs ELECTRICAL CHARACTERISTICS (continued) = Dual Supply (Vpp = +11.4V to +15.75V, Vsg = -11.4V to -15.75V, VREF = +10V, AGND = DGND = OV, RL = 2k, CL = 100pF, all grades, Ta = TmIN to Tmax, unless otherwise noted.) (Note 2) > PARAMETER | SYMBOL | CONDITIONS MIN TYP MAX | UNITS < DIGITAL INPUTS OQ Input Ci t | Vv OV and V Tas tere 4 A nput Curren = Q0V an li P IN IN OD Ta = TmIN to Tmax +10 \ input Low Voitage Vit 0.8 Vv Input High Voltage VIH 2.4 Vv = Input Capacitance Cin 7 pF > POWER SUPPLIES >< v 11.40 15.75 Supply Voltage pp Vv QO Vss ~11.40 -15.75 I Vv unloaded 10 Supply Current DD OUT mA N Iss | Vout unloaded 4 VREF = -10V Vop = 15V + 5% AGain/AVop +0.02 VREF = -8.9V . Vpp = 12V + 5% Power-Supply Rejection PSR %/% VREF = 10V Vss = -15V + 5% AGain/AVss +0.02 VREF = 8.9V Vss = -12V + 5% DYNAMIC PERFORMANCE (Note 3) Output-Voltage Settling Time ts To +0.01% of full scale 5 US Slew Rate SR 5 V/us DAC Glitch Impulse Major carry transition 450 nv-s Multiplying Feedthrough Error VREF = +10V at 10kHz, DAC = all Os 5 mVp-p pnity-Gain Smail-Signal 3 MHz Full-Power Bandwidth 250 kHz Total Harmonic Distortion THD VREF = 6Vpws at 1kHz -90 dB OUTPUT CHARACTERISTICS Open-Loop Gain Avo RFB not connected, Vout = +10V, Rp = 2kQ 90 dB Output Resistance Ro 0.2 2 Short-Circuit Current Ta = +25C 20 mA 0.1Hz to 10Hz, Ta = +25C 2 iNRMS Output Noise Voltage f= 1kHz, Ta = +25C 25 nvw//Hz MIAXKIZVI 9-7MAX501/MAX502 Voltage-Output, 12-Bit Multiplying DACs TIMING CHARACTERISTICS (See Figures 1a, 1b) Dual Supply (Vpp = +11.4V to +15.75V, Vgs = -11.4V to -15.75V, VREF = +10V, AGND = DGND = OV, RL = 2kQ, C= 100pF, all grades, Ta = Tun to Tmax, unless otherwise noted.) (Note 2) PARAMETER _[symeot | CONDITIONS _[ MIN TYP MAX | UNITS MAX501 Chip Select to Write-Setup Time ics 0 ns . . Ta = +25C 55 Write Pulse Width twr ns TA = Tain to Tmax 70 . MAX501_C/E 50 Data-Setup Time tos ns MAX501_M 60 Data-Hold Time tDH 10 0 ns LDAC Pulse Width tLpac 70 ns CLR Pulse Width tcLR 70 ns SET Puise Width tseT 200 ns MAX502 Chip Select to Write-Setup Time tcs 0 ns Ta = +26C 40 Write Pulse Width twR Ta=TwntoT MAX502_C/E 50 ns = oO TMA AMINES UNAS MAX502_M 60 : MAX502_C/E 50 Oata-Setup Time tos ns MAX502_M 60 Data-Hold Time tbH 10 0 ns Note 2: Vout must be less than Vpp - 2.5V and greater than Vss + 2.5V to ensure correct operation. Performance at supplies other than Vpp = +15V and Vss = -15V is guaranteed by PSRR tests. Note 3: Dynamic Performance and Output Characteristics are included for design guidance and are not subject to test. MIAXIS/VIVoltage-Output, 12-Bit Multiplying DACs Typical Operating Characteristics = FREQUENCY RESPONSE, OUTPUT VOLTAGE SWING > GAIN = -1 vs. RESISTIVE LOAD *< 180 28 * 2 Vop = +15V 3 +99 24 bVsg = -15 & VREF = 30Vp-p @ tkHz 08 20 re @ wd, S ~90 2 = 16 \ z -139 5 = oOo > Voo = +15V 8 > Vsg = -15V >< VREF = 20Vp-p 4 DAC CODE: 11... 111 Q 100 1k = 10k = 100k.-1M~10M 1 10100 tk~10k FREQUENCY (Hz) LOAD RESISTANCE (Q) N NOISE SPECTRAL DENSITY THD vs. FREQUENCY 2 ~ T SS Vpp = +15V Vpp = +15V zo Wee Wee = DAC CODE: 11... 111 ~ pac cone tt. 111 ZB op GAIN = -1 GAIN = -1 a @ -50 = S ed 2 = 2 100 5 /| 2 S +00 10 = 100s tk 10k 100k 100 tk 10k 100k FREQUENCY (Hz) FREQUENCY (Hz) MULTIPLYING FEEDTHROUGH MULTIPLYING FEEDTHROUGH ERROR ERROR vs. FREQUENCY = 200 Vop = +15V F reo | vier ~20y | a s = 20Ve4 VREF = DAC CODE: 00... 000 5W/DIV = 109 GAIN =0 Ss : | = 80 Vour = 40 (FEEDTHROUGH) 3 SmV/DIV 0 _ 20us/DIV : 100 tk = 10k = 100k tM FREQUENCY (Hz) MAKI SV 39MAX501/MAX502 Voltage-Output, 12-Bit Multiplying DACs tes t tes >} CSLSB OR | CSMSB < twr ] wR \ ft tos pe tow DATA DATA VALID tuna LDAC tser SET tor CLR Figure 1a. MAX501 Timing Diagram | < twe - DATA ce tps -7t toy >] DATA VALID Figure 1b. MAX502 Timing Diagram 9-10 NOTES: 1. All input signal rise and fall times measured from 10% to 90% of +5V, ta = te = 20ns. 2. Timing measurement reference level is Vin * Vi SVIA KI sviVoltage-Output, 12-Bit Multiplying DACs Pin Descriptions = MAX501 MAX502 > PIN NAME FUNCTION PIN NAME FUNCTION < 1 VouT Voltage Output 1 VouT Voltage Output Q 2 LDAC Asynchronous Load DAC input is 2-11 | D1N-D2 Data Bits 2 to 11 (MSB) S __ active low 12 |DGND | Digital Ground wk, 3 SET Sets DAC register to all 1s 13,14 [D1,D0 | Data Bits 0 to 1 (LSB) \ 4 CLR Sets DAC register to ali 0s 16 |wR Write Input is active low = 5-8 | 07-04 Data Bits 7 to 4 16 {CS Chip-Select Input is active low > 9 b3/D11 Data Bit 3 or 11 17 VREF Reference Input to DAC 10 02/D10 Data Bit 2 or 10 18 AGND Analog Ground < " p1/b9 Data Bit 1 or 9 19 | Vss ~12V to -15V Supply Voltage input oO 12 DGND Digital Ground 20 Vpb +12V to +15V Supply Voltage Input S 13 {B0/D8__| Data Bit 0 or 8 (LSB) a1 [RA Scaling Resistor: RA = 4RFB N 14 CSLSB LSB Chip-Setect input is active low 22 RB Scaling Resistor. RB = 2RFB 15 [WR Write Input is active low 23 | RC Scaling Resistor: RC = 2AFB 16 CSMSB MSB Chip-Select Input is active iow 24 RFB Feedback Resistor 17 VREF Reference Input to DAC 18 AGND Analog Ground 19 Vss ~12V to -15V Supply Voltage Input 20 Vop +12V to +15V Supply Voitage Input 21 RA Scaling Resistor: RA = 4RFB 22 RB Scaling Resistor: RB = 2RFB 23 RC Scaling Resistor: RC = 2RFB 24 RFB Feedback Resistor MAXI VI 9-11MAX501/MAX502 Voltage-Output, 12-Bit Multiplying DACs Detailed Description Digital Circuit Figures 2a and 2b are simplified circuit diagrams of the MAX501 and MAX502 input control logic. For the MAX501, a low on CSLSB and WR with CSMSB high loads the least significant bit (LSB) byte into the input register. The LSB byte is then latched into the input register on the rising edge of either a WR or a CSLSB. Similarly, a low on CSMSB and WR with CSLSB high Table 1. MAX501 Truth Table loads the most significant bit (MSB) nibble into the input register. The MSB nibble is then latched into the input register on the rising edge of either a WR or a CSMSB pulse. With all 12 bits loaded, a low on LDAC transfers the data to the DAC register. For the MAX502, a low on CS and WR transfers the data on the input registers to the DAC latch. Both parts digital inputs are TTL and CMOS compatible, providing easy microprocessor (uP) interfacing. Tables 1 and 2 are MAX501 and MAX502 truth tables. wR | CSmsB | CSLSB | LDAC CLR SET OPERATION xX x x x xX 0 DAC Register overridden by 1s Input Register unaffected xX X X X 0 1 DAC Register overridden by 0's Input Register unaffected 0 0 1 1 1 1 Load MSB nibble into Input Register 0 1 0 1 1 1 Load LSB byte into Input Register X X xX 0 1 1 Transfer Input Register to DAC Register 1 x xX 1 1 1 No Operation 0 1 1 1 1 1 No Operation 0 R 1 1 1 1 Latching MSB nibble into Input Register R 0 1 1 1 1 Latching MSB nibble into input Register 0 1 R 1 1 1 Latching LSB byte into input Register R 1 0 1 1 1 Latching LSB byte into Input Register H = High State, L = Low State, R = Rising Edge, X = Dont Care Table 2. MAX502 Truth Table wR cs OPERATION H x No Operation x H No Operation L L Input Register is Transparent L R input Register is Latched R L Input Register is Latched H = High State, L = Low State, R = Rising Edge, X = Don't Care SVIAXKISVIVoltage-Output, 12-Bit Multiplying DACs CSMSB . 4-BIT Q REGISTER 1) ol, wr ears BTS > umey > reas > 2 LN CSLSB Coac LOAC SET SET CLA CLR Figure 2a. MAX501 input Control Logic Digital-to-Analog Converter The MAX501/MAX502 have a 12-bit, binary-weighted, current-output DAC with standard R-2R ladder (Figure ao) INPUT RENTER 3). Binarily weighted currents are switched between AGND and the inverting input of the internal output amplifier. The output amplifier, typically connected to the feedback resistor RFB, converts the output current WR jJ>- to a voltage. With RFB connected to VourT, cs Vout = -D VREF, where D is the fractional expression of the digital input code divided by full scale. D can vary from 0 to 4095/4096 in unipolar mode. Figure 2b. MAX502 Input Control Logic VREF R R R RA RB RC RFB 2R 2R 2R 2h V2R YaR SR BR ZA DEPT y Y - Vout | [ + | Oft DO (MSB) (LSB) AGND Figure 3. MAX501/MAX502 Simplitied DAC and Amplifier Circuit VIA AKI svi 9-13MAX501/MAX502 Voltage-Output, 12-Bit Multiplying DACs Output-Buffer Amplifier The output amplifier is an internally compensated, non- inverting, gain-scalable amplifier that can develop +10V across a 2kQ load. Maximum settling time is less than 5us (to within 0.01% FSR). Input offset voltage is laser trimmed at the wafer level. Slew rate is typically 7V/us. The gain-setting resistors (RA, RB, and RC) connect to the amplifier inverting termina). Unipolar Configuration Figure 4, a typical configuration for the MAX501/502, provides for unipolar-bipolar operation or two-quadrant multiplication when Vin is an AC signal. R1 adjusts gain and R3 adjusts zero offset. For fixed-reference applica- tions, trim the reference voltage and omit R1 and R2. IfR1 and R2are included, you must take into account their gain- temperature coefficient. The typical gain-temperature coefficient of the MAX502 is 1ppm/C, which corres- ponds to a gain shift of LSB over a+100C temperature range. Table 3 is the code table for unipolar- binary operation. Bipolar Operation Figure 5 shows a 4-quadrant, bipolar operation. Gain error may be adjusted by changing the R1 and R2 ratio. These resistors should be ratio-matched to 0.01% to stay within gain-error specifications and to eliminate trimming. The offset value is defined by matching the RB and RC internal resistors. Table 4 is the code table for bipolar-binary operation. MIAXKIA 3 MAX400 Yoo Ves 22 20 ial VREF RB Vop Vss MWIAXKIM 1 Vou MAX501 > Vout Vin Vop R3 Vs5 DGND AGND RC 100k 9 Rt R4 2000 40k ; - - ear 7 20} 231 19 Figure 5. Bipolar Operation (4-Quadrant Multiplication) VREF Von RC Vss Table 4. MAX501/MAX502 Bipolar-Binary Code Table V 4 Your MAKIN DIGITAL INPUT ANALOG OUTPUT MAX501/MAX502 R2 2047 DGND AGND FB 1002 My (VIN) 504g 1 + s 1000 0000 = 0001 (+VIN) Soag Figure 4. Unipolar-Binary Operation 1000 =0000 = 0000 ov (2-Quadrant Multiplication) 1 . 0111 1411 1111 (-Vin) => Table 3. MAX501/MAX502 Unipolar-Binary Code Table 2048 DIGITAL INPUT ANALOG OUTPUT 0000 0000 = a000 (-Vin) Spas = Vine 4095 141100111 1411 -Vin) ' (VIN) 7096 2048 4 1000 ~Vin) = -= 0000 = 0000 (-ViN) 4096 3 VIN 1 0000 001 -Vin) 0000 =-000 (Vin) 3556 0000 = 0000Ss 0000 ov 9-14 MIAAIsVIVoltage-Output, 12-Bit Multiplying DACs Applications Information Noise AC or transient voltages between AGND and DGND can cause noise injection into the analog output. Tie the MAX502 AGND to DGND to ensure both pins are at the same potential. If these ground pins connect to separate backplanes, use two back-to-back diodes to tie the pins together. Also, decouple Vpp and Vss to AGND, as uP-based systems generally have noisy grounds that couple into the power supplies. Digital Glitches Any digital word written into the DAC causes a glitch impulse. This impulse couples across the stray capaci- tance of the DAC switches to the output bus. A glitch impulse on this bus is converted to a voltage by RFB and the output amplifier. The output voltage glitch energy is the product of its duration and its average magnitude (the net area under the curve), and is expressed in (nV)(s). The energy is measured with VREF connected to analog ground and the DAC register alternately loaded with all Os and all 1s. Digital Feedthrough Most of the MAX501/MAX502s digital inputs are directly connected to the uP bus. These inputs are constantly changing, even when the DAC is not selected. High- frequency logic activity on the data bus can feed through the DAC package capacitance as noise on the DAC output. Figure 6 shows an interface that minimizes digital feedthrough. All data inputs are latched from the busy by CS. Alternatively, using peripheral interface devices reduces digital feedthrough. - ADDRESS A0-AtS ph DECODE MAXKIM MAX502 uP _ 16 cs Wo 15) WR = |_) EN 14 WR 00-D15 16-BIT DO-D11 LATCH 4 Figure 6. MAXS502 Interface Circuit Latches Minimize Digital Feedthrough SULA Xi svi MAX502 Microprocessor Interfacing 16-Bit Microprocessor Systems Figures 7-9 show the MAX502 interfaced with the MC68000, the 8086, and the TMS32010. The MAX502 appears as a memory-mapped peripheral to the pro- cessors. In each case, a write instruction loads the MAX502 with the appropriate data. The particular instructions used are as follows: McC68000: MOVE 8086: MOV TMS32010: OUT AI~A23 = ADDRESS |16] AS pecope [465 MAXIM DTACK MAX502 vos 14 D0-D15 } 0-011 2 Figure 7, MAX502 to MC6800 Interface 8086 Tb ave tare | | AoDRESS Al oxe2i2 | | OECODE MAXIM ZN MAX502 Wa Sl wa 14 ADO-AD15 > DO-D11 2 Figure 8. MAX502 to 8086 Interface 9-15 : oa S \ : 9 x}MAX501/MAX502 Voltage-Output, 12-Bit Multiplying DACs AQ-A11 j MIAXIsI TMS32010 ADDRESS |16} NODRESS [64g MAXS02 wa i 14 DO-D15 d0-D11 2 Figure 9. MAX502 to TMS32010 Interface MAX501 Microprocessor Interfacing 8-Bit Microprocessor Systems Figure 10 shows an interface circuit for the MAX501 to the 8085A 8-bit uP. The software routine to load data to the device is given in Table 3. Note that transferring 12 data bits requires two write operations. The first of these loads the 4 MSBs into the 7475 latch. The second write operation loads the 8 LSBs plus the 4 MSBs (which are Pin Configurations (continued) TOP VIEW Vour (41 LDAC [2] Set (3 | CuR 4] 07 (81 06 [6] 05 C7] 04 [a] p3o11 [9 | 02/010 Go] o1/o9 (11 DGND [iz] MAASAI MAXS01 za] RFB [23] RC [22] RB Bi} RA [20] Von 119] Vss /48} AGND Fiz] VREF 16} CSMSB re WR Fa) CSLS8 13 | DO/D8 DIP/SO ___ Ordering Information (continued) held by the latch) into the DAC. A8-A15 ALE 8085A/8088 WR ADO-AD7 Figure 10. MAX501 to 8085A/8088 Interface PART TEMP. RANGE PACKAGE tsBa) MAX502ACNG 0C to+70C 24 Narrow Plastic DIP = 1/2 MAX502BCNG OCto+70C 24 Narrow Plastic DIP 3/4 Ml acres MAXS02ACWG = 0C: to +70C 24 Wide SO v2 ra) Avene ey CSMSE MAX502BCWG 0C to +70C 24 Wide SO 3/4 [| LbAC MAX502BC/D 00C to #70C._- Dice* 3/4 in 5 arr ae oh MAX502AENG -40C to +85C 24 Narrow Plastic DIP_1/2 we MAXS502BENG -40C to +85C 24 Narrow Plastic DIP 3/4 3 MAXS02AEWG -40C to +85C 24 Wide SO 12 po/D8-07 MAX502BEWG -40C to +86C 24 Wide SO 3/4 5 MAXS02AMRG -55C to +125C 24 Narrow CERDIP ~ 1/2 MAX502BMRG -55C to +125C 24 Narrow CERDIP** 3/4 Contact factory for dice specifications. Contact factory for availability and processing to MIL-STD-883. Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time 9-16 SHIA KI svi