December 2003 Advance Information AS7C331MPFS32A AS7C331MPFS36A (R) 3.3V 1M x 32/36 pipelined burst synchronous SRAM Features *3.3V core power supply *2.5V or 3.3V I/O operation with separate VDDQ *Linear or interleaved burst control *Snooze mode for reduced power-standby *Common data inputs and data outputs *Boundary scan using IEEE 1149.1 JTAG function *NTDTM1 pipelined architecture available (AS7C332MNTD18A, AS7C331MNTD32A/ AS7C331MNTD36A) * Organization: 1,048,576 words x 32 or 36 bits *Fast clock speeds to 250MHz in LVTTL/LVCMOS *Fast clock to data access: 2.6/3/3.4/3.8 ns *Fast OE access time: 2.6/3/3.4/3.8 ns *Fully synchronous register-to-register operation *Single register flow-through mode *Single-cycle deselect - Dual-cycle deselect also available (AS7C332MPFD18A, AS7C331MPFD32A/ AS7C331MPFD36A) *Asynchronous output enable control *Available in 100-pin TQFP and 165-ball BGA packages *Individual byte write and global write *Multiple chip enables for easy expansion 1 NTDTM is a trademark of Alliance Semiconductor Corporation. All trademarks mentioned in this document are the property of their respective owners. Logic block diagram LBO CLK ADV ADSC ADSP CLK CE CLR A[19:0] 20 GWE BWE BWd D Q CE Address register CLK 2 20 18 1M x 32/36 Memory array 2 20 32/36 D DQd Q Byte write registers CLK 32/36 D DQc Q Byte write registers CLK BWc D DQb Q Byte write registers CLK BWb D DQa Q Byte write registers CLK BWa CE0 CE1 CE2 ZZ Q0 Burst logic Q1 D 4 OE Output registers CLK Q Enable CE register CLK Power down Input registers CLK D Enable Q delay register CLK 32/36 OE FT DQ[a:d] Selection guide Minimum cycle time Maximum clock frequency Maximum pipelined clock access time Maximum operating current Maximum standby current Maximum CMOS standby current (DC) 12/22/03, v.2.3 -250 4 250 2.6 450 140 70 -200 5 200 3.0 400 120 70 Alliance Semiconductor -167 6 166 3.4 350 110 70 -133 7.5 133 3.8 325 100 70 Units ns MHz ns mA mA mA 1 of 22 Copyright (c) Alliance Semiconductor. All rights reserved. AS7C331MPFS32A AS7C331MPFS36A (R) Pin and ball assignment 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 TQFP 14 x 20mm DQPb/NC DQb DQb VDDQ VSSQ DQb DQb DQb DQb VSSQ VDDQ DQb DQb VSS NC VDD ZZ DQa DQa VDDQ VSSQ DQa DQa DQa DQa VSSQ VDDQ DQa DQa DQPa/NC LBO A A A A A1 A0 NC A VSS VDD A A A A A A A A A 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC/DQPc DQc DQc VDDQ VSSQ DQc DQc DQc DQc VSSQ VDDQ DQc DQc FT VDD NC VSS DQd DQd VDDQ VSSQ DQd DQd DQd DQd VSSQ VDDQ DQd DQd NC/DQPd 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 A A CE0 CE1 BWd BWc BWb BWa CE2 VDD VSS CLK GWE BWE OE ADSC ADSP ADV A A 100-pin TQFP - top view Note: For pins 1, 30, 51, and 80, NC applies to the x32 configuration. DQPn applies to the x36 Ball assignment for 165-ball BGA for 1M x 36 1 2 3 4 5 6 7 8 9 10 11 A NC A CE0 BWc BWb CE2 BWE ADSC ADV A NC B NC A CE1 BWd BWa CLK GWE OE ADSP A NC C DQPc NC VDDQ VSS VSS VSS VSS VSS VDDQ NC DQPb D DQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb E DQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb F DQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb G DQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb H FT VSS NC VDD VSS VSS VSS VDD NC NC ZZ J DQd DQd VDDQ VDD Vss VSS VSS VDD VDDQ DQa DQa K DQd DQd VDDQ VDD Vss VSS VSS VDD VDDQ DQa DQa L DQd DQd VDDQ VDD Vss VSS VSS VDD VDDQ DQa DQa M DQd DQd VDDQ VDD Vss VSS VSS VDD VDDQ DQa DQa N DQPd NC VDDQ VSS NC A VSS VSS VDDQ NC DQPa 1 P NC NC A A TDI A1 TDO A A A A R LBO A A A TMS A01 TCK A A A A 1 A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. 12/22/03, v.2.3 Alliance Semiconductor 2 of 22 AS7C331MPFS32A AS7C331MPFS36A (R) Functional description The AS7C331MPFS32A/36A is a high-performance CMOS 32-Mbit synchronous Static Random Access Memory (SRAM) device organized as 1,048,576 words x 32/36. It incorporates a two-stage register-register pipeline for highest frequency on any given technology. Fast cycle times of 4/5/6/7.5 ns with clock access times (tCD) of 2.6/3/3.4/3.8 ns enable 250, 200,167and 133MHz bus frequencies. Three chip enable (CE) inputs permit easy memory expansion. Burst operation is initiated in one of two ways: the controller address strobe (ADSC), or the processor address strobe (ADSP). The burst advance pin (ADV) allows subsequent internally generated burst addresses. Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip address register when ADSP is sampled low, the chip enables are sampled active, and the output buffer is enabled with OE. In a read operation, the data accessed by the current address registered in the address registers by the positive edge of CLK are carried to the data-out registers and driven on the output pins on the next positive edge of CLK. ADV is ignored on the clock edge that samples ADSP asserted, but is sampled on all subsequent clock edges. Address is incremented internally for the next access of the burst when ADV is sampled low and both address strobes are high. Burst mode is selectable with the LBO input. With LBO unconnected or driven high, burst operations use an interleaved count sequence. With LBO driven low, the device uses a linear count sequence. Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable GWE writes all 32/36 regardless of the state of individual BW[a:d] inputs. Alternately, when GWE is high, one or more bytes may be written by asserting BWE and the appropriate individual byte BWn signals. BWn is ignored on the clock edge that samples ADSP low, but it is sampled on all subsequent clock edges. Output buffers are disabled when BWn is sampled lOW regardless of OE. Data is clocked into the data input register when BWn is sampled low. Address is incremented internally to the next burst address if BWn and ADV are sampled low. This device operates in singlecycle deselect feature during read cycles. Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC and ADSP follow. ADSP must be sampled high when ADSC is sampled low to initiate a cycle with ADSC. WE signals are sampled on the clock edge that samples ADSC low (and ADSP high). Master chip enable CE0 blocks ADSP, but not ADSC. The AS7C331MPFS32A/36A family operates from a core 3.3V power supply. I/Os use a separate power supply that can operate at 2.5V or 3.3V. These devices are available in a 100-pin TQFP and 165-ball BGA. TQFP and BGA capacitance Parameter Input capacitance I/O capacitance 12/22/03, v.2.3 Symbol CIN CI/O Signals Address and control pins I/O pins Alliance Semiconductor Test conditions VIN = 0V VOUT = 0V Max 5 7 Unit pF pF 3 of 22 AS7C331MPFS32A AS7C331MPFS36A (R) Signal descriptions Pin CLK A0-A19 I/O I I Properties CLOCK SYNC DQ[a,b,c,d] I/O SYNC CE0 I SYNC CE1, CE2 I SYNC ADSP ADSC ADV I I I SYNC SYNC SYNC GWE I SYNC BWE I SYNC BW[a,b,c,d] I SYNC OE I ASYNC LBO I STATIC TDO TDI TMS O I I SYNC SYNC SYNC TCK I Test Clock FT I STATIC ZZ I ASYNC Description Clock. All inputs except OE, FT, ZZ, and LBO are synchronous to this clock. Address. Sampled when all chip enables are active and when ADSC or ADSP are asserted. Data. Driven as output when the chip is enabled and when OE is active. Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When CE0 is inactive, ADSP is blocked. Refer to the "Synchronous truth table" for more information. Synchronous chip enables, active high, and active low, respectively. Sampled on clock edges when ADSC is active or when CE0 and ADSP are active. Address strobe processor. Asserted low to load a new address or to enter standby mode. Address strobe controller. Asserted low to load a new address or to enter standby mode. Advance. Asserted low to continue burst read/write. Global write enable. Asserted low to write all 32/36 and 18 bits. When high, BWE and BW[a:d] control write enable. Byte write enable. Asserted low with GWE high to enable effect of BW[a:d] inputs. Write enables. Used to control write of individual bytes when GWE is high and BWE is low. If any of BW[a:d] is active with GWE high and BWE low, the cycle is a write cycle. If all BW[a:d] are inactive, the cycle is a read cycle. Asynchronous output enable. I/O pins are driven when OE is active and chip is in read mode. Selects Burst mode. When tied to VDD or left floating, device follows interleaved Burst order. When driven Low, device follows linear Burst order. This signal is internally pulled High. Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK (BGA only). Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK (BGA only). This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK (BGA only). Test Clock. All inputs are sampled on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Selects Pipeline or Flow-through mode. When tied to VDD or left floating, enables Pipeline mode. When driven Low, enables single register Flow-through mode. This signal is internally pulled High. Snooze. Places device in low power mode; data is retained. Connect to GND if unused. Write enable truth table (per byte) Function Write All Bytes Write Byte a Write Byte c and d Read GWE L H H H H H BWE X L L L H L BWa X L L H X H BWb X L H H X H BWc X L H L X H BWd X L H L X H Key: X = don't care, L = low, H = high, n = a, b, c, d; BWE, BWn = internal write signal. 12/22/03, v.2.3 Alliance Semiconductor 4 of 22 AS7C331MPFS32A AS7C331MPFS36A (R) Burst sequence table Interleaved burst address A1 A0 A1 A0 A1 A0 Starting Address First Increment Second Increment Third Increment 00 01 10 11 01 00 11 10 Linear burst address A1 A0 A1 A0 A1 A0 10 11 00 01 11 10 01 00 Starting Address First Increment Second Increment Third Increment 00 01 10 11 01 10 11 10 A1 A0 A1 A0 10 11 00 01 11 00 01 10 Synchronous truth table CE01 CE1 CE2 ADSP ADSC ADV BWn2 OE Address accessed CLK Operation DQ H L L L L L L L L X X X X H H H H L X H X H X L L X X H H H H X X X X X X X X H X X X X X X X H H L L L L X X X X X X X X L X X X X X L H L H L L H H H H H H X X X X H H X H X L X L X L X X L L H H H H H H H H L H H H H X X X X X X X X X L L H H L L H H X L L H H X X X X X X X F F F F F F F F F F T T T T T X X X X X L H L H L H L H L H L H X X X X X NA NA NA NA NA External External External External Next Next Current Current Next Next Current Current External Next Next Current Current L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H Deselect Deselect Deselect Deselect Deselect Begin read Begin read Begin read Begin read Continue read Continue read Suspend read Suspend read Continue read Continue read Suspend read Suspend read Begin write Continue write Continue write Suspend write Suspend write Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z3 Hi-Z Hi-Z3 Hi-Z Q Hi-Z Q Hi-Z Q Hi-Z Q Hi-Z D4 D D D D 1 X = don't care, L = low, H = high 2 See "Write enable truth table (per byte)," on page 4 for more information. 3 Q in flow-through mode. 4 For write operation following a READ, OE must be high before the input data set up time and held high throughout the input hold time TQFP and BGA thermal resistance Description Thermal resistance (junction to ambient)1 Thermal resistance (junction to top of case)1 Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51 1-layer Symbol JA JA Typical 40 22 Units C/W C/W 4-layer JC 8 C/W 1 This parameter is sampled 12/22/03, v.2.3 Alliance Semiconductor 5 of 22 AS7C331MPFS32A AS7C331MPFS36A (R) Absolute maximum ratings Parameter Power supply voltage relative to GND Input voltage relative to GND (input pins) Input voltage relative to GND (I/O pins) Symbol VDD, VDDQ VIN VIN Power dissipation Short circuit output current Storage temperature (TQFP) Storage temperature (BGA) Temperature under bias Pd IOUT Tstg (TQFP) Tstg (BGA) Tbias Min -0.5 -0.5 Max +4.6 VDD + 0.5 Unit V V -0.5 - - -65 -65 -65 VDDQ + 0.5 1.8 20 +150 +125 +135 V W mA o C o C o C Stresses greater than those listed under "Absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect reliability. Recommended operating conditions at 3.3V I/O Parameter Supply voltage for inputs Supply voltage for I/O Ground supply Symbol VDD VDDQ Vss Min 3.135 3.135 0 Nominal 3.3 3.3 0 Max 3.465 3.465 0 Unit V V V Min 3.135 2.375 0 Nominal 3.3 2.5 0 Max 3.465 2.625 0 Unit V V V Recommended operating conditions at 2.5V I/O Parameter Supply voltage for inputs Supply voltage for I/O Ground supply 12/22/03, v.2.3 Symbol VDD VDDQ Vss Alliance Semiconductor 6 of 22 AS7C331MPFS32A AS7C331MPFS36A (R) DC electrical characteristics for 3.3V I/O operation Parameter Input leakage current1 Output leakage current Sym |ILI| |ILO| Input high (logic 1) voltage VIH Input low (logic 0) voltage VIL Output high voltage Output low voltage VOH VOL Conditions VDD = Max, OV < VIN < VDD OE VIH, VDD = Max, OV < VOUT < VDDQ Address and control pins I/O pins Address and control pins I/O pins IOH = -4 mA, VDDQ = 3.135V IOL = 8 mA, VDDQ = 3.465V Min -2 -2 2 2 -0.3 -0.5 2.4 - Max 2 2 VDD+0.3 VDDQ+0.3 0.8 0.8 - 0.4 Unit A A V V V V 1 FTX, LBO, and ZZX pins and the 165 BGA JTAG pins (TMSX, TDIX, and TCKX) have an internal pull-up or pull-down, and input leakage = 10 A. DC electrical characteristics for 2.5V I/O operation Parameter Input leakage current Output leakage current Sym |ILI| |ILO| Input high (logic 1) voltage VIH Input low (logic 0) voltage VIL Output high voltage Output low voltage VOH VOL Conditions VDD = Max, OV < VIN < VDD OE VIH, VDD = Max, OV < VOUT < VDDQ Address and control pins I/O pins Address and control pins Min -2 -2 1.7 1.7 -0.3 Max 2 2 VDD+0.3 VDDQ+0.3 0.7 Unit A A V V V I/O pins IOH = -4 mA, VDDQ = 2.375V IOL = 8 mA, VDDQ = 2.625V -0.3 1.7 - 0.7 - 0.7 V V V IDD operating conditions and maximum limits Parameter Operating power supply current1(pipelined mode) Operating power supply current1(flow-through mode) Standby power supply current Sym ICC ICC (FT) ISB ISB1 ISB2 Conditions CE0 = VIL, CE1 = VIH, CE2 = VIL, f = fMax, IOUT = 0 mA Deselected, f = fMax, ZZ < VIL Deselected, f = 0, ZZ < 0.2V, all VIN 0.2V or VDD - 0.2V Deselected, f = fMax, ZZ VDD - 0.2V, all VIN VIL or VIH -250 -200 -167 -133 Unit 450 400 350 325 mA 375 325 280 260 mA 140 120 110 100 70 70 70 70 60 60 60 60 mA 1 ICC given with no output loading. ICC increases with faster cycle times and greater output loading. 12/22/03, v.2.3 Alliance Semiconductor 7 of 22 AS7C331MPFS32A AS7C331MPFS36A (R) Timing characteristics over operating range -250 Min Max 250 -200 Min Max - 200 -167 Min Max - 166 -133 Min Max - 133 Unit Notes1 MHz Parameter Sym fMax Cycle time (pipelined mode) Cycle time (flow-through mode) Clock access time (pipelined mode) Clock access time (flow-through mode) Output enable low to data valid Clock high to output low Z Data output invalid from clock high (pipelined mode) tCYC tCYCF tCD tCDF tOE tLZC 4 7.0 0 2.6 6.0 2.6 - 5 7.5 - - - 0 - - 3.0 7.5 3.0 - 6 8.5 - - - 0 - - 3.4 8.5 3.4 - 7.5 12 - - - 0 - - 3.8 10 3.8 - ns ns ns ns ns ns 2,3,4 tOH 1.5 - 1.5 - 1.5 - 1.5 - ns 2 tOHF 3.0 - 3.0 - 3.0 - 3.0 - ns 2 tLZOE tHZOE tHZC tOHOE tCH tCL tAS tDS tWS tCSS tAH tDH tWH tCSH tADVS tADSPS tADSCS tADVH tADSPH tADSCH 0 0 1.7 1.7 1.2 1.2 1.2 1.2 0.3 0.3 0.3 0.3 1.2 1.2 1.2 0.3 0.3 0.3 2.6 2.6 - 0 - - 0 2.0 2.0 1.4 1.4 1.4 1.4 0.4 0.4 0.4 0.4 1.4 1.4 1.4 0.4 0.4 0.4 - 3.0 3.0 - - - - - - - - - - - - - - - - - 0 - - 0 2.4 2.3 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 1.5 1.5 1.5 0.5 0.5 0.5 - 3.4 3.4 - - - - - - - - - - - - - - - - - 0 - - 0 2.4 2.4 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 1.5 1.5 1.5 0.5 0.5 0.5 - 3.8 3.8 - - - - - - - - - - - - - - - - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 2,3,4 2,3,4 2,3,4 Clock frequency Data Output invalid from clock high (flowthrough mode) Output enable low to output low Z Output enable high to output high Z Clock high to output high Z Output enable high to invalid output Clock high pulse width Clock low pulse width Address setup to clock high Data setup to clock high Write setup to clock high Chip select setup to clock high Address hold from clock high Data hold from clock high Write hold from clock high Chip select hold from clock high ADV setup to clock high ADSP setup to clock high ADSC setup to clock high ADV hold from clock high ADSP hold from clock high ADSC hold from clock high 1 See "Notes" on page 19. 12/22/03, v.2.3 Alliance Semiconductor 8 of 22 5 5 6 6 6,7 6,8 6 6 6,7 6,8 6 6 6 6 6 6 AS7C331MPFS32A AS7C331MPFS36A (R) IEEE 1149.1 serial boundary scan (JTAG) The SRAM incorporates a serial boundary scan test access port (TAP). The port operates in accordance with IEEE Standard 1149.1-1990. The SRAM contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register. Disabling the JTAG feature If the JTAG function is not being implemented, TCK should be grounded to avoid mid-level input. At power-up, the device will come up in a reset state which will not interfere with the operation of the device. TAP controller state diagram TAP controller block diagram TEST-LOGIC RESET 1 0 0 RUN-TEST/ IDLE 1 SELECT DR-SCAN 1 SELECT IR-SCAN 0 0 Bypass Register 1 Selection Circuitry 0 TDI 1 1 CAPTURE-DR 0 1 EXIT1-IR 1 TCK 0 0 PAUSE-DR PAUSE-IR 0 1 1 EXIT2-DR 0 TAP Controller TMS 0 1 x = 75 EXIT2-IR 1 1 UPDATE-DR 1 . . . 2 1 0 Boundary Scan Register1 0 1 EXIT1-DR 0 x . . SHIFT-IR 1 TDO Identification Register 0 SHIFT-DR Selection Circuitry 31 30 29 . . . 2 1 0 CAPTURE-IR 0 2 1 0 Instruction Register 0 UPDATE-IR 1 0 Note: The 0 or 1 next to each state represents the value of TMS at the rising edge of TCK. Test access port (TAP) Test clock (TCK) The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Test mode select (TMS) The TAP controller receives commands from TMS input. It is sampled on the rising edge of TCK. You can leave this pin/ball unconnected if the TAP is not used. The pin/ball is pulled up internally, resulting in a logic high level. 12/22/03, v.2.3 Alliance Semiconductor 9 of 22 AS7C331MPFS32A AS7C331MPFS36A (R) Test data-in (TDI) The TDI pin/ball serially inputs information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see the TAP Controller State Diagram. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) of any register. Test data-out (TDO) The TDO output pin/ball serially clocks data-out from the registers. The output is active depending upon the current state of the TAP state machine. The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. (See the TAP Controller State Diagram.) Performing a TAP RESET You can perform a RESET by forcing TMS high (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and can be performed while the SRAM is operating. At power-up, the TAP is reset internally to ensure that TDO comes up in a high-Z state. TAP registers Registers are connected between the TDI and TDO pins/balls. They allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction register. Data is serially loaded into the TDI pin/ ball on the rising edge of TCK. Data is output on the TDO pin/ball on the falling edge of TCK. Instruction register You can serially load three-bit instructions into the instruction register. The register is loaded when it is placed between the TDI and TDO pins/balls as shown in the TAP Controller Block Diagram. The instruction register is loaded with the IDCODE instruction at power up and also if the controller is placed in a reset state, as described in the previous section. When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary "01" pattern to allow for fault isolation of the board-level series test data path. Bypass register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between the TDI and TDO pins/balls. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set low (Vss) when the BYPASS instruction is executed. Boundary scan register The boundary scan register is connected to all the input and bidirectional pins/balls on the SRAM. The chip has a 76-bit-long register. The boundary scan register is loaded with the contents of the RAM I/O ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO pins/balls when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions can be used to capture the contents of the I/O ring. The boundary scan order table shows the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The most significant bit (MSB) of the register is connected to TDI, and the least significant bit (LSB) is connected to TDO. Identification (ID) register The ID register has a vendor code and other information described in the Identification Register Definitions table. The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in 12/22/03, v.2.3 Alliance Semiconductor 10 of 22 AS7C331MPFS32A AS7C331MPFS36A (R) the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. TAP instruction set Eight different instructions are possible with the 3-bit instruction register. All combinations are listed in the Instruction Codes table. One of these instructions is reserved and should not be used. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO pins/balls. To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state. EXTEST EXTEST is a mandatory 1149.1 instruction which is to be executed whenever the instruction register is loaded with all 0s. EXTEST is not implemented in this SRAM TAP controller, and therefore this device is not compliant to 1149.1. The TAP controller does recognize an all-0 instruction. When an EXTEST instruction is loaded into the instruction register, the SRAM responds as if a SAMPLE/PRELOAD instruction has been loaded. There is one difference between the two instructions, unlike the SAMPLE/PRELOAD instruction, EXTEST places the SRAM outputs in a High-Z state. IDCODE The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state. The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the identification register. It also places the identification register between the TDI and TDO pins/balls and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins/balls when the TAP controller is in a Shift-DR state. It also places all SRAM outputs into a high-Z state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE/PRELOAD instruction is loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAM's input and I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet.Because the RAM clock is independent from the TAP clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i./e in a metastable state). Although allowing the TAP to sample metastable inputs will not harm the device, repeatable results cannot be accepted. RAM input signals must be stabilized for long enough to meet the TAP's input data capture set-up plus hold time (tCS plus tCH). The RAM's clock inputs need not be paused for any other TAP operation except capturing the I/O ring contents into the boundary Scan Register. Moving the controller to Shift-DR state then places the boundary scan register between the TDI and TDO pins. BYPASS The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between TDI and TDO. RESERVED 12/22/03, v.2.3 Alliance Semiconductor 11 of 22 AS7C331MPFS32A AS7C331MPFS36A (R) Do not use a reserved instruction. These instructions are not implemented but are reserved for future use. TAP timing diagram 1 2 3 4 5 6 Test Clock (TCK) tTHTL tTLTH tTHTH Test Mode Select (TMS) tMVTH tTHMX Test Data-In (TDI) tDVTH tTHDX tTLOX tTLOV Test Data-Out (TDO) Don't care Undefined TAP AC electrical characteristics For notes 1 and 2, +10oC TJ +110oC and +2.4V VDD +2.6V. Description Clock Clock cycle time Clock frequency Clock high time Clock low time Output Times TCK low to TDO unknown TCK low to TDO valid TDI valid to TCK high TCK high to TDI invalid Setup Times TMS setup Capture setup Hold Times TMS hold Capture hold Symbol Min tTHTH 50 fTF tTHTL 20 tTLTH 20 20 tTLOX 0 tTHDX tMVTH tCS1 tTHMX tCH1 Units ns MHz ns ns 5 5 ns ns ns ns 5 5 ns ns 5 5 ns ns tTLOV tDVTH Max 10 1 tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register. 2 Test conditions are specified using the load in the figure TAP AC output load equivalent. 12/22/03, v.2.3 Alliance Semiconductor 12 of 22 AS7C331MPFS32A AS7C331MPFS36A (R) TAP AC test conditions TAP AC output load equivalent VDDQ/2 Input pulse levels. . . . . . . . . . . . . . . Vss to VDD Input rise and fall times. . . . . . . . . . . . . . . 1 ns Input timing reference levels. . . . . . . . . . VDDQ/2 Output reference levels . . . . . . . . . . . . . . VDDQ/2 Test load termination supply voltage. . . . VDDQ/2 50 TDO 20p ZO=50 3.3V VDD, TAP DC electrical characteristics and operating conditions (+10oC < TJ < +110oC and +3.135V < VDD < +3.465V unless otherwise noted) Description Input high (logic 1) voltage Input low (logic 0) voltage Input leakage current Output leakage current Output low voltage Output low voltage Output high voltage Output high voltage Conditions 0V VIN VDD Outputs disabled, 0V VIN VDDQ(DQx) IOLC = 100A IOLT = 2mA IOHS = -100A IOHT = -2mA Symbol VIH VIL ILI Min 2.0 -0.3 -5.0 Max VDD + 0.3 0.8 5.0 Units V V A ILO -5.0 5.0 A 0.7 0.8 V V V V 1 1 1 1 Notes 1, 2 1, 2 VOL1 VOL2 VOH1 VOH2 2.9 2.0 Notes 1, 2 1, 2 2.5V VDD, TAP DC electrical characteristics and operating conditions (+10oC < TJ < +110oC and +2.4V < VDD < +2.6V unless otherwise noted) Description Input high (logic 1) voltage Input low (logic 0) voltage Input leakage current Conditions Output low voltage Output low voltage 0V VIN VDD Outputs disabled, 0V VIN VDDQ(DQx) IOLC = 100A IOLT = 2mA Output high voltage Output high voltage IOHS = -100A IOHT = -2mA Output leakage current Symbol VIH VIL ILI Min 1.7 -0.3 -5.0 Max VDD + 0.3 0.7 5.0 Units V V A ILO -5.0 5.0 A 0.2 0.7 V V 1 1 V V 1 1 VOL1 VOL2 VOH1 VOH2 2.1 1.7 1. All voltage referenced to VSS(GND). 2. Overshoot: VIH(AC) VDD + 1.5V for t tKHKH/2 Undershoot:VIL(AC) -0.5 for t tKHKH/2 Power-up: VIH +2.6V and VDD 2.4V and VDDQ 1.4V for t 200ms During normal operation, VDDQ must not exceed VDD. Control input signals (such as LD, R/W, etc.) may not have pulsed widths less than tKHKL(Min) or operate at frequencies exceeding fKF(Max). Identification register definitions Instruction field Revision number (31:28) Device depth (27:23) 12/22/03, v.2.3 1M x 36 xxxx xxxxx/xxxxx Description Reserved for version number. Defines the depth of 1M words. Alliance Semiconductor 13 of 22 AS7C331MPFS32A AS7C331MPFS36A (R) Instruction field Device width (22:18) Device ID (17:12) JEDEC ID code (11:1) ID register presence indicator (0) 1M x 36 xxxxx/xxxxx xxxxxx 00000110100 1 Description Defines the width of x32 or x36 bits. Reserved for future use. Allows unique identification of SRAM vendor. Indicates the presence of an ID register. Scan register sizes Register name Instruction Bypass ID Boundary scan Bit size 3 1 32 x36:76 Instruction codes Instruction EXTEST 000 IDCODE 001 SAMPLE Z 010 RESERVED SAMPLE/ PRELOAD 101 Description Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM outputs to High-Z state. This instruction is not 1149.1-compliant. Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operations. Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a high-Z state. Do not use. This instruction is reserved for future use. 100 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. BYPASS 12/22/03, v.2.3 Code 111, 011, 110 Places the bypass register between TDI and TDO. This operation does not affect SRAM operations. Alliance Semiconductor 14 of 22 AS7C331MPFS32A AS7C331MPFS36A (R) 165-ball BGA boundary scan exit order (x36) Bit #s 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 Signal Name A A A A A A A A A ZZ DQPa DQa DQa DQa DQa DQa DQa DQa DQa DQb DQb DQb DQb DQb DQb DQb DQb DQPb NC NC A A ADV ADSP ADSC OE BWE GWE Ball ID 6N 8P 8R 9R 9P 10P 10R 11R 11P 11H 11N 11M 11L 11K 11J 10M 10L 10K 10J 11G 11F 11E 11D 10G 10F 10E 10D 11C 11A 11B 10A 10B 9A 9B 8A 8B 7A 7B Bit #s 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 Signal Name CLK CE2 BWa BWb BWc BWd CE1 CE0 A A NC NC DQPc DQc DQc DQc DQc DQc DQc DQc DQc DQd DQd DQd DQd DQd DQd DQd DQd DQPd A LBO A A A A A1 A0 Ball ID 6B 6A 5B 5A 4A 4B 3B 3A 2A 2B 1B 1A 1C 1D 1E 1F 1G 2D 2E 2F 2G 1J 1K 1L 1M 2J 2K 2L 2M 1N 2R 1R 3P 3R 4R 4P 6P 6R Note 1 : NC and VSS pins included in the scan exit order are read as "X" (i.e. Don't care) 12/22/03, v.2.3 Alliance Semiconductor 15 of 22 AS7C331MPFS32A AS7C331MPFS36A (R) Key to switching waveforms Rising input Falling input Undefined or don't care Timing waveform of read cycle tCYC tCL tCH CLK tADSPS tADSPH ADSP tADSCS tADSCH ADSC LOAD NEW ADDRESS tAS tAH Address A1 A2 A3 tWS tWH GWE, BWE tCSS tCSH CE0, CE2 CE1 tADVS tADVH ADV ADV inserts wait states OE tHZOE DOUT (pipelined mode) Q(A1) tCD tHZC tOH Q(A2) Q(A2Y01) Q(A2Y10) Q(A2Y11) Q(A3) Q(A3Y01) Q(A3Y10) tOE tLZOE DOUT (flow-through mode) Q(A2Y01) Q(A1) Q(A2Y10) Q(A2Y11) Q(A3) Q(A3Y01) Q(A3Y10) Q(A3Y11) tHZC Read Q(A1) Suspend Read Read Q(A2) Burst Burst Read Suspend Burst Burst Burst Burst Read Read Q(A3) Read Read Read Read Read Q(A 2Y01) Q(A 2Y10) Q(A 2Y10) Q(A 2Y11) Q(A 3Y01) Q(A 3Y10) Q(A 3Y11) DSEL Note: Y = XOR when LBO = high/no connect; Y = ADD when LBO = low. BW[a:d] is don't care. 12/22/03, v.2.3 Alliance Semiconductor 16 of 22 AS7C331MPFS32A AS7C331MPFS36A (R) Timing waveform of write cycle tCH tCYC tCL CLK tADSPS tADSPH ADSP tADSCS tADSCH ADSC ADSC LOADS NEW ADDRESS tAS tAH Address A1 A3 A2 tWS tWH BWE BW[a:d] tCSS tCSH CE0, CE2 CE1 tADVS tADVH ADV SUSPENDS BURST ADV OE tDS Data In D(A1) Read Q(A1) Suspend Write D(A2) Read Q(A2) Suspend Write D(A 2) D(A2Y01) D(A2Y01) D(A2Y10) D(A2Y11) ADV Suspend ADV ADV Burst Write Burst Burst Write Write Write D(A 2Y01) D(A 2Y01) Q(A 2Y10) Q(A 2Y11) D(A3) Write D(A 3) tDH D(A3Y01) D(A3Y10) Burst Write D(A 3Y01) ADV Burst Write D(A 3Y10) Note: Y = XOR when LBO = high/no connect; Y = ADD when LBO = low. 12/22/03, v.2.3 Alliance Semiconductor 17 of 22 AS7C331MPFS32A AS7C331MPFS36A (R) Timing waveform of read/write cycle tCYC tCL tCH CLK tADSPS tADSPH ADSP tAS tAH A2 A1 Address A3 tWS tWH GWE CE0, CE2 CE1 tADVS tADVH ADV OE tDS tDH DIN D(A2) tOE tCD tLZC DOUT (pipelined mode) tHZOE tOH tLZOE Q(A1) Q(A3Y01) Q(A3) Q(A3Y10) Q(A3Y11) tCDF DOUT (flow-through mode) Q(A1) DSEL Read Q(A1) Suspend Read Q(A1) Q(A3Y01) Read Q(A2) Suspend Write D(A 2) Read Q(A3) ADV Burst Read D(A 3Y01) ADV Burst Read Q(A 3Y10) Q(A3Y10) ADV Burst Read Q(A 3Y11) Q(A3Y11) Suspend Read Q(A 3Y11) Note: Y = XOR when LBO = high/no connect; Y = ADD when LBO = low. 12/22/03, v.2.3 Alliance Semiconductor 18 of 22 AS7C331MPFS32A AS7C331MPFS36A (R) AC test conditions * Output load: For tLZC, tLZOE, tHZOE, tHZC, see Figure C. For all others, see Figure B. * Input pulse level: GND to 3V. See Figure A. Thevenin equivalent: * Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A. +3.3V for 3.3V I/O; /+2.5V for 2.5V I/O * Input and output timing reference levels: 1.5V. +3.0V 90% 10% GND 90% 10% Figure A: Input waveform DOUT Z0 = 50 50 VL = 1.5V for 3.3V I/O; 30 pF* = V DDQ/2 for 2.5V I/O Figure B: Output load (A) DOUT 353/1538 319/1667 5 pF* GND *including scope and jig capacitance Figure C: Output load(B) Notes 1 2 3 4 5 6 7 8 For test conditions, see "AC test conditions", Figures A, B, and C. This parameter is measured with output load condition in Figure C. This parameter is sampled but not 100% tested. tHZOE is less than tLZOE, and tHZC is less than tLZC at any given temperature and voltage. tCH is measured as high if above VIH, and tCL is measured as low if below VIL. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must meet the setup and hold times for all rising edges of CLK when chip is enabled. Write refers to GWE, BWE, and BW[a:d]. Chip select refers to CE0, CE1, and CE2. 12/22/03, v.2.3 Alliance Semiconductor 19 of 22 AS7C331MPFS32A AS7C331MPFS36A (R) Package dimensions 100-pin quad flat pack (TQFP) TQFP Min Max A1 0.05 0.15 A2 1.35 1.45 b 0.22 0.38 c 0.09 0.20 D 13.90 14.10 E 19.90 20.10 e Hd D b e 0.65 nominal Hd 15.85 16.15 He 21.80 22.20 L 0.45 0.75 L1 He E 1.00 nominal 0 7 Dimensions in millimeters c L1 L A1 A2 165-ball BGA (ball grid array) Top A1 corner index area 17.10 14.00 14.90 15.00 15.10 10.00 E 14.00 C 15.000.10 0.45 1.26 1.36 1.46 I 0.45 0.50 0.55 10.00 15.000.10 G 0.12 Z F Side View 12/22/03, v.2.3 A E 0.20 Z 0.70 H 1.00 D Alliance Semiconductor 1.46 MAX 0.40 0.400.05 0.35 1.00 B 0.26 F G 17.00 A B C D E F G H J K L M N P R A 17.000.10 16.90 C D Max 0.26 B Typ 1.00 11 10 9 8 7 6 5 4 3 2 1 17.000.10 Min 1 2 3 4 5 6 7 8 9 10 11 A B C D E F G H J K L M N P R All measurements are in mm. A Bottom H D / 0.500.05 M Z XY O M Z O Detail of Solder Ball 20 of 22 AS7C331MPFS32A AS7C331MPFS36A (R) Ordering information Package & Width TQFP x32 TQFP x36 BGA x32 BGA x36 250 MHz AS7C331MPFS32A-250TQC AS7C331MPFS32A-250TQI AS7C331MPFS36A-250TQC AS7C331MPFS36A-250TQI AS7C331MPFS32A-250BC AS7C331MPFS32A-250BI AS7C331MPFS36A-250BC AS7C331MPFS36A-250BI 200 MHz AS7C331MPFS32A-200TQC AS7C331MPFS32A-200TQI AS7C331MPFS36A-200TQC AS7C331MPFS36A-200TQI AS7C331MPFS32A-200BC AS7C331MPFS32A-200BI AS7C331MPFS36A-200BC AS7C331MPFS36A-200BI 167 MHz AS7C331MPFS32A-167TQC AS7C331MPFS32A-167TQI AS7C331MPFS36A-167TQC AS7C331MPFS36A-167TQI AS7C331MPFS32A-167BC AS7C331MPFS32A-167BI AS7C331MPFS36A-167BC AS7C331MPFS36A-167BI 133 MHz AS7C331MPFS32A-133TQC AS7C331MPFS32A-133TQI AS7C331MPFS36A-133TQC AS7C331MPFS36A-133TQI AS7C331MPFS32A-133BC AS7C331MPFS32A-133BI AS7C331MPFS36A-133BC AS7C331MPFS36A-133BI Part numbering guide AS7C 33 1M PF S 32/36 A -XXX TQ or B C/I 1 2 3 4 5 6 7 8 9 10 1. Alliance Semiconductor SRAM prefix 2. Operating voltage: 33 = 3.3V 3. Organization: 1M = 1M 4. Pipelined/flow-through mode (each device works in both modes) 5. Deselect: S = single cycle deselect 6. Organization: 32 = x 32; 36 = x 36 7. Production version: A = first production version 8. Clock speed (MHz) 9. Package type: TQ = TQFP, B = BGA 10. Operating temperature: C = commercial (0 C to 70 C); I = industrial (-40 C to 85 C) 12/22/03, v.2.3 Alliance Semiconductor 21 of 22 (R) Alliance Semiconductor Corporation 2575, Augustine Drive, Santa Clara, CA 95054 Tel: 408 - 855 - 4900 Fax: 408 - 855 - 4999 www.alsc.com Copyright (c) Alliance Semiconductor All Rights Reserved Advance Information Part Number: AS7C331MPFS32A/36A Document Version: v.2.3 (c) Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. 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