December 2003
Advance Information
Copyright © Alliance Semiconductor. All rights reserved.
®
AS7C331MPFS32A
AS7C331MPFS36A
12/22/03, v.2.3 Alliance Semiconductor 1 of 22
3.3V 1M × 32/36 pipelined burst synchronous SRAM
Features
• Organization: 1,048,576 words × 32 or 36 bits
•Fast clock speeds to 250MHz in LVTTL/LVCMOS
•Fast clock to data access: 2.6/3/3.4/3.8 ns
•Fast OE access time: 2.6/3/3.4/3.8 ns
•Fully synchronous register-to-register operation
•Single register flow-through mode
•Single-cycle deselect
- Dual-cycle deselect also available (AS7C332MPFD18A,
AS7C331MPFD32A/ AS7C331MPFD36A)
•Asynchronous output enable control
•Available in 100-pin TQFP and 165-ball BGA packages
•Individual byte write and global write
•Multiple chip enables for easy expansion
•3.3V core power supply
•2.5V or 3.3V I/O operation with separate VDDQ
•Linear or interleaved burst control
•Snooze mode for reduced power-standby
•Common data inputs and data outputs
•Boundary scan using IEEE 1149.1 JTAG function
•NTD™1 pipelined architecture available
(AS7C332MNTD18A, AS7C331MNTD32A/
AS7C331MNTD36A)
1 NTD™ is a trademark of Alliance Semiconductor Corporation. All trade-
marks mentioned in this document are the property of their respective own-
ers.
Logic block diagram
Selection guide
-250 -200 -167 -133 Units
Minimum cycle time 4 5 6 7.5 ns
Maximum clock frequency 250 200 166 133 MHz
Maximum pipelined clock access time 2.6 3.0 3.4 3.8 ns
Maximum operating current 450 400 350 325 mA
Maximum standby current 140 120 110 100 mA
Maximum CMOS standby current (DC) 70 70 70 70 mA
A
[19:0]
20 18 20
20
Q0
Q1 1M × 32/36
Memory
array
Burst logic
CLK
CLR
CE
Address
DQ
CE
CLK
DQ
d
CLK
DQ
Byte write
registers
register
DQ
c
CLK
DQ
Byte write
registers
DQ
b
CLK
DQ
Byte write
registers
DQ
a
CLK
DQ
Byte write
registers
Enable
CLK
DQ
register
Enable
CLK
DQ
delay
register
CE
Output
registers Input
registers
Power
down
DQ[a:d]
4
32/36
GWE
BWE
BW
d
ADV
ADSC
ADSP
CLK
CE0
CE1
CE2
BW
c
BW
b
BW
a
OE
ZZ
LBO
OE
FT
CLK CLK
32/36
32/36
2
2
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AS7C331MPFS32A
AS7C331MPFS36A
®
Pin and ball assignment
100-pin TQFP - top view
Ball assignment for 165-ball BGA for 1M x 36
1 2 3 4 5 6 7 8 9 10 11
ANC A CE0
BWc
BWb CE2 BWE ADSC ADV ANC
BNC A CE1
BWd
BWa CLK GWE OE ADSP ANC
CDQPc NC VDDQ VSS VSS VSS VSS VSS VDDQ NC DQPb
DDQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb
EDQc DQc VDDQ
V
DD
VSS VSS VSS VDD VDDQ DQb DQb
FDQc DQc VDDQ
V
DD
VSS VSS VSS VDD VDDQ DQb DQb
GDQc DQc VDDQ
V
DD
VSS VSS VSS VDD VDDQ DQb DQb
HFT VSS NC
V
DD
VSS VSS VSS VDD NC NC ZZ
JDQd DQd VDDQ VDD Vss VSS VSS VDD VDDQ DQa DQa
KDQd DQd VDDQ VDD Vss VSS VSS VDD VDDQ DQa DQa
LDQd DQd VDDQ VDD Vss VSS VSS VDD VDDQ DQa DQa
MDQd DQd VDDQ VDD Vss VSS VSS VDD VDDQ DQa DQa
NDQPd NC VDDQ VSS NC A VSS VSS VDDQ NC DQPa
PNC NC A A TDI A11
1 A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
TDO A A A A
RLBO A
A
A
TMS
A01TCK A A A A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
LBO
A
A
A
A
A1
A0
NC
A
V
SS
V
DD
A
A
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
CE0
CE1
BWd
BWc
BWb
BWa
CE2
V
DD
V
SS
CLK
GWE
BWE
OE
ADSC
ADSP
ADV
A
A
TQFP 14 x 20mm
A
NC/DQPc
DQc
DQc
V
DDQ
V
SSQ
DQc
DQc
DQc
DQc
V
SSQ
V
DDQ
DQc
DQc
FT
V
DD
NC
V
SS
DQd
DQd
V
DDQ
V
SSQ
DQd
DQd
DQd
DQd
V
SSQ
V
DDQ
DQd
DQd
NC/DQPd
DQPb/NC
DQb
DQb
V
DDQ
V
SSQ
DQb
DQb
DQb
DQb
V
SSQ
V
DDQ
DQb
DQb
V
SS
ZZ
DQa
DQa
V
DDQ
V
SSQ
DQa
DQa
DQa
DQa
V
SSQ
V
DDQ
DQa
DQa
DQPa/NC
V
DD
NC
Note: For pins 1, 30, 51, and 80, NC applies to the x32 configuration. DQPn applies to the x36
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AS7C331MPFS32A
AS7C331MPFS36A
®
Functional description
The AS7C331MPFS32A/36A is a high-performance CMOS 32-Mbit synchronous Static Random Access Memory (SRAM)
device organized as 1,048,576 words x 32/36. It incorporates a two-stage register-register pipeline for highest frequency on
any given technology.
Fast cycle times of 4/5/6/7.5 ns with clock access times (tCD) of 2.6/3/3.4/3.8 ns enable 250, 200,167and 133MHz bus
frequencies. Three chip enable (CE) inputs permit easy memory expansion. Burst operation is initiated in one of two ways: the
controller address strobe (ADSC), or the processor address strobe (ADSP). The burst advance pin (ADV) allows subsequent
internally generated burst addresses.
Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip
address register when ADSP is sampled low, the chip enables are sampled active, and the output buffer is enabled with OE. In
a read operation, the data accessed by the current address registered in the address registers by the positive edge of CLK are
carried to the data-out registers and driven on the output pins on the next positive edge of CLK. ADV is ignored on the clock
edge that samples ADSP asserted, but is sampled on all subsequent clock edges. Address is incremented internally for the next
access of the burst when ADV is sampled low and both address strobes are high. Burst mode is selectable with the
LBO
input.
With
LBO
unconnected or driven high, burst operations use an interleaved count sequence. With
LBO
driven low, the device
uses a linear count sequence.
Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable
GWE writes all 32/36 regardless of the state of individual BW[a:d] inputs. Alternately, when GWE is high, one or more bytes
may be written by asserting BWE and the appropriate individual byte BWn signals.
BWn is ignored on the clock edge that samples ADSP low, but it is sampled on all subsequent clock edges. Output buffers are
disabled when BWn is sampled lOW regardless of OE. Data is clocked into the data input register when BWn is sampled low.
Address is incremented internally to the next burst address if BWn and ADV are sampled low. This device operates in single-
cycle deselect feature during read cycles.
Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC
and ADSP follow.
ADSP must be sampled high when ADSC is sampled low to initiate a cycle with ADSC.
WE signals are sampled on the clock edge that samples ADSC low (and ADSP high).
Master chip enable CE0 blocks ADSP, but not ADSC.
The AS7C331MPFS32A/36A family operates from a core 3.3V power supply. I/Os use a separate power supply that can
operate at 2.5V or 3.3V. These devices are available in a 100-pin TQFP and 165-ball BGA.
TQFP and BGA capacitance
Parameter Symbol Signals Test conditions Max Unit
Input capacitance CIN Address and control pins VIN = 0V 5 pF
I/O capacitance CI/O I/O pins VOUT = 0V 7 pF
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AS7C331MPFS32A
AS7C331MPFS36A
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Signal descriptions
Write enable truth table (per byte)
Key: X = don’t care, L = low, H = high, n = a, b, c, d;
BWE
,
BWn
= internal write signal.
Pin I/O Properties Description
CLK I CLOCK Clock. All inputs except OE, FT, ZZ, and LBO are synchronous to this clock.
A0–A19 I SYNC Address. Sampled when all chip enables are active and when ADSC or ADSP are asserted.
DQ[a,b,c,d] I/O SYNC Data. Driven as output when the chip is enabled and when OE is active.
CE0 I SYNC Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When CE0 is inactive,
ADSP is blocked. Refer to the “Synchronous truth table” for more information.
CE1, CE2 I SYNC Synchronous chip enables, active high, and active low, respectively. Sampled on clock edges when
ADSC is active or when CE0 and ADSP are active.
ADSP I SYNC Address strobe processor. Asserted low to load a new address or to enter standby mode.
ADSC I SYNC Address strobe controller. Asserted low to load a new address or to enter standby mode.
ADV I SYNC Advance. Asserted low to continue burst read/write.
GWE I SYNC Global write enable. Asserted low to write all 32/36 and 18 bits. When high, BWE and BW[a:d]
control write enable.
BWE I SYNC Byte write enable. Asserted low with GWE high to enable effect of BW[a:d] inputs.
BW[a,b,c,d] I SYNC
Write enables. Used to control write of individual bytes when GWE is high and BWE is low. If any of
BW[a:d] is active with GWE high and BWE low, the cycle is a write cycle. If all BW[a:d] are inactive,
the cycle is a read cycle.
OE I ASYNC Asynchronous output enable. I/O pins are driven when OE is active and chip is in read mode.
LBO ISTATIC
Selects Burst mode. When tied to VDD or left floating, device follows interleaved Burst order. When
driven Low, device follows linear Burst order. This signal is internally pulled High.
TDO O SYNC Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK (BGA only).
TDI I SYNC Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK (BGA only).
TMS I SYNC This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK (BGA only).
TCK I Test Clock Test Clock. All inputs are sampled on the rising edge of TCK. All outputs are driven from the falling
edge of TCK.
FT ISTATIC
Selects Pipeline or Flow-through mode. When tied to VDD or left floating, enables Pipeline mode.
When driven Low, enables single register Flow-through mode. This signal is internally pulled High.
ZZ I ASYNC Snooze. Places device in low power mode; data is retained. Connect to GND if unused.
Function GWE BWE BWa BWb BWc BWd
Write All Bytes LXXXXX
HLLLLL
Write Byte a H L L H H H
Write Byte c and d H L H H L L
Read HHXXXX
HLHHHH
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AS7C331MPFS32A
AS7C331MPFS36A
®
Burst sequence table
Synchronous truth table
TQFP and BGA thermal resistance
Interleaved burst address Linear burst address
A1 A0 A1 A0 A1 A0 A1 A0 A1 A0 A1 A0 A1 A0 A1 A0
Starting Address 0 0 0 1 1 0 1 1 Starting Address 0 0 0 1 1 0 1 1
First Increment 0 1 0 0 1 1 1 0 First Increment 0 1 1 0 1 1 0 0
Second Increment 1 0 1 1 0 0 0 1 Second Increment 1 0 1 1 0 0 0 1
Third Increment 1 1 1 0 0 1 0 0 Third Increment 1 1 1 0 0 1 1 0
CE01
1 X = don’t care, L = low, H = high
CE1 CE2 ADSP ADSC ADV
BWn
2
2 See "Write enable truth table (per byte)," on page 4 for more information.
OE Address accessed CLK Operation DQ
HXXXLXXX NA L to H DeselectHi−Z
L L X L X X X X NA L to H Deselect Hi−Z
L L X H L X X X NA L to H Deselect Hi−Z
L X H L X X X X NA L to H Deselect Hi−Z
L X H H L X X X NA L to H Deselect Hi−Z
L H L L X X X L External L to H Begin read Hi−Z3
3 Q in flow-through mode.
L H L L X X X H External L to H Begin read Hi−Z
L H L H L X F L External L to H Begin read Hi−Z3
L H L H L X F H External L to H Begin read Hi−Z
XXXHHLFL Next L to HContinue readQ
XXXHHLFH Next L to HContinue readHi−Z
XXXHHHFL Current L to HSuspend readQ
XXXHHHFH Current L to HSuspend readHi−Z
HXXXHLFL Next L to HContinue readQ
HXXXHLFH Next L to HContinue readHi−Z
HXXXHHFL Current L to HSuspend readQ
HXXXHHFH Current L to HSuspend readHi−Z
L H L H L X T X External L to H Begin write D4
4 For write operation following a READ,
OE
must be high before the input data set up time and held high throughout the input hold time
XXXHHLTX Next L to HContinue writeD
HXXXHLTX Next L to HContinue writeD
XXXHHHTX Current L to HSuspend writeD
HXXXHHTX Current L to HSuspend writeD
Description Conditions Symbol Typical Units
Thermal resistance
(junction to ambient)1
1 This parameter is sampled
Test conditions follow standard test methods
and procedures for measuring thermal
impedance, per EIA/JESD51
1–layer θJA 40 °C/W
4–layer θJA 22 °C/W
Thermal resistance
(junction to top of case)1θJC 8°C/W
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AS7C331MPFS36A
12/22/03, v.2.3 Alliance Semiconductor 6 of 22
Absolute maximum ratings
Stresses greater than those listed under “Absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only, and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to abso-
lute maximum rating conditions may affect reliability.
Recommended operating conditions at 3.3V I/O
Recommended operating conditions at 2.5V I/O
Parameter Symbol Min Max Unit
Power supply voltage relative to GND VDD, VDDQ –0.5 +4.6 V
Input voltage relative to GND (input pins) VIN –0.5 VDD + 0.5 V
Input voltage relative to GND (I/O pins) VIN –0.5 VDDQ + 0.5 V
Power dissipation Pd–1.8W
Short circuit output current IOUT – 20 mA
Storage temperature (TQFP) Tstg (TQFP) –65 +150 oC
Storage temperature (BGA) Tstg (BGA) –65 +125 oC
Temperature under bias Tbias –65 +135 oC
Parameter Symbol Min Nominal Max Unit
Supply voltage for inputs VDD 3.135 3.3 3.465 V
Supply voltage for I/O VDDQ 3.135 3.3 3.465 V
Ground supply Vss 0 0 0 V
Parameter Symbol Min Nominal Max Unit
Supply voltage for inputs VDD 3.135 3.3 3.465 V
Supply voltage for I/O VDDQ 2.375 2.5 2.625 V
Ground supply Vss 0 0 0 V
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AS7C331MPFS32A
AS7C331MPFS36A
®
DC electrical characteristics for 3.3V I/O operation
DC electrical characteristics for 2.5V I/O operation
IDD operating conditions and maximum limits
Parameter Sym Conditions Min Max Unit
Input leakage current1
1 FTX, LBO, and ZZX pins and the 165 BGA JTAG pins (TMSX, TDIX, and TCKX) have an internal pull-up or pull-down, and input leakage = ±10 µA.
|ILI|V
DD = Max, OV < VIN < VDD -2 2 µA
Output leakage current |ILO|OE ≥ VIH, VDD = Max, OV < VOUT < VDDQ -2 2 µA
Input high (logic 1) voltage VIH
Address and control pins 2 VDD+0.3 V
I/O pins 2 VDDQ+0.3
Input low (logic 0) voltage VIL
Address and control pins -0.3 0.8 V
I/O pins -0.5 0.8
Output high voltage VOH IOH = –4 mA, VDDQ = 3.135V 2.4 – V
Output low voltage VOL IOL = 8 mA, VDDQ = 3.465V – 0.4 V
Parameter Sym Conditions Min Max Unit
Input leakage current |ILI|V
DD = Max, OV < VIN < VDD -2 2 µA
Output leakage current |ILO|OE ≥ VIH, VDD = Max, OV < VOUT < VDDQ -2 2 µA
Input high (logic 1) voltage VIH
Address and control pins 1.7 VDD+0.3 V
I/O pins 1.7 VDDQ+0.3 V
Input low (logic 0) voltage VIL
Address and control pins -0.3 0.7 V
I/O pins -0.3 0.7 V
Output high voltage VOH IOH = –4 mA, VDDQ = 2.375V 1.7 – V
Output low voltage VOL IOL = 8 mA, VDDQ = 2.625V – 0.7 V
Parameter Sym Conditions -250 -200 -167 -133 Unit
Operating power supply
current1(pipelined mode)
1 ICC given with no output loading. ICC increases with faster cycle times and greater output loading.
ICC CE0 = VIL, CE1 = VIH, CE2 = VIL, f = fMax,
IOUT = 0 mA
450 400 350 325 mA
Operating power supply
current1(flow-through mode)
ICC
(FT) 375 325 280 260 mA
Standby power supply current
ISB Deselected, f = fMax, ZZ < VIL 140 120 110 100
mA
ISB1 Deselected, f = 0, ZZ < 0.2V,
all VIN ≤ 0.2V or ≥ VDD – 0.2V 70 70 70 70
ISB2
Deselected, f = f
Max
, ZZ
≥
V
DD
– 0.2V,
all VIN ≤ VIL or ≥ VIH 60 60 60 60
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AS7C331MPFS32A
AS7C331MPFS36A
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Timing characteristics over operating range
Parameter Sym
-250 –200 –167 -133
Unit Notes1
1 See “Notes” on page 19.
Min Max Min Max Min Max Min Max
Clock frequency fMax - 250 – 200 – 166 – 133 MHz
Cycle time (pipelined mode) tCYC 4 - 5 – 6 – 7.5 – ns
Cycle time (flow-through mode) tCYCF 7.0 - 7.5 – 8.5 – 12 – ns
Clock access time (pipelined mode) tCD - 2.6 – 3.0 – 3.4 – 3.8 ns
Clock access time (flow-through mode) tCDF - 6.0 – 7.5 – 8.5 – 10 ns
Output enable low to data valid tOE - 2.6 – 3.0 – 3.4 – 3.8 ns
Clock high to output low Z tLZC 0 - 0 – 0 – 0 – ns 2,3,4
Data output invalid from clock high (pipelined
mode) tOH 1.5 - 1.5 – 1.5 – 1.5 – ns 2
Data Output invalid from clock high (flow-
through mode) tOHF 3.0 - 3.0 – 3.0 – 3.0 – ns 2
Output enable low to output low Z tLZOE 0 - 0 – 0 – 0 – ns 2,3,4
Output enable high to output high Z tHZOE - 2.6 – 3.0 – 3.4 – 3.8 ns 2,3,4
Clock high to output high Z tHZC - 2.6 – 3.0 – 3.4 – 3.8 ns 2,3,4
Output enable high to invalid output tOHOE 0-0–0–0 –ns
Clock high pulse width tCH 1.7 - 2.0 – 2.4 – 2.4 – ns 5
Clock low pulse width tCL 1.7 - 2.0 – 2.3 – 2.4 – ns 5
Address setup to clock high tAS 1.2 - 1.4 – 1.5 – 1.5 – ns 6
Data setup to clock high tDS 1.2 - 1.4 – 1.5 – 1.5 – ns 6
Write setup to clock high tWS 1.2 - 1.4 – 1.5 – 1.5 – ns 6,7
Chip select setup to clock high tCSS 1.2 - 1.4 – 1.5 – 1.5 – ns 6,8
Address hold from clock high tAH 0.3 - 0.4 – 0.5 – 0.5 – ns 6
Data hold from clock high tDH 0.3 - 0.4 – 0.5 – 0.5 – ns 6
Write hold from clock high tWH 0.3 - 0.4 – 0.5 – 0.5 – ns 6,7
Chip select hold from clock high tCSH 0.3 - 0.4 – 0.5 – 0.5 – ns 6,8
ADV setup to clock high tADVS 1.2 - 1.4 – 1.5 – 1.5 – ns 6
ADSP setup to clock high tADSPS 1.2 - 1.4 – 1.5 – 1.5 – ns 6
ADSC setup to clock high tADSCS 1.2 - 1.4 – 1.5 – 1.5 – ns 6
ADV hold from clock high tADVH 0.3 - 0.4 – 0.5 – 0.5 – ns 6
ADSP hold from clock high tADSPH 0.3 - 0.4 – 0.5 – 0.5 – ns 6
ADSC hold from clock high tADSCH 0.3 - 0.4 – 0.5 – 0.5 – ns 6
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AS7C331MPFS32A
AS7C331MPFS36A
®
IEEE 1149.1 serial boundary scan (JTAG)
The SRAM incorporates a serial boundary scan test access port (TAP). The port operates in accordance with IEEE Standard
1149.1-1990. The SRAM contains a TAP controller, instruction register, boundary scan register, bypass register, and ID
register.
Disabling the JTAG feature
If the JTAG function is not being implemented, TCK should be grounded to avoid mid-level input. At power-up, the device
will come up in a reset state which will not interfere with the operation of the device.
Test access port (TAP)
Test clock (TCK)
The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Test mode select (TMS)
The TAP controller receives commands from TMS input. It is sampled on the rising edge of TCK. You can leave this pin/ball
unconnected if the TAP is not used. The pin/ball is pulled up internally, resulting in a logic high level.
UPDATE-IR
CAPTURE-IR
SHIFT-IR
EXIT1-IR
PAUSE-IR
EXIT2-IR
SELECT
IR-SCAN
UPDATE-DR
CAPTURE-DR
SHIFT-DR
EXIT1-DR
PAUSE-DR
EXIT2-DR
RUN-TEST/
IDLE
TEST-LOGIC
RESET
SELECT
DR-SCAN
0
0
0
0
0
1
0
0
00
0
0
00
0
0
0
11 1
11
1
1
1
11
1
1
1
11
Note: The 0 or 1 next to each state represents the value of TMS at the rising edge of TCK.
TAP controller state diagram TAP controller block diagram
Selection
Circuitry
Selection
Circuitry
3130 29 012
...
Boundary Scan Register1
Identification Register
Bypass Register
Instruction Register
x012
012
0
.. ...
TDI
TMS
TCK
TDO
TAP Controller
1 x = 75
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AS7C331MPFS36A
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Test data-in (TDI)
The TDI pin/ball serially inputs information into the registers and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on
loading the instruction register, see the TAP Controller State Diagram. TDI is internally pulled up and can be unconnected if
the TAP is unused in an application. TDI is connected to the most significant bit (MSB) of any register.
Test data-out (TDO)
The TDO output pin/ball serially clocks data-out from the registers. The output is active depending upon the current state of
the TAP state machine. The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of
any register. (See the TAP Controller State Diagram.)
Performing a TAP RESET
You can perform a RESET by forcing TMS high (VDD) for five rising edges of TCK. This RESET does not affect the
operation of the SRAM and can be performed while the SRAM is operating.
At power-up, the TAP is reset internally to ensure that TDO comes up in a high-Z state.
TAP registers
Registers are connected between the TDI and TDO pins/balls. They allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through the instruction register. Data is serially loaded into the TDI pin/
ball on the rising edge of TCK. Data is output on the TDO pin/ball on the falling edge of TCK.
Instruction register
You can serially load three-bit instructions into the instruction register. The register is loaded when it is placed between the
TDI and TDO pins/balls as shown in the TAP Controller Block Diagram. The instruction register is loaded with the IDCODE
instruction at power up and also if the controller is placed in a reset state, as described in the previous section.
When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary “01” pattern to allow
for fault isolation of the board-level series test data path.
Bypass register
To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the TDI and TDO pins/balls. This allows data to be shifted through
the SRAM with minimal delay. The bypass register is set low (Vss) when the BYPASS instruction is executed.
Boundary scan register
The boundary scan register is connected to all the input and bidirectional pins/balls on the SRAM. The chip has a 76-bit-long
register.
The boundary scan register is loaded with the contents of the RAM I/O ring when the TAP controller is in the Capture-DR state
and is then placed between the TDI and TDO pins/balls when the controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD, and SAMPLE Z instructions can be used to capture the contents of the I/O ring.
The boundary scan order table shows the order in which the bits are connected. Each bit corresponds to one of the bumps on
the SRAM package. The most significant bit (MSB) of the register is connected to TDI, and the least significant bit (LSB) is
connected to TDO.
Identification (ID) register
The ID register has a vendor code and other information described in the Identification Register Definitions table. The ID
register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in
12/22/03, v.2.3 Alliance Semiconductor 11 of 22
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the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the
Shift-DR state.
TAP instruction set
Eight different instructions are possible with the 3-bit instruction register. All combinations are listed in the Instruction Codes
table. One of these instructions is reserved and should not be used.
Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI
and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO pins/balls. To
execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be executed whenever the instruction register is loaded with all 0s.
EXTEST is not implemented in this SRAM TAP controller, and therefore this device is not compliant to 1149.1.
The TAP controller does recognize an all-0 instruction. When an EXTEST instruction is loaded into the instruction register, the
SRAM responds as if a SAMPLE/PRELOAD instruction has been loaded. There is one difference between the two
instructions, unlike the SAMPLE/PRELOAD instruction, EXTEST places the SRAM outputs in a High-Z state.
IDCODE
The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test
logic reset state. The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the identification register. It
also places the identification register between the TDI and TDO pins/balls and allows the IDCODE to be shifted out of the
device when the TAP controller enters the Shift-DR state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins/balls when the
TAP controller is in a Shift-DR state. It also places all SRAM outputs into a high-Z state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE/PRELOAD instruction is loaded
in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAM’s input and I/O
buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and are
loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet.Because the
RAM clock is independent from the TAP clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents
while the input buffers are in transition (i./e in a metastable state). Although allowing the TAP to sample metastable inputs will
not harm the device, repeatable results cannot be accepted. RAM input signals must be stabilized for long enough to meet the
TAP’s input data capture set-up plus hold time (tCS plus tCH). The RAM’s clock inputs need not be paused for any other TAP
operation except capturing the I/O ring contents into the boundary Scan Register. Moving the controller to Shift-DR state then
places the boundary scan register between the TDI and TDO pins.
BYPASS
The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected
together on a board. When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR
state, the bypass register is placed between TDI and TDO.
RESERVED
®
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Do not use a reserved instruction. These instructions are not implemented but are reserved for future use.
TAP timing diagram
TAP AC electrical characteristics
For notes 1 and 2, +10oC ≤ TJ ≤ +110oC and +2.4V ≤ VDD ≤ +2.6V.
Description Symbol Min Max Units
Clock
Clock cycle time tTHTH 50 ns
Clock frequency fTF 20 MHz
Clock high time tTHTL 20 ns
Clock low time tTLTH 20 ns
Output Times
TCK low to TDO unknown tTLOX 0 ns
TCK low to TDO valid tTLOV 10 ns
TDI valid to TCK high tDVTH 5 ns
TCK high to TDI invalid tTHDX 5 ns
Setup Times
TMS setup tMVTH 5 ns
Capture setup tCS1
1 tCS and tCH refer to the setup and hold time requirements of latching
data from the boundary scan register.
2 Test conditions are specified using the load in the figure TAP AC output
load equivalent.
5ns
Hold Times
TMS hold tTHMX 5 ns
Capture hold tCH15ns
123456
tTHTL tTLTH tTHTH
tMVTH tTHMX
tDVTH tTHDX tTLOX
tTLOV
Test Clock
(TCK)
Test Mode Select
(TMS)
Test Data-In
(TDI)
Tes t Da ta-O ut
(TDO)
Don’t care Undefined
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3.3V VDD, TAP DC electrical characteristics and operating conditions
(+10oC < TJ < +110oC and +3.135V < VDD < +3.465V unless otherwise noted)
2.5V VDD, TAP DC electrical characteristics and operating conditions
(+10oC < TJ < +110oC and +2.4V < VDD < +2.6V unless otherwise noted)
1. All voltage referenced to VSS(GND).
2. Overshoot: VIH(AC) ≤ VDD + 1.5V for t ≤ tKHKH/2
Undershoot:VIL(AC) ≥ -0.5 for t ≤ tKHKH/2
Power-up: VIH ≤ +2.6V and VDD ≤ 2.4V and VDDQ ≤ 1.4V for t ≤ 200ms
During normal operation, VDDQ must not exceed VDD. Control input signals (such as LD, R/W, etc.) may not have pulsed
widths less than tKHKL(Min) or operate at frequencies exceeding fKF(Max).
Identification register definitions
Description Conditions Symbol Min Max Units Notes
Input high (logic 1) voltage VIH 2.0 VDD + 0.3 V 1, 2
Input low (logic 0) voltage VIL -0.3 0.8 V 1, 2
Input leakage current 0V ≤ VIN ≤ VDD ILI-5.0 5.0 µA
Output leakage current Outputs disabled,
0V ≤ VIN ≤ VDDQ(DQx) ILO-5.0 5.0 µA
Output low voltage IOLC = 100µAV
OL1 0.7 V 1
Output low voltage IOLT = 2mA VOL2 0.8 V 1
Output high voltage IOHS = -100µAV
OH1 2.9 V 1
Output high voltage IOHT = -2mA VOH2 2.0 V 1
Description Conditions Symbol Min Max Units Notes
Input high (logic 1) voltage VIH 1.7 VDD + 0.3 V 1, 2
Input low (logic 0) voltage VIL -0.3 0.7 V 1, 2
Input leakage current 0V ≤ VIN ≤ VDD ILI-5.0 5.0 µA
Output leakage current Outputs disabled,
0V ≤ VIN ≤ VDDQ(DQx) ILO-5.0 5.0 µA
Output low voltage IOLC = 100µAV
OL1 0.2 V 1
Output low voltage IOLT = 2mA VOL2 0.7 V 1
Output high voltage IOHS = -100µAV
OH1 2.1 V 1
Output high voltage IOHT = -2mA VOH2 1.7 V 1
Instruction field 1M x 36 Description
Revision number (31:28) xxxx Reserved for version number.
Device depth (27:23) xxxxx/xxxxx Defines the depth of 1M words.
Input pulse levels. . . . . . . . . . . . . . . Vss to VDD
Input rise and fall times. . . . . . . . . . . . . . . 1 ns
Input timing reference levels. . . . . . . . . . VDDQ/2
Output reference levels . . . . . . . . . . . . . . VDDQ/2
Test load termination supply voltage. . . . VDDQ/2
TAP AC test conditions TAP AC output load equivalent
TDO
50Ω
ZO=50
VDDQ/2
20p
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Scan register sizes
Instruction codes
Device width (22:18) xxxxx/xxxxx Defines the width of x32 or x36 bits.
Device ID (17:12) xxxxxx Reserved for future use.
JEDEC ID code (11:1) 00000110100 Allows unique identification of SRAM vendor.
ID register presence indicator (0) 1 Indicates the presence of an ID register.
Register name Bit size
Instruction 3
Bypass 1
ID 32
Boundary scan x36:76
Instruction Code Description
EXTEST 000 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all
SRAM outputs to High-Z state. This instruction is not 1149.1-compliant.
IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operations.
SAMPLE Z 010 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all
SRAM output drivers to a high-Z state.
RESERVED 101 Do not use. This instruction is reserved for future use.
SAMPLE/
PRELOAD 100 Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
BYPASS 111, 011, 110 Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
Instruction field 1M x 36 Description
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165-ball BGA boundary scan exit order (x36)
Bit #s Signal Name Ball ID
39 CLK 6B
40 CE2 6A
41 BWa 5B
42 BWb 5A
43 BWc 4A
44 BWd 4B
45 CE1 3B
46 CE0 3A
47 A 2A
48 A 2B
49 NC 1B
50 NC 1A
51 DQPc 1C
52 DQc 1D
53 DQc 1E
54 DQc 1F
55 DQc 1G
56 DQc 2D
57 DQc 2E
58 DQc 2F
59 DQc 2G
60 DQd 1J
61 DQd 1K
62 DQd 1L
63 DQd 1M
64 DQd 2J
65 DQd 2K
66 DQd 2L
67 DQd 2M
68 DQPd 1N
69 A 2R
70 LBO 1R
71 A 3P
72 A 3R
73 A 4R
74 A 4P
75 A1 6P
76 A0 6R
Bit #s Signal Name Ball ID
1A 6N
2A 8P
3A 8R
4A 9R
5A 9P
6 A 10P
7 A 10R
8A 11R
9A 11P
10 ZZ 11H
11 DQPa 11N
12 DQa 11M
13 DQa 11L
14 DQa 11K
15 DQa 11J
16 DQa 10M
17 DQa 10L
18 DQa 10K
19 DQa 10J
20 DQb 11G
21 DQb 11F
22 DQb 11E
23 DQb 11D
24 DQb 10G
25 DQb 10F
26 DQb 10E
27 DQb 10D
28 DQPb 11C
29 NC 11A
30 NC 11B
31 A 10A
32 A 10B
33 ADV 9A
34 ADSP 9B
35 ADSC 8A
36 OE 8B
37 BWE 7A
38 GWE 7B
Note 1 : NC and VSS pins included in the scan exit order are read as “X” (i.e. Don’t care)
®
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12/22/03, v.2.3 Alliance Semiconductor 16 of 22
Key to switching waveforms
Timing waveform of read cycle
Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low. BW[a:d] is don’t care.
Undefined or don’t careFalling inputRising input
CE1
t
CYC
t
CH
t
CL
t
ADSPS
t
ADSPH
t
AS
t
AH
t
WS
t
ADVS
t
OH
CLK
ADSP
ADSC
Address
GWE, BWE
CE0, CE2
ADV
OE
D
OUT
t
CSS
t
HZC
t
CD
t
WH
t
ADVH
t
HZOE
t
ADSCS
t
ADSCH
LOAD NEW ADDRESS
ADV inserts wait states
Q(A2Ý10)
Q(A2Ý11)
Q(A3)
Q(A2)
Q(A2Ý01) Q(A3Ý01) Q(A3Ý10)
Q(A1)
A2A1 A3
(pipelined
D
OUT
Q(A2Ý10)
Q(A2Ý11)
Q(A3)
Q(A2Ý01) Q(A3Ý01) Q(A3Ý10)
Q(A3Ý11)
Q(A1)
t
HZC
t
OE
t
LZOE
t
CSH
(flow-through
mode)
mode)
Read
Q(A1)
Sus-
pend
Read
Read
Q(A2)
Burst
Read
Q(A 2Ý01
)
Read
Q(A3) DSEL
Burst
Read
Q(A 2Ý10
)
Suspend
Read
Q(A 2Ý10
)
Burst
Read
Q(A 2Ý11
)
Burst
Read
Q(A 3Ý01
)
Burst
Read
Q(A 3Ý10
)
Burst
Read
Q(A 3Ý11
)
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Timing waveform of write cycle
Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low.
t
CYC
t
CL
t
ADSPS
t
ADSPH
t
ADSCS
t
ADSCH
t
AS
t
AH
t
WS
t
WH
t
CSS
t
ADVS
t
DS
t
DH
CLK
ADSP
ADSC
Address
BWE
CE0, CE2
ADV
OE
Data In
t
CSH
t
ADVH
D(A2Ý01)
D(A2Ý10) D(A3)D(A2) D(A2Ý01) D(A3Ý01) D(A3Ý10)
D(A1) D(A2Ý11)
ADV SUSPENDS BURST
ADSC LOADS NEW ADDRESS
A1 A2 A3
t
CH
CE1
BW[a:d]
Read Q(A1) Sus-
pend
Write
Read
Q(A2)
Suspend
Write
D(A 2
)
ADV
Burst
Write
D(A 2Ý01
)
Suspend
Write
D(A 2Ý01
)
ADV
Burst
Write
Q(A 2Ý10
)
Write
D(A 3
)
Burst
Write
D(A 3Ý01
)
ADV
Burst
Write
Q(A 2Ý11
)
ADV
Burst
Write
D(A 3Ý10
)
®
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12/22/03, v.2.3 Alliance Semiconductor 18 of 22
Timing waveform of read/write cycle
Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low.
t
CH
t
CYC
t
CL
t
ADSPS
t
ADSPH
t
AS
t
AH
t
WS
t
WH
t
ADVS
t
DS
t
DH
t
OH
CLK
ADSP
Address
GWE
CE0, CE2
ADV
OE
D
IN
D
OUT
t
CD
t
ADVH
t
LZOE
t
OE
t
LZC
Q(A1)
Q(A3Ý01)
D(A2)
Q(A3)
Q(A3Ý10) Q(A3Ý11)
A1 A2 A3
CE1
t
HZOE
(pipelined mode)
D
OUT
Q(A1)
Q(A3Ý01) Q(A3Ý10)
(flow-through mode)
t
CDF
Q(A3Ý11)
DSEL Suspend
Read
Q(A1)
Read
Q(A1)
Suspend
Write
D(A 2
)
ADV
Burst
Read
D(A 3Ý01
)
Suspend
Read
Q(A 3Ý11
)
ADV
Burst
Read
Q(A 3Ý10
)
ADV
Burst
Read
Q(A 3Ý11
)
Read
Q(A2)
Read
Q(A3)
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AC test conditions
Notes
1 For test conditions, see “AC test conditions”, Figures A, B, and C.
2 This parameter is measured with output load condition in Figure C.
3 This parameter is sampled but not 100% tested.
4t
HZOE is less than tLZOE, and tHZC is less than tLZC at any given temperature and voltage.
5t
CH is measured as high if above VIH, and tCL is measured as low if below VIL.
6 This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must
meet the setup and hold times for all rising edges of CLK when chip is enabled.
7 Write refers to
GWE
,
BWE
, and
BW[a:d].
8 Chip select refers to
CE0
,
CE1
, and
CE2
.
Z
0
= 50
Ω
D
OUT
50
Ω
Figure B: Output load (A)
30 pF*
Figure A: Input waveform
10%
90%
GND
90%
10%
+3.0V
• Output load: For tLZC, tLZOE, tHZOE, tHZC, see Figure C. For all others, see Figure B.
• Input pulse level: GND to 3V. See Figure A.
• Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A.
• Input and output timing reference levels: 1.5V.
V
L
= 1.5V
for 3.3V I/O;
= V
DDQ
/2
for 2.5V I/O
Thevenin equivalent:
353
Ω/1538Ω
5 pF*
319
Ω/1667Ω
D
OUT
GND
Figure C: Output load(B)
*including scope
and jig capacitance
+3.3V for 3.3V I/O;
/+2.5V for 2.5V I/O
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Package dimensions
100-pin quad flat pack (TQFP)
165-ball BGA (ball grid array)
TQFP
Min Max
A1 0.05 0.15
A2 1.35 1.45
b 0.22 0.38
c 0.09 0.20
D 13.90 14.10
E 19.90 20.10
e 0.65 nominal
Hd 15.85 16.15
He 21.80 22.20
L 0.45 0.75
L1 1.00 nominal
α0° 7°
Dimensions in millimeters
A1 A2
L1
L
c
He E
Hd
D
b
e
α
/ 0.50±0.05
Ø
Ø
67891011 123456543211110987
H
D
F
E
G
A
C
B
M
P
N
R
J
L
K
15.00±0.10
10.00
1.00
17.00±0.10
14.00
1.00
17.00±0.10
15.00±0.10
A1 corner index area
All measurements are in mm.
Min Typ Max
A1.00
B16.90 17.00 17.10
C14.00
D14.90 15.00 15.10
E10.00
F0.26
G0.35 0.40 0.45
H1.26 1.36 1.46
I0.45 0.50 0.55
Z
ZXY
0.40±0.05
1.46 MAX
0.26
0.70
0.20 Z
Top Bottom
Side View Detail of Solder Ball
A
B
C
A
E
D
D
FH
G
H
D
F
E
G
A
C
B
M
P
N
R
J
L
K
0.12 Z
M
M
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®
Ordering information
Part numbering guide
1. Alliance Semiconductor SRAM prefix
2. Operating voltage: 33 = 3.3V
3. Organization: 1M = 1M
4. Pipelined/flow-through mode (each device works in both modes)
5. Deselect: S = single cycle deselect
6. Organization: 32 = x 32; 36 = x 36
7. Production version: A = first production version
8. Clock speed (MHz)
9. Package type: TQ = TQFP, B = BGA
10. Operating temperature: C = commercial (
0
°
C to 70
°
C); I = industrial (
-40
°
C to 85
°
C)
Package &
Width 250 MHz 200 MHz 167 MHz 133 MHz
TQFP x32 AS7C331MPFS32A-250TQC AS7C331MPFS32A-200TQC AS7C331MPFS32A-167TQC AS7C331MPFS32A-133TQC
AS7C331MPFS32A-250TQI AS7C331MPFS32A-200TQI AS7C331MPFS32A-167TQI AS7C331MPFS32A-133TQI
TQFP x36 AS7C331MPFS36A-250TQC AS7C331MPFS36A-200TQC AS7C331MPFS36A-167TQC AS7C331MPFS36A-133TQC
AS7C331MPFS36A-250TQI AS7C331MPFS36A-200TQI AS7C331MPFS36A-167TQI AS7C331MPFS36A-133TQI
BGA x32 AS7C331MPFS32A-250BC AS7C331MPFS32A-200BC AS7C331MPFS32A-167BC AS7C331MPFS32A-133BC
AS7C331MPFS32A-250BI AS7C331MPFS32A-200BI AS7C331MPFS32A-167BI AS7C331MPFS32A-133BI
BGA x36 AS7C331MPFS36A-250BC AS7C331MPFS36A-200BC AS7C331MPFS36A-167BC AS7C331MPFS36A-133BC
AS7C331MPFS36A-250BI AS7C331MPFS36A-200BI AS7C331MPFS36A-167BI AS7C331MPFS36A-133BI
AS7C 33 1M PF S32/36 A–XXX TQ or B C/I
1
23
45678
910
Alliance Semiconductor Corporation
2575, Augustine Drive,
Santa Clara, CA 95054
Tel: 408 - 855 - 4900
Fax: 408 - 855 - 4999
www.alsc.com
Copyright © Alliance Semiconductor
All Rights Reserved
Advance Information
Part Number: AS7C331MPFS32A/36A
Document Version: v.2.3
© Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alli-
ance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products
at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/
or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under develop-
ment, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential cus-
tomers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability
arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products
including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in
Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Condi-
tions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual
property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure
may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer
assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.
®
