MT42C4256 883C 256K x 4 VRAM AUSTIN SEMICONDUCTOR, INC. Limited Supply - Consult Factory 256K x 4 DRAM WITH 512 x 4 SAM VRAM AVAILABLE AS MILITARY SPECIFICATION PIN ASSIGNMENT (Top View) * SMD 5962-89497 * MIL-STD-883 28-Pin DIP (400 MIL) FEATURES * * * * * * * Industry standard pinout, timing and functions High-performance, CMOS silicon-gate process Single +5V 10% power supply Inputs and outputs are fully TTL compatible Refresh modes: /R/A/S-ONLY, /C/A/S-BEFORE-/R/A/S (CBR) and HIDDEN 512-cycle refresh within 8ms Optional FAST PAGE MODE access cycles Dual port organization: 256K x 4 DRAM port 512 x 4 SAM port No refresh required for serial access memory Low power: 15mW standby; 275mW active, typical * * * * * * JEDEC Standard Function set PERSISTENT MASKED WRITE SPLIT READ TRANSFER WRITE TRANSFER/SERIAL INPUT ALTERNATE WRITE TRANSFER BLOCK WRITE SC SDQ1 SDQ2 TR/OE DQ1 DQ2 ME/WE NC RAS A8 A6 A5 A4 Vcc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Vss SDQ4 SDQ3 SE DQ4 DQ3 DSF CAS QSF A0 A1 A2 A3 A7 28-Pin SOJ 28-Pin LCC SC SDQ1 SDQ2 TR/OE DQ1 DQ2 ME/WE NC RAS A8 A6 A5 A4 Vcc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D E D N E NS M IG M - S I28-Pin O T Y FP E C SPECIAL FUNCTIONS D ABIL (F-12) E R E W VAIL T N ED A O N O R IMIT L OPTIONS F MARKING - * * * * Timing [DRAM, SAM (cycle/access)] 80ns, 30ns/25ns 100ns, 30ns/27ns 120ns, 35ns/35ns - 8 -10 -12 * Packages Ceramic SOJ Ceramic DIP (400 mil) Ceramic LCC Ceramic Flat Pack DCJ No. 500 C No. 109 EC No. 203 F No. 302 SC SDQ1 SDQ2 TR/OE DQ1 DQ2 ME/WE NC RAS A8 A6 A5 A4 Vcc 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Vss SDQ4 SDQ3 SE DQ4 DQ3 DSF CAS QSF A0 A1 A2 A3 A7 Vss SDQ4 SDQ3 SE DQ4 DQ3 DSF CAS QSF A0 A1 A2 A3 A7 The DRAM portion of the VRAM is functionally identical to the MT4C4256 (256K x 4 DRAM). Four 512-bit data registers make up the SAM portion of the VRAM. Data I/O and internal data transfer are accomplished using three separate bidirectional data paths; the 4-bit random access I/O port, the four internal 512 bit wide paths between the DRAM and the SAM, and the 4-bit serial I/O port for the SAM. The rest of the circuitry consists of the control, timing and address decoding logic. Each port may be operated asynchronously and independently of the other except when data is being transferred GENERAL DESCRIPTION The MT42C4256 883C is a high-speed, dual port CMOS dynamic random access memory or video RAM (VRAM) containing 1,048,576 bits. These bits may be accessed by a 4-bit wide DRAM port or a 512 x 4-bit serial access memory (SAM) port. Data may be transferred bidirectionally between the DRAM and the SAM. MT42C4256 883C REV. 3/97 DS000016 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 3-27 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice. MT42C4256 883C 256K x 4 VRAM AUSTIN SEMICONDUCTOR, INC. Limited Supply - Consult Factory internally. As with all DRAMs, the VRAM must be refreshed to maintain data. Refresh cycles must be timed so that all 512 combinations of /R/A/S addresses are executed at least every 8ms, (regardless of sequence). Micron recommends evenly spaced refresh cycles for maximum data integrity. An internal transfer between the DRAM and the SAM counts as a refresh cycle. The SAM portion of the VRAM is fully static and does not require any refresh. The operation and control of the MT42C4256 are optimized for high performance graphics and communication designs. The dual port architecture is well suited to buffering the sequential data used in raster graphics display, serial and parallel networking and data communications. Special features, such as SPLIT READ TRANSFER and BLOCK WRITE allow further enhancements to system performance. FUNCTIONAL BLOCK DIAGRAM COLUMN MASK 4 4 8 DQ1 512 M A S K SENSE AMPLIFIERS 512 WRITE CONTROL LOGIC DQ4 4 MUX 4 9 ROW DECODER ROW ADDRESS LATCH/BUFFER 9 512 SAM ADDRESS COUNTER 4 DRAM INPUT BUFFERS 4 512 x 512 x 4 DRAM ARRAY MASK DATA REGISTER 256 256 TRANSFER GATE LOWER SAM TRANSFER GATE UPPER SAM 256 256 SAM LOCATION DECODER SAM ADDRESS LATCH/BUFFER 4 MASKED WRITE CONTROL LOGIC BLOCK WRITE CONTROL LOGIC RAS CAS TR/OE ME/WE DSF SC SE TIMING GENERATOR & CONTROL LOGIC 4 9 REFRESH COUNTER 9 4 4 4 A0-A8 DRAM OUTPUT BUFFERS COLUMN DECODER COLOR REGISTER 9 COLUMN ADDRESS LATCH/BUFFER 4 TRANSFER CONTROL SAM OUTPUT BUFFERS 4 SAM INPUT BUFFERS 9 SDQ1 4 4 SDQ4 SPLIT SAM STATUS & CONTROL QSF MT42C4256 883C REV. 3/97 DS000016 3-28 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice. AUSTIN SEMICONDUCTOR, INC. MT42C4256 883C 256K x 4 VRAM Limited Supply - Consult Factory PIN DESCRIPTIONS PIN NUMBERS SYMBOL TYPE 1 SC Input Serial Clock: Clock input to the serial address counter for the SAM registers. 4 /T/R//O/E Input Transfer Enable: Enables an internal TRANSFER operation at /R/A/S (H > L), or DESCRIPTION Output Enable: Enables the DRAM output buffers when taken LOW after /R/A/S goes LOW (/C/A/S must also be LOW), otherwise the output buffers are in a High-Z state. 7 ?M/E/?W/E Input Mask Enable: If ?M/E/?W/E is LOW at the falling edge of /R/A/S a MASKED WRITE cycle is performed, or Write Enable: ?M/E/?W/E is also used to select a READ (??M/E/?W/E = H) or WRITE (??M/E/?W/E = L) cycle when accessing the DRAM. This includes a READ TRANSFER (??M/E/?W/E = H) or WRITE TRANSFER (??M/E/?W/E = L). 25 /S/E Input Serial Port Enable: /S/E enables the serial I/O buffers and allows a serial READ or WRITE operation to occur, otherwise the output buffers are in a High-Z state. /S/E is also used during a WRITE TRANSFER operation to indicate whether a WRITE TRANSFER or a SERIAL INPUT MODE ENABLE cycle is performed. 22 DSF Input Special Function Select: DSF is used to indicate which special functions (BLOCK WRITE, MASKED WRITE vs. PERSISTENT MASKED WRITE, etc.) are used on a particular access cycle. 9 /R/A/S Input Row Address Strobe: /R/A/S is used to clock-in the 9 row-address bits and strobe the ?M/E/?W/E, /T/R//O/E, DSF, /S/E, /C/A/S and DQ inputs. It also acts as the master chip enable and must fall for initiation of any DRAM or TRANSFER cycle. 21 /C/A/S Input Column Address Strobe: /C/A/S is used to clock-in the 9 columnaddress bits, enable the DRAM output buffers (along with /T/R/?O/E), and strobe the DSF input. 19, 18, 17, A0-A8 Input Address Inputs: For the DRAM operation, these inputs are multiplexed and clocked by /R/A/S and /C/A/S to select one 4-bit word out of the 256K available. During TRANSFER operations, A0 to A8 indicate the DRAM row being accessed (when /R/A/S goes LOW) and the SAM start address (when /C/A/S goes LOW). 5, 6, 23, 24 DQ1-DQ4 Input/ Output DRAM Data I/O: Data input/output for DRAM cycles; inputs for Mask Data Register and Color Register load cycles, and DQ and Column Mask inputs for BLOCK WRITE. 2, 3, 26, 27 SDQ1-SDQ4 Input/ Output Serial Data I/O: Input, output, or High-Z. 20 QSF Output Split SAM Status: QSF indicates which half of the SAM is being accessed. LOW if address is 0-255, HIGH if address is 256-511. 8 NC - No Connect: This pin should be left either unconnected or tied to ground. 14 VCC Supply Power Supply: +5V 10% 28 VSS Supply Ground MT42C4256 883C REV. 3/97 DS000016 3-29 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice. AUSTIN SEMICONDUCTOR, INC. MT42C4256 883C 256K x 4 VRAM Limited Supply - Consult Factory FUNCTIONAL DESCRIPTION The MT42C4256 may be divided into three functional blocks (see Figure 1): the DRAM, the transfer circuitry, and the SAM. All of the operations described below are shown in the AC Timing Diagrams section of this data sheet and summarized in the Truth Table. Note: The 18 address bits that are used to select a 4-bit word from the 262,144 available are latched into the chip using the A0-A8, /R/A/S and /C/A/S inputs. First, the 9 row-address bits are set up on the address inputs and clocked into the part when /R/A/S transitions from HIGH-to-LOW. Next, the 9 column address bits are set up on the address inputs and clocked-in when /C/A/S goes from HIGH-to-LOW. For dual-function pins, the function not being discussed will be surrounded by parentheses. For example, the /T/R//O/E pin will be shown as /T/R/(/O/E) in references to transfer operations. Note: DRAM OPERATION DRAM REFRESH Like any DRAM based memory, the MT42C4256 VRAM must be refreshed to retain data. All 512 row address combinations must be accessed within 8ms. The MT42C4256 supports /C/A/S-BEFORE-/R/A/S, /R/A/S-ONLY and HIDDEN types of refresh cycles. For the /C/A/S-BEFORE-/R/A/S REFRESH cycle, the row addresses are generated and stored in an internal address counter. The user need not supply any address data, and simply must perform 512 /C/A/S-BEFORE-/R/A/S cycles within the 8ms time period. The refresh address must be generated externally and applied to A0-A8 inputs for /R/A/S-ONLY refresh cycles. The DQ pins remain in a High-Z state for both the /R/A/S-ONLY and /C/A/S-BEFORE-/R/A/S refresh cycles. HIDDEN REFRESH cycles are performed by toggling /R/A/S (and keeping /C/A/S LOW) after a READ or WRITE cycle. This performs /C/A/S-BEFORE-/R/A/S cycles but does not disturb the DQ lines. Any DRAM READ, WRITE, or TRANSFER cycle also refreshes the DRAM row being accessed. The SAM portion of the MT42C4256 is fully static and does not require any refreshing. For single port DRAMS, the /O/E pin is a "don't care" when / /A/S goes LOW. However, for the VRAM, when /R/A/S goes R LOW, /T/R/(/O/E) selects between DRAM access or TRANSFER cycles. /T/R/(/O/E) must be HIGH at the /R/A/S HIGH-toLOW transition for all DRAM operations (except /C/A/SBEFORE-/RA / /S). If (?M/E)/?W/E is HIGH when /C/A/S goes LOW, a DRAM READ operation is performed and the data from the memory cells selected will appear at the DQ1-DQ4 port. The (/T/R)/ /O/E input must transition from HIGH-to-LOW some time after /R/A/S falls to enable the DRAM output port. For single port normal DRAMs, ?W/E is a "don't care" when /R/A/S goes LOW. For the VRAM, ?M/E/(?W/E) is used, when /R/A/S goes LOW, to select between a MASKED WRITE cycle and a normal WRITE cycle. If ?M/E/(?W/E) is LOW at the /R/A/S HIGH-to-LOW transition, a MASKED WRITE operation is selected. For any DRAM access cycle (READ or WRITE), ?M/E/(?W/E) must be HIGH at the /R/A/S HIGH-toLOW transition. If (?M/E)/?W/E is LOW before /C/A/S goes LOW, a DRAM EARLY-WRITE operation is performed and the data present on the DQ1-DQ4 data port will be written into the selected memory cells. If (?M/E)/?W/E goes LOW after /C/A/S goes LOW, a DRAM LATE-WRITE operation is performed. Refer to the AC timing diagrams. The VRAM can perform all the normal DRAM cycles including READ, EARLY-WRITE, LATE-WRITE, READ-MODIFY-WRITE, FAST-PAGE-MODE READ, FAST-PAGE-MODE WRITE (Late or Early), and FASTPAGE-MODE READ-MODIFY-WRITE. Refer to the AC timing parameters and diagrams in the data sheet for more details on these operations. DRAM READ AND WRITE CYCLES The DRAM portion of the VRAM is nearly identical to standard 256K x 4 DRAMs. However, because several of the DRAM control pins are used for additional functions on this part, several conditions that were undefined or in "don't care" states for the DRAM are specified for the VRAM. These conditions are highlighted in the following discussion. In addition, the VRAM has several special functions that can be used when writing to the DRAM. MT42C4256 883C REV. 3/97 DS000016 /R?A/S also acts as a "master" chip enable for the VRAM. If /R?A/S is inactive, HIGH, all other DRAM control pins (?C?A/S, /T/R/?O/E, ?M/E/?W/E, etc.) are "don't care" and may change state without effect. No DRAM or TRANSFER cycles will be initiated without /R?A/S falling. 3-30 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice. MT42C4256 883C 256K x 4 VRAM AUSTIN SEMICONDUCTOR, INC. Limited Supply - Consult Factory NONPERSISTENT MASKED WRITE The MASKED WRITE feature eliminates the need for a READ-MODIFY-WRITE cycle when changing only specific bits within a 4-bit word. The MT42C4256 supports two types of MASKED WRITE cycles, NONPERSISTENT MASKED WRITE and PERSISTENT MASKED WRITE. If ?M/E/(?W/E) and DSF are LOW at the /R/A/S HIGH-toLOW transition, a NONPERSISTENT MASKED WRITE is performed and the data (mask data) present on the DQ1DQ4 inputs will be written into the mask data register. The mask data acts as an individual write enable for each of the four DQ1-DQ4 pins. If a LOW (logic "0") is written to a mask data register bit, the input port for that bit is disabled during the subsequent WRITE operation and no new data will be written to that DRAM cell location. A HIGH (logic "1") on a mask data register bit enables the input port and allows normal WRITE operation to proceed. Note that /C/A/S is still HIGH. When /C/A/S goes LOW, the bits present on the DQ1-DQ4 inputs will be either written to the DRAM (if the mask data bit is HIGH) or ignored (if the mask data bit is LOW). The DRAM contents that correspond to masked input bits will not be changed during the WRITE cycle. The MASKED WRITE is nonpersistent (must be re-entered at every /R?A/S cycle) if DSF is LOW when /R?A/S goes LOW. The mask data register is cleared at the end of every NONPERSISTENT MASKED WRITE. FAST PAGE MODE can be used with NONPERSISTENT MASKED WRITE to write several column locations in an addressed row. The same mask is used during the entire FAST-PAGE-MODE /R/A/S cycle. An example NONPERSISTENT MASKED WRITE cycle is shown in Figure 1. NONPERSISTENT MASKED WRITE RAS CAS ME/WE DSF STORED DATA 1 1 0 0 BEFORE NONPERSISTENT MASKED WRITE , , , , , , , , , , , , , , , MASK INPUT 0 1 0 1 X 0 X 1 STORED STORED MASK DATA DATA (RE-WRITE) 1 0 0 0 0 1 0 0 0 1 0 1 AFTER BEFORE ADDRESS 0 STORED X 1 X 1 STORED DATA 0 1 0 1 AFTER ,, ADDRESS 1 X = NOT EFFECTIVE (DON'T CARE) DON'T CARE Figure 1 NONPERSISTENT MASKED WRITE EXAMPLE MT42C4256 883C REV. 3/97 DS000016 3-31 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice. MT42C4256 883C 256K x 4 VRAM AUSTIN SEMICONDUCTOR, INC. Limited Supply - Consult Factory PERSISTENT MASKED WRITE The PERSISTENT MASKED WRITE feature eliminates the need to rewrite the mask data before each MASKED WRITE cycle if the same mask data is being used repeatedly. To initiate a PERSISTENT MASKED WRITE, a LOAD MASK REGISTER cycle is performed by taking ?M/E/(?W/E) and DSF HIGH when /R/A/S goes LOW. The mask data is loaded into the internal register when /C/A/S goes LOW. PERSISTENT MASKED WRITE cycles may then be performed by taking ?M/E/(?W/E) LOW and DSF HIGH when /R/A/S goes LOW. The contents of the mask data register will then be used as the mask data for the DRAM inputs. Unlike the NONPERSISTENT MASKED WRITE cycle, the data present on the DQ inputs is not loaded into the mask LOAD MASK REGISTER register when /R/A/S falls, and the mask data register will not be cleared at the end of the cycle. Any number of PERSISTENT MASKED WRITE cycles, to any address, may be performed without having to reload the mask data register. Figure 2 shows the LOAD MASK REGISTER and two PERSISTENT MASKED WRITE cycles in operation. The LOAD MASK REGISTER and PERSISTENT MASKED WRITE cycles allow controllers that cannot provide mask data to the DQ pins at /R/A/S time to perform MASKED WRITE operations. PERSISTENT MASKED WRITE operations may be performed during FAST PAGE MODE cycles and the same mask will apply to all addressed columns in the addressed row. PERSISTENT MASKED WRITE PERSISTENT MASKED WRITE RAS CAS ME/WE DSF MASK 0 1 0 1 (Stored in Mask Data Register) STORED DATA 1 1 0 0 BEFORE INPUT APPLY MASK REG. X 0 X 1 STORED DATA 1 0 0 1 AFTER STORED DATA 0 0 0 0 BEFORE ADDRESS 0 INPUT APPLY MASK REG. X 1 X 1 STORED DATA 0 1 0 1 AFTER ADDRESS 1 X = NOT EFFECTIVE (DON'T CARE) Figure 2 PERSISTENT MASKED WRITE EXAMPLE MT42C4256 883C REV. 3/97 DS000016 3-32 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice. AUSTIN SEMICONDUCTOR, INC. MT42C4256 883C 256K x 4 VRAM Limited Supply - Consult Factory COLUMN (A2-A8 at CAS) ROW (A0-A8 at RAS) DQ1 COLUMN MASK (A0,A1) ON THE DQ INPUTS AT CAS DQ2 DQ3 DQ4 CAS (DQ1) (DQ2) (DQ3) (DQ4) D1 MASK DATA REGISTER D2 D3 D4 4 MUX 4 DQ1 DQ2 DQ3 RAS * DSF DQ4 RAS LOAD COLOR REGISTER COLOR REGISTER (must be previously loaded) Figure 3 BLOCK WRITE EXAMPLE BLOCK WRITE If DSF is HIGH when /C/A/S goes LOW, the MT42C4256 will perform a BLOCK WRITE cycle instead of a normal WRITE cycle. In BLOCK WRITE cycles, the contents of the color register are directly written to four adjacent column locations (see Figure 3). The color register must be loaded prior to beginning BLOCK WRITE cycles (see LOAD COLOR REGISTER). Each DQ location of the color register is written to the four column locations (or any of the four that are enabled) in the corresponding DQ bit plane. The row is addressed as in a normal DRAM WRITE cycle. MT42C4256 883C REV. 3/97 DS000016 However, when /C/A/S goes LOW only the A2-A8 inputs are used. A2-A8 specify the "block" of four adjacent column locations that will be accessed. The DQ inputs are then used to determine what combination of the four column locations will be changed. DQ1 acts as a write enable for column location A0 = 0, A1 = 0; DQ2 controls column location A0 = 1, A1 = 0; DQ3 controls A0 = 0, A1 = 1; and DQ4 controls A0 = 1, A1 = 1. The write enable controls are active HIGH; the WRITE function is enabled by a logic 1 and disabled by a logic 0. 3-33 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice. AUSTIN SEMICONDUCTOR, INC. MT42C4256 883C 256K x 4 VRAM Limited Supply - Consult Factory NONPERSISTENT MASKED BLOCK WRITE The MASKED WRITE functions can also be used during BLOCK WRITE cycles. NONPERSISTENT MASKED BLOCK WRITE operates exactly like the normal NONPERSISTENT MASKED WRITE, except that the mask is now applied to four column locations instead of just one. Like NONPERSISTENT MASKED WRITE, the combination of ?M/E/(?W/E) LOW and DSF LOW when /R/A/S goes LOW initiates a NONPERSISTENT MASKED cycle. The DSF pin must be driven HIGH when /C/A/S goes LOW, to perform the NONPERSISTENT MASKED BLOCK WRITE. By using both the column mask input and the MASKED WRITE function, any combination of the four bit planes or column locations may be masked. TER cycle. DSF is used when /C/A/S goes LOW to select the register to be loaded and must be LOW for a LOAD MASK REGISTER cycle. The data present on the DQ lines will then be written to the mask data register. Note: The row address supplied will be refreshed, but it is not necessary to provide any particular row address. The column address inputs are ignored during a LOAD MASK REGISTER cycle. The mask data register contents are used during PERSISTENT MASKED WRITE and PERSISTENT MASKED BLOCK WRITE cycles to selectively enable writes to the four DQ planes. PERSISTENT MASKED BLOCK WRITE This cycle is also performed exactly like the normal PERSISTENT MASKED WRITE except that DSF is HIGH when /C/A/S goes LOW to indicate the BLOCK WRITE function. Both the mask data register and the color register must be loaded with the appropriate data prior to starting a PERSISTENT MASKED BLOCK WRITE. LOAD COLOR REGISTER A LOAD COLOR REGISTER cycle is identical to the LOAD MASK REGISTER cycle except DSF is HIGH when /C/A/S goes LOW. The contents of the color register are retained until changed by another LOAD COLOR REGISTER cycle (or the part loses power) and are used as data inputs during BLOCK WRITE cycles. LOAD MASK DATA REGISTER The LOAD MASK REGISTER operation and timing are identical to a normal WRITE cycle except that DSF is HIGH when /R/A/S goes LOW. As shown in the Truth Table, the combination of /T/R/(/O/E), ?M/E/(?W/E), and DSF being HIGH when /R/A/S goes LOW indicates the cycle is a LOAD REGIS- MT42C4256 883C REV. 3/97 DS000016 For a normal DRAM WRITE cycle, the mask data register is disabled but not modified. The contents of mask data register will not be changed unless a NONPERSISTENT MASKED WRITE cycle or a LOAD MASK REGISTER cycle is performed. 3-34 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice. MT42C4256 883C 256K x 4 VRAM AUSTIN SEMICONDUCTOR, INC. Limited Supply - Consult Factory TRANSFER OPERATIONS TRANSFER operations are initiated when /T/R/(/O/E) is LOW then /R/A/S goes LOW. The state of (?M/E)/?W/E when /R/A/S goes LOW indicates the direction of the TRANSFER (to or from the DRAM), and DSF is used to select between NORMAL TRANSFER, SPLIT READ TRANSFER, and ALTERNATE WRITE TRANSFER cycles. Each of the TRANSFER cycles available is described below. with SC (REAL-TIME READ TRANSFER), /T/R/(?O/E) is taken HIGH after ?/C/A/S goes LOW. If the transfer does not have to be synchronized with SC (READ TRANSFER), /T/R/ (?O/E) may go HIGH before ?C/A/S goes LOW (refer to the AC Timing Diagrams). The 2,048 bits of DRAM data are written into the SAM data registers and the serial shift start address is stored in an internal 9-bit register. QSF will be LOW if access is from the lower half (addresses 0 through 255), and HIGH if access is from the upper half (256 through 511). If /S/E is LOW, the first bits of the new row data will appear at the serial outputs with the first SC clock pulse. /S/E enables the serial outputs and may be either HIGH or LOW during this operation. The SAM address pointer will increment with the SC LOW-to-HIGH transition, regardless of the state of /S/E. Performing a READ TRANSFER cycle sets the direction of the SAM I/O buffers to the output mode. READ TRANSFER (DRAM-TO-SAM TRANSFER) If (?M/E)/?W/E is HIGH and DSF is LOW when /R/A/S goes LOW, a READ TRANSFER cycle is selected. The row address bits indicate the four 512-bit DRAM row planes that are to be transferred to the four SAM data register planes. The column address bits indicate the start address (or Tap address) of the serial output cycle from the SAM data registers. /C?A/S must fall for every TRANSFER in order to load a valid Tap address. A read transfer may be accomplished in two ways. If the transfer is to be synchronized , , , , , , , ,,, ,, ,,,, ,,, , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , ,, ,, , ,, ,, ,, , ,, , ,, ,,,,,,,,,,,,,,,,,,,,,, , , , , , ,, RAS CAS A0-A8 ROW 0 A0-A7 = TAP A8 = X ROW 0 A0-A8 = 0 A0-A7 = TAP A8 = X ROW 1 ME/WE TR/OE DSF ,,,, ,,,, SC SDQ Output 0 ROW 0 1 7 8 9 ROW 0 255 260 ROW 0 319 320 321 ROW 0 QSF (NORMAL) READ TRANSFER SPLIT READ TRANSFER (OPTIONAL) FROM: ROW 0 TO: FULL SAM, SAM I/O IS SET TO OUTPUT MODE AND SERIAL OUTPUT FROM LOWER SAM BEGINS (QSF GOES LOW) FROM: ROW 0 TO: UPPER SAM, TAP ADDRESS = 4 SERIAL OUTPUT FROM LOWER SAM CONTINUES SPLIT READ TRANSFER SERIAL OUTPUT SWITCHES FROM LOWER SAM TO UPPER SAM (QSF GOES HIGH) ,,, FROM: ROW 1 TO: LOWER SAM, TAP ADDRESS = 0 TO 255 SERIAL OUTPUT FROM UPPER SAM CONTINUES (QSF REMAINS HIGH) , DON'T CARE UNDEFINED Figure 4 TYPICAL SPLIT-READ-TRANSFER INITIATION SEQUENCE MT42C4256 883C REV. 3/97 DS000016 3-35 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice. MT42C4256 883C 256K x 4 VRAM AUSTIN SEMICONDUCTOR, INC. Limited Supply - Consult Factory SPLIT READ TRANSFER (SPLIT DRAM-TO-SAM TRANSFER) The SPLIT READ TRANSFER (SRT) cycle eliminates the critical transfer timing required to maintain a continuous serial output data stream. When using normal TRANSFER cycles, the REAL-TIME READ TRANSFER cycle has to occur immediately after the last bit of "old data" was clocked out of the SAM port. When using the SPLIT TRANSFER mode, the SAM is divided into an upper half and a lower half. While data is being serially read from one half of the SAM, new DRAM data may be transferred to the other half. The transfer may occur at any time while the other half is sending data and need not be synchronized with the SC clock. The / T / R /(? O / E ) timing is also relaxed for SPLIT TRANSFER cycles. The rising edge of /T/R/(/O/E) is not used to complete the TRANSFER cycle and therefore is independent of the rising edges of /R/A/S or /C/A/S. The transfer timing is generated internally for SPLIT TRANSFER cycles. A SPLIT READ TRANSFER does not change the direction of the SAM port. A normal, non-split READ TRANSFER cycle must precede any sequence of SPLIT READ TRANSFER cycles to set SAM I/O direction and provide a reference to which half of the SAM the access will begin. Then SPLIT READ TRANSFERS may be initiated by taking DSF HIGH when /R/A/S goes LOW during the TRANSFER cycle. As in nonsplit transfers, the row address is used to specify the DRAM row to be transferred. The column address, A0-A7, is used to input the SAM Tap address. Address pin A8 is a "don't care" when the Tap address is loaded at the HIGH-to-LOW transition of ?C/A/S. It is internally generated so that the SPLIT TRANSFER will be to the SAM half not currently being accessed. Figure 4 shows a typical SPLIT READ TRANSFER initiation sequence. The normal READ TRANSFER is first performed, followed by a SPLIT READ TRANSFER of the same row to the upper half of the SAM. The SRT to the upper half is optional and need only be done if the Tap for the upper half is 0. Serial access continues, and when the SAM address counter reaches 255 ("A8" = 0, A0-A7 = 1), the new Tap address is loaded for the next half ("A8" = 1, A0-A7 = Tap) and the QSF output goes HIGH. Once the serial access has switched to the upper SAM, new data may be transferred to the lower SAM. The controller must wait for the state of QSF to change and then the new data may be transferred to the SAM half not being accessed. For example, the next step in Figure 4 would be to wait until QSF went LOW (indicating that row-1 data is shifting out of the lower SAM) and then transfer the upper half of row 1 to the upper SAM. If the half boundary is reached before an SRT is done for the next half a Tap address of "0" will be used. Access will start at 0 if going to the lower half, or 256 if going to the upper half. See Figure 5. WRITE TRANSFER (SAM-TO-DRAM TRANSFER) The operation of the WRITE TRANSFER is identical to the READ TRANSFER described previously except (?M/E)/?W/E and /S/E must be LOW when /R/A/S goes LOW. The row address indicates the DRAM row to which the SAM data registers will be written. The column address (Tap) indicates the starting address of the next SERIAL INPUT cycle for the SAM data registers. A WRITE TRANSFER changes the direction of the SAM I/O buffers to the input mode. QFS is LOW if access is to the lower half of the SAM, and HIGH if access is to the upper half. LOWER HALF UPPER HALF NO SRT 0 TAP NO SRT 255 256 511 Start Split Figure 5 SPLIT SAM TRANSFER MT42C4256 883C REV. 3/97 DS000016 3-36 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice. AUSTIN SEMICONDUCTOR, INC. MT42C4256 883C 256K x 4 VRAM Limited Supply - Consult Factory PSEUDO WRITE TRANSFER (SERIAL-INPUT-MODE ENABLE) The PSEUDO WRITE TRANSFER cycle is used to change the direction of SAM port from output to input without performing a WRITE TRANSFER cycle. A PSEUDO WRITE TRANSFER cycle is a WRITE TRANSFER cycle with /S/E held HIGH instead of LOW. The DRAM data will not be disturbed and the SAM will be ready to accept input data. and will wrap around (after count 255 or 511) to the Tap address of the next half for split modes. If an SRT was not performed before the half boundary is reached the count will progress as illustrated in Figure 5. Address count will wrap around (after count 511) to Tap address 0 if in the "full" SAM modes. SC is also used to clock-in data when the device is in the serial input mode. As in the serial output operation, the contents of the SAM address counter (loaded when the serial input mode was enabled) will determine the serial address of the first 4-bit word written. /S/E acts as a write enable for serial input data and must be LOW for valid serial input. If /S/E = HIGH, the data inputs are disabled and the SAM contents will not be modified. The serial address counter is incremented with every LOW-to-HIGH transition of SC, regardless of the logic level on the /S/E input. ALTERNATE WRITE TRANSFER (SAM-TO-DRAM TRANSFER) The operation of the ALTERNATE WRITE TRANSFER is identical to the WRITE TRANSFER except that the DSF pin is HIGH and (?M/E)/?W/E is LOW when /R?A/S goes LOW, allowing /S/E to be a "don't care." This allows the outputs to be disabled using /S/E during a WRITE TRANSFER cycle. ALTERNATE WRITE TRANSFER will change the SAM I/ O direction to an input condition. SERIAL INPUT AND SERIAL OUTPUT The control inputs for SERIAL INPUT and SERIAL OUTPUT are SC and /S/E. The rising edge of SC increments the serial address counter and provides access to the next SAM location. /S/E enables or disables the serial input/output buffers. Serial output of the SAM contents will start at the serial start address that was loaded in the SAM address counter during a READ or SPLIT READ TRANSFER cycle. The SC input increments the address counter and presents the contents of the next SAM location to the 4-bit port. /S/E is used as an output enable during the SAM output operation. The serial address is automatically incremented with every SC LOW-to-HIGH transition, regardless of whether /S/E is HIGH or LOW. The address progresses through the SAM MT42C4256 883C REV. 3/97 DS000016 POWER-UP AND INITIALIZATION After Vcc is at specified operating conditions, for 100s minimum, eight /R/A/S cycles must be executed to initialize the dynamic memory array. Micron recommends that /R?A/S = (/T/R)/?O/E VIH during power up to ensure that the DRAM I/O pins (DQs) are in a High-Z state. The DRAM array will contain random data. The SAM portion of the MT42C4256 is completely static in operation and does not require refresh or initialization. The SAM port will power-up in the serial input mode (WRITE TRANSFER) and the I/O pins (SDQs) will be High-Z, regardless of the state of /S/E. The mask and color register will contain random data after power-up. QSF initializes in the LOW state. 3-37 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice. MT42C4256 883C 256K x 4 VRAM AUSTIN SEMICONDUCTOR, INC. Limited Supply - Consult Factory CODE /R/A/S FALLING EDGE FUNCTION C / A / S / FALL A0 - A81 DQ1 - DQ42 CAS /T/R//O/E /M/E//W/E DSF /S/E DSDF /R/A/S /C/A/S /R/A/S /C/A/S3 /W/E REGISTERS MASK COLOR DRAM OPERATIONS CBR CAS-BEFORE-RAS REFRESH 0 X 1 X X X - X - X X X ROR RAS-ONLY REFRESH 1 1 X X X - ROW - X - X X RW NORMAL DRAM READ OR WRITE 1 1 1 0 X 0 ROW COLUMN X DATA X X 1 1 0 0 X 0 ROW COLUMN WRITE DATA LOAD & X RWNM NONPERSISTANT (LOAD AND USE) MASKED WRITE TO DRAM RWOM PERSISTENT (USE REGISTER) MASKED WRITE TO DRAM BW BLOCK WRITE TO DRAM (NO DATA MASK) MASK 1 1 0 1 X 0 ROW COLUMN X DATA USE X 1 1 1 0 X 1 ROW COLUMN X COLUMN X USE (A2 - A8) BWMN NO PERSISTENT (LOAD & USE) MASKED 1 1 0 0 X 1 ROW 1 1 0 1 X 1 ROW WRITE TO DRAM MASK COLUMN WRITE COLUMN LOAD & BLOCK WRITE TO DRAM BWOM PERSISTENT (USE MASKED REGISTER) MASKED BLOCK USE COLUMN USE MASK MASK USE X COLUMN USE USE LOAD X X LOAD (A2 - A8) MASK REGISTER OPERATIONS LMR LOAD MASK REGISTER 1 1 1 1 X 0 ROW4 X X WRITE MASK LCR LOAD COLOR REGISTER 1 1 1 1 X 1 ROW4 X X COLOR DATA TRANSFER OPERATIONS RT READ TRANSFER (DRAM-TO-SAM TRANSFER 1 0 1 0 X X ROW TAP5 X X X X SRT SPLIT READ TRANSFER (SPILT DRAM-TO-SAM TRANSFER) 1 0 1 1 X X ROW TAP5 X X X X WT WRITE TRANSFER (SAM-TO-DRAM TRANSFER) 1 0 0 0 0 X ROW TAP5 X X X X PWT PSEUDO WRITE TRANSFER (SERIAL-INPUT-MODE ENABLE) 1 0 0 0 1 X ROW4 TAP5 X X X X ALTERNATE WRITE TRANSFER 1 0 0 1 X X ROW TAP5 X X X X AWT (SAM-TO-DRAM TRANSFER) NOTE: MT42C4256 883C REV. 3/97 DS000016 1. These columns show what must be present on the A0-A8 inputs when /R/A/S falls and when /C/A/S falls. 2. These columns show what must be present on the DQ1-DQ4 inputs when /R/A/S falls and when /C/A/S falls. 3. On WRITE cycles (except BLOCK WRITE), the input data is latched at the falling edge of /C/A/S or ?M/E/?W/E, whichever is later. Similarly, on READ cycles, the output data is activated at the falling edge of /C/A/S or /T/R//O/E, whichever is later. 4. The ROW that is addressed will be refreshed, but no particular ROW address is required. 5. This is the SAM location that the first SC cycle will access. For split SAM transfers, the Tap will be the first address location accessed of the "new" SAM half after the boundary of the current half is reached (255 for lower half, 511 for upper half). 3-38 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice. MT42C4256 883C 256K x 4 VRAM AUSTIN SEMICONDUCTOR, INC. Limited Supply - Consult Factory *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. ABSOLUTE MAXIMUM RATINGS* Voltage on Vcc Supply Relative to Vss .............. -1V to +7V Operating Temperature, TA (Ambient) ..... 55C to +125C Storage Temperature (Plastic) .................... -65C to +150C Power Dissipation ............................................................. 1W Short Circuit Output Current ..................................... 50mA Lead Temperature (soldering 10 seconds) .............. +300C Junction Temperature ............................................... +165C RECOMMENDED DC OPERATING CONDITIONS (-55C TA 125C) PARAMETER/CONDITION SYMBOL MIN MAX UNITS Supply Voltage VCC 4.5 5.5 V NOTES 1 Input High (Logic 1) Voltage, All Inputs VIH 2.4 VCC+.5 V 1 Input Low (Logic 0) Voltage, All Inputs VIL -.5 0.8 V 1 NOTES DC ELECTRICAL CHARACTERISTICS (-55C TA 125C; VCC = 5V 10%) PARAMETER/CONDITION SYMBOL MIN MAX UNITS INPUT LEAKAGE CURRENT Any input (0V VIN VCC); all other pins not under test = 0V IL -5 5 A OUTPUT LEAKAGE CURRENT (DQ, SDQ disabled, 0V VOUT VCC) IOZ -5 5 A OUTPUT LEVELS Output High Voltage (IOUT = -2.5mA) Output Low Voltage (IOUT = 2.5mA) VOH 2.4 V 1 VOL 0.5 V CAPACITANCE PARAMETER MAX UNITS NOTES Input Capacitance: A0-A8 CI1 7 pF 2 Input Capacitance: /R/A/S, /C/A/S, ?M/E/?W/E, /T/R//O/E, SC, /S/E, DSF CI2 7 pF 2 Input/Output Capacitance: DQ, SDQ CI/O 7 pF 2 Output Capacitance: QSF CO 9 pF 2 MT42C4256 883C REV. 3/97 DS000016 SYMBOL 3-39 MIN Austin Semiconductor, Inc., reserves the right to change products or specifications without notice. MT42C4256 883C 256K x 4 VRAM AUSTIN SEMICONDUCTOR, INC. Limited Supply - Consult Factory CURRENT DRAIN, SAM IN STANDBY (-55C TA 125C; VCC = 5V 10%) SYMBOL -8 MAX -10 -12 OPERATING CURRENT (/R/A/S and /C/A/S = Cycling: tRC = tRC (MIN)) ICC1 95 90 80 mA 3, 4 26 OPERATING CURRENT: FAST PAGE MODE (/R/A/S = VIL; /C/A/S = Cycling: tPC = tPC (MIN)) ICC2 85 75 65 mA 3, 4 27 ICC3 8 8 8 mA 4 REFRESH CURRENT: /R/A/S-ONLY (/R/A/S = Cycling; /C/A/S = VIH) ICC4 95 90 80 mA 3, 26 REFRESH CURRENT: ?C/A/S-BEFORE-/R/A/S (/R/A/S and /C/A/S = Cycling) ICC5 95 90 80 mA 3, 5 SAM/DRAM DATA TRANSFER ICC6 105 95 95 mA 3 SYMBOL -8 -10 -12 OPERATING CURRENT (/R/A/S and /C/A/S = Cycling: tRC = tRC (MIN)) ICC7 150 130 120 mA 3, 4, 26 OPERATING CURRENT: FAST PAGE MODE (/R/A/S = VIL; /C/A/S = Cycling: tPC = tPC (MIN)) ICC8 140 120 110 mA 3, 4, 27 ICC9 35 30 25 mA 3, 4 REFRESH CURRENT: /R/A/S-ONLY (/R/A/S = Cycling; /C/A/S = VIH) ICC10 150 130 120 mA 3, 4, 26 REFRESH CURRENT: ?C/A/S-BEFORE-/R/A/S (/R/A/S and /C/A/S = Cycling) ICC11 150 130 120 mA 3, 4, 5 SAM/DRAM DATA TRANSFER ICC12 160 130 125 mA PARAMETER/CONDITION STANDBY CURRENT: TTL INPUT LEVELS Power supply standby current (/R/A/S = /C/A/S = VIH after 8 /R/A/S cycles (MIN), other inputs VIH or VIL) UNITS NOTES CURRENT DRAIN, SAM ACTIVE ( tSC = MIN) (-55C TA 125C; VCC = 5V 10%) MAX PARAMETER/CONDITION STANDBY CURRENT: TTL INPUT LEVELS Power supply standby current (/R/A/S = /C/A/S = VIH after 8 /R/A/S cycles (MIN), other inputs VIH or VIL) MT42C4256 883C REV. 3/97 DS000016 3-40 UNITS NOTES 3, 4 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice. MT42C4256 883C 256K x 4 VRAM AUSTIN SEMICONDUCTOR, INC. Limited Supply - Consult Factory DRAM TIMING PARAMETERS ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Notes: 6, 7, 8, 9, 10, 11, 12, 13) (-55C TA +125C; VCC = 5V 10%) AC CHARACTERISTICS PARAMETER Random READ or WRITE cycle time READ-MODIFY-WRITE cycle time FAST-PAGE-MODE READ or WRITE cycle time FAST-PAGE-MODE READ-MODIFY-WRITE cycle time Access time from /R/A/S Access time from /C/A/S Access time from (/T/R)//O/E Access time from column address Access time from /C/A/S precharge /R/A/S pulse width /R/A/S pulse width (FAST PAGE MODE) /R/A/S hold time /R/A/S precharge time /C/A/S pulse width /C/A/S hold time /C/A/S precharge time /R/A/S to /C/A/S delay time /C/A/S to /R/A/S precharge time Row address setup time Row address hold time /R/A/S to column address delay time Column address setup time Column address hold time Column address hold time (referenced to /R/A/S) Column address to /R/A/S lead time Read command setup time Read command hold time (referenced to /C/A/S) Read command hold time (referenced to /R/A/S) -8 SYM tRC tRWC tPC MIN 150 195 45 tPRWC 90 tRAC tCAC tOE tAA tCPA tRAS tRASP tRSH tRP tCAS tCSH tCP tRCD tCRP tASR tRAH tRAD tASC MIN 180 235 55 -12 MAX 110 80 20 20 40 45 20,000 100,000 10,000 60 40 100 100 25 70 25 100 12 25 5 0 15 20 MIN 210 275 65 MAX 130 100 25 25 50 50 20,000 100,000 10,000 75 50 100 100 30 80 30 120 15 25 10 0 15 20 UNITS NOTES ns ns ns ns 120 30 30 60 50 20,000 100,000 10,000 90 60 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 14 15 17 18 tAR 0 15 60 0 20 70 0 20 80 ns ns ns tRAL 40 50 60 ns tRCS tRCH 0 0 0 0 0 0 ns ns 19 tRRH 0 0 0 ns 19 tCLZ 0 0 ns ns 20, 23 tCAH /C/A/S to output in Low-Z Output buffer turn-off delay tOFF Output disable Output disable hold time from start of WRITE ?O/E LOW to /R/A/S HIGH delay time tOEH MT42C4256 883C REV. 3/97 DS000016 80 80 20 60 20 80 10 20 5 0 10 15 -10 MAX tOD tROH 0 20 0 3-41 20 20 0 0 0 20 0 20 20 0 0 0 25 0 20 25 ns ns ns 20, 23 25 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice. MT42C4256 883C 256K x 4 VRAM AUSTIN SEMICONDUCTOR, INC. Limited Supply - Consult Factory DRAM TIMING PARAMETERS (continued) ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Notes: 6, 7, 8, 9, 10, 11, 12, 13) (-55C TA +125C; VCC = 5V 10%) AC CHARACTERISTICS PARAMETER Write command setup time Write command hold time Write command hold time (referenced to /R/A/S) Write command pulse width Write command to /R/A/S lead time Write command to /C/A/S lead time Data-in setup time Data-in hold time Data-in hold time (referenced to /R/A/S) -8 -10 MIN 0 15 60 tWP 15 20 20 0 15 60 20 25 25 0 20 70 25 30 30 0 25 80 ns ns ns ns ns ns 105 65 125 75 150 90 ns ns 21 21 21 9, 10 5 tRWL tCWL tDS tDH tDHR MAX MIN 0 20 70 -12 SYM tWCS tWCH tWCR MAX MIN 0 25 80 MAX UNITS NOTES ns 21 ns ns /R/A/S to ?W/E delay time Column address to ?W/E delay time tRWD /C/A/S to ?W/E delay time Transition time (rise or fall) Refresh period (512 cycles) /R/A/S to /C/A/S precharge time /C/A/S setup time (/C/A/S-BEFORE-/R/A/S REFRESH) tCWD tCSR 0 10 0 10 0 10 ns ns ms ns ns /C/A/S hold time (/C/A/S-BEFORE-/R/A/S REFRESH) tCHR 15 20 25 ns tWSR 0 15 0 15 0 15 0 15 0 15 0 15 ns ns ns ns ?M/E/?W/E to /R/A/S setup time ?M/E/?W/E to /R/A/S hold time Mask Data to /R/A/S setup time Mask Data to /R/A/S hold time MT42C4256 883C REV. 3/97 DS000016 tAWD tT 45 3 tREF tRPC tRWH tMS tMH 3-42 50 8 50 3 50 8 60 3 50 8 22 22 5 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice. MT42C4256 883C 256K x 4 VRAM AUSTIN SEMICONDUCTOR, INC. Limited Supply - Consult Factory TRANSFER AND MODE CONTROL TIMING PARAMETERS ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Notes 6, 7, 8, 9, 10) (-55 C TA +125C; VCC = 5V 10%) AC CHARACTERISTICS PARAMETER /T/R/(?O/E) LOW to /R/A/S setup time /T/R/(?O/E) LOW to /R/A/S hold time /T/R/(?O/E) LOW to /R/A/S hold time (REAL-TIME READ TRANSFER only) -8 -10 MIN 0 10 75 tCTH 25 25 30 ns tTSL tTSD 5 60 20 15 5 70 30 15 5 80 35 15 ns ns ns ns Serial output buffer turn-off delay from /R/A/S tSDZ 7 SC to /R/A/S setup time Serial data input to /S/E delay time Serial data input delay from /R/A/S Serial data input to /R/A/S delay time Serial-input-mode enable (/S/E) to /R/A/S setup time tSRS tESR 30 0 50 0 0 35 0 50 0 0 40 0 55 0 0 ns ns ns ns ns tREH 10 15 15 ns tYS 0 10 0 10 0 15 0 15 0 15 0 15 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns /T/R/(?O/E) LOW to /C/A/S hold time (REAL-TIME READ TRANSFER only) /T/R/(?O/E) HIGH to SC lead time /T/R/(?O/E) HIGH to /R/A/S precharge time /T/R/(?O/E) precharge time First SC edge to /T/R/(?O/E) HIGH delay time Serial-input-mode enable (/S/E) to /R/A/S hold time /T/R/(?O/E) HIGH to /R/A/S setup time /T/R/(?O/E) HIGH to /R/A/S hold time DSF to /R/A/S setup time DSF to /R/A/S hold time SC to QSF delay time SPLIT TRANSFER setup time SPLIT TRANSFER hold time /R/A/S to QSF delay time DSF to /R/A/S hold time DSF to /C/A/S setup time DSF to /C/A/S hold time /T/R/?O/E to QSF delay time /C/A/S to QSF delay time /R/A/S to first SC delay /C/A/S to first SC delay MT42C4256 883C REV. 3/97 DS000016 tTRP tTRW tSZE tSDD tSZS tYH tFSR tRFH tSQD tSTS tSTH tFSC tCFH 7 40 7 10,000 10,000 40 30 75 75 80 0 25 30 40 100 40 MAX 30 0 70 0 20 30 40 3-43 10,000 10,000 MIN 0 15 90 30 75 85 30 MAX 30 0 60 0 15 tTQD tCSD 40 MIN 0 15 80 30 tCQD tRSD 10,000 10,000 30 0 tRQD tFHR MAX -12 SYM tTLS tTLH tRTH 30 40 115 45 UNITS NOTES ns ns ns ns Austin Semiconductor, Inc., reserves the right to change products or specifications without notice. MT42C4256 883C 256K x 4 VRAM AUSTIN SEMICONDUCTOR, INC. Limited Supply - Consult Factory SAM TIMING PARAMETERS ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Notes 6, 7, 8, 9, 10) (-55 C TA +125C; VCC = 5V 10%) AC CHARACTERISTICS PARAMETER Serial clock-cycle time Access time from SC SC precharge time (SC LOW time) SC pulse width (SC HIGH time) Access time from /S/E /S/E precharge time /S/E pulse width Serial data-out hold time after SC high Serial output buffer turn-off delay from /S/E -8 SYM tSC tSAC tSP tSAS tSEA tSEP tSE tSOH MIN 25 tSEZ 0 -10 MAX MIN 30 25 10 10 -12 MAX 30 10 10 20 7 10 0 35 25 0 MAX 10 10 10 15 0 15 MIN 35 30 15 15 0 15 0 15 UNITS NOTES ns ns 24, 28 ns ns ns 24 ns ns ns 24, 28 ns Serial data-in setup time tSDS 0 0 0 ns Serial data-in hold time Serial input (Write) Enable setup time tSDH tSWS 10 0 15 0 20 0 ns ns Serial input (Write) Enable hold time tSWH 15 20 25 ns Serial input (Write) disable setup time tSWIS 0 0 0 ns Serial input (Write) disable hold time tSWIH 15 20 25 ns MT42C4256 883C REV. 3/97 DS000016 3-44 20, 24 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice. AUSTIN SEMICONDUCTOR, INC. MT42C4256 883C 256K x 4 VRAM Limited Supply - Consult Factory NOTES 19. Either tRCH or tRRH must be satisfied for a READ cycle. 20. tOD, tOFF and tSEZ define the time when the output achieves open circuit (VOH -200mV, VOL +200mV). This parameter is sampled and not 100 percent tested. 21. tWCS, tRWD, tAWD and tCWD are restrictive operating parameters in LATE-WRITE, READ-WRITE and READ-MODIFY-WRITE cycles only. If tWCS tWCS (MIN), the cycle is an EARLY-WRITE cycle and the data output will remain an open circuit throughout the entire cycle, regardless of /T/R/?O/E. If tWCS tWCS (MIN), the cycle is a LATE-WRITE and /T/R/?O/E must control the output buffers during the WRITE to avoid data contention. If tRWD tRWD (MIN), tAWD tAWD (MIN) and tCWD tCWD (MIN), the cycle is a READ-WRITE and the data output will contain data read from the selected cell. If neither of the above conditions is met, the state of the output buffers (at access time and until /C/A/S goes back to VIH) is indeterminate but the WRITE will be valid, if tOD and tOEH are met. See the LATE-WRITE AC Timing diagram. 22. These parameters are referenced to /C/A/S leading edge in EARLY-WRITE cycles and ?M/E/?W/E leading edge in LATE-WRITE or READ-WRITE cycles. 23. During a READ cycle, if /T/R//O/E is LOW then taken HIGH, DQ goes open. The DQs will go open with /O/E or /C/A/S, whichever goes HIGH first. 24. SAM output timing is measured with a load equivalent to 1 TTL gate and 30pF. Output reference levels: VOH = 2.0V; VOL = 0.8V. 25. tOD and tOEH must be met in LATE-WRITE and READ-MODIFY-WRITE cycles (/O/E HIGH during WRITE cycle) in order to ensure that the output buffers will be open during the WRITE cycle. The DQs will provide previously read data if /C/A/S remains LOW and /O/E is taken LOW after tOEH is met. If /C/A/S goes HIGH prior to /O/E going back LOW, the DQs will remain open. 26. Address (A0-A8) may be changed two times or less while /R?A/S = VIL. 27. Address (A0-A8) may be changed once or less while /C?A/S = VIH and /R?A/S = VIL. 28. tSAC is MAX at +125C and 4.5V Vcc; tSOH is MIN at -55C and 5.5V Vcc. These limits will not occur simultaneously at any given voltage or temperature. tSOH = tSAC - output transition time; this is guaranteed by design. 1. 2. 3. 4. All voltages referenced to VSS. This parameter is sampled. VCC = 5V 10%, f = 1 MHz. ICC is dependent on cycle rates. ICC is dependent on I/O loading. Specified values are obtained with minimum cycle time and the I/Os open. 5. Enables on-chip refresh and address counters. 6. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (-55C TA +125C) is assured. 7. An initial pause of 100s is required after power-up followed by any eight /R/A/S cycles before proper device operation is assured. The eight /R/A/S cycle wake-up should be repeated any time the tREF refresh requirement is exceeded. 8. AC characteristics assume tT = 5ns. 9. VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL (or between VIL and VIH). Input signals transition between 0V and 3V for AC testing. 10. In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 11. If /C/A/S = VIH, DRAM data output (DQ1-DQ4) is High-Z. 12. If /C/A/S = VIL, DRAM data output (DQ1-DQ4) may contain data from the last valid READ cycle. 13. DRAM output timing measured with a load equivalent to 2 TTL gates and 100pF. Output reference levels: VOH = 2.0V; VOL = 0.8V. 14. Assumes that tRCD < tRCD (MAX). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase by the amount that tRCD exceeds the value shown. 15. Assumes that tRCD tRCD (MAX). 16. If /C/A/S is LOW at the falling edge of /R/A/S, DQ will be maintained from the previous cycle. To initiate a new cycle and clear the data out buffer, /C/A/S must be pulsed HIGH for tCPN. 17. Operation within the tRCD (MAX) limit ensures that tRAC (MAX) can be met. tRCD (MAX) is specified as a reference point only; if tRCD is greater than the specified tRCD (MAX) limit, then access time is controlled exclusively by tCAC. 18. Operation within the tRAD (MAX) limit ensures that tRCD (MAX) can be met. tRAD (MAX) is specified as a reference point only; if tRAD is greater than the specified tRAD (MAX) limit, then access time is controlled exclusively by tAA. MT42C4256 883C REV. 3/97 DS000016 3-45 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice. MT42C4256 883C 256K x 4 VRAM AUSTIN SEMICONDUCTOR, INC. Limited Supply - Consult Factory DRAM READ CYCLE t RC t RP t RAS RAS V IH V IL t CSH t RRH t RSH , , , , , , , , , , , , , , , , , , , ,, ,, ,, ,,, ,, ,,, , , ,, , , , , , , ,,,, ,, ,,,, ,,, t CRP CAS t RCD t CAS V IH V IL t AR t RAD t ASR ADDR V IH V IL t RAL t ASC t RAH ROW t CAH ROW COLUMN t RCH t RCS ME/WE V IH V IL t FHR t FSR DSF t FSC t RFH t CFH V IH V IL t AA t RAC t OFF t CAC t ROH V DQ V IOH IOL TR/OE OPEN t YS VALID DATA t YH t OE V IH V IL OPEN t OD , DON'T CARE UNDEFINED MT42C4256 883C REV. 3/97 DS000016 3-46 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice. MT42C4256 883C 256K x 4 VRAM AUSTIN SEMICONDUCTOR, INC. Limited Supply - Consult Factory DRAM FAST-PAGE-MODE READ CYCLE t RP t RASP RAS V IH V IL t RSH t PC t CSH , , , , , , , , , , , , ,, ,, ,, ,, ,,, , , , , , , , , , , , , , , , , , ,, ,, , ,, ,, , , , , , , ,, ,, , , , , ,, ,, ,, , ,, ,,,,,, ,, t CRP CAS t RCD V IH V IL t CP t CAS t CP t CAS t CAS t AR t RAD tASR ADDR V IH V IL t RAH t RAL t ASC t CAH t ASC COLUMN ROW t CAH t ASC COLUMN t RCH t CAH ROW COLUMN t RCS t RCS ME/WE t CP t RRH t RCS t RCH t RCH V IH V IL t FHR t FSR DSF t RFH t FSC t CFH t FSC t CFH t FSC t AA t AA t RAC t AA t CPA t CAC t OFF t CPA t CAC t OFF t CLZ DQ V IOH V IOL t YH t OE t CAC VALID DATA t OD t OFF t CLZ VALID DATA t YS TR/OE t CFH V IH V IL t OE t OD VALID DATA t OE OPEN t OD V IH V IL DON'T CARE UNDEFINED NOTE: MT42C4256 883C REV. 3/97 DS000016 WRITE cycles or READ-MODIFY-WRITE cycles may be mixed with READ cycles while in FAST PAGE MODE. 3-47 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice. MT42C4256 883C 256K x 4 VRAM AUSTIN SEMICONDUCTOR, INC. Limited Supply - Consult Factory WRITE CYCLE FUNCTION TABLE 1 LOGIC STATES /R/A/S Falling Edge /C/A/S Falling Edge C DQ (Input) D DSF E2 DQ (Input) 0 X 0 DRAM Data 0 Write Mask 0 DRAM Data (Masked) 0 1 X 0 DRAM Data (Masked) BLOCK WRITE to DRAM (No Data Mask) 1 0 X 1 Column Mask3 NONPERSISTENT (Load and Use) MASKED BLOCK WRITE to DRAM 0 0 Write Mask 1 Column Mask3 PERSISTENT (Use Register) MASKED BLOCK WRITE to DRAM 0 1 X 1 Column Mask3 Load Mask Register 1 1 X 0 Write Mask Load Color Register 1 1 X 1 Color Data FUNCTION A ?M/E/?W/E B DSF Normal DRAM WRITE 1 NONPERSISTENT (Load and Use) MASKED WRITE to DRAM 0 PERSISTENT (Use Register) MASKED WRITE to DRAM NOTE: MT42C4256 883C REV. 3/97 DS000016 1. Refer to this function table to determine the logic states of "A", "B", "C", "D" and "E" for the WRITE cycle timing diagrams on the following pages. 2. /C/A/S or ?M/E/?W/E, whichever occurs later (Except BLOCK WRITE). 3. ?W/E = "don't care" for BLOCK WRITE. The DQ column-mask data will be latched at the falling edge of ?C/A/S, regardless of the state of ?M/E/?W/E. 3-48 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice. AUSTIN SEMICONDUCTOR, INC. MT42C4256 883C 256K x 4 VRAM Limited Supply - Consult Factory CYCLE 1 DRAM EARLY-WRITE t RC t RP t RAS RAS V IH V IL t CSH t RSH , , , , , , , , ,, , ,, , , , , , , , , , ,,,, , ,, ,, ,,, ,, ,,, ,,,,,,,,, , , , , , , , , , , , , , , , , , , , , , ,, , ,,,,, ,,,,,,,, , , ,, t RCD t CRP CAS t CAS V IH V IL tAR t RAD t ASR ADDR V IH V IL t RAL t ASC t RAH ROW t CAH ROW COLUMN t CWL t RWL t WCR t WCS t WSR ME/WE V IH V IL t RWH t WCH t WP A NOTE 2 t FHR t FSR DSF V IH V IL t RFH t FSC B t CFH D t DHR t MS V IOH DQ V IOL t DH t DS E C t YS TR/OE t MH t YH V IH V IL DON'T CARE UNDEFINED NOTE: MT42C4256 883C REV. 3/97 DS000016 1. The logic states of "A", "B", "C", "D" and "E" determine the type of WRITE operation performed. See the Write Cycle Function Table for a detailed description. 2. For BLOCK WRITE, ?M/E/?W/E = "don't care." For all other EARLY-WRITE cycles, ?M/E/?W/E = LOW. 3-49 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice. AUSTIN SEMICONDUCTOR, INC. MT42C4256 883C 256K x 4 VRAM Limited Supply - Consult Factory DRAM LATE-WRITE CYCLE 1 t RC t RP t RAS RAS V IH V IL t CSH t RSH t RCD t CRP t CAS ,, ,, ,,,,,, , , , , , , , , , ,, , , , , , , , , , , , ,, , ,, ,,, ,, ,,, , , , , , , , , , , , , , , , , , , , , , , , ,,,, ,, , ,,,, ,,,,,,, CAS V IH V IL tAR t RAL t RAD t RAH t ASR ADDR V IH V IL t ASC ROW t CAH COLUMN t CWL t RWL t WSR ME/WE V IH V IL t RWH t WP A t FHR t RFH t FSR DSF V IH V IL t FSC t CFH B t DHR t MS V DQ V IOH IOL C t YS TR/OE t DS t MH t DH E t YH t OD t OEH V IH V IL ,, DON'T CARE UNDEFINED NOTE: MT42C4256 883C REV. 3/97 DS000016 1. The logic states of "A", "B", "C" and "E" determine the type of WRITE operation performed. See the Write Cycle Function Table for a detailed description. 3-50 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice. MT42C4256 883C 256K x 4 VRAM AUSTIN SEMICONDUCTOR, INC. Limited Supply - Consult Factory DRAM READ-WRITE CYCLE (READ-MODIFY-WRITE CYCLE) t RWC t RAS RAS t RP V IH V IL t CSH t RSH , , , , , , , ,,, ,,, , ,, ,,, ,, ,,, , , , , , , , , , , , ,, ,, ,, , , ,, ,, CAS t CAS t RCD t CRP V IH V IL t AR t RAD t RAH t ASR ADDR V IH V IL t RAL t ASC ROW t CAH ROW COLUMN t RWD t CWL t RCS ME/WE V IH V IL t CWD t RWH t WSR t RWL t AWD t WP A t FHR t RFH t FSR DSF V IH V IL t FSC t CFH B t AA t RAC t CAC t MH t MS V DQ V IOH IOL C t YS TR/OE t DS VALID DOUT t OE t YH t DH E OPEN t OD V IH V IL DON'T CARE , UNDEFINED NOTE: MT42C4256 883C REV. 3/97 DS000016 The logic states of "A", "B", "C" and "E" determine the type of WRITE operation performed. See the Write Cycle Function Table for a detailed description. 3-51 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice. MT42C4256 883C 256K x 4 VRAM AUSTIN SEMICONDUCTOR, INC. Limited Supply - Consult Factory DRAM FAST-PAGE-MODE EARLY-WRITE CYCLE t RASP t RP RAS V IH V IL t PC t CSH t CRP t RSH t CAS , , , , , , , , , ,, ,, , , , ,,, , , ,,, ,,, ,,, , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , ,, ,,,,,, ,,,,,,,,,,,,, , CAS t RCD t CAS t CP t CAS t CP t CP V IH V IL t AR t RAD t RAH t ASR ADDR V IH V IL t RAL t ASC t CAH t ASC COLUMN ROW t CAH COLUMN t CWL t WCS t WSR ME/WE V IH V IL t CAH COLUMN t CWL t WCH t WCS t WCH t WP t RWH t ASC ROW t CWL t WCS t WCH t WP t WP A A t FHR t RFH t FSR DSF V IH V IL t CFH t FSC B t FSC t CFH t FSC D D t CFH B D t WCR t RWL t DHR t MS DQ V IOH V IOL C t YS TR/OE t MH t DS t DH t DS t DH E E t DS t DH E t YH V IH V IL , NOTE: MT42C4256 883C REV. 3/97 DS000016 DON'T CARE UNDEFINED 1. READ cycles or READ-MODIFY-WRITE cycles can be mixed with WRITE cycles while in FAST PAGE MODE. 2. The logic states of "A", "B", "C", "D" and "E" determine the type of WRITE operation performed. See the Write Cycle Function Table for a detailed description. 3-52 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice. MT42C4256 883C 256K x 4 VRAM AUSTIN SEMICONDUCTOR, INC. Limited Supply - Consult Factory DRAM FAST-PAGE-MODE READ-WRITE CYCLE (READ-MODIFY-WRITE OR LATE-WRITE CYCLES) t RASP t RP V IH V IL RAS t PRWC t CSH t RSH , , , , , , , , , ,, ,, , ,, ,, , , , , ,,, , , , , , , , , , , , ,,,, , , ,, , ,, ,,, ,,, , t CRP t RCD t CP t CAS t CP t CAS t CAS t CP V IH V IL CAS t AR t RAD t ASR V IH V IL ADDR t RAH t ASC ROW t CAH t ASC t CAH t ASC COLUMN COLUMN t RAL t CAH ROW COLUMN t RWD t RWL t RCS t WSR V IH V IL ME/WE t RWH t CWL t WP t AWD t CWD V IH V IL t RFH t FSC t WP t AWD t CWD t CFH t CWD t FSC t CFH t FSC t CFH B t AA t RAC t MS DQ t CWL t WP A t FSR DSF t CWL t AWD V IOH V IOL t MH t AA t DH t DS t CPA t CAC t AA t DH t DS t CPA t CAC t CAC t CLZ VALID D OUT C t DH t DS t CLZ VALID D IN VALID D OUT VALID D IN VALID D OUT VALID D IN OPEN t OEH tYS TR/OE t YH t OD t OE t OE t OD t OD t OE V IH V IL DON'T CARE UNDEFINED NOTE: MT42C4256 883C REV. 3/97 DS000016 1. READ or WRITE cycles can be mixed with READ-MODIFY-WRITE cycles while in FAST PAGE MODE. Use the Write Function Table to determine the proper DSF state for the desired WRITE operation. 2. The logic states of "A", "B" and "C" determine the type of WRITE operation performed. See the Write Cycle Function Table for a detailed description. 3-53 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice. MT42C4256 883C 256K x 4 VRAM AUSTIN SEMICONDUCTOR, INC. Limited Supply - Consult Factory DRAM /R/A/S-ONLY REFRESH CYCLE (ADDR = A0-A8) t RC t RAS t RP , , , , , , , , ,,, , ,,,,,,, ,, ,, , , , , , , , , , , , , ,,,,,,,, ,, ,,,,,,, , ,, ,,,,,,,,,,,,, ,,, , , , , RAS V IH V IL tCRP CAS t RPC V IH V IL t ASR ADDR V IH V IL ME/WE V IH V IL DSF V IH V IL t RAH ROW ROW V DQ V IOH IOL OPEN t YS TR/OE OPEN t YH V IH V IL , ,,, , , , , , , , , , , , , , , ,,,,, ,,,,,,, ,,,,,,, , , , , , , , , , , , , , , , , ,, ,, , , ,, ,, , , , , , , , , , , , , , , , , , ,, , , , ,, , ,,, , , DRAM /C/A/S-BEFORE-//R/A/S REFRESH CYCLE RAS t RP t RAS t RP t RAS V IH V IL t RPC t CP CAS V IH V IL ADDR V IH V IL ME/WE V IH V IL DSF V IH V IL V DQ V IOH IOL TR/OE t CSR t CHR t RPC OPEN t CSR t CHR OPEN V IH V IL DON'T CARE UNDEFINED MT42C4256 883C REV. 3/97 DS000016 3-54 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice. MT42C4256 883C 256K x 4 VRAM AUSTIN SEMICONDUCTOR, INC. Limited Supply - Consult Factory DRAM HIDDEN-REFRESH CYCLE (READ) (REFRESH) t RAS RAS t RP t RAS V IH V IL , , ,, ,, , ,,,,,,,,,,, ,,,,,,, , ,,,,,,,,, , , , , , , , , , , , , , , , , , , , , ,,,, t CRP CAS t RCD t CHR t RSH V IH V IL t AR t RAD t ASR ADDR V IH V IL t RAH t RAL t ASC ROW t CAH COLUMN t RCS ME/WE t RRH V IH V IL t FHR t FSR DSF t RFH t FSC t CFH V IH V IL tAA t RAC t CAC t OFF V DQ V IOH IOL VALID D OUT OPEN t YS t YH t OE OPEN t OD t ROH V TR/OE V IH IL DON'T CARE UNDEFINED NOTE: MT42C4256 883C REV. 3/97 DS000016 A HIDDEN REFRESH may also be performed after a WRITE or TRANSFER cycle. In the WRITE case, ?M/E/?W/E = LOW (when /C/A/S goes LOW) and /T/R//O/E = HIGH and the DQ pins stay High-Z. In the TRANSFER case, /T/R//O/E = LOW (when /R/A/S goes LOW) and the DQ pins stay High-Z during the refresh period, regardless of /T/R//O/E. 3-55 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice. MT42C4256 883C 256K x 4 VRAM AUSTIN SEMICONDUCTOR, INC. Limited Supply - Consult Factory TRANSFER 3 READ (DRAM-TO-SAM TRANSFER) (When part was previously in the SERIAL INPUT mode or SC idle) t RC t RP t RAS RAS V IH V IL t CSH t RSH , , , , , , , , , , , , , ,, ,,,,,,,,,,,,,,,,, , ,,,,,,,,,,,,,,,,, , , ,, , , , , , , , , , , , , , , , , , , , , , , ,,,,,,,,,,,,, , , ,, ,,, t RCD t CRP CAS t CAS V IH V IL t AR t RAD t ASR ADDR V IH V IL V IH V IL DSF V IH V IL DQ V IOH V IOL t ASC ROW t WSR ME/WE t RAL t RAH t FSR t CAH SAM START (TAP) t RWH t RFH t OFF OPEN OPEN t CSD t RSD t TLS TR/OE t TLH t TRP V IH V IL t TRW t RTH t SRS t SC t SAS SC V IH V IL t TSD t SAC t SZS t SDS V IOH V IOL t SP NOTE 1 t SDH SDQ t SAS t SAC t SOH VALID D OUT VALID D IN VALID D OUT VALID D OUT t SEA t TQD t SWH SE V IH V IL t CQD t RQD QSF V OH V OL NOTE 2 NOTE 2 DON'T CARE NOTE: MT42C4256 883C REV. 3/97 DS000016 1. There must be no rising edges on the SC input during this time period. UNDEFINED 2. QSF = 0 when the Lower SAM (bits 0-255) is being accessed. QSF = 1 when the Upper SAM (bits 256-511) is being accessed. 3. If tTLH is timing for the /T/R/(?O/E) rising edge, the transfer is self-timed and the tCSD and tRSD times must be met. If tRTH is timing for the /T/R/(?O/E) rising edge, the transfer is done off of the /T/R/(?O/E) rising edge and tTSD must be met. 3-56 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice. MT42C4256 883C 256K x 4 VRAM AUSTIN SEMICONDUCTOR, INC. Limited Supply - Consult Factory REAL-TIME READ-TRANSFER (DRAM-TO-SAM TRANSFER) (When part was previously in the SERIAL OUTPUT mode) t RC t RP t RAS RAS V IH V IL t CSH t RSH , , , , , , , , , , , , , , , , , , , , , ,,,,,,,,,,,,,,,,,,,,, , ,,,,,,, ,,,,,,, , , , , , ,, , , , ,, , t RCD t CRP CAS t CAS V IH V IL t AR t RAL t RAD t ASR ADDR V IH V IL ME/WE V IH V IL DSF V IH V IL t ASC t RAH SAM START ROW t WSR t CAH t RWH t FSR t RFH t OFF V DQ V IOH IOL OPEN OPEN t TRP t CTH t TLS TR/OE t TRW t RTH V IH V IL t TSL t SC t SP SC t SAS V IH V IL SDQ V IOH V IOL ,,,, , VALID D OUT t SEA t SEZ t SE SE t TSD t SP V IH V IL V QSF V OH OL t SAC PREVIOUS ROW DATA VALID D OUT VALID D OUT NEW ROW DATA VALID D OUT VALID D OUT VALID D OUT t TQD t SEA t SEP NOTE 1 , ,,, NOTE 2 NOTE 2 DON'T CARE NOTE: MT42C4256 883C REV. 3/97 DS000016 1. The /S/E pulse is shown to illustrate the SERIAL OUTPUT ENABLE and DISABLE timing. It is not required. 2. QSF = 0 when the Lower SAM (bits 0-255) is being accessed. QSF = 1 when the Upper SAM (bits 256-511) is being accessed. 3-57 UNDEFINED Austin Semiconductor, Inc., reserves the right to change products or specifications without notice. MT42C4256 883C 256K x 4 VRAM AUSTIN SEMICONDUCTOR, INC. Limited Supply - Consult Factory SPLIT READ TRANSFER (SPLIT DRAM-TO-SAM TRANSFER) t RC t RP t RAS RAS V IH V IL t CSH t RSH , , , , , , , , ,, ,, ,,,,,, ,,,,,,,,, , , , , , , , , , , , , , , , ,, ,,,,,,,,, ,,,,,,,, , , , , , , , , , , , , , ,, , ,, ,, ,, , ,, ,,, t RCD t CRP CAS V IH V IL t CAS t AR t RAD t ASR ADDR V IH V IL ME/WE V IH V IL DSF V IH V IL t RAL t ASC t RAH ROW t WSR t FSR t CAH SAM START (B) t RWH t RFH t OFF V DQ V IOH IOL OPEN t TLS TR/OE OPEN t TLH V IH V IL t STH t STS t SC t SP SC t SP V IH V IL V SDQ V IOH IOL SE t SAS t SAC t SAC t SOH t SOH 511 (255) A (256 + A) 253 (509) 254 (510) V QSF V OH OL MT42C4256 883C REV. 3/97 DS000016 256 + B(B) V IH V IL t SQD t SQD NOTE: 255 (511) SAM MSB (NOTE 1) 1. QSF = 0 when the Lower SAM (bits 0-255) is being accessed. QSF = 1 when the Upper SAM (bits 256-511) is being accessed. 3-58 ,, NEW MSB , DON'T CARE UNDEFINED Austin Semiconductor, Inc., reserves the right to change products or specifications without notice. MT42C4256 883C 256K x 4 VRAM AUSTIN SEMICONDUCTOR, INC. Limited Supply - Consult Factory WRITE TRANSFER and PSEUDO WRITE TRANSFER (SAM-TO-DRAM TRANSFER) (When part was previously in the SERIAL OUTPUT mode) t RC t RP t RAS RAS V IH V IL t CSH t RSH , , , , , , , , , , , ,,,, ,,,,,,,,,,,,,,,,, , , , , , , , , , , , ,,, ,,,,,, ,,,,,,, ,,, , , , ,,,,, ,,,,,,,,,,,,,,,,, , , , , , , ,, , , , , , , ,, , , , , , , , , , ,, , , , ,,, , t RCD t CRP CAS t CAS V IH V IL t AR tRAD t RAH t ASR ADDR V IH V IL ME/WE V IH V IL DSF V IH V IL SAM START ROW t WSR t FSR t RAL t CAH t ASC t RWH t RFH t OFF V DQ V IOH IOL OPEN TR/OE tCSD t TLH t TLS OPEN VIH VIL tRSD t SRS tSC t SAS SC tSP V IH V IL tSP tSAS NOTE 3 t SDD t SOH V SQD V IOH IOL t SDS t SDZ VALID DOUT VALID DOUT t SDS tSDH VALID DIN HIGH Z t SDH VALID DIN t SWS t ESR SE V IH V IL t REH t SWIS NOTE 2 NOTE 1 t CQD t RQD QSF V OH V OL NOTE 4 NOTE 4 DON'T CARE NOTE: MT42C4256 883C REV. 3/97 DS000016 UNDEFINED 1. If /S/E is LOW, the SAM data will be transferred to the DRAM. If /S/E is HIGH, the SAM data will not be transferred to the DRAM (SERIAL-INPUT-MODE ENABLE cycle). 2. /S/E must be LOW to input new serial data, but the serial address register is incremented by SC regardless of /S/E. 3. There must be no rising edges on the SC input during this time period. 4. QSF = 0 when the Lower SAM (bits 0-255) is being accessed. QSF = 1 when the Upper SAM (bits 256-511) is being accessed. 3-59 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice. MT42C4256 883C 256K x 4 VRAM AUSTIN SEMICONDUCTOR, INC. Limited Supply - Consult Factory WRITE TRANSFER (SAM-TO-DRAM TRANSFER) (When part was previously in the SERIAL INPUT mode) t RC t RP t RAS RAS V IH V IL t CSH t RSH , , , , , , ,,,,, ,,,,,, ,,,,,,,, , , , , , , , , , , , , , , , , , , , , , , , , , ,, ,, ,, , ,, ,, ,,, , , , , , , , , , , , , , , , ,, , , ,, ,, , , , , ,, ,,,,,,,,, ,,, , , , , , , , , , ,, ,, , ,, ,,, , ,,, t RCD t CRP CAS t CAS V IH V IL t AR tRAD t RAH t ASR ADDR ME/WE DSF V IH V IL ROW t RAL t CAH t ASC SAM START t WSR t RWH t FSR t RFH V IH V IL V IH V IL t OFF V DQ V IOH IOL OPEN t TLS TR/OE t TLH OPEN tCSD V IH V IL t SRS tRSD tSC t SAS SC V IH V IL tSP tSAS tSP NOTE 2 t SDH t SDS t SDS V SDQ V IOH IOL tSDH t SDS VALID DIN VALID DIN VALID DIN t SWS t ESR SE t SWIS t REH V IH V IL NOTE 1 t CQD t RQD QSF V OH V OL NOTE: MT42C4256 883C REV. 3/97 DS000016 NOTE 3 NOTE 3 1. /S/E must be LOW to input new serial data, but the serial address register is incremented by SC regardless of /S/E. 2. There must be no rising edges on the SC input during this time period. 3. QSF = 0 when the Lower SAM (bits 0-255) is being accessed. QSF = 1 when the Upper SAM (bits 256-511) is being accessed. 3-60 DON'T CARE UNDEFINED Austin Semiconductor, Inc., reserves the right to change products or specifications without notice. MT42C4256 883C 256K x 4 VRAM AUSTIN SEMICONDUCTOR, INC. Limited Supply - Consult Factory ALTERNATE WRITE TRANSFER (SAM-TO-DRAM TRANSFER) t RC t RP t RAS RAS V IH V IL t CSH t RSH t RCD t CRP t CAS , , , , , ,, , , ,,,, ,, ,,,, ,,,,,,,,,,,,,,,,,,,,, ,, ,,,,,,,,,,,,,,,,,, , , , , , , , , , , , , , ,, ,, ,, ,, , ,, ,,, ,,,, ,, ,, ,,, , , , , ,, ,, , , , , , , , , , , , , , , CAS V IH V IL t AR tRAD t RAH t ASR ADDR V IH V IL ROW t WSR ME/WE SAM START t RWH V IH V IL t FSR DSF t RAL t CAH t ASC t RFH V IH V IL t OFF V DQ V IOH IOL OPEN t TLS TR/OE t TLH OPEN tCSD VIH VIL t SRS tRSD tSC t SAS SC tSP V IH V IL tSAS tSP NOTE 2 t SDD t SOH V SDQ V IOH IOL VALID DOUT t SDS t SDZ VALID DOUT tSDH VALID DIN HIGH-Z t SDS t SDH VALID DIN t SWS t SWIS SE V IH V IL NOTE 1 t CQD t RQD V QSF V OH OL NOTE 3 NOTE 3 ,, DON'T CARE NOTE: MT42C4256 883C REV. 3/97 DS000016 1. /S/E must be LOW to input new serial data, but the serial address register is incremented by SC regardless of /S/E. 2. There must be no rising edges on the SC input during this time period. 3. QSF = 0 when the Lower SAM (bits 0-255) is being accessed. QSF = 1 when the Upper SAM (bits 256-511) is being accessed. 3-61 UNDEFINED Austin Semiconductor, Inc., reserves the right to change products or specifications without notice. MT42C4256 883C 256K x 4 VRAM AUSTIN SEMICONDUCTOR, INC. Limited Supply - Consult Factory SAM SERIAL INPUT tSWH SE tSC tSAS V IH V IL SDQ V IH V IL tSWIH tSWS ,, , ,,,,, , , , , , , V IH V IL SC tSWIS tSC tSP tSDH tSC tSAS tSDS A-1 tSP tSAS tSP tSDH tSZE tSAS tSDS A tSDH A+2 A+3 SAM SERIAL OUTPUT tSEP V IH V IL SE tSC ,, ,, tSAS V IH V IL SC tSC tSP tSAS tSAC V OH V OL MT42C4256 883C REV. 3/97 DS000016 A-1 tSEZ ,, ,, tSAS tSAC tSOH SDQ tSC tSP tSP tSAC tSEA A+1 A 3-62 ,, , ,,, ,,, , tSAC tSOH tSOH A+2 A+3 DON'T CARE UNDEFINED Austin Semiconductor, Inc., reserves the right to change products or specifications without notice. AUSTIN SEMICONDUCTOR, INC. MT42C4256 883C 256K x 4 VRAM Limited Supply - Consult Factory ELECTRICAL TEST REQUIREMENTS SUBGROUPS (per Method 5005, Table I) MIL-STD-883 TEST REQUIREMENTS INTERIM ELECTRICAL (PRE-BURN-IN) TEST PARAMETERS (Method 5004) 2, 8A, 10 FINAL ELECTRICAL TEST PARAMETERS (Method 5004) 1*, 2, 3, 7*, 8, 9, 10, 11 GROUP A TEST REQUIREMENTS (Method 5005) 1, 2, 3, 4**, 7, 8, 9, 10, 11 GROUP C AND D END-POINT ELECTRICAL PARAMETERS (Method 5005) 1, 2, 3, 7, 8, 9, 10, 11 * PDA applies to subgroups 1 and 7. ** Subgroup 4 shall be measured only for initial qualification and after process or design changes, which may affect input or output capacitance. MT42C4256 883C REV. 3/97 DS000016 3-63 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice. AUSTIN SEMICONDUCTOR, INC. MT42C4256 883C 256K x 4 VRAM Limited Supply - Consult Factory MT42C4256 883C REV. 3/97 DS000016 3-64 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.