3-27
MT42C4256 883C Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
REV. 3/97
DS000016
MT42C4256 883C
256K x 4 VRAM
Limited Supply - Consult Factory
AUSTIN SEMICONDUCTOR, INC.
NOT RECOMMENDED
FOR NEW DESIGNS
–LIMITED AVAILABILITY–
256K x 4 DRAM
WITH 512 x 4 SAM
AVAILABLE AS MILITARY
SPECIFICATION
• SMD 5962-89497
• MIL-STD-883
FEATURES
• Industry standard pinout, timing and functions
• High-performance, CMOS silicon-gate process
• Single +5V ±10% power supply
• Inputs and outputs are fully TTL compatible
• Refresh modes: /R/A/S-ONLY, /C/A/S-BEFORE-/R/A/S (CBR)
and HIDDEN
• 512-cycle refresh within 8ms
• Optional FAST PAGE MODE access cycles
• Dual port organization: 256K x 4 DRAM port
512 x 4 SAM port
• No refresh required for serial access memory
• Low power: 15mW standby; 275mW active, typical
SPECIAL FUNCTIONS
• JEDEC Standard Function set
• PERSISTENT MASKED WRITE
• SPLIT READ TRANSFER
• WRITE TRANSFER/SERIAL INPUT
• ALTERNATE WRITE TRANSFER
• BLOCK WRITE
OPTIONS MARKING
• Timing [DRAM, SAM (cycle/access)]
80ns, 30ns/25ns - 8
100ns, 30ns/27ns -10
120ns, 35ns/35ns -12
• Packages
Ceramic SOJ DCJ No. 500
Ceramic DIP (400 mil) C No. 109
Ceramic LCC EC No. 203
Ceramic Flat Pack F No. 302
PIN ASSIGNMENT (Top View)
28-Pin DIP
(400 MIL) 28-Pin SOJ
28-Pin LCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
SC
SDQ1
SDQ2
TR/OE
DQ1
DQ2
ME/WE
NC
RAS
A8
A6
A5
A4
Vcc
Vss
SDQ4
SDQ3
SE
DQ4
DQ3
DSF
CAS
QSF
A0
A1
A2
A3
A7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
SC
SDQ1
SDQ2
TR/OE
DQ1
DQ2
ME/WE
NC
RAS
A8
A6
A5
A4
Vcc
Vss
SDQ4
SDQ3
SE
DQ4
DQ3
DSF
CAS
QSF
A0
A1
A2
A3
A7
GENERAL DESCRIPTION
The MT42C4256 883C is a high-speed, dual port CMOS
dynamic random access memory or video RAM (VRAM)
containing 1,048,576 bits. These bits may be accessed by a
4-bit wide DRAM port or a 512 x 4-bit serial access memory
(SAM) port. Data may be transferred bidirectionally be-
tween the DRAM and the SAM.
The DRAM portion of the VRAM is functionally identical
to the MT4C4256 (256K x 4 DRAM). Four 512-bit data
registers make up the SAM portion of the VRAM. Data I/O
and internal data transfer are accomplished using three
separate bidirectional data paths; the 4-bit random access
I/O port, the four internal 512 bit wide paths between the
DRAM and the SAM, and the 4-bit serial I/O port for the
SAM. The rest of the circuitry consists of the control, timing
and address decoding logic.
Each port may be operated asynchronously and indepen-
dently of the other except when data is being transferred
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
SC
SDQ1
SDQ2
TR/OE
DQ1
DQ2
ME/WE
NC
RAS
A8
A6
A5
A4
Vcc
Vss
SDQ4
SDQ3
SE
DQ4
DQ3
DSF
CAS
QSF
A0
A1
A2
A3
A7
28-Pin FP
(F-12)
VRAM
3-28
MT42C4256 883C Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
REV. 3/97
DS000016
MT42C4256 883C
256K x 4 VRAM
Limited Supply - Consult Factory
AUSTIN SEMICONDUCTOR, INC.
FUNCTIONAL BLOCK DIAGRAM
99
9
9
BLOCK
WRITE
CONTROL
LOGIC
4
44
4
4
4
4
M
A
S
K
WRITE
CONTROL
LOGIC MUX
COLOR
REGISTER
DRAM
INPUT
BUFFERS
DRAM
OUTPUT
BUFFERS
SAM
INPUT
BUFFERS
SAM
OUTPUT
BUFFERS
COLUMN ADDRESS
LATCH/BUFFER
SAM ADDRESS
COUNTER
SAM ADDRESS
LATCH/BUFFER ROW ADDRESS
LATCH/BUFFER
ROW DECODER
REFRESH
COUNTER TRANSFER
CONTROL
SPLIT SAM
STATUS & CONTROL
QSF
TIMING
GENERATOR
&
CONTROL
LOGIC
RAS
CAS
TR/OE
ME/WE
DSF
SC
SE
4
4
44
9
MASK DATA
REGISTER
4
DQ1
DQ4
SDQ1
SDQ4
4
8
COLUMN
MASK
MASKED WRITE
CONTROL
LOGIC
A0-A8
9
512
256256
512
256 256
512
512 x 512 x 4
DRAM ARRAY
TRANSFER
GATE
LOWER
SAM
TRANSFER
GATE
UPPER
SAM
SENSE AMPLIFIERS
SAM LOCATION
DECODER
COLUMN DECODER
4
4
internally. As with all DRAMs, the VRAM must be re-
freshed to maintain data. Refresh cycles must be timed so
that all 512 combinations of /R/A/S addresses are executed at
least every 8ms, (regardless of sequence). Micron recom-
mends evenly spaced refresh cycles for maximum data
integrity. An internal transfer between the DRAM and the
SAM counts as a refresh cycle. The SAM portion of the
VRAM is fully static and does not require any refresh.
The operation and control of the MT42C4256 are opti-
mized for high performance graphics and communication
designs. The dual port architecture is well suited to buffer-
ing the sequential data used in raster graphics display,
serial and parallel networking and data communications.
Special features, such as SPLIT READ TRANSFER and
BLOCK WRITE allow further enhancements to system
performance.
3-29
MT42C4256 883C Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
REV. 3/97
DS000016
MT42C4256 883C
256K x 4 VRAM
Limited Supply - Consult Factory
AUSTIN SEMICONDUCTOR, INC.
PIN DESCRIPTIONS
PIN
NUMBERS SYMBOL TYPE DESCRIPTION
1 SC Input Serial Clock: Clock input to the serial address counter for the SAM
registers.
4/T/R//O/E Input Transfer Enable: Enables an internal TRANSFER operation at /R/A/S
(H > L), or
Output Enable: Enables the DRAM output buffers when taken LOW
after /R/A/S goes LOW (/C/A/S must also be LOW), otherwise the
output buffers are in a High-Z state.
7?M/E/?W/E Input Mask Enable: If ?M/E/?W/E is LOW at the falling edge of /R/A/S a
MASKED WRITE cycle is performed, or
Write Enable: ?M/E/?W/E is also used to select a READ (??M/E/?W/E = H)
or WRITE (??M/E/?W/E = L) cycle when accessing the DRAM. This
includes a READ TRANSFER (??M/E/?W/E = H) or
WRITE TRANSFER (??M/E/?W/E = L).
25 /S/E Input Serial Port Enable: /S/E enables the serial I/O buffers and allows a
serial READ or WRITE operation to occur, otherwise the output
buffers are in a High-Z state. /S/E is also used during a WRITE
TRANSFER operation to indicate whether a WRITE TRANSFER or
a SERIAL INPUT MODE ENABLE cycle is performed.
22 DSF Input Special Function Select: DSF is used to indicate which special
functions (BLOCK WRITE, MASKED WRITE vs. PERSISTENT
MASKED WRITE, etc.) are used on a particular access cycle.
9/R/A/S Input Row Address Strobe: /R/A/S is used to clock-in the 9 row-address bits
and strobe the ?M/E/?W/E, /T/R//O/E, DSF, /S/E, /C/A/S and DQ inputs. It
also acts as the master chip enable and must fall for initiation of any
DRAM or TRANSFER cycle.
21 /C/A/S Input Column Address Strobe: /C/A/S is used to clock-in the 9 column-
address bits, enable the DRAM output buffers (along with /T/R/?O/E),
and strobe the DSF input.
19, 18, 17, A0-A8 Input Address Inputs: For the DRAM operation, these inputs are multi-
plexed and clocked by /R/A/S and /C/A/S to select one 4-bit word out of
the 256K available. During TRANSFER operations, A0 to A8
indicate the DRAM row being accessed (when /R/A/S goes LOW) and
the SAM start address (when /C/A/S goes LOW).
5, 6, 23, 24 DQ1-DQ4 Input/ DRAM Data I/O: Data input/output for DRAM cycles; inputs for
Output Mask Data Register and Color Register load cycles, and DQ and
Column Mask inputs for BLOCK WRITE.
2, 3, 26, 27 SDQ1-SDQ4 Input/ Serial Data I/O: Input, output, or High-Z.
Output
20 QSF Output Split SAM Status: QSF indicates which half of the SAM is being
accessed. LOW if address is 0-255, HIGH if address is 256-511.
8 NC – No Connect: This pin should be left either unconnected or tied to
ground.
14 VCC Supply Power Supply: +5V ±10%
28 VSS Supply Ground
3-30
MT42C4256 883C Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
REV. 3/97
DS000016
MT42C4256 883C
256K x 4 VRAM
Limited Supply - Consult Factory
AUSTIN SEMICONDUCTOR, INC.
FUNCTIONAL DESCRIPTION
The MT42C4256 may be divided into three functional
blocks (see Figure 1): the DRAM, the transfer circuitry, and
the SAM. All of the operations described below are shown
in the AC Timing Diagrams section of this data sheet and
summarized in the Truth Table.
Note: For dual-function pins, the function not being
discussed will be surrounded by parentheses. For
example, the
/
T
/
R/
/
O
/
E pin will be shown as
/
T
/
R/(
/
O
/
E) in
references to transfer operations.
DRAM OPERATION
DRAM REFRESH
Like any DRAM based memory, the MT42C4256 VRAM
must be refreshed to retain data. All 512 row address
combinations must be accessed within 8ms. The MT42C4256
supports /C/A/S-BEFORE-/R/A/S, /R/A/S-ONLY and HIDDEN
types of refresh cycles.
For the /C/A/S-BEFORE-/R/A/S REFRESH cycle, the row ad-
dresses are generated and stored in an internal address
counter. The user need not supply any address data, and
simply must perform 512 /C/A/S-BEFORE-/R/A/S cycles within
the 8ms time period.
The refresh address must be generated externally and
applied to A0-A8 inputs for /R/A/S-ONLY refresh cycles. The
DQ pins remain in a High-Z state for both the /R/A/S-ONLY
and /C/A/S-BEFORE-/R/A/S refresh cycles.
HIDDEN REFRESH cycles are performed by toggling
/R/A/S (and keeping /C/A/S LOW) after a READ or WRITE
cycle. This performs /C/A/S-BEFORE-/R/A/S cycles but does not
disturb the DQ lines.
Any DRAM READ, WRITE, or TRANSFER cycle also
refreshes the DRAM row being accessed. The SAM portion
of the MT42C4256 is fully static and does not require any
refreshing.
DRAM READ AND WRITE CYCLES
The DRAM portion of the VRAM is nearly identical to
standard 256K x 4 DRAMs. However, because several of the
DRAM control pins are used for additional functions on
this part, several conditions that were undefined or in
“don’t care” states for the DRAM are specified for the
VRAM. These conditions are highlighted in the following
discussion. In addition, the VRAM has several special func-
tions that can be used when writing to the DRAM.
The 18 address bits that are used to select a 4-bit word
from the 262,144 available are latched into the chip using
the A0-A8, /R/A/S and /C/A/S inputs. First, the 9 row-address
bits are set up on the address inputs and clocked into the
part when /R/A/S transitions from HIGH-to-LOW. Next, the
9 column address bits are set up on the address inputs and
clocked-in when /C/A/S goes from HIGH-to-LOW.
Note:
/
R
?
A
/
S also acts as a “master” chip enable for the
VRAM. If
/
R
?
A
/
S is inactive, HIGH, all other DRAM
control pins (
?
C
?
A
/
S,
/
T
/
R/
?
O
/
E,
?
M
/
E/
?
W
/
E, etc.) are “don’t
care” and may change state without effect. No DRAM
or TRANSFER cycles will be initiated without
/
R
?
A
/
S
falling.
For single port DRAMS, the /O/E pin is a “don’t care” when
/R/A/S goes LOW. However, for the VRAM, when /R/A/S goes
LOW, /T/R/(/O/E) selects between DRAM access or TRANS-
FER cycles. /T/R/(/O/E) must be HIGH at the /R/A/S HIGH-to-
LOW transition for all DRAM operations (except /C/A/S-
BEFORE-/R/A/S).
If (?M/E)/?W/E is HIGH when /C/A/S goes LOW, a DRAM
READ operation is performed and the data from the memory
cells selected will appear at the DQ1-DQ4 port. The (/T/R)/
/O/E input must transition from HIGH-to-LOW some time
after /R/A/S falls to enable the DRAM output port.
For single port normal DRAMs, ?W/E is a “don’t care”
when /R/A/S goes LOW. For the VRAM, ?M/E/(?W/E) is used,
when /R/A/S goes LOW, to select between a MASKED WRITE
cycle and a normal WRITE cycle. If ?M/E/(?W/E) is LOW at the
/R/A/S HIGH-to-LOW transition, a MASKED WRITE opera-
tion is selected. For any DRAM access cycle (READ or
WRITE), ?M/E/(?W/E) must be HIGH at the /R/A/S HIGH-to-
LOW transition. If (?M/E)/?W/E is LOW before /C/A/S goes
LOW, a DRAM EARLY-WRITE operation is performed and
the data present on the DQ1-DQ4 data port will be written
into the selected memory cells. If (?M/E)/?W/E goes LOW after
/C/A/S goes LOW, a DRAM LATE-WRITE operation is per-
formed. Refer to the AC timing diagrams.
The VRAM can perform all the normal DRAM cycles
including READ, EARLY-WRITE, LATE-WRITE,
READ-MODIFY-WRITE, FAST-PAGE-MODE READ,
FAST-PAGE-MODE WRITE (Late or Early), and FAST-
PAGE-MODE READ-MODIFY-WRITE. Refer to the AC
timing parameters and diagrams in the data sheet for more
details on these operations.
3-31
MT42C4256 883C Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
REV. 3/97
DS000016
MT42C4256 883C
256K x 4 VRAM
Limited Supply - Consult Factory
AUSTIN SEMICONDUCTOR, INC.
Figure 1
NONPERSISTENT MASKED WRITE EXAMPLE
NONPERSISTENT MASKED WRITE
The MASKED WRITE feature eliminates the need for a
READ-MODIFY-WRITE cycle when changing only specific
bits within a 4-bit word. The MT42C4256 supports two
types of MASKED WRITE cycles, NONPERSISTENT
MASKED WRITE and PERSISTENT MASKED WRITE.
If ?M/E/(?W/E) and DSF are LOW at the /R/A/S HIGH-to-
LOW transition, a NONPERSISTENT MASKED WRITE is
performed and the data (mask data) present on the DQ1-
DQ4 inputs will be written into the mask data register. The
mask data acts as an individual write enable for each of the
four DQ1-DQ4 pins. If a LOW (logic “0”) is written to a
mask data register bit, the input port for that bit is disabled
during the subsequent WRITE operation and no new data
will be written to that DRAM cell location. A HIGH (logic
“1”) on a mask data register bit enables the input port and
allows normal WRITE operation to proceed. Note that /C/A/S
is still HIGH. When /C/A/S goes LOW, the bits present on the
DQ1-DQ4 inputs will be either written to the DRAM (if the
mask data bit is HIGH) or ignored (if the mask data bit is
LOW). The DRAM contents that correspond to masked
input bits will not be changed during the WRITE cycle. The
MASKED WRITE is nonpersistent (must be re-entered at
every /R?A/S cycle) if DSF is LOW when /R?A/S goes LOW. The
mask data register is cleared at the end of every NONPER-
SISTENT MASKED WRITE. FAST PAGE MODE can be
used with NONPERSISTENT MASKED WRITE to write
several column locations in an addressed row. The same
mask is used during the entire FAST-PAGE-MODE /R/A/S
cycle. An example NONPERSISTENT MASKED WRITE
cycle is shown in Figure 1.
,
,,
STORED
DATA
1
1
0
0
BEFORE
RAS
CAS
ME/WE
DSF
MASK
0
1
0
1
INPUT
X
0
X
1
STORED
DATA
1
0
0
1
AFTER
STORED
DATA
0
0
0
0
BEFORE
MASK
(RE-WRITE)
0
1
0
1
STORED
X
1
X
1
STORED
DATA
0
1
0
1
AFTER
X = NOT EFFECTIVE (DON’T CARE)
NONPERSISTENT MASKED WRITE
ADDRESS 1ADDRESS 0
DON’T CARE
,,
NONPERSISTENT MASKED WRITE
,,,
,,
,
,,
,,,
,
3-32
MT42C4256 883C Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
REV. 3/97
DS000016
MT42C4256 883C
256K x 4 VRAM
Limited Supply - Consult Factory
AUSTIN SEMICONDUCTOR, INC.
Figure 2
PERSISTENT MASKED WRITE EXAMPLE
PERSISTENT MASKED WRITE
The PERSISTENT MASKED WRITE feature eliminates
the need to rewrite the mask data before each MASKED
WRITE cycle if the same mask data is being used repeat-
edly. To initiate a PERSISTENT MASKED WRITE, a LOAD
MASK REGISTER cycle is performed by taking ?M/E/(?W/E)
and DSF HIGH when /R/A/S goes LOW. The mask data is
loaded into the internal register when /C/A/S goes LOW.
PERSISTENT MASKED WRITE cycles may then be per-
formed by taking ?M/E/(?W/E) LOW and DSF HIGH when
/R/A/S goes LOW. The contents of the mask data register will
then be used as the mask data for the DRAM inputs. Unlike
the NONPERSISTENT MASKED WRITE cycle, the data
present on the DQ inputs is not loaded into the mask
register when /R/A/S falls, and the mask data register will not
be cleared at the end of the cycle. Any number of PERSIS-
TENT MASKED WRITE cycles, to any address, may be
performed without having to reload the mask data register.
Figure 2 shows the LOAD MASK REGISTER and two
PERSISTENT MASKED WRITE cycles in operation. The
LOAD MASK REGISTER and PERSISTENT MASKED
WRITE cycles allow controllers that cannot provide mask
data to the DQ pins at /R/A/S time to perform MASKED
WRITE operations. PERSISTENT MASKED WRITE opera-
tions may be performed during FAST PAGE MODE cycles
and the same mask will apply to all addressed columns in
the addressed row.
LOAD MASK REGISTER PERSISTENT MASKED WRITE
ADDRESS 1
MASK
0
1
0
1
(Stored in
Mask Data
Register)
INPUT
X
0
X
1
STORED
DATA
1
1
0
0
BEFORE
STORED
DATA
0
0
0
0
BEFORE
INPUT
X
1
X
1
STORED
DATA
0
1
0
1
AFTER
X = NOT EFFECTIVE (DON’T CARE)
STORED
DATA
1
0
0
1
AFTER
ADDRESS 0
RAS
CAS
ME/WE
DSF
PERSISTENT MASKED WRITE
APPLY
MASK
REG.
APPLY
MASK
REG.
3-33
MT42C4256 883C Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
REV. 3/97
DS000016
MT42C4256 883C
256K x 4 VRAM
Limited Supply - Consult Factory
AUSTIN SEMICONDUCTOR, INC.
4
COLUMN
(A2-A8 at CAS)
ROW
(A0-A8 at RAS)
DQ1
DQ2
DQ3
DQ4
CAS
COLUMN MASK (A0,A1)
ON THE DQ INPUTS AT CAS
MASK
DATA
REGISTER
RAS * DSF
(DQ1)
(DQ2)
(DQ3)
(DQ4)
LOAD
COLOR
REGISTER COLOR REGISTER
(
must be previousl
y
loaded
)
DQ1
DQ2
DQ3
DQ4
MUX
D1
D2
D3
D4
RAS
4
However, when /C/A/S goes LOW only the A2-A8 inputs are
used. A2-A8 specify the “block” of four adjacent column
locations that will be accessed. The DQ inputs are then used
to determine what combination of the four column loca-
tions will be changed. DQ1 acts as a write enable for column
location A0 = 0, A1 = 0; DQ2 controls column location
A0 = 1, A1 = 0; DQ3 controls A0 = 0, A1 = 1; and DQ4 controls
A0 = 1, A1 = 1. The write enable controls are active HIGH;
the WRITE function is enabled by a logic 1 and disabled by
a logic 0.
BLOCK WRITE
If DSF is HIGH when /C/A/S goes LOW, the MT42C4256
will perform a BLOCK WRITE cycle instead of a normal
WRITE cycle. In BLOCK WRITE cycles, the contents of the
color register are directly written to four adjacent column
locations (see Figure 3). The color register must be loaded
prior to beginning BLOCK WRITE cycles (see LOAD
COLOR REGISTER). Each DQ location of the color register
is written to the four column locations (or any of the four
that are enabled) in the corresponding DQ bit plane.
The row is addressed as in a normal DRAM WRITE cycle.
Figure 3
BLOCK WRITE EXAMPLE
3-34
MT42C4256 883C Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
REV. 3/97
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MT42C4256 883C
256K x 4 VRAM
Limited Supply - Consult Factory
AUSTIN SEMICONDUCTOR, INC.
NONPERSISTENT MASKED BLOCK WRITE
The MASKED WRITE functions can also be used during
BLOCK WRITE cycles. NONPERSISTENT MASKED
BLOCK WRITE operates exactly like the normal NONPER-
SISTENT MASKED WRITE, except that the mask is now
applied to four column locations instead of just one.
Like NONPERSISTENT MASKED WRITE, the combina-
tion of ?M/E/(?W/E) LOW and DSF LOW when /R/A/S goes LOW
initiates a NONPERSISTENT MASKED cycle. The DSF pin
must be driven HIGH when /C/A/S goes LOW, to perform the
NONPERSISTENT MASKED BLOCK WRITE. By using
both the column mask input and the MASKED WRITE
function, any combination of the four bit planes or column
locations may be masked.
PERSISTENT MASKED BLOCK WRITE
This cycle is also performed exactly like the normal
PERSISTENT MASKED WRITE except that DSF is HIGH
when /C/A/S goes LOW to indicate the BLOCK WRITE func-
tion. Both the mask data register and the color register must
be loaded with the appropriate data prior to starting a
PERSISTENT MASKED BLOCK WRITE.
LOAD MASK DATA REGISTER
The LOAD MASK REGISTER operation and timing are
identical to a normal WRITE cycle except that DSF is HIGH
when /R/A/S goes LOW. As shown in the Truth Table, the
combination of /T/R/(/O/E), ?M/E/(?W/E), and DSF being HIGH
when /R/A/S goes LOW indicates the cycle is a LOAD REGIS-
TER cycle. DSF is used when /C/A/S goes LOW to select the
register to be loaded and must be LOW for a LOAD MASK
REGISTER cycle. The data present on the DQ lines will then
be written to the mask data register.
Note: For a normal DRAM WRITE cycle, the mask data
register is disabled but not modified. The contents of
mask data register will not be changed unless a NON-
PERSISTENT MASKED WRITE cycle or a LOAD
MASK REGISTER cycle is performed.
The row address supplied will be refreshed, but it is not
necessary to provide any particular row address. The col-
umn address inputs are ignored during a LOAD MASK
REGISTER cycle.
The mask data register contents are used during PERSIS-
TENT MASKED WRITE and PERSISTENT MASKED
BLOCK WRITE cycles to selectively enable writes to the
four DQ planes.
LOAD COLOR REGISTER
A LOAD COLOR REGISTER cycle is identical to the
LOAD MASK REGISTER cycle except DSF is HIGH when
/C/A/S goes LOW. The contents of the color register are
retained until changed by another LOAD COLOR REGIS-
TER cycle (or the part loses power) and are used as data
inputs during BLOCK WRITE cycles.
3-35
MT42C4256 883C Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
REV. 3/97
DS000016
MT42C4256 883C
256K x 4 VRAM
Limited Supply - Consult Factory
AUSTIN SEMICONDUCTOR, INC.
TRANSFER OPERATIONS
TRANSFER operations are initiated when /T/R/(/O/E) is
LOW then /R/A/S goes LOW. The state of (?M/E)/?W/E when
/R/A/S goes LOW indicates the direction of the TRANSFER
(to or from the DRAM), and DSF is used to select between
NORMAL TRANSFER, SPLIT READ TRANSFER, and AL-
TERNATE WRITE TRANSFER cycles. Each of the TRANS-
FER cycles available is described below.
READ TRANSFER (DRAM-TO-SAM TRANSFER)
If (?M/E)/?W/E is HIGH and DSF is LOW when /R/A/S goes
LOW, a READ TRANSFER cycle is selected. The row ad-
dress bits indicate the four 512-bit DRAM row planes that
are to be transferred to the four SAM data register planes.
The column address bits indicate the start address (or Tap
address) of the serial output cycle from the SAM data
registers. /C?A/S must fall for every TRANSFER in order to
load a valid Tap address. A read transfer may be accom-
plished in two ways. If the transfer is to be synchronized
with SC (REAL-TIME READ TRANSFER), /T/R/(?O/E) is
taken HIGH after ?/C/A/S goes LOW. If the transfer does not
have to be synchronized with SC (READ TRANSFER), /T/R/
(?O/E) may go HIGH before ?C/A/S goes LOW (refer to the AC
Timing Diagrams). The 2,048 bits of DRAM data are written
into the SAM data registers and the serial shift start
address is stored in an internal 9-bit register. QSF will be
LOW if access is from the lower half (addresses 0 through
255), and HIGH if access is from the upper half (256 through
511). If /S/E is LOW, the first bits of the new row data will
appear at the serial outputs with the first SC clock pulse.
/S/E enables the serial outputs and may be either HIGH or
LOW during this operation. The SAM address pointer will
increment with the SC LOW-to-HIGH transition, regard-
less of the state of /S/E. Performing a READ TRANSFER cycle
sets the direction of the SAM I/O buffers to the output
mode.
,,
,,,
,,
,,,
,,,
,
,
,,,
,,,
,,,
,,,
,,
,,,
,,,
,
TR/OE
ME/WE
DSF
,,
,,
SC
,,
,,
,
,,
,,,
,,
,,,
,,,
,,,
,
,,
,,
,,,
,,,
,
,
,,
,,
,
,
,
,,
,,,,
,,
,
,
,
,,,
,,
,,,,
,,,,
,,
,,
,
,
,,,
,,,
,
,
,,
,,,
,
SDQ
Output
QSF
A0-A8
RAS
CAS
A0-A8 = 0ROW 0 A0-A7 = TAP
A8 = X
A0-A7 = TAP
A8 = X
1 7 8 255 260 319 320
(NORMAL) READ TRANSFER SPLIT READ TRANSFER
(OPTIONAL) SPLIT READ TRANSFER
FROM: ROW 0
TO: FULL SAM,
SAM I/O IS SET TO OUTPUT
MODE AND SERIAL OUTPUT
FROM LOWER SAM BEGINS
(QSF GOES LOW)
FROM: ROW 0
TO: UPPER SAM,
TAP ADDRESS = 4
SERIAL OUTPUT FROM
LOWER SAM CONTINUES
SERIAL OUTPUT
SWITCHES FROM
LOWER SAM TO
UPPER SAM (QSF
GOES HIGH)
FROM: ROW 1
TO: LOWER SAM,
TAP ADDRESS = 0 TO 255
SERIAL OUTPUT FROM
UPPER SAM CONTINUES
(QSF REMAINS HIGH)
0
ROW 0ROW 0ROW 0ROW 0
DON’T CARE
UNDEFINED
,,
,
,
ROW 0 ROW 1
3219
Figure 4
TYPICAL SPLIT-READ-TRANSFER INITIATION SEQUENCE
3-36
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REV. 3/97
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MT42C4256 883C
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SPLIT READ TRANSFER (SPLIT DRAM-TO-SAM
TRANSFER)
The SPLIT READ TRANSFER (SRT) cycle eliminates the
critical transfer timing required to maintain a continuous
serial output data stream. When using normal TRANSFER
cycles, the REAL-TIME READ TRANSFER cycle has to
occur immediately after the last bit of “old data” was
clocked out of the SAM port.
When using the SPLIT TRANSFER mode, the SAM is
divided into an upper half and a lower half. While data is
being serially read from one half of the SAM, new DRAM
data may be transferred to the other half. The transfer may
occur at any time while the other half is sending data and
need not be synchronized with the SC clock.
The /T/R/(?O/E) timing is also relaxed for SPLIT
TRANSFER cycles. The rising edge of /T/R/(/O/E) is not used
to complete the TRANSFER cycle and therefore is inde-
pendent of the rising edges of /R/A/S or /C/A/S. The transfer
timing is generated internally for SPLIT TRANSFER cycles.
A SPLIT READ TRANSFER does not change the direction
of the SAM port.
A normal, non-split READ TRANSFER cycle must pre-
cede any sequence of SPLIT READ TRANSFER cycles to set
SAM I/O direction and provide a reference to which half of
the SAM the access will begin. Then SPLIT READ TRANS-
FERS may be initiated by taking DSF HIGH when /R/A/S
goes LOW during the TRANSFER cycle. As in nonsplit
transfers, the row address is used to specify the DRAM row
to be transferred. The column address, A0-A7, is used to
input the SAM Tap address. Address pin A8 is a “don’t care”
when the Tap address is loaded at the HIGH-to-LOW
transition of ?C/A/S. It is internally generated so that the
SPLIT TRANSFER will be to the SAM half not currently
being accessed.
Figure 4 shows a typical SPLIT READ TRANSFER initia-
tion sequence. The normal READ TRANSFER is first per-
formed, followed by a SPLIT READ TRANSFER of the same
row to the upper half of the SAM. The SRT to the upper half
is optional and need only be done if the Tap for the upper
half is ≠ 0. Serial access continues, and when the SAM
address counter reaches 255 (“A8” = 0, A0-A7 = 1), the new
Tap address is loaded for the next half (“A8” = 1, A0-A7 =
Tap) and the QSF output goes HIGH. Once the serial access
has switched to the upper SAM, new data may be trans-
ferred to the lower SAM. The controller must wait for the
state of QSF to change and then the new data may be
transferred to the SAM half not being accessed. For
example, the next step in Figure 4 would be to wait until
QSF went LOW (indicating that row-1 data is shifting out of
the lower SAM) and then transfer the upper half of row 1 to
the upper SAM. If the half boundary is reached before an
SRT is done for the next half a Tap address of “0” will be
used. Access will start at 0 if going to the lower half, or 256
if going to the upper half. See Figure 5.
WRITE TRANSFER (SAM-TO-DRAM TRANSFER)
The operation of the WRITE TRANSFER is identical to the
READ TRANSFER described previously except (?M/E)/?W/E
and /S/E must be LOW when /R/A/S goes LOW. The row
address indicates the DRAM row to which the SAM data
registers will be written. The column address (Tap) indi-
cates the starting address of the next SERIAL INPUT cycle
for the SAM data registers. A WRITE TRANSFER changes
the direction of the SAM I/O buffers to the input mode. QFS
is LOW if access is to the lower half of the SAM, and HIGH
if access is to the upper half.
0 TAP 255 256 511
Start Split
NO SRT NO SRT
LOWER HALF UPPER HALF
Figure 5
SPLIT SAM TRANSFER
3-37
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PSEUDO WRITE TRANSFER (SERIAL-INPUT-MODE
ENABLE)
The PSEUDO WRITE TRANSFER cycle is used to change
the direction of SAM port from output to input without
performing a WRITE TRANSFER cycle. A PSEUDO WRITE
TRANSFER cycle is a WRITE TRANSFER cycle with /S/E
held HIGH instead of LOW. The DRAM data will not be
disturbed and the SAM will be ready to accept input data.
ALTERNATE WRITE TRANSFER (SAM-TO-DRAM
TRANSFER)
The operation of the ALTERNATE WRITE TRANSFER is
identical to the WRITE TRANSFER except that the DSF pin
is HIGH and (?M/E)/?W/E is LOW when /R?A/S goes LOW,
allowing /S/E to be a “don’t care.” This allows the outputs to
be disabled using /S/E during a WRITE TRANSFER cycle.
ALTERNATE WRITE TRANSFER will change the SAM I/
O direction to an input condition.
SERIAL INPUT AND SERIAL OUTPUT
The control inputs for SERIAL INPUT and SERIAL OUT-
PUT are SC and /S/E. The rising edge of SC increments the
serial address counter and provides access to the next SAM
location. /S/E enables or disables the serial input/output
buffers.
Serial output of the SAM contents will start at the serial
start address that was loaded in the SAM address counter
during a READ or SPLIT READ TRANSFER cycle. The SC
input increments the address counter and presents the
contents of the next SAM location to the 4-bit port. /S/E is used
as an output enable during the SAM output operation. The
serial address is automatically incremented with every SC
LOW-to-HIGH transition, regardless of whether /S/E is
HIGH or LOW. The address progresses through the SAM
and will wrap around (after count 255 or 511) to the Tap
address of the next half for split modes. If an SRT was not
performed before the half boundary is reached the count
will progress as illustrated in Figure 5. Address count will
wrap around (after count 511) to Tap address 0 if in the
“full” SAM modes.
SC is also used to clock-in data when the device is in the
serial input mode. As in the serial output operation, the
contents of the SAM address counter (loaded when the
serial input mode was enabled) will determine the serial
address of the first 4-bit word written. /S/E acts as a write
enable for serial input data and must be LOW for valid
serial input. If /S/E = HIGH, the data inputs are disabled and
the SAM contents will not be modified. The serial address
counter is incremented with every LOW-to-HIGH transi-
tion of SC, regardless of the logic level on the /S/E input.
POWER-UP AND INITIALIZATION
After Vcc is at specified operating conditions, for 100µs
minimum, eight /R/A/S cycles must be executed to initialize
the dynamic memory array. Micron recommends that
/R?A/S = (/T/R)/?O/E ≥ VIH during power up to ensure that the
DRAM I/O pins (DQs) are in a High-Z state. The DRAM
array will contain random data.
The SAM portion of the MT42C4256 is completely static
in operation and does not require refresh or initialization.
The SAM port will power-up in the serial input mode
(WRITE TRANSFER) and the I/O pins (SDQs) will be
High-Z, regardless of the state of /S/E. The mask and color
register will contain random data after power-up. QSF
initializes in the LOW state.
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MT42C4256 883C Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
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NOTE: 1. These columns show what must be present on the A0-A8 inputs when /R/A/S falls and when /C/A/S falls.
2. These columns show what must be present on the DQ1-DQ4 inputs when /R/A/S falls and when /C/A/S falls.
3. On WRITE cycles (except BLOCK WRITE), the input data is latched at the falling edge of /C/A/S or ?M/E/?W/E, whichever is later.
Similarly, on READ cycles, the output data is activated at the falling edge of /C/A/S or
/T/R//O/E, whichever is later.
4. The ROW that is addressed will be refreshed, but no particular ROW address is required.
5. This is the SAM location that the first SC cycle will access. For split SAM transfers, the Tap will be the first address location
accessed of the “new” SAM half after the boundary of the current half is reached (255 for lower half, 511 for upper half).
CODE FUNCTION /R/A/S FALLING EDGE /C/A/S FALL A0 - A81DQ1 - DQ42REGISTERS
CAS /T/R//O/E/M/E//W/E DSF /S/E DSDF /R/A/S/C/A/S/R/A/S/C/A/S3MASK COLOR
DRAM OPERATIONS
CBR CAS-BEFORE-RAS REFRESH 0 X 1 X X X – X – X X X
ROR RAS-ONLY REFRESH 1 1 X X X – ROW – X – X X
RW NORMAL DRAM READ OR WRITE 1 1 1 0 X 0 ROW COLUMN X DATA X X
RWNM NONPERSISTANT (LOAD AND USE) MASKED 1 1 0 0 X 0 ROW COLUMN WRITE DATA LOAD & X
WRITE TO DRAM MASK USE
RWOM PERSISTENT (USE REGISTER) MASKED 1 1 0 1 X 0 ROW COLUMN X DATA USE X
WRITE TO DRAM
BW BLOCK WRITE TO DRAM (NO DATA MASK) 1 1 1 0 X 1 ROW COLUMN X COLUMN X USE
(A2 - A8) MASK
BWMN NO PERSISTENT (LOAD & USE) MASKED 1 1 0 0 X 1 ROW COLUMN WRITE COLUMN LOAD & USE
BLOCK WRITE TO DRAM MASK MASK USE
BWOM PERSISTENT (USE MASKED REGISTER) MASKED BLOCK 1 1 0 1 X 1 ROW COLUMN X COLUMN USE USE
WRITE TO DRAM (A2 - A8) MASK
REGISTER OPERATIONS
LMR LOAD MASK REGISTER 1 1 1 1 X 0 ROW4X X WRITE LOAD X
MASK
LCR LOAD COLOR REGISTER 1 1 1 1 X 1 ROW4X X COLOR X LOAD
DATA
TRANSFER OPERATIONS
RT READ TRANSFER (DRAM-TO-SAM TRANSFER 1 0 1 0 X X ROW TAP5XX XX
SRT SPLIT READ TRANSFER (SPILT DRAM-TO-SAM TRANSFER) 1 0 1 1 X X ROW TAP5XX XX
WT WRITE TRANSFER (SAM-TO-DRAM TRANSFER) 1 0 0 0 0 X ROW TAP5XX XX
PWT PSEUDO WRITE TRANSFER (SERIAL-INPUT-MODE ENABLE) 1 0 0 0 1 X ROW4TAP5XX XX
AWT ALTERNATE WRITE TRANSFER 1 0 0 1 X X ROW TAP5XX XX
(SAM-TO-DRAM TRANSFER)
/////W/////E
3-39
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REV. 3/97
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CAPACITANCE
PARAMETER SYMBOL MIN MAX UNITS NOTES
Input Capacitance: A0-A8 CI17pF2
Input Capacitance: /R/A/S, /C/A/S, ?M/E/?W/E, /T/R//O/E, SC, /S/E, DSF CI27pF2
Input/Output Capacitance: DQ, SDQ CI/O7pF2
Output Capacitance: QSF CO9pF2
ABSOLUTE MAXIMUM RATINGS*
Voltage on Vcc Supply Relative to Vss.............. -1V to +7V
Operating Temperature, TA (Ambient)..... 55°C to +125°C
Storage Temperature (Plastic).................... -65°C to +150°C
Power Dissipation ............................................................. 1W
Short Circuit Output Current ..................................... 50mA
Lead Temperature (soldering 10 seconds) .............. +300°C
Junction Temperature ............................................... +165°C
RECOMMENDED DC OPERATING CONDITIONS
(-55°C ≤ TA ≤ 125°C)
PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES
Supply Voltage VCC 4.5 5.5 V 1
Input High (Logic 1) Voltage, All Inputs VIH 2.4 VCC+.5 V 1
Input Low (Logic 0) Voltage, All Inputs VIL -.5 0.8 V 1
*Stresses greater than those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indi-
cated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS
(-55°C ≤ TA ≤ 125°C; VCC = 5V ±10%)
PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES
INPUT LEAKAGE CURRENT IL-5 5 µA
Any input (0V ≤ VIN ≤ VCC); all other pins not under test = 0V
OUTPUT LEAKAGE CURRENT IOZ -5 5 µA
(DQ, SDQ disabled, 0V ≤ VOUT ≤ VCC)
OUTPUT LEVELS VOH 2.4 V
Output High Voltage (IOUT = -2.5mA) 1
Output Low Voltage (IOUT = 2.5mA) VOL 0.5 V
3-40
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CURRENT DRAIN, SAM ACTIVE (tSC = MIN)
(-55°C ≤ TA ≤ 125°C; VCC = 5V ±10%)
PARAMETER/CONDITION SYMBOL -8 -10 -12 UNITS NOTES
OPERATING CURRENT ICC7150 130 120 mA 3, 4,
(/R/A/S and /C/A/S = Cycling: tRC = tRC (MIN)) 26
OPERATING CURRENT: FAST PAGE MODE ICC8140 120 110 mA 3, 4,
(/R/A/S = VIL; /C/A/S = Cycling: tPC = tPC (MIN)) 27
STANDBY CURRENT: TTL INPUT LEVELS
Power supply standby current ICC935 30 25 mA 3, 4
(/R/A/S = /C/A/S = VIH after 8 /R/A/S cycles (MIN), other inputs ≥ VIH or ≤ VIL)
REFRESH CURRENT: /R/A/S-ONLY ICC10 150 130 120 mA 3, 4,
(/R/A/S = Cycling; /C/A/S = VIH)26
REFRESH CURRENT: ?C/A/S-BEFORE-/R/A/SI
CC11 150 130 120 mA 3, 4, 5
(/R/A/S and /C/A/S = Cycling)
SAM/DRAM DATA TRANSFER ICC12 160 130 125 mA 3, 4
MAX
MAX
CURRENT DRAIN, SAM IN STANDBY
(-55°C ≤ TA ≤ 125°C; VCC = 5V ±10%)
PARAMETER/CONDITION SYMBOL -8 -10 -12 UNITS NOTES
OPERATING CURRENT ICC195 90 80 mA 3, 4
(/R/A/S and /C/A/S = Cycling: tRC = tRC (MIN)) 26
OPERATING CURRENT: FAST PAGE MODE ICC285 75 65 mA 3, 4
(/R/A/S = VIL; /C/A/S = Cycling: tPC = tPC (MIN)) 27
STANDBY CURRENT: TTL INPUT LEVELS
Power supply standby current ICC388 8mA4
(/R/A/S = /C/A/S = VIH after 8 /R/A/S cycles (MIN), other inputs ≥ VIH or ≤ VIL)
REFRESH CURRENT: /R/A/S-ONLY ICC495 90 80 mA 3, 26
(/R/A/S = Cycling; /C/A/S = VIH)
REFRESH CURRENT: ICC595 90 80 mA 3, 5
?C/A/S-BEFORE-/R/A/S (/R/A/S and /C/A/S = Cycling)
SAM/DRAM DATA TRANSFER ICC6105 95 95 mA 3
3-41
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DRAM TIMING PARAMETERS
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9, 10, 11, 12, 13) (-55°C ≤ TA ≤ +125°C; VCC = 5V ±10%)
AC CHARACTERISTICS -8 -10 -12
PARAMETER SYM MIN MAX MIN MAX MIN MAX UNITS NOTES
Random READ or WRITE cycle time tRC 150 180 210 ns
READ-MODIFY-WRITE cycle time tRWC 195 235 275 ns
FAST-PAGE-MODE READ or WRITE tPC 45 55 65 ns
cycle time
FAST-PAGE-MODE READ-MODIFY-WRITE tPRWC 90 110 130 ns
cycle time
Access time from /R/A/StRAC 80 100 120 ns 14
Access time from /C/A/StCAC 20 25 30 ns 15
Access time from (/T/R)//O/EtOE 20 25 30 ns
Access time from column address tAA 40 50 60 ns
Access time from /C/A/S precharge tCPA 45 50 50 ns
/R/A/S pulse width tRAS 80 20,000 100 20,000 100 20,000 ns
/R/A/S pulse width (FAST PAGE MODE) tRASP 80 100,000 100 100,000 100 100,000 ns
/R/A/S hold time tRSH 20 25 30 ns
/R/A/S precharge time tRP 60 70 80 ns
/C/A/S pulse width tCAS 20 10,000 25 10,000 30 10,000 ns
/C/A/S hold time tCSH 80 100 120 ns
/C/A/S precharge time tCP 10 12 15 ns
/R/A/S to /C/A/S delay time tRCD 20 60 25 75 25 90 ns 17
/C/A/S to /R/A/S precharge time tCRP 5 5 10 ns
Row address setup time tASR 0 0 0 ns
Row address hold time tRAH 10 15 15 ns
/R/A/S to column tRAD 15 40 20 50 20 60 ns 18
address delay time
Column address setup time tASC 0 0 0 ns
Column address hold time tCAH 15 20 20 ns
Column address hold time tAR 60 70 80 ns
(referenced to /R/A/S)
Column address to tRAL 40 50 60 ns
/R/A/S lead time
Read command setup time tRCS 0 0 0 ns
Read command hold time tRCH 0 0 0 ns 19
(referenced to /C/A/S)
Read command hold time tRRH 0 0 0 ns 19
(referenced to /R/A/S)
/C/A/S to output in Low-Z tCLZ 0 0 0 ns
Output buffer tOFF 0 20 0 20 0 20 ns 20, 23
turn-off delay
Output disable tOD 0 20 0 20 0 25 ns 20, 23
Output disable hold time from start of WRITE tOEH 20 20 25 ns 25
?O/E LOW to /R/A/S HIGH delay time tROH 0 0 0 ns
3-42
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REV. 3/97
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DRAM TIMING PARAMETERS (continued)
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9, 10, 11, 12, 13) (-55°C ≤ TA ≤ +125°C; VCC = 5V ±10%)
AC CHARACTERISTICS -8 -10 -12
PARAMETER SYM MIN MAX MIN MAX MIN MAX UNITS NOTES
Write command setup time tWCS 0 0 0 ns 21
Write command hold time tWCH 15 20 25 ns
Write command hold time tWCR 60 70 80 ns
(referenced to /R/A/S)
Write command pulse width tWP 15 20 25 ns
Write command to /R/A/S lead time tRWL 20 25 30 ns
Write command to /C/A/S lead time tCWL 20 25 30 ns
Data-in setup time tDS000ns22
Data-in hold time tDH 15 20 25 ns 22
Data-in hold time tDHR 60 70 80 ns
(referenced to /R/A/S)
/R/A/S to ?W/E delay time tRWD 105 125 150 ns 21
Column address tAWD 65 75 90 ns 21
to ?W/E delay time
/C/A/S to ?W/E delay time tCWD 45 50 60 ns 21
Transition time (rise or fall) tT 3 50 3 50 3 50 ns 9, 10
Refresh period (512 cycles) tREF 8 8 8 ms
/R/A/S to /C/A/S precharge time tRPC 0 0 0 ns
/C/A/S setup time tCSR 10 10 10 ns 5
(/C/A/S-BEFORE-/R/A/S REFRESH)
/C/A/S hold time tCHR 15 20 25 ns 5
(/C/A/S-BEFORE-/R/A/S REFRESH)
?M/E/?W/E to /R/A/S setup time tWSR 0 0 0 ns
?M/E/?W/E to /R/A/S hold time tRWH 15 15 15 ns
Mask Data to /R/A/S setup time tMS000ns
Mask Data to /R/A/S hold time tMH 15 15 15 ns
3-43
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TRANSFER AND MODE CONTROL TIMING PARAMETERS
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes 6, 7, 8, 9, 10) (-55° C ≤ TA ≤ +125°C; VCC = 5V ±10%)
AC CHARACTERISTICS -8 -10 -12
PARAMETER SYM MIN MAX MIN MAX MIN MAX UNITS NOTES
/T/R/(?O/E) LOW to /R/A/S setup time tTLS 0 0 0 ns
/T/R/(?O/E) LOW to /R/A/S hold time tTLH 10 10,000 15 10,000 15 10,000 ns
/T/R/(?O/E) LOW to /R/A/S hold time tRTH 75 10,000 80 10,000 90 10,000 ns
(REAL-TIME READ TRANSFER only)
/T/R/(?O/E) LOW to /C/A/S hold time tCTH 25 25 30 ns
(REAL-TIME READ TRANSFER only)
/T/R/(?O/E) HIGH to SC lead time tTSL 5 5 5 ns
/T/R/(?O/E) HIGH to /R/A/S precharge time tTRP 60 70 80 ns
/T/R/(?O/E) precharge time tTRW 20 30 35 ns
First SC edge to /T/R/(?O/E) HIGH tTSD 15 15 15 ns
delay time
Serial output buffer turn-off tSDZ 7 40 7 40 7 40 ns
delay from /R/A/S
SC to /R/A/S setup time tSRS 30 35 40 ns
Serial data input to /S/E delay time tSZE 0 0 0 ns
Serial data input delay from /R/A/StSDD 50 50 55 ns
Serial data input to /R/A/S delay time tSZS 0 0 0 ns
Serial-input-mode enable tESR 0 0 0 ns
(/S/E) to /R/A/S setup time
Serial-input-mode enable tREH 10 15 15 ns
(/S/E) to /R/A/S hold time
/T/R/(?O/E) HIGH to /R/A/S setup time tYS 0 0 0 ns
/T/R/(?O/E) HIGH to /R/A/S hold time tYH 10 15 15 ns
DSF to /R/A/S setup time tFSR 0 0 0 ns
DSF to /R/A/S hold time tRFH 10 15 15 ns
SC to QSF delay time tSQD 30 30 30 ns
SPLIT TRANSFER setup time tSTS 30 30 30 ns
SPLIT TRANSFER hold time tSTH 0 0 0 ns
/R/A/S to QSF delay time tRQD 75 75 75 ns
DSF to /R/A/S hold time tFHR 60 70 80 ns
DSF to /C/A/S setup time tFSC 0 0 0 ns
DSF to /C/A/S hold time tCFH 15 20 25 ns
/T/R/?O/E to QSF delay time tTQD 30 30 30 ns
/C/A/S to QSF delay time tCQD 40 40 40 ns
/R/A/S to first SC delay tRSD 85 100 115 ns
/C/A/S to first SC delay tCSD 30 40 45 ns
3-44
MT42C4256 883C Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
REV. 3/97
DS000016
MT42C4256 883C
256K x 4 VRAM
Limited Supply - Consult Factory
AUSTIN SEMICONDUCTOR, INC.
SAM TIMING PARAMETERS
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes 6, 7, 8, 9, 10) (-55° C ≤ TA ≤ +125°C; VCC = 5V ±10%)
AC CHARACTERISTICS -8 -10 -12
PARAMETER SYM MIN MAX MIN MAX MIN MAX UNITS NOTES
Serial clock-cycle time tSC 25 30 35 ns
Access time from SC tSAC 25 30 35 ns 24, 28
SC precharge time (SC LOW time) tSP 10 10 10 ns
SC pulse width (SC HIGH time) tSAS 10 10 10 ns
Access time from /S/EtSEA 20 25 30 ns 24
/S/E precharge time tSEP 7 10 15 ns
/S/E pulse width tSE 10 15 15 ns
Serial data-out hold time after tSOH 0 0 0 ns 24, 28
SC high
Serial output buffer turn-off tSEZ 0 15 0 15 0 15 ns 20, 24
delay from /S/E
Serial data-in setup time tSDS 0 0 0 ns
Serial data-in hold time tSDH 10 15 20 ns
Serial input (Write) Enable tSWS 0 0 0 ns
setup time
Serial input (Write) Enable tSWH 15 20 25 ns
hold time
Serial input (Write) disable tSWIS 0 0 0 ns
setup time
Serial input (Write) disable tSWIH 15 20 25 ns
hold time
3-45
MT42C4256 883C Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
REV. 3/97
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MT42C4256 883C
256K x 4 VRAM
Limited Supply - Consult Factory
AUSTIN SEMICONDUCTOR, INC.
19. Either tRCH or tRRH must be satisfied for a READ
cycle.
20. tOD, tOFF and tSEZ define the time when the output
achieves open circuit (VOH -200mV, VOL +200mV).
This parameter is sampled and not 100 percent tested.
21. tWCS, tRWD, tAWD and tCWD are restrictive
operating parameters in LATE-WRITE, READ-WRITE
and READ-MODIFY-WRITE cycles only. If tWCS ≥
tWCS (MIN), the cycle is an EARLY-WRITE cycle and
the data output will remain an open circuit through-
out the entire cycle, regardless of /T/R/?O/E. If tWCS ≤
tWCS (MIN), the cycle is a LATE-WRITE and
/T/R/?O/E must control the output buffers during the
WRITE to avoid data contention. If tRWD ≥ tRWD
(MIN), tAWD ≥ tAWD (MIN) and tCWD ≥ tCWD
(MIN), the cycle is a READ-WRITE and the data
output will contain data read from the selected cell. If
neither of the above conditions is met, the state of the
output buffers (at access time and until /C/A/S goes
back to VIH) is indeterminate but the WRITE will be
valid, if tOD and tOEH are met. See the LATE-WRITE
AC Timing diagram.
22. These parameters are referenced to /C/A/S leading edge
in EARLY-WRITE cycles and ?M/E/?W/E leading edge in
LATE-WRITE or READ-WRITE cycles.
23. During a READ cycle, if /T/R//O/E is LOW then taken
HIGH, DQ goes open. The DQs will go open with /O/E
or /C/A/S, whichever goes HIGH first.
24. SAM output timing is measured with a load
equivalent to 1 TTL gate and 30pF. Output reference
levels: VOH = 2.0V; VOL = 0.8V.
25. tOD and tOEH must be met in LATE-WRITE and
READ-MODIFY-WRITE cycles (/O/E HIGH during
WRITE cycle) in order to ensure that the output
buffers will be open during the WRITE cycle. The
DQs will provide previously read data if /C/A/S
remains LOW and /O/E is taken LOW after tOEH is
met. If /C/A/S goes HIGH prior to /O/E going back LOW,
the DQs will remain open.
26. Address (A0-A8) may be changed two times or less
while /R?A/S = VIL.
27. Address (A0-A8) may be changed once or less while
/C?A/S = VIH and /R?A/S = VIL.
28. tSAC is MAX at +125°C and 4.5V Vcc; tSOH is MIN at
-55°C and 5.5V Vcc. These limits will not occur
simultaneously at any given voltage or temperature.
tSOH = tSAC - output transition time; this is guaran-
teed by design.
NOTES
1. All voltages referenced to VSS.
2. This parameter is sampled. VCC = 5V ±10%, f = 1 MHz.
3. ICC is dependent on cycle rates.
4. ICC is dependent on I/O loading. Specified values are
obtained with minimum cycle time and the I/Os
open.
5. Enables on-chip refresh and address counters.
6. The minimum specifications are used only to indicate
cycle time at which proper operation over the full
temperature range (-55°C ≤ TA ≤ +125°C) is assured.
7. An initial pause of 100µs is required after power-up
followed by any eight /R/A/S cycles before proper
device operation is assured. The eight /R/A/S cycle
wake-up should be repeated any time the tREF
refresh requirement is exceeded.
8. AC characteristics assume tT = 5ns.
9. VIH (MIN) and VIL (MAX) are reference levels for
measuring timing of input signals. Transition times
are measured between VIH and VIL (or between VIL
and VIH). Input signals transition between 0V and 3V
for AC testing.
10. In addition to meeting the transition rate specifica-
tion, all input signals must transit between VIH and
VIL (or between VIL and VIH) in a monotonic manner.
11. If /C/A/S = VIH, DRAM data output (DQ1-DQ4) is
High-Z.
12. If /C/A/S = VIL, DRAM data output (DQ1-DQ4) may
contain data from the last valid READ cycle.
13. DRAM output timing measured with a load equiva-
lent to 2 TTL gates and 100pF. Output reference
levels: VOH = 2.0V; VOL = 0.8V.
14. Assumes that tRCD < tRCD (MAX). If tRCD is greater
than the maximum recommended value shown in this
table, tRAC will increase by the amount that tRCD
exceeds the value shown.
15. Assumes that tRCD ≥ tRCD (MAX).
16. If /C/A/S is LOW at the falling edge of /R/A/S, DQ will be
maintained from the previous cycle. To initiate a new
cycle and clear the data out buffer, /C/A/S must be
pulsed HIGH for tCPN.
17. Operation within the tRCD (MAX) limit ensures that
tRAC (MAX) can be met. tRCD (MAX) is specified as
a reference point only; if tRCD is greater than the
specified tRCD (MAX) limit, then access time is
controlled exclusively by tCAC.
18. Operation within the tRAD (MAX) limit ensures that
tRCD (MAX) can be met. tRAD (MAX) is specified as
a reference point only; if tRAD is greater than the
specified tRAD (MAX) limit, then access time is
controlled exclusively by tAA.
3-46
MT42C4256 883C Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
REV. 3/97
DS000016
MT42C4256 883C
256K x 4 VRAM
Limited Supply - Consult Factory
AUSTIN SEMICONDUCTOR, INC.
DRAM READ CYCLE
V
VIH
IL
CAS
V
VIH
IL
RAS
tCRP
tRAS
tRC tRP
tCSH tRSH
tCAS
tRCD
V
VIH
IL
ME/WE
V
VIH
IL
DSF
V
VIOH
IOL
DQ
TR/OE
V
VIH
IL
ADDR
,
,
tASR
tRAD tRAL
tCAH
VALID DATA
tRAH tASC
ROW ROW
tRCH
,,
,,,
,,,
,
,,
,,,
,,
,,
,,,
,
,,
,,
OPENOPEN
,,
,,,
,,,
,,
,,,
,,
,,
COLUMN
,,
,,,
,,
tRRH
tRCS
tFHRtFSC tCFH
tRFH
tFSR
tYS tYH tOE tOD
tOFF
tCAC
tRAC
tAA
tAR
,,
,,,,
,,,
,
DON’T CARE
UNDEFINED
,
,,
,
tROH
V
VIH
IL
3-47
MT42C4256 883C Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
REV. 3/97
DS000016
MT42C4256 883C
256K x 4 VRAM
Limited Supply - Consult Factory
AUSTIN SEMICONDUCTOR, INC.
DRAM FAST-PAGE-MODE READ CYCLE
,,
,,
,,
,,
V
VIH
IL
CAS
V
VIH
IL
RAS
V
VIH
IL
ADDR
V
VIH
IL
ME/WE
,
,,
tRASP tRP
ROW
,,
COLUMN
,,
,
COLUMN
,,,
,,
ROW
V
VIH
IL
DSF
V
VIH
IL
TR/OE
V
VIOH
IOL
COLUMN
,,
,
tCRP
tCSH tCAS
tRCD
tASR tRAH
tRAD tASC
tAR
tCAH tASC tCAH tASC tCAH
tRAL
tCP
tCAS
tCP
tRSH
tCAS
tCP
tPC
,
,,
,,
,,
,,
,,
,,,
,,,
,,,
,,
,,
,,
VALID
DATA
,,
,,,,
,,
,,
,,,
,,
,,,
,,
,,
,
,
,,
tRCH
tRCS
tRCH
tRCS tRCH
tRRH
tCFH
tFSC
tCFH
tFSC
tCFH
tFSC
tRFH
tFSR
tYH
tYS tOD
tOE tOD
tOE tOD
tOE
VALID
DATA
VALID
DATA
tCLZ tCLZ tOFF
tCAC
tCPA
tAA
tOFF
tCAC
tCPA
tAA
tOFF
tCAC
tRAC
tAA
OPEN
tFHR
,
,,,
,,,
DON’T CARE
UNDEFINED
,
,,
DQ
tRCS
NOTE: WRITE cycles or READ-MODIFY-WRITE cycles may be mixed with READ cycles while in FAST PAGE MODE.
3-48
MT42C4256 883C Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
REV. 3/97
DS000016
MT42C4256 883C
256K x 4 VRAM
Limited Supply - Consult Factory
AUSTIN SEMICONDUCTOR, INC.
WRITE CYCLE FUNCTION TABLE 1
LOGIC STATES
/R/A/S Falling Edge /C/A/S Falling Edge
FUNCTION A B C D E2
?M/E/?W/E DSF DQ (Input) DSF DQ (Input)
Normal DRAM WRITE 1 0 X 0 DRAM Data
NONPERSISTENT (Load and Use) 0 0 Write 0 DRAM
MASKED WRITE to DRAM Mask Data (Masked)
PERSISTENT (Use Register) 0 1 X 0 DRAM
MASKED WRITE to DRAM Data (Masked)
BLOCK WRITE to DRAM (No Data Mask) 1 0 X 1 Column Mask3
NONPERSISTENT (Load and Use) 0 0 Write 1 Column
MASKED BLOCK WRITE to DRAM Mask Mask3
PERSISTENT (Use Register) 0 1 X 1 Column
MASKED BLOCK WRITE to DRAM Mask3
Load Mask Register 1 1 X 0 Write Mask
Load Color Register 1 1 X 1 Color Data
NOTE: 1. Refer to this function table to determine the logic states of “A”, “B”, “C”, “D” and “E” for the WRITE cycle
timing diagrams on the following pages.
2. //C/A//S or ?M/E/?W/E, whichever occurs later (Except BLOCK WRITE).
3. ?W/E = “don’t care” for BLOCK WRITE. The DQ column-mask data will be latched at the falling edge of ?C/A/S,
regardless of the state of ?M/E/?W/E.
3-49
MT42C4256 883C Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
REV. 3/97
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MT42C4256 883C
256K x 4 VRAM
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AUSTIN SEMICONDUCTOR, INC.
NOTE: 1. The logic states of “A”, “B”, “C”, “D” and “E” determine the type of WRITE operation performed. See the Write
Cycle Function Table for a detailed description.
2. For BLOCK WRITE, ?M/E/?W/E = “don’t care.” For all other EARLY-WRITE cycles, ?M/E/?W/E = LOW.
V
VIH
IL
CAS
V
VIH
IL
ADDR
V
VIH
IL
RAS
,,
,,
tASR
tCRP
,,
,,
tRAD
,,
,,,
,
tRAS
tRC tRP
tCSH tRSH
tCAS
tRAL
tCAH
COLUMN
tRCD
tAR
tRAH tASC
ROW
V
VIH
IL
ME/WE
,,
,,,
tWP
tWSR tRWH
A
ROW
V
VIH
IL
DSF
,,
,
tFSR
,
,,
,,
,,,,
,,,,
,,
tRFH
BD
t
V
VIOH
IOL
DQ
,
,,
tMH
,,
,,
,
,,,
,,,,
,,,
C
tDS
tMS
E
TR/OE
,,,
,,,
,,,,
,,,,
,,,
,,
,,
,,,
tYS tYH
tWCS tWCH
tWCR
tRWL
tCWL
tCFH
tFHR
tDHR tDH
V
VIH
IL
DON’T CARE
UNDEFINED
,
,
,,
,,
,,,,
,,,,
,,
,,
FSC
NOTE 2
DRAM EARLY-WRITE CYCLE 1
3-50
MT42C4256 883C Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
REV. 3/97
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MT42C4256 883C
256K x 4 VRAM
Limited Supply - Consult Factory
AUSTIN SEMICONDUCTOR, INC.
DRAM LATE-WRITE CYCLE 1
V
VIH
IL
CAS
V
VIH
IL
ADDR
V
VIH
IL
ME/WE
V
VIH
IL
RAS
V
VIH
IL
DSF
TR/OE
V
VIOH
IOL
,,
tASR
tCRP
,,
tRAD
,
,,,
,,,
,,
,,,
,,
,,,,
,,,
,,
,,
,
tFSR
,
,,
,,
,,,,
,,,,
,,
,,
,
tMH
,
,,,
,,
,
,,,,
,,,
,,,,
,
,,
,,,
,,
,,,
,
tRAS
tRC tRP
tCSH tRSH
tCAS
tRAL
tCAH
tCWL
tRWL
tWP
COLUMN
tRCD
tAR
tRAH tASC
ROW
tWSR tRWH
tRFH
A
B
C
tFSC
tDH
tDS
tMS
tYS tYH
tFHR
E
DON’T CARE
UNDEFINED
,,
,,
,,
DQ
tDHR
,,
,,,
,,,,
,,,
,
tOD tOEH
,
,,,
,
tCFH
V
VIH
IL
NOTE: 1. The logic states of “A”, “B”, “C” and “E” determine the type of WRITE operation performed. See the Write
Cycle Function Table for a detailed description.
3-51
MT42C4256 883C Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
REV. 3/97
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AUSTIN SEMICONDUCTOR, INC.
DRAM READ-WRITE CYCLE
(READ-MODIFY-WRITE CYCLE)
NOTE: The logic states of “A”, “B”, “C” and “E” determine the type of WRITE operation performed. See the Write Cycle
Function Table for a detailed description.
,
,,
V
VIH
IL
CAS
V
VIH
IL
RAS
V
VIH
IL
ADDR
V
VIH
IL
ME/WE
,,
,,
tRAS tRP
tRAH
ROW
,,
,
tCRP
tASR
,,
,,
A
,,
,,
tAR
tRCD
tRAD
tRCS tWP
ROW
tCAS
COLUMN
,
,,,
,,,,
,,
tASC
,
,,
B
,,,
,,
,,,
,,,
,,,
,
C
tRWC
tRSH
tCSH
tRAL
tCAH
tRWL
tCWL
tAWD
tCWD
tRWD
tRWH
tWSR
tRFH
tFSR
tMH
tMS
tYH
tYS
tFSC tCFH
tFHR
tCAC
tRAC
tAA
tOE tOD
VALID D
E
tDH
tDS
OPEN
OUT
V
VIH
IL
TR/OE
V
VIOH
IOL
V
VIH
IL
DSF
DON’T CARE
UNDEFINED
,
,
,
DQ
3-52
MT42C4256 883C Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
REV. 3/97
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MT42C4256 883C
256K x 4 VRAM
Limited Supply - Consult Factory
AUSTIN SEMICONDUCTOR, INC.
DRAM FAST-PAGE-MODE EARLY-WRITE CYCLE
,
,,
V
VIH
IL
CAS
V
VIH
IL
RAS
V
VIH
IL
ADDR
V
VIH
IL
ME/WE
,,
,
tRASP tRP
tRAH
ROW
,,
,,
tCAS
tCSH
tCRP
tASR
tRSH
tCAH
COLUMN
,,
,,
tCAH
,
,,
tASC tCAH
COLUMN
,,
,,
,
A
,
tWSR
,,
,,
,,
,,
,
,
tRFH
,
tFSR
,,
,,,
tFSC tCFH
,,
,
tFSC tCFH
,,
,,,
,
,
,
,
tMS
,
,,
tDS
,
,
,
,,,
,
,,
,,
tAR
tRCD
tRAD tASC
tRWH
tWCS
tCWL tWCH
tWP
tWCS
tCWL
tWCH
tWP
tWCS
tCWL
tWCH
tWP
tASC
tRAL
ROW
tCP
tPC tCAS tCP tCAS tCP
A
B
D
B
tCFH
tFSC
tFHR
tWCR
tDHR
C
tMH tDH
E
tDS tDH tDS tDH
tYS
V
VIH
IL
DSF
V
VIH
IL
TR/OE
V
VIOH
IOL
tRWL
COLUMN
DON’T CARE
UNDEFINED
,
,,
,
DQ
,
,,,
,,,
,,,
,,,,
,,,,
,,,
,
tYH
D
E
D
E
NOTE: 1. READ cycles or READ-MODIFY-WRITE cycles can be mixed with WRITE cycles while in FAST PAGE
MODE.
2. The logic states of “A”, “B”, “C”, “D” and “E” determine the type of WRITE operation performed. See the Write
Cycle Function Table for a detailed description.
3-53
MT42C4256 883C Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
REV. 3/97
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MT42C4256 883C
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Limited Supply - Consult Factory
AUSTIN SEMICONDUCTOR, INC.
DRAM FAST-PAGE-MODE READ-WRITE CYCLE
(READ-MODIFY-WRITE OR LATE-WRITE CYCLES)
NOTE: 1. READ or WRITE cycles can be mixed with READ-MODIFY-WRITE cycles while in FAST PAGE MODE. Use
the Write Function Table to determine the proper DSF state for the desired WRITE operation.
2. The logic states of “A”, “B” and “C” determine the type of WRITE operation performed. See the Write Cycle
Function Table for a detailed description.
V
VIH
IL
CAS
V
VIH
IL
RAS
V
VIH
IL
ADDR
V
VIH
IL
ME/WE
,,
,
tRASP tRP
ROW
,,
,
COLUMN
,
,,
,,
,,
COLUMN
,,
,,,
,
ROW
V
VIH
IL
TR/OE
V
VIOH
IOL
COLUMN
,,
,,
,
,,
C
,
,
,,
,,
,,
,
tCRP
tCSH tCAS
tRCD
tASR tRAH
tRAD tASC
tAR
tCAH tASC tCAH tASC tCAH
tRAL
tCP
tCAS
tCP
tRSH
tCAS
tCP
tWSR tRWH
tMS tMH
tYS tYH tOE
tOD tOE tOD tOE
tOD
OPEN
VALID
DIN
VALID
D
A
tCAC tCLZ
tCAC tCLZ
tCAC
tDS
tDH
tDS
tDH
tDS
tDH
tAA
tRAC
tAA
tCPA
tAA
tCPA
tRWL
tCWL
tWP
tAWD
tCWD
tAWD
tCWD
tAWD
tCWD
tRWD
tRCS tCWL
tWP
tCWL
tWP
DON’T CARE
UNDEFINED
,,
,,
DQ
tOEH
V
VIH
IL
DSF
,
,,
,
,
,,
,
,
,,
tFSR tRFH
B
tFSC tCFH tFSC tCFH tFSC tCFH
tPRWC
VALID
DOUT VALID
DOUTOUT IN
VALID
D IN
VALID
D
,,,
,,
3-54
MT42C4256 883C Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
REV. 3/97
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DRAM /////R// ///A// ///S-ONLY REFRESH CYCLE
(ADDR = A0-A8)
DRAM /////C// ///A// ///S-BEFORE-/////R// ///A// ///S REFRESH CYCLE
,,,
,,
,,
,,,,
,,,
,,,
,,,
V
VIH
IL
CAS
V
VIH
IL
ADDR
V
VIH
IL
ME/WE
V
VIH
IL
RAS
TR/OE V
VIH
IL
,,
,,
,,
,,,
,,,,
,,,
,
,,
,
tYS
V
VIOH
IOL
tCRP
tASR tRAH
ROW
OPEN
tRP
tRAS
tRC
ROW
tYH
V
VIH
IL
DSF
,,
,,,,
,,,
,,,
,,,,
,,,,
,,,
,,,
DQ
,,
,,,
,,,
,,,,
,,,,
,,,
,,,
,,,
tRPC
OPEN
V
VIH
IL
CAS
V
VIH
IL
ADDR
V
VIH
IL
ME/WE
V
VIH
IL
RAS
V
VIH
IL
DSF
TR/OE V
VIH
IL
V
VIOH
IOL
tCSR
OPEN
tRAS
tCHR
tRP
DON’T CARE
UNDEFINED
,
,
,
DQ
,,
,,
,
,
tRPC
tCP
tRP
,,,
,,
tRPC tCSR
,,
,
tCHR
tRAS
OPEN
,,
,,,
,,,
,,,,
,,,,
,,,
,,,,
,,
,,
,,,,
,,,,
,,,
,,,
,,,,
,,,,
,,
,,
,,,,
,,,
,,,
,,,,
,,,,
,,,
,,
,,
,,,
,,,
,,,,
,,,,
,,,
,,,
,,,
3-55
MT42C4256 883C Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
REV. 3/97
DS000016
MT42C4256 883C
256K x 4 VRAM
Limited Supply - Consult Factory
AUSTIN SEMICONDUCTOR, INC.
NOTE: A HIDDEN REFRESH may also be performed after a WRITE or TRANSFER cycle. In the WRITE case,
?M/E/?W/E = LOW (when /C/A/S goes LOW) and /T/R//O/E = HIGH and the DQ pins stay High-Z. In the TRANSFER
case, /T/R//O/E = LOW (when /R/A/S goes LOW) and the DQ pins stay High-Z during the refresh period, regardless
of /T/R//O/E.
DRAM HIDDEN-REFRESH CYCLE
tYS
ROW
V
VIH
IL
CAS
V
VIH
IL
ADDR
V
VIH
IL
ME/WE
V
VIH
IL
RAS
V
VIH
IL
DSF
TR/OE V
VIH
IL
V
VIOH
IOL
,,
,,,
,,,
,,,
,
,,
,,,,
,,,,
,,,
,,
,,
,
,
,,
,
,
,
,,,
,,,,
,,,,
,,,
,
,,
(READ) (REFRESH)
COLUMN
OPEN
tYH tOE tOD
tOFF
VALID DOUT
tCAC
tRAC
tAA
tCFH
tFSC
tFHR
tRFH
tFSR
tRCS tRRH
tASC tCAH
tRAL
tRAH
tASR
tRAD
tAR
tCRP tRCD tRSH
tRAS tRP tRAS
tCHR
,,
,,,
,,
DON’T CARE
UNDEFINED
,,
,,
,
DQ
tROH
OPEN
3-56
MT42C4256 883C Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
REV. 3/97
DS000016
MT42C4256 883C
256K x 4 VRAM
Limited Supply - Consult Factory
AUSTIN SEMICONDUCTOR, INC.
READ TRANSFER 3
(DRAM-TO-SAM TRANSFER)
(When part was previously in the SERIAL INPUT mode or SC idle)
V
VIH
IL
CAS
V
VIH
IL
RAS
tCRP
tRAS
tRC tRP
tCSH tRSH
tCAS
tRCD
V
VIH
IL
ADDR
,
,
tASR
,,
,
,,
,,,,
,,,
,,,,
,,
tCAH
SAM START (TAP)
tRAH tASC
ROW
V
VIH
IL
ME/WE
V
VIH
IL
DSF
TR/OE
,,
,,,,
,,,
,,,,
,,,,
,,,
,,
,,
tWSR
V
VIH
IL
V
VIOH
IOL
V
VIOH
IOL
,,
,,,,
,,,,
,,,
,,,
,,,,
,,
,
,
,,,
,
,,,
,,,,
,,
,,,
,,,
,,,
,,,,
,,
SC V
VIH
IL
SE V
VIH
IL
QSF V
VOH
OL
tRAL
tRAD
tAR
tRWH
tRFH
tFSR
tOFF
tTLS tTLH
tSRS
tSAS
tSDH
tSDS tSZS
VALID DIN
tSWH
VALID DOUT VALID DOUT VALID DOUT
tSEA
tSOH
tSAC
tSAC
tSAS
tTQD
tSP
tSC
tTRW
SDQ
DON’T CARE
UNDEFINED
,
,
,,
,,
DQ
tCSD
tRSD
OPEN
NOTE 2
tRQD
tCQD
NOTE 2
,
,,,
,,,,
,,,
,
NOTE 1
tTSD
tTRP
tRTH
OPEN
NOTE: 1. There must be no rising edges on the SC input during this time period.
2. QSF = 0 when the Lower SAM (bits 0–255) is being accessed.
QSF = 1 when the Upper SAM (bits 256–511) is being accessed.
3. If tTLH is timing for the /T/R/(?O/E) rising edge, the transfer is self-timed and the tCSD and tRSD times must be
met. If tRTH is timing for the /T/R/(?O/E) rising edge, the transfer is done off of the /T/R/(?O/E) rising edge and
tTSD must be met.
3-57
MT42C4256 883C Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
REV. 3/97
DS000016
MT42C4256 883C
256K x 4 VRAM
Limited Supply - Consult Factory
AUSTIN SEMICONDUCTOR, INC.
REAL-TIME READ-TRANSFER
(DRAM-TO-SAM TRANSFER)
(When part was previously in the SERIAL OUTPUT mode)
V
VIH
IL
CAS
V
VIH
IL
RAS
tCRP
tRAS
tRC tRP
tCSH tRSH
tCAS
tRCD
V
VIH
IL
ADDR
,
,
,
,
,,,
,,,,
,,,
,,,,
,,,
SAM START
ROW
tASR tCAH
RAH tASC
t
V
VIH
IL
ME/WE
V
VIH
IL
DSF
,,
,,,
,,,,
,,,,
,,,
,,,,
,,,
,,
,
tWSR
,,
,,,,
,,,
,,,,
,,,,
,,,
,,
,
,
tRFH
tFSR
TR/OE V
VIH
IL
V
VIOH
IOL
DQ
,,,
,
,,
,,,
,,,
tOFF
OPEN OPEN
tTLS
tTRP
tTRW
tCTH
tSAS
tSP tSP
SC
t
SC V
VIH
IL
VALID DOUT
tSAC
VALID DOUT VALID DOUT VALID DOUT VALID DOUT
NEW ROW DATAPREVIOUS ROW DATA
VALID
DOUT
tSEZ
,,,
,,
V
VIH
IL
SE
tSEA
tSE tSEP
V
VIOH
IOL
SDQ
tTSD
tTSL
tRTH
tRAD
tAR tRAL
tRWH
QSF V
VOH
OL
DON’T CARE
UNDEFINED
,
,
,,
NOTE 2
tTQD
NOTE 2
tSEA
NOTE 1
NOTE: 1. The /S/E pulse is shown to illustrate the SERIAL OUTPUT
ENABLE and DISABLE timing. It is not required.
2. QSF = 0 when the Lower SAM (bits 0–255) is being accessed.
QSF = 1 when the Upper SAM (bits 256–511) is being accessed.
3-58
MT42C4256 883C Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
REV. 3/97
DS000016
MT42C4256 883C
256K x 4 VRAM
Limited Supply - Consult Factory
AUSTIN SEMICONDUCTOR, INC.
SPLIT READ TRANSFER
(SPLIT DRAM-TO-SAM TRANSFER)
V
VIH
IL
CAS
V
VIH
IL
RAS
tCRP
tRAS
tRC tRP
tCSH tRSH
tCAS
tRCD
V
VIH
IL
ADDR
,,
,,
,,
,,
,,
,,,
,,,,
,,,,
,,,
,
SAM START (B)ROW
tASR tCAH
RAH tASC
t
V
VIH
IL
ME/WE
V
VIH
IL
DSF
,,
,,,,
,,,
,,,
,,,,
,,,,
,,,
,,
,,
WSR
,
,,,
,,,,
,,,
,,,
,,,,
,,,
,,
,
tRWH
tRFH
tFSR
TR/OE V
VIH
IL
V
VIOH
IOL
DQ
,,
,,
tOFF
OPEN OPEN
tTLS
QSF V
VOH
OL
tSP
SC V
VIH
IL
253 (509) 254 (510) 255 (511) 256 + B(B)
V
VIH
IL
SE
V
VIOH
IOL
SDQ
t
RAD
tAR
tRAL
,
,,,
,,,,
,,,,
,,,
,,,
,,,,
,,
A (256 + A)511 (255)
tSOH
tSAC
tSOH
tSAC
SAM MSB (NOTE 1)
t
tTLH
tSTS
tSQD
tSTH
tSQD
tSP
tSAS
tSC
DON’T CARE
UNDEFINED
,,
,
NEW MSB
NOTE: 1. QSF = 0 when the Lower SAM (bits 0–255) is being accessed.
QSF = 1 when the Upper SAM (bits 256–511) is being accessed.
3-59
MT42C4256 883C Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
REV. 3/97
DS000016
MT42C4256 883C
256K x 4 VRAM
Limited Supply - Consult Factory
AUSTIN SEMICONDUCTOR, INC.
V
VIH
IL
CAS
V
VIH
IL
RAS
tCRP
tRAS
tRC tRP
tCSH tRSH
tCAS
tRCD
V
VIH
IL
ADDR
,
,,
,,
,
,,,
,,,,
,,,,
,,,
,
SAM START
tASR tCAH
tASC
V
VIH
IL
ME/WE
V
VIH
IL
DSF
,,
,,,
,,,,
,,,,
,,,
,,,,
,,
,
,,,
WSR tRWH
tRFH
tFSR
TR/OE IH
IL
V
VIOH
IOL
DQ
,,,
,,
tOFF
tTLS
tRAD
tAR
tRAL
t
tTLH
RAH
t
,
,,,
,,,
,,,,
,,,,
,,,
,,,
,,
,,
,,
,,
,,
,,
,,,
,
,
,,,
,,,,
,,,
,
tSWS
tSWIS
NOTE 2
tSDH
VALID DOUT
tSOH
tSAS
tSRS tRSD
tSP
tSC
tSAS tSP
V
V
SC V
VIH
IL
V
VIH
IL
SE
V
VIOH
IOL
SQD
ROW
NOTE 3
NOTE 1
VALID DOUT VALID DIN
,
,
VALID DIN
,,
,
HIGH Z
tSDS
SDH
t
tSDS
tESR tREH
tSDZ
tSDD
QSF V
VOH
OL
DON’T CARE
UNDEFINED
,,
,,
,,
tRQD
tCQD
NOTE 4 NOTE 4
OPEN OPEN
tCSD
,
,,,
,,,,
,,,,
,,,
,,,
,,,
NOTE: 1. If /S/E is LOW, the SAM data will be transferred to the DRAM.
If /S/E is HIGH, the SAM data will not be transferred to the DRAM (SERIAL-INPUT-MODE ENABLE cycle).
2. /S/E must be LOW to input new serial data, but the serial address register is incremented by SC regardless
of /S/E.
3. There must be no rising edges on the SC input during this time period.
4. QSF = 0 when the Lower SAM (bits 0–255) is being accessed.
QSF = 1 when the Upper SAM (bits 256–511) is being accessed.
WRITE TRANSFER and PSEUDO WRITE TRANSFER
(SAM-TO-DRAM TRANSFER)
(When part was previously in the SERIAL OUTPUT mode)
3-60
MT42C4256 883C Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
REV. 3/97
DS000016
MT42C4256 883C
256K x 4 VRAM
Limited Supply - Consult Factory
AUSTIN SEMICONDUCTOR, INC.
NOTE: 1. /S/E must be LOW to input new serial data, but the serial address
register is incremented by SC regardless of /S/E.
2. There must be no rising edges on the SC input during this time period.
3. QSF = 0 when the Lower SAM (bits 0–255) is being accessed.
QSF = 1 when the Upper SAM (bits 256–511) is being accessed.
WRITE TRANSFER
(SAM-TO-DRAM TRANSFER)
(When part was previously in the SERIAL INPUT mode)
V
VIH
IL
CAS
V
VIH
IL
RAS
tCRP
tRAS
tRC tRP
tCSH tRSH
tCAS
tRCD
V
VIH
IL
ADDR
,,
,,
,,
,,,
,,,
,,,,
,,,,
,,,
SAM START
tASR tCAH
tASC
V
VIH
IL
ME/WE
V
VIH
IL
DSF
,,
,,,,
,,,
,,,,
,,,,
,,,
,,
,,
,,
WSR tRWH
tRFH
tFSR
TR/OE
V
VIOH
IOL
DQ
,
,,
tOFF
OPEN OPEN
tTLS
tRAD
tAR
tRAL
t
tTLH
RAH
t
,,
,,,,
,,,
,,,
,,,,
,,,,
,,
,,
,,
,,
,,,
,,,,
,,,
,
,
,
,,
tSWS
tSWIS
NOTE 1
tSDS tSDS
VALID DIN
VALID DIN
VALID DIN
tSDH
tSAS
tSRS
tSDS
tRSD
tSP
tSC
tSAS tSP
SC V
VIH
IL
V
VIH
IL
SE
V
VIOH
IOL
SDQ
ROW
NOTE 2
tREH
tESR
QSF V
VOH
OL
DON’T CARE
UNDEFINED
,
,
,
,
tRQD
tCQD
NOTE 3 NOTE 3
tCSD
,,
,,
,,
,,,
,,,,
,,,,
,,
,,,
,,,
,,,
,,,,
,,,,
,,,
,
V
VIH
IL
tSDH
3-61
MT42C4256 883C Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
REV. 3/97
DS000016
MT42C4256 883C
256K x 4 VRAM
Limited Supply - Consult Factory
AUSTIN SEMICONDUCTOR, INC.
NOTE: 1. /S/E must be LOW to input new serial data, but the serial address register
is incremented by SC regardless of /S/E.
2. There must be no rising edges on the SC input during this time period.
3. QSF = 0 when the Lower SAM (bits 0–255) is being accessed.
QSF = 1 when the Upper SAM (bits 256–511) is being accessed.
ALTERNATE WRITE TRANSFER
(SAM-TO-DRAM TRANSFER)
V
VIH
IL
CAS
V
VIH
IL
RAS
tCRP
tRAS
tRC tRP
tCSH tRSH
tCAS
tRCD
V
VIH
IL
ADDR
,,
,
,
,,
,,,,
,,,
,,,
,,,
SAM START
tASR tCAH
tASC
V
VIH
IL
ME/WE
V
VIH
IL
DSF
,,
,,,,
,,,,
,,,
,,,
,,,,
,,,
,,
,
WSR tRWH
tRFH
tFSR
TR/OE IH
IL
V
VIOH
IOL
DQ
,,
,,
tOFF
OPEN OPEN
tTLS
tRAD
tAR
tRAL
,,
,,,,
,,,,
,,,
,,,
,,,,
,,
t
tTLH
RAH
t
,,
,,,
,,,,
,,,,
,,,
,,,
,,,
,,
,,
,,
,,,
,,
,
,,,
,,,
,,,,
,,,,
,,
tSWS
tSWIS
NOTE 1
tSDH
VALID DOUT
tSOH
tSAS
tSRS
tSP
tSC
tSAS tSP
V
V
SC V
VIH
IL
V
VIH
IL
SE
V
VIOH
IOL
SDQ
ROW
NOTE 2
VALID DOUT VALID DIN
,
,,
VALID DIN
,
,,
HIGH-Z
tSDS
SDH
t
tSDS
tSDZ
tSDD
QSF V
VOH
OL
DON’T CARE
UNDEFINED
,
,,
tRQD
tCQD
NOTE 3
tRSD
tCSD
NOTE 3
3-62
MT42C4256 883C Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
REV. 3/97
DS000016
MT42C4256 883C
256K x 4 VRAM
Limited Supply - Consult Factory
AUSTIN SEMICONDUCTOR, INC.
SAM SERIAL INPUT
,,
,
,,
,,,
,,,
,
,,
tSWH tSWIS tSWIH tSWS
tSC tSC tSC tSAS
tSP
tSAS
tSP
tSAS
tSP
tSAS
tSDH tSDS tSDH tSDS tSDH
A - 1
V
VIH
IL
SE
V
VIH
IL
SC
V
VIH
IL
SDQ
tSZE
A A + 2 A + 3
SAM SERIAL OUTPUT
,,
,,
,,
,,
DON’T CARE
UNDEFINED
,,
,,
,
,
tSEP
V
VIH
IL
SE
V
VIH
IL
SC
V
VOH
OL
SDQ
tSC
tSAS tSP tSAS tSP tSAS tSP
tSC tSC
tSAC tSEZ
tSAC tSAC
tSOH tSOH tSOH
tSEA
tSAC
A - 1 AA + 2 A + 3A + 1
,,
,,
3-63
MT42C4256 883C Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
REV. 3/97
DS000016
MT42C4256 883C
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AUSTIN SEMICONDUCTOR, INC.
ELECTRICAL TEST REQUIREMENTS
SUBGROUPS
MIL-STD-883 TEST REQUIREMENTS (per Method 5005, Table I)
INTERIM ELECTRICAL (PRE-BURN-IN) TEST PARAMETERS 2, 8A, 10
(Method 5004)
FINAL ELECTRICAL TEST PARAMETERS 1*, 2, 3, 7*, 8, 9, 10, 11
(Method 5004)
GROUP A TEST REQUIREMENTS 1, 2, 3, 4**, 7, 8, 9, 10, 11
(Method 5005)
GROUP C AND D END-POINT ELECTRICAL PARAMETERS 1, 2, 3, 7, 8, 9, 10, 11
(Method 5005)
* PDA applies to subgroups 1 and 7.
** Subgroup 4 shall be measured only for initial qualification and after process or design changes, which may affect input
or output capacitance.
3-64
MT42C4256 883C Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
REV. 3/97
DS000016
MT42C4256 883C
256K x 4 VRAM
Limited Supply - Consult Factory
AUSTIN SEMICONDUCTOR, INC.
