FT28C010-xxxxx-X 128K x 8 Bit 5V EEPROM FEATURES * Access Time: 120ns * Simple Byte and Page Write --Single 5V Supply --No External High Voltages or VPP Control Circuits * * * * * * --Self-Timed --No Erase Before Write --No Complex Programming Algorithms --No Overerase Problem Low Power CMOS: --Active: 50mA --Standby: 500A Software Data Protection --Protects Data Against System Level Inadvertant Writes High Speed Page Write Capability Highly Reliable Cell --Endurance: 100,000 Write Cycles --Data Retention: 100 Years Early End of Write Detection --DATA Polling --Toggle Bit Polling -X Manufactured using Xicor Die DESCRIPTION The Force FT28C010 is a 128K x 8 E 2PROM, fabricated with, high performance, floating gate CMOS technology. Like most Force programmable nonvolatile memories the FT28C010 is a 5V only device. The FT28C010 features the JEDEC approved pinout for bytewide memories, compatible with industry standard EPROMs. The FT28C010 supports a 256-byte page write operation, effectively providing a 19 s/byte write cycle and enabling the entire memory to be typically written in less than 2.5 seconds. The FT28C010 also features DATA Polling and Toggle Bit Polling, system software support schemes used to indicate the early completion of a write cycle. In addition, the FT28C010 supports Software Data Protection option. Force E 2PROMs are designed and tested for applications requiring extended endurance. Data retention is specified to be greater than 100 years. FT28C010-xxxxx-AT 128K x 8 Bit 5V EEPROM FEATURES * Fast Read Access Time 120ns * Automatic Page Write Operation Internal Address and Data Latches for 128-Bytes Internal Control Timer * Fast Write Cycle Time Page Write Cycle Time - 10 ms Maximum 1 to 128-Byte Page Write Operation * Low Power Dissipation 80 mA Active Current 300 A CMOS Standby Current * Hardware and Software Data Protection * DATA Polling for End of Write Detection * High Reliability CMOS Technology Endurance: 104 Data Retention: 10 Years * Single 5V 10% Supply * CMOS and TTL Compatible Inputs and Outputs * -AT Manufactured using Atmel Die Rev 1.1 DESCRIPTION The FT28C010 is a high-performance Electrically Erasable and Programmable Read Only Memory. Its one megabit of memory isorganised as 131,072 words by 8 bits. Manufactured with advanced nonvolatile CMOS technology, the device offersaccess times to 120 ns with power dissipation of just 440 mW. When the device isdeselected, the CMOS standby current is less than 300 mA. (Cont) 1/30 2011 FT28C010-xxxxx-X 31 3 30 A12 A7 A6 A5 4 29 5 28 6 27 7 FT28C010 26 A4 8 A2 25 A3 9 24 10 23 A1 11 22 12 21 13 20 14 19 15 18 16 17 A0 I/O0 I/O1 I/O2 VSS WE NC A14 A13 A8 A9 A11 OE A10 A0 14 CE I/O1 VSS I/O4 I/O7 16 18 20 23 24 A2 12 A3 11 A10 25 OE 26 A4 10 9 A11 27 A9 28 A8 29 A13 30 NC 32 A14 31 A1 13 A5 A6 A7 8 7 A12 6 A15 5 A 16 CE FT28C010 (BOTTOM VIEW) 4 NC 2 VCC NC 36 34 NC 3 NC 1 WE 35 8 9 FT28C010 27 26 25 (TOP VIEW) 24 10 11 23 12 22 13 15 16 17 18 19 20 21 14 OE A10 CE I/O7 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 5 6 NC 29 28 7 8 9 10 30 27 26 25 FT28C010 (TOP VIEW) 24 23 11 12 13 22 21 A14 A13 A8 A9 A11 OE A10 CE I/O7 14 15 16 17 18 19 20 I/O3 I/O4 2 7 A14 A13 A8 A9 A11 32 31 1 I/O1 I/O2 VSS A16 A15 I/O0 I/O2 I/O3 I/O5 I/O6 15 17 19 21 22 VCC 4 3 2 I/O3 I/O4 I/O5 I/O6 32 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 PGA 30 32 31 29 54 3 2 1 6 28 I/O1 I/O2 VSS 1 A12 A15 A16 NC VCC WE A12 A15 A16 NC VCC WE NC CERDIP FLAT PACK SOIC (R) NC EXTENDED LCC PLCC LCC I/O5 I/O6 PIN CONFIGURATIONS TSOP A11 A9 A8 A13 A14 NC NC NC WE VCC NC NC NC A16 A15 A12 A7 A6 A5 A4 NC 33 I/O7 I/O6 I/O5 I/O4 I/O3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 FT28C010 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 NC NC VSS NC NC I/O2 I/O1 I/O0 A0 A1 A2 A3 FT28C010-xxxxx-AT PIN CONFIGURATIONS CERDIP, FLATPACK Top View Rev 1.1 PGA Top V iew A15 A16 NC NC NC NC VCC WE NC NC A14 VCC WE NC A14 A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 A12 A7 A6 A5 NC NC NC A4 A3 A2 A1 6 5 4 3 2 1 44 43 42 41 40 1 32 2 31 3 30 4 29 5 28 6 27 7 26 8 25 9 24 10 23 11 22 12 21 13 20 14 19 15 18 16 17 FT28C010 7 8 9 10 11 12 13 14 15 16 17 FT28C010 39 38 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 A14 A13 A8 A9 A11 OE A10 CE I/O7 NC A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND A0 I/O0 I/O1 I/O2 VSS NC I/O3 I/O4 I/O5 I/O6 I/O7 FT28C010 29 28 27 26 25 24 23 22 21 14 15 16 17 18 19 20 5 6 7 8 9 10 11 12 13 I/O1 I/O2 GND I/O3 I/O4 I/O5 I/O6 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 4 3 2 1 32 31 30 A12 A15 A16 NC VCC WE NC 32 LCC Top View 44LCC Top View 2/30 A13 A8 A9 A11 NC NC NC NC OE A10 CE FT28C010 2011 FT28C010-xxxxx-X PIN DESCRIPTIONS PIN NAMES Addresses (A0-A16) The Address inputs select an 8-bit memory location during a read or write operation. Chip Enable (CE) The Chip Enable input must be LOW to enable all read/ write operations. When CE is HIGH, power consumption is reduced. Output Enable (OE) The Output Enable input controls the data output buffers and is used to initiate read operations. Symbol A0-A16 I/O0-I/O7 WE CE OE VCC VSS NC Description Address Inputs Data Input/Output Write Enable Chip Enable Output Enable +5V Ground No Connect Data In/Data Out (I/O0-I/O7) Data is written to or read from the FT28C010 through the I/O pins. Write Enable (WE) The Write Enable input controls the writing of data to the FT28C010. FUNCTIONAL DIAGRAM A8-A16 X BUFFERS LATCHES AND DECODER A0-A7 Y BUFFERS LATCHES AND DECODER 1M-BIT E2PROM ARRAY I/O BUFFERS AND LATCHES I/O0-I/O7 DATA INPUTS/OUTPUTS CE OE WE CONTROL LOGIC AND TIMING VCC VSS Rev 1.1 3/30 2011 FT28C010-xxxxx-X DEVICE OPERATION Write Operation Status Bits Read The FT28C010 provides the user two write operation status bits. These can be used to optimise a system write cycle time. The status bits are mapped onto the I/O bus as shown in Figure 1. Read operations are initiated by both OE and CE LOW. The read operation is terminated by either CE or OE returning HIGH. This two line control architecture eliminates bus contention in a system environment. The data bus will be in a high impedance state when either OE or CE is HIGH. Write Write operations are initiated when both CE and WE are LOW and OE is HIGH. The FT28C010 supports both a CE and WE controlled write cycle. That is, the address is latched by the falling edge of either CE or WE, whichever occurs last. Similarly, the data is latched internally by the rising edge of either CE or WE, whichever occurs first. A byte write operation, once initiated, will automatically continue to completion, typically within 5ms. Page Write Operation The page write feature of the FT28C010 allows the entire memory to be written in 5 seconds. Page write allows two to two hundred fifty-six bytes of data to be consecutively written to the FT28C010 prior to the commencement of the internal programming cycle. The host can fetch data from another device within the system during a page write operation (change the source address), but the page address (A8 through A 16) for each subsequent valid write cycle to the part during this operation must be the same as the initial page address. The page write mode can be initiated during any write operation. Following the initial byte write cycle, the host can write an additional one to two hundred fifty six bytes in the same manner as the first byte was written. Each successive byte load cycle, started by the WE HIGH to LOW transition, must begin within 100 s of the falling edge of the preceding WE. If a subsequent WE HIGH to LOW transition is not detected within 100 s, the internal automatic programming cycle will commence. There is no page write window limitation. Effectively the page write window is infinitely wide, so long as the host continues to access the device within the byte load cycle time of 100s. Rev 1.1 4/30 Figure 1. Status Bit Assignment I/O DP TB 5 4 3 2 1 0 RESERVED TOGGLE BIT DATA POLLING DATA Polling (I/O7) The FT28C010 features DATA Polling as a method to indicate to the host system that the byte write or page write cycle has completed. DATA Polling allows a simple bit test operation to determine the status of the FT28C010, eliminating additional interrupt inputs or external hardware. During the internal programming cycle, any attempt to read the last byte written will produce the complement of that data on I/O 7 (i.e., write data = 0xxx xxxx, read data = 1xxx xxxx). Once the programming cycle is complete, I/O7 will reflect true data. Note: If the FT28C010 is in the protected state and an illegal write operation is attempted DATA Polling will not operate. Toggle Bit (I/O6) The FT28C010 also provides another method for determining when the internal write cycle is complete. During the internal programming cycle, I/O 6 will toggle from HIGH to LOW and LOW to HIGH on subsequent attempts to read the device. When the internal cycle is complete the toggling will cease and the device will be accessible for additional read or write operations. 2011 FT28C010-xxxxx-X DATA Polling I/O7 Figure 2. DATA Polling Bus Sequence WE LAST WRITE CE OE I/O7 A0-A14 VIH VOH HIGH Z VOL An An An FT28C010 READY An An An An Figure 3. DATA Polling Software Flow DATA Polling can effectively halve the time for writing to the FT28C010. The timing diagram in Figure 2 illustrates the sequence of events on the bus. The software flow diagram in Figure 3 illustrates one method of implementing the routine. WRITE DATA WRITES COMPLETE? NO YES SAVE LAST DATA AND ADDRESS READ LAST ADDRESS I/O7 COMPARE? NO YES FT28C010 READY Rev 1.1 5/30 2011 FT28C010-xxxxx-X The Toggle Bit I/O6 Figure 4. Toggle Bit Bus Sequence WE LAST WRITE CE OE I/O6 * VOH HIGH Z VOL * Beginning and ending state of I/O6 will vary. * FT28C010 READY Figure 5. Toggle Bit Software Flow The Toggle Bit can eliminate the software housekeeping chore of saving and fetching the last address and data written to a device in order to implement DATA Polling. This can be especially helpful in an array comprised of multiple FT28C010 memories that is frequently updated. Toggle Bit Polling can also provide a method for status checking in multiprocessor applications. The timing diagram in Figure 4 illustrates the sequence of events on the bus. The software flow diagram in Figure 5 illustrates a method for polling the Toggle Bit. LAST WRITE LOAD ACCUM FROM ADDR n COMPARE ACCUM WITH ADDR n COMPARE OK? NO YES FT28C010 READY Rev 1.1 6/30 2011 FT28C010-xxxxx-X HARDWARE DATA PROTECTION The FT28C010 provides three hardware features that protect nonvolatile data from inadvertent writes. * Noise Protection--A WE pulse less than 10ns will not initiate a write cycle. * Default VCC Sense--All functions are inhibited when VCC is 3.5V. * Write inhibit--Holding either OE LOW, WE HIGH, or CE HIGH will prevent an inadvertent write cycle during power-up and power-down, maintaining data integrity. The FT28C010 can be automatically protected during power-up and power-down without the need for external circuits by employing the software data protection feature. The internal software data protection circuit is enabled after the first write operation utilising the software algorithm. This circuit is nonvolatile and will remain set for the life of the device unless the reset command is issued. Once the software protection is enabled, the FT28C010 is also protected from inadvertent and accidental writes in the powered-up state. That is, the software algorithm must be issued prior to writing additional data to the device. SOFTWARE DATA PROTECTION SOFTWARE ALGORITHM The FT28C010 offers a software controlled data protection feature. The FT28C010 is shipped from Force with the software data protection NOT ENABLED: that is the device will be in the standard operating mode. In this mode data should be protected during power-up/-down operations through the use of external circuits. The host would then have open read and write access of the device once VCC was stable. Selecting the software data protection mode requires the host system to precede data write operations by a series of three write operations to three specific addresses. Refer to Figures 6 and 7 for the sequence. The three byte sequence opens the page write window enabling the host to write from one to two hundred fiftysix bytes of data. Once the page load cycle has been completed, the device will automatically be returned to the data protected state. Rev 1.1 7/30 2011 FT28C010-xxxxx-X Software Data Protection Figure 6. Timing Sequence--Byte or Page Write VCC (VCC) 0V DATA ADDR AA 5555 55 2AAA A0 5555 WRITES OK tWC WRITE PROTECTED CE tBLC MAX WE BYTE OR PAGE Figure 7. Write Sequence for Software Data Protection Regardless of whether the device has previously been protected or not, once the software data protection algorithm is used and data has been written, the FT28C010 will automatically disable further writes unless another command is issued to cancel it. If no further commands are issued the FT28C010 will be write protected during power-down and after any subsequent power-up. The state of A 15 and A 16 while executing the algorithm is don't care. WRITE DATA AA TO ADDRESS 5555 WRITE DATA 55 TO ADDRESS 2AAA Note: Once initiated, the sequence of write operations should not be interrupted. WRITE DATA A0 TO ADDRESS 5555 WRITE DATA XX TO ANY ADDRESS OPTIONAL BYTE/PAGE LOAD OPERATION WRITE LAST BYTE TO LAST ADDRESS AFTER tWC RE-ENTERS DATA PROTECTED STATE Rev 1.1 8/30 2011 FT28C010-xxxxx-X Resetting Software Data Protection Figure 8. Reset Software Data Protection Timing Sequence VCC DATA ADDR AA 5555 55 2AAA 80 5555 AA 5555 55 2AAA 20 5555 tWC STANDARD OPERATING MODE CE WE Figure 9. Software Sequence to Deactivate Software Data Protection In the event the user wants to deactivate the software data protection feature for testing or reprogramming in an E 2PROM programmer, the following six step algorithm will reset the internal protection circuit. After tWC, the FT28C010 will be in standard operating mode. WRITE DATA AA TO ADDRESS 5555 Note: Once initiated, the sequence of write operations should not be interrupted. WRITE DATA 55 TO ADDRESS 2AAA WRITE DATA 80 TO ADDRESS 5555 WRITE DATA AA TO ADDRESS 5555 WRITE DATA 55 TO ADDRESS 2AAA WRITE DATA 20 TO ADDRESS 5555 Rev 1.1 9/30 2011 FT28C010-xxxxx-X SYSTEM CONSIDERATIONS prime concern. Enabling CE will cause transient current spikes. The magnitude of these spikes is dependent on Because the FT28C010 is frequently used in large memory the output capacitive loading of the I/Os. Therefore, the arrays it is provided with a two line control architecture larger the array sharing a common bus, the larger the for both read and write operations. Proper usage can transient spikes. The voltage peaks associated with the provide the lowest possible power dissipation and elimicurrent transients can be suppressed by the proper nate the possibility of contention where multiple I/O pins selection and placement of decoupling capacitors. As a share the same bus. minimum, it is recommended that a 0.1 F high frequency ceramic capacitor be used between V CC and To gain the most benefit it is recommended that CE be VSS at each device. Depending on the size of the array, decoded from the address bus and be used as the the value of the capacitor may have to be larger. primary device selection input. Both OE and WE would then be common among all devices in the array. For a In addition, it is recommended that a 4.7F electrolytic read operation this assures that all deselected devices bulk capacitor be placed between VCC and V SS for each are in their standby mode and that only the selected eight devices employed in the array. This bulk capacitor device(s) is outputting data on the bus. is employed to overcome the voltage droop caused by the inductive effects of the PC board traces. Because the FT28C010 has two power modes, standby and active, proper decoupling of the memory array is of ICC (RD) by Temperature over Frequency Active Supply Current vs. Ambient Temperature 18 60 VCC = 5V 50 ICC RD (mA) ICC WR (mA) 16 14 12 10 -55 5.0 VCC -55 C +25 C 40 +125 C 30 20 -10 +35 +80 10 +125 AMBIENT TEMPERATURE (C) 0 3 6 9 12 15 FREQUENCY (MHz) Standby Supply Current vs. Ambient Temperature 0.3 VCC = 5V 0.25 ISB (mA) 0.2 0.15 0.1 0.05 -55 -10 +35 +80 +125 AMBIENT TEMPERATURE (C) Rev 1.1 10/30 2011 FT28C010-xxxxx-X ABSOLUTE MAXIMUM RATINGS* Temperature under Bias FT28C010 ...................................... -10 C to +85C FT28C010I ................................... -65 C to +135C FT28C010M ................................. -65 C to +135C Storage Temperature ......................... -65 C to +150C Voltage on any Pin with Respect to VSS ....................................... -1V to +7V D.C. Output Current ............................................. 5mA Lead Temperature (Soldering, 10 seconds) .............................. 300C *COMMENT Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMEND OPERATING CONDITIONS Temperature Min. Commercial Industrial Military 0C -40C -55C Supply Voltage Max. Limits FT28C010 +70C +85C +125C 5V10% D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.) Limits Symbol Parameter Min. Max. Units Test Conditions CE = OE = VIL, WE = VIH, All I/O's = Open, Address Inputs = .4V/2.4V Levels @ f = 5MHz CE = VIH, OE = VIL All I/O's = Open, Other Inputs = VIH CE = VCC - 0.3V, OE = VIL All I/O's = Open, Other Inputs = VCC VIN = VSS to VCC VOUT = VSS to VCC, CE = VIH ICC VCC Current (Active) (TTL Inputs) 50 mA ISB1 VCC Current (Standby) (TTL Inputs) VCC Current (Standby) (CMOS Inputs) Input Leakage Current Output Leakage Current Input LOW Voltage Input HIGH Voltage Output LOW Voltage Output HIGH Voltage 3 mA 500 A 10 10 0.8 VCC + 1 0.4 A A V V V V ISB2 ILI ILO VlL(1) VIH(1) VOL VOH -1 2 2.4 IOL = 2.1mA IOH = -400A Notes: (1) VIL min. and VIH max. are for reference only and are not tested. Rev 1.1 11/30 2011 FT28C010-xxxxx-X POWER-UP TIMING Symbol Parameter Max. Units tPUR(2) tPUW(2) Power-up to Read Operation Power-up to Write Operation 100 5 s ms CAPACITANCE TA = +25 C, f = 1MHz, VCC = 5V Symbol Parameter Max. Units Test Conditions CI/O(2) Input/Output Capacitance Input Capacitance 10 10 pF pF VI/O = 0V VIN = 0V CIN(2) ENDURANCE AND DATA RETENTION Parameter Min. Endurance Endurance Data Retention 10,000 100,000 100 A.C. CONDITIONS OF TEST Input Pulse Levels 10ns 1.5V OE L H X WE H L X X X L X X H WAVEFORM 1.92K OUTPUT 100pF (2) This parameter is periodically sampled and not 100% tested. Rev 1.1 Mode Read Write Standby and Write Inhibit Write Inhibit Write Inhibit I/O DOUT DIN High Z Power Active Active Standby -- -- -- -- SYMBOL TABLE 5V Note: Cycles Per Byte Cycles Per Page Years CE L L H EQUIVALENT A.C. LOAD CIRCUIT 1.37K Units MODE SELECTION 0V to 3V Input Rise and Fall Times Input and Output Timing Levels Max. 12/30 INPUTS OUTPUTS Must be steady Will be steady May change from LOW to HIGH Will change from LOW to HIGH May change from HIGH to LOW Will change from HIGH to LOW Don't Care: Changes Allowed N/A Changing: State Not Known Center Line is High Impedance 2011 FT28C010-xxxxx-X A.C. CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.) Read Cycle Limits FT28C010-12 FT28C010-15 FT28C010-20 FT28C010-25 Symbol Parameter Min. tRC tCE tAA tOE tLZ(3) tOLZ(3) tHZ(3) tOHZ(3) tOH Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time CE LOW to Active Output OE LOW to Active Output CE HIGH to High Z Output OE HIGH to High Z Output Output Hold from Address Change 120 Max. Min. Max. 150 120 120 50 0 0 150 150 50 50 50 Max. 200 0 0 0 Min. Max. 250 200 200 50 0 0 50 50 0 Min. 250 250 50 0 0 50 50 0 50 50 0 Units ns ns ns ns ns ns ns ns ns Read Cycle tRC ADDRESS tCE CE tOE OE VIH WE tOLZ tOHZ tLZ DATA I/O HIGH Z tOH tHZ DATA VALID DATA VALID tAA Note: (3) tLZ min.,tHZ, tOLZ min., and tOHZ are periodically sampled and not 100% tested. tHZ max. and tOHZ max. are measured, with CL = 5pF, from the point when CE or OE return HIGH (whichever occurs first) to the time when the outputs are no longer driven. Rev 1.1 13/30 2011 FT28C010-xxxxx-X Write Cycle Limits Symbol Parameter Min. tWC(4) tAS tAH tCS tCH tCW tOES tOEH tWP tWPH tDV tDS tDH tDW tBLC Write Cycle Time Address Setup Time Address Hold Time Write Setup Time Write Hold Time CE Pulse Width OE HIGH Setup Time OE HIGH Hold Time WE Pulse Width WE HIGH Recovery Data Valid Data Setup Data Hold Delay to Next Write Byte Load Cycle Max. Units 10 ms ns ns ns ns ns ns ns ns ns s ns ns s s 0 50 0 0 100 10 10 100 100 1 50 0 10 0.2 100 WE Controlled Write Cycle tWC ADDRESS tAS tCS tAH tCH CE OE tOES tOEH tWP WE tWPH tDV DATA IN DATA VALID tDS DATA OUT tDH HIGH Z 3858 FHD F06 Notes: (4) tWC is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time the device requires to complete internal write operation. Rev 1.1 14/30 2011 FT28C010-xxxxx-X CE Controlled Write Cycle tWC ADDRESS tAS tAH CE tCW tWPH tOES OE tOEH tCS tCH WE tDV DATA IN DATA VALID tDS tDH HIGH Z DATA OUT 3858 FHD F07 Page Write Cycle OE (5) CE tWP WE tBLC tWPH ADDRESS * (6) I/O LAST BYTE BYTE 0 BYTE 1 BYTE 2 BYTE n *For each successive write within the page write operation, A8-A16 should be the same or writes to an unknown address could occur. BYTE n+1 BYTE n+2 tWC Notes: (5) Between successive byte writes within a page write operation, OE can be strobed LOW: e.g. this can be done with CE and WE HIGH to fetch data from another memory device within the system for the next write; or with WE HIGH and CE LOW effectively performing a polling operation. (6) The timings shown above are unique to page write operations. Individual byte load operations within the page write must conform to either the CE or WE controlled write cycle timing. Rev 1.1 15/30 2011 FT28C010-xxxxx-X DATA Polling Timing Diagram(7) ADDRESS AN AN AN CE WE tOEH tOES OE tDW I/O7 DIN=X DOUT=X DOUT=X tWC 3858 FHD F09 Toggle Bit Timing Diagram CE WE tOES tOEH OE I/O6 HIGH Z tDW * * tWC * I/O6 beginning and ending state will vary. Note: (7) Polling operations are by definition read cycles and are therefore subject to read cycle timings. Rev 1.1 16/30 2011 FT28C010-xxxxx-AT The FT28C010 is accessed like a Static RAM for the read or write cycle without the need for external components. The device contains a 128-byte page register to allow writing of up to 128-bytes simultaneously. During a write cycle, the address and 1 to 128-bytes of data are internally latched, freeing the address and data bus for other operations. Following the initiation of a write cycle, the device will automatically write the latched data using an inter nal control timer. The end of a write cycle can be detected by DATA POLLING of I/O7. Once the end of a write cycle has been detected a new access for a read or write can begin. Force's 28C010 has additional features to ensure high quality and manufacturability. The device utilises internal error correction for extended endurance and improved data retention characteristics. An optional software data protection mechanism is available to guard against inadvertent writes. The device also includes an extra 128-bytes of EEPROM for device identification or tracking. Block Diagram Absolute Maximum Ratings* Temperature Under Bias ................................ -55C to +125C *NOTICE: Storage Temperature ..................................... -65C to +150C All Input Voltages (including NC Pins) with Respect to Ground ...................................-0.6V to +6.25V All Output Voltages with Respect to Ground .............................-0.6V to VCC + 0.6V Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Voltage on OE and A9 with Respect to Ground ...................................-0.6V to +13.5V Pin Configuration Pin Name Function A0 - A16 Addresses CE Chip Enable OE Output Enable WE Write Enable I/O0 - I/O7 Data Inputs/Outputs NC No Connect Rev 1.1 17/30 2011 FT28C010-xxxxx-AT Device Operation READ: The FT28C010 is accessed like a Static RAM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the hi gh impedance state when either CE or OE is high. This dualline control gives designers flexibility in preventing bus contention in their system. BYTE WRITE: A low pulse on the WE or CE input with CE or WE low (respectively) and OE high initiates a write cycle. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Once a byte write has been started it will automatically time itself to completion. Once a programming operation has been initiated and for the duration of t WC, a read operation will effectively be a polling operation. PAGE WRITE: The page write operation of the FT28C010 allows 1 to 128-bytes of data to be written into the device during a single internal programming period. A page write operation is initiated in the same manner as a byte write; the first byte written can then be followed by 1 to 127 additional bytes. Each successive byte must be written within 150 s (t BLC ) of the previous byte. If the t BLC limit is exceeded the FT28C010 will cease accepting data and commence the internal programming operation. All bytes during a page write operation must reside on the same page as defined by the state of the A7 - A16 inputs. For each WE high to low transition during the page write operation, A7 - A16 must be the same. The A0 to A6 inputs are used to specify which bytes within the page are to be written. The bytes may be loaded in any order and may be altered within the same load period. Only bytes which are specified for writing will be written; unnecessary cycling of other bytes within the page does not occur. DATA POLLING: The FT28C010 features DATA Polling to indicate the end of a w rite cycle. During a byte o r page write cycle an attempted read of the last byte written will result in the complement of the written data to be presented on I/O7. Once the write cycle has been completed, true data is valid on all outputs, and the next w rite cycle may begin. DATA Polling may begin at anytime during the write cycle. TOGGLE BIT: In addition to DATA Polling the FT28C010 provides another method for determining the end of a write cycle. During the write operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the write has completed, I/O6 will stop toggling and valid data will be read. Reading the toggle bit may begin at any time during the write cycle. DATA PROTECTION: If precautions are not taken, inadvertent writes may occur during transitions of the host sys- Rev 1.1 tem power supply. Force has incorporated both hardware and software features that will protect the memory against inadvertent writes. HARDWARE PROTECTION: Hardware features protect against inadvertent writes to the FT28C010 in the following ways: (a) VCC sense - if VCC is below 3.8V (typical) the write function is inhibited; (b) VCC power-on delay - once VCC has reached 3.8V the device will automatically time out 5 ms (typical) before allowing a write: (c) write inhibit - holding any one of OE low, CE high or WE high inhibits write cycles; (d) noise filter - pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a write cycle. SOFTWARE DATA PROTECTION: A software controlled data protection feature has been implemented on t he FT28C010. When enabled, the software data protection (SDP), will prevent inadvertent writes. The SDP feature may be enabled or disabled by the user; the FT28C010 is shipped from Force with SDP disabled. SDP is enabled by the host system issuing a series of three write commands; three specific bytes of data are written to three specific addresses (refer to Software Data Protection Algorithm). After writing the 3-byte command sequence and after tWC the entire FT28C010 will be protected against inadvertent write operations. It should be noted, that once protected the host may still perform a byte or page write to the FT28C010. This is done by preceding the data to be written by the same 3-byte command sequence used to enable SDP. Once set, SDP will remain active unless the disable command sequence is issued. Power transitions do not disable SDP and SDP will protect the FT28C010 during power-up and power-down conditions. All command sequences must conform to the page write timing specifications. The data in the enable and disable command sequences is not written to the device and the memory addresses used in the sequence may be written with data in either a byte or page write operation. After setting SDP, any attempt to write to the device without the 3-byte command sequence will start the internal write timers. No data will be written to the device; however, for the duration of t WC, read operations will effectively be polling operations. DEVICE ID ENTIFICATION: An e x tra 128 - by tes of EEPROM memory are available to the user for device identification. By raising A9 to 12V 0.5V and using address locations 1FF80H to 1FFFFH the bytes may be written to or read from in the same manner as the r egular memory array. OPTIONAL CHIP ERASE MODE: The entire device can be erased using a 6-byte software code. Please see Software Chip Erase application note for details. 18/30 2011 FT28C010-xxxxx-AT DC and AC Operating Range (Commercial/Industrial) Operating Temperature (Case) Com. Ind. VCC Power Supply FT28C010-12 FT28C010-15 FT28C010-20 0C - 70C 0C - 70C 0C - 70C -40C - 85C -40C - 85C -40C - 85C 5V 10% 5V 10% 5V 10% DC and AC Operating Range (Military) Operating Temperature (Case) Mil. FT28C010-12 FT28C010-15 FT28C010-20 FT28C010-25 -55C - 125C -55C - 125C -55C - 125C -55C - 125C 5V 10% 5V 10% 5V 10% 5V 10% VCC Power Supply Operating Modes (Commercial/Industrial/Military) Mode CE OE WE I/O VIL VIL VIH DOUT VIL VIH VIL DIN VIH X (1) X High Z Write Inhibit X X VIH Write Inhibit X VIL X Output Disable X VIH X Read Write (2) Standby/Write Inhibit Notes: High Z 1. X can be VIL or VIH. 2. Refer to AC Programming Waveforms DC Characteristics (Commercial/Industrial) Symbol Parameter Condition ILI Input Load Current ILO Max Units VIN = 0V to VCC + 1V 10 A Output Leakage Current VI/O = 0V to VCC 10 A ISB1 VCC Standby Current CMOS CE = VCC - 0.3V to VCC + 1V 200 A ISB2 VCC Standby Current TTL CE = 2.0V to VCC + 1V 3 mA ICC VCC Active Current f = 5 MHz; IOUT = 0 mA 40 mA VIL Input Low Voltage 0.8 V VIH Input High Voltage VOL Output Low Voltage IOL = 2.1 mA VOH1 Output High Voltage IOH = -400 A 2.4 V VOH2 Output High Voltage CMOS IOH = -100 A; VCC = 4.5V 4.2 V Rev 1.1 Min 2.0 V 0.45 19/30 V 2011 FT28C010-xxxxx-AT DC Characteristics (Military) Symbol Parameter Condition ILI Input Load Current ILO Max Units VIN = 0V to VCC + 1V 10 A Output Leakage Current VI/O = 0V to VCC 10 A ISB1 VCC Standby Current CMOS CE = VCC - 0.3V to VCC + 1V 300 A ISB2 VCC Standby Current TTL CE = 2.0V to VCC + 1V 3 mA ICC VCC Active Current f = 5 MHz; IOUT = 0 mA 80 mA VIL Input Low Voltage 0.8 V VIH Input High Voltage VOL Output Low Voltage IOL = 2.1 mA VOH1 Output High Voltage IOH = -400 A 2.4 V VOH2 Output High Voltage CMOS IOH = -100 A; VCC = 4.5V 4,2 V Rev 1.1 Min 2.0 V 0.45 20/30 V 2011 FT28C010-xxxxx-AT AC Read Characteristics (Commercial/Industrial/Military) FT28C010-12 Symbol Parameter tACC Min FT28C010-15 Max Min Max FT28C010-20 Min Max FT28C010-25 Min Max Units Address to Output Delay 120 150 200 250 ns tCE (1) CE to Output Delay 120 150 200 250 ns tOE (2) OE o utput t Oelay D tDF (3, 4) CE or OE o Output t loat tOH Output Hold from OE, CE or Address, whichever occurred first F 0 50 0 55 0 55 0 55 ns 0 50 0 55 0 55 0 55 ns 0 0 0 0 ns AC Read Waveforms(1)(2)(3)(4) Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC. 2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change without impact in tACC. 3. tDF is specified from OE or CE wichever occurs first (CL = 5 pF). 4. This parameter is characterised and is not 100% tested. Input Test Waveforms and Measurement Level Output Test Load Pin Capacitance f = 1 MHz, T = 25C(1) Symbol Typ Max Units Conditions CIN 4 10 pF VIN = 0V COUT 8 12 pF VOUT = 0V Note: 1. This parameter is 100% characterised and is not 100% tested. Rev 1.1 21/30 2011 FT28C010-xxxxx-AT AC Write Characteristics (Commercial/Industrial/Military) Symbol Parameter Min Max Units tWC Write Cycle Time 10 ms tAS Address Set-up Time 0 ns tAH Address Hold Time 50 ns tDS Data Set-up Time 50 ns tDH Data Hold Time 0 ns tWP Write Pulse Width 100 ns tBLC Byte Load Cycle Time tWPH Write Pulse Width High 150 50 s ns AC Write Waveforms WE Controlled CE Controlled Rev 1.1 22/30 2011 FT28C010-xxxxx-AT Page Mode Characteristics (Commercial/Industrial/Military) Symbol Parameter Min Max Units tAS, tOES Address, OE Set-up Time 0 ns tAH Address Hold Time 50 ns tCS Chip Select Set-up Time 0 ns tCH Chip Select Hold Time 0 ns tWP Write Pulse Width (WE or CE) 100 ns tDS Data Set-up Time 50 ns tDH, tOEH Data, OE Hold Time 0 ns Page Mode Write Waveforms (1)(2) Notes: 1. A7 through A16 must specify the page address during each high to low transition of WE (or CE). 2. OE must be high only when WE and CE are both low. Chip Erase Waveforms tS = 5 msec (min.) tW = tH = 10 msec (min.) VH = 12.0V 0.5V Rev 1.1 23/30 2011 FT28C010-xxxxx-AT Software Data Protection Enable Algorithm(1) Software Data Protection Disable Algorithm(1) LOAD DATA AA TO ADDRESS 5555 LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA A0 TO ADDRESS 5555 LOAD DATA 80 TO ADDRESS 5555 WRITES ENABLED(2) LOAD DATA AA TO ADDRESS 5555 LOAD DATA XX TO ANY ADDRESS(4) LOAD LAST BYTE TO LAST ADDRESS Notes: LOAD DATA 55 TO ADDRESS 2AAA ENTER DATA PROTECT STATE LOAD DATA 20 TO ADDRESS 5555 1. Data Format: I/O7 - I/O0 (Hex); Address Format: A14 - A0 (Hex). 2. Write Protect state will be activated at end of write even if no other data is loaded. EXIT DATA PROTECT STATE(3) LOAD DATA XX TO ANY ADDRESS(4) 3. Write Protect state will be deactivated at end of write period even if no other data if loaded. LOAD LAST BYTE TO LAST ADDRESS 4. 1 to 128 bytes of data are loaded. Software Protected Program Cycle Waveform(1)(2)(3) Notes: 1. A0 - A14 must conform to the addressing sequence for the first 3 bytes as shown above. 2. After the command sequence has been issued and a page write operation follows, the page address inputs (A7 - A16) must be the same for each high to low transition of WE (or CE). 3. OE must be high only when WE and CE are both low. Rev 1.1 24/30 2011 FT28C010-xxxxx-AT Data Polling Characterstics (Commercial/Industrial/Military)(1) Symbol Parameter tDH Data Hold Time tOEH OE Hold Time Min Max Units 10 ns 10 ns (2) tOE OE to Output Delay tWR Write Recovery Time Notes: Typ ns 0 ns 1. These parameters are characterised and not 100% tested. 2. See AC Read Characteristics. Data Polling Waveforms Toggle Bit Characteristics (Commercial/Industrial/Military)(1) Symbol Parameter tDH Data Hold Time 10 ns tOEH OE Hold Time 10 ns tOE OE to Output Delay (2) tOEHP OE High Pulse tWR Write Recovery Time Notes: Min Typ Max Units ns 150 ns 0 ns 1. These parameters are characterised and not 100% tested. 2. See AC Read Characteristics. Toggle Bit Waveforms(1)(2)(3) Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit. 2. Beginning and ending state of I/O6 will vary. 3. Any addres location may be used but the address should not vary. Rev 1.1 25/30 2011 FT28C010 Packaging Information D 32-Lead, 0.600" Wide, Non-Windowed, F 32-Lead, Non-Windowed, Ceramic Bottom MIL-STD-1835 D-16 CONFIG A MIL-STD-1835 F-18 CONFIG B JEDEC OUTLINE MO-115 Ceramic Dual inline Package (Cerdip) Dimensions in Inches and (Millimeters) 1.68(42.7) 1.64(41.7) Brazed Flat Package (Flatpack) Dimensions in Inches and (Millimeters) PIN #1 ID PIN 1 .370(9.40) .270(6.86) .019(.482) .015(.381) .610(15.5) .570(14.5) 1.500(38.10) REF .110(2.79) .090(2.29) .015(.381) .008(.203) .045(1.14) MAX .488(12.4) .472(12.0) .060(1.52) .015(.381) .023(.584) .014(.356) .065(1.65) .045(1.14) .620(15.7) .590(15.0) .050(1.27) BSC .005(.127) MIN .225(5.72) MAX SEATING PLANE .200(5.08) .125(3.18) .829(21.1) .811(20.6) .098(2.49) MAX .120(3.05) .098(2.49) .006(.152) .004(.101) .408(10.4) .355(9.02) 0 REF 15 .072(1.82) .030(0.76) .700(17.8) MAX .045(1.14) .026(.660) E 32-Pad, Non-Windowed, Ceramic Leadless L 44-Pad, Non-Windowed, Ceramic Leadless MIL-STD-1835 C-12 MIL-STD-1835 C-5 Chip Carrier (LCC) Dimensions in Inches and (Millimeters)* Chip Carrier (LCC) Dimensions in Inches and (Millimeters)* *Controlling dimension: millimeters Rev 1.1 *Controlling dimension: millimeters 26/30 2011 FT28C010 Packaging Information G 36-Lead Ceramic Pin Grid Array Package Typ U 30-Pin, Ceramic Pin Grid Array (PGA) Dimensions in Inches and (Millimeters) 15 17 19 21 22 13 14 16 18 20 23 24 12 11 25 26 10 9 27 28 8 7 29 30 6 5 2 36 34 32 31 4 3 1 35 33 A 0.008 (0.20) 0.050 (1.27) A TYP. 0.180 (.010) (4.57 .25) 4 CORNERS NOTE: LEADS 5, 14, 23, & 32 TYP. 0.100 (2.54) ALL LEADS TYP. 0.180 (.010) (4.57 .25) 4 CORNERS 0.120 (3.05) 0.100 (2.54) 0.072 (1.83) 0.062 (1.57) PIN 1 INDEX 0.770 (19.56) 0.750 (19.05) SQ 0.020 (0.51) 0.016 (0.41) A A 0.185 (4.70) 0.175 (4.45) NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) Rev 1.1 27/30 2011 FT28C010 Ordering Information FT28C010 -- xx x x -- x Device Die --AT = Manufactured Using Atmel Die --X = Manufactured Using Xicor Die Temperature Range Blank = Commercial = 0C to +70C I = Industrial = -40C to +85C M = Military = -55C to +125C B = MIL-STD-883 M5004 Package D-32 Lead Cerdip E-32 Lead LCC F-32 Lead Flatpack L-44 Pad LCC U-30 Pin PGA G-36 Pin Ceramic PGA Access Time --12 = 120ns = 150ns --20 = 200ns --25 = 250ns --15 Rev 1.1 28/30 2011 Monolithic Devices-Product Flow Matrix The device shall be screened as specified in the table below. NON-COMPLIANT but in accordance with Mil-Std-883. Manufactured batches shall have Lots tests carried out in accordance with Mil-Std-883 (Mil-M-38510) All manufacturing is carried out at DSCC approved facilities. Screening Method Visual Inspection Kit Temperature Cycling Centrifuge Constant acceleration Seal a. Fine b. Gross Visual inspection Interim (pre-BI)Electrical Burn-in test Incoming and Outgoing Inspection Procedures /B05 (5005) 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 5% QCI 100% -40oC +85oC 100% -55oC +125oC 100% -55oC +125oC 5005 p2 100% Tmin Tmax 100% 100% - 100% 100% 100% 100% 100% - 100% 100% 100% 2009 2015/2003/2011 1005 2016/2004/1014/1011/ 1010/1004/2002/2007/ 2001/1009/1018/2025/2024 100% 100% 100% 100% 100% 100% 100% In accordance with applicable device specification. or as defined in QM p4.1.1 Dynamic Review Marking & Inspect As FT WIP documentation As FT QA documentation As FT WIP documentation Dry Bake store/ship /B (5004) 100% 100% /I 100% Percentage defective allowable (PDA) calculation Final GrpA Electrical Tests A)Static Tests: 25oC (subgrp.1) Max.& Min. subgrp 2,3) B) Dynamic (Linear devices) 25oC (subgrp.4) Max.& Min. subgrp 5,6) C)Functional 25oC (subgrp.7) Max.& Min. subgrp 8) D) Switching (Digital devices) 25oC (subgrp.9) Max.& Min. subgrp 10,11) External Visual Group B Group C Group D Data Preparation /C In accordance with applicable device specification. or as defined in QM p4.1.1 100% QA test condition UpScreen only 100% 1010, test condition C 2001E 2001, test condition E (min)Y1 orientation 1014 Cond A or B Cond C FT WIP documentation 100% 100% - 1015, 160 hours at 125C minimum - 100% 100% JEDEC 100% Note. Suffix code /C /I /B /B5 = = = = Parts are assembled and tested to Commercial temperature 0oC to +70oC Parts are assembled and tested to Extended temperature -40oC to +85oC Parts are Based on METHOD 5004 screening procedures and Mil-Std-883F Test methods. Parts are Based on Control Procedures for : GroupA (Electrical) GroupB (Enviromental) GroupC (Die related) GroupD (Package related) Tests. It is based on METHOD 5005 Conformance procedures and Mil-Std-883F Test methods Rev 1.1 29/30 2011 FT28C010 Revision History Rev. 1 Rev 1.1 Rev 1.1 First Draft Added 36 Lead Ceramic PGA (G) 30/30 12/01/11 02/03/11 2011