1. General description
The 74LVT244A; 74LVTH244A is a high-performance BiCMOS product designed for VCC
operation at 3.3 V.
This device is an octal buffer that is ideal for driving bus lines. The device features two
output enables (1OE, 2OE), each controlling four of the 3-state outputs.
2. Features
nOctal bus interface
n3-state buffers
nOutput capability: +64 mA and −32 mA
nTTL input and output switching levels
nInput and output interface capability to systems at 5 V supply
nBus hold data inputs eliminate need for external pull-up resistors to hold unused inputs
nLive insertion and extraction permitted
nPower-up 3-state
nNo bus current loading when output is tied to 5 V bus
nLatch-up protection
uJESD78 Class II exceeds 500 mA
nESD protection:
uHBM JESD22-A114E exceeds 2000 V
uMM JESD22-A115-A exceeds 200 V
3. Ordering information
74LVT244A; 74LVTH244A
3.3 V octal buffer/line driver; 3-state
Rev. 04 — 3 September 2008 Product data sheet
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74LVT244AD −40 °C to +85 °C SO20 plastic small outline package; 20 leads;
body width 7.5 mm SOT163-1
74LVTH244AD
74LVT244ADB −40 °C to +85 °C SSOP20 plastic shrink small outline package; 20 leads;
body width 5.3 mm SOT339-1
74LVTH244ADB
74LVT244APW −40 °C to +85 °C TSSOP20 plastic thin shrink small outline package; 20 leads;
body width 4.4 mm SOT360-1
74LVTH244APW
74LVT244ABQ −40 °Cto+85°C DHVQFN20 plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads;
20 terminals; body 2.5 ×4.5 ×0.85 mm
SOT764-1
74LVTH244ABQ
74LVT_LVTH244A_4 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 04 — 3 September 2008 2 of 15
NXP Semiconductors 74LVT244A; 74LVTH244A
3.3 V octal buffer/line driver; 3-state
4. Functional diagram
Fig 1. Logic symbol Fig 2. IEC logic symbol
mna825
1A3
1A2
1A1
1A0
2
4
6
8
1
1Y0
1Y1
18
16
14
12
1Y2
1Y3
1OE
2A3
2A2
2A1
2A0
11
13
15
17
19
2Y0
2Y1
9
7
5
3
2Y2
2Y3
2OE
2
4
6
8
1EN
mna826
11
13
15
17
12
14
18
16
3
5
9
7
19 EN
74LVT_LVTH244A_4 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 04 — 3 September 2008 3 of 15
NXP Semiconductors 74LVT244A; 74LVTH244A
3.3 V octal buffer/line driver; 3-state
5. Pinning information
5.1 Pinning
5.2 Pin description
(1) The die substrate is attached to this pad using a
conductive die attach material. It cannot be used as a
supply pin or input.
Fig 3. Pin configuration for SO20 and (T)SSOP20 Fig 4. Pin configuration for DHVQFN20
74LVT244A
74LVTH244A
1OE VCC
1A0 2OE
2Y3 1Y0
1A1 2A3
2Y2 1Y1
1A2 2A2
2Y1 1Y2
1A3 2A1
2Y0 1Y3
GND 2A0
001aae510
1
2
3
4
5
6
7
8
9
10
12
11
14
13
16
15
18
17
20
19
001aah764
74LVT244A
74LVTH244A
Transparent top view
1Y3
1A3
2Y0
2A1
2Y1 1Y2
1A2 2A2
2Y2 1Y1
1A1 2A3
2Y3 1Y0
1A0 2OE
GND
2A0
1OE
VCC
912
8 13
7 14
6 15
5 16
4 17
3 18
2 19
10
11
1
20
terminal 1
index area
GND(1)
Table 2. Pin description
Symbol Pin Description
1OE, 2OE 1, 19 output enable input (active low)
1A0, 1A1, 1A2, 1A3 2, 4, 6, 8 data input
2Y0, 2Y1, 2Y2, 2Y3 9, 7, 5, 3 data output
GND 10 ground (0 V)
2A0, 2A1, 2A2, 2A3 11, 13, 15, 17 data input
1Y0, 1Y1, 1Y2, 1Y3, 18, 16, 14, 12 data output
VCC 20 supply voltage
74LVT_LVTH244A_4 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 04 — 3 September 2008 4 of 15
NXP Semiconductors 74LVT244A; 74LVTH244A
3.3 V octal buffer/line driver; 3-state
6. Functional description
6.1 Function table
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
7. Limiting values
[1] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
[2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability.
[3] For SO20 packages: above 70 °C derate linearly with 8 mW/K.
For SSOP20 and TSSOP20 packages: above 60 °C derate linearly with 5.5 mW/K.
For DHVQFN20 packages: above 60 °C derate linearly with 4.5 mW/K.
8. Recommended operating conditions
Table 3. Function table [1]
Control Input Output
nOE nAn nYn
LLL
HH
HXZ
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage −0.5 +4.6 V
VIinput voltage [1] −0.5 +7.0 V
VOoutput voltage output in OFF-state or
HIGH-state [1] −0.5 +7.0 V
IIK input clamping current VI < 0 V - −50 mA
IOK output clamping current VO < 0 V - −50 mA
IOoutput current output in LOW-state - 128 mA
output in HIGH-state - −64 mA
Tstg storage temperature −65 +150 °C
Tjjunction temperature [2] - 150 °C
Ptot total power dissipation Tamb = −40 to +85 °C[3] 500 mW
Table 5. Operating conditions
Symbol Parameter Conditions Min Typ Max Unit
VCC supply voltage 2.7 - 3.6 V
VIinput voltage 0 - 5.5 V
IOH HIGH-level output current - - −32 mA
74LVT_LVTH244A_4 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 04 — 3 September 2008 5 of 15
NXP Semiconductors 74LVT244A; 74LVTH244A
3.3 V octal buffer/line driver; 3-state
9. Static characteristics
IOL LOW-level output current none - - 32 mA
current duty cycle ≤50 %; fi≥1 kHz - - 64 mA
Tamb ambient temperature in free-air −40 - +85 °C
∆t/∆V input transition rise and fall rate outputs enabled - - 10 ns/V
Table 5. Operating conditions
…continued
Symbol Parameter Conditions Min Typ Max Unit
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
Tamb = −40 °C to +85 °C[1]
VIK input clamping voltage VCC = 2.7 V; IIK = −18 mA −1.2 −0.9 - V
VIH HIGH-level input voltage 2.0 - - V
VIL LOW-level input voltage - - 0.8 V
VOH HIGH-level output voltage VCC = 2.7 V to 3.6 V; IOH =−100 µAV
CC −0.2 VCC −0.1 - V
VCC = 2.7 V to 3.6 V; IOH = −8 mA 2.4 2.5 - V
VCC = 3.0 V; IOH = −32 mA 2.0 2.2 - V
VOL LOW-level output voltage VCC = 2.7 V; IOL = 100 µA - 0.1 0.2 V
VCC = 2.7 V; IOL = 24 mA - 0.3 0.5 V
VCC = 3.0 V; IOL = 16 mA - 0.25 0.4 V
VCC = 3.0 V; IOL = 32 mA - 0.3 0.5 V
VCC = 3.0 V; IOL = 64 mA - 0.4 0.55 V
IIinput leakage current all input pins
VCC = 0 V or 3.6 V; VI= 5.5 V - 0.1 10 µA
control pins
VCC = 3.6 V; VI=V
CC or GND - ±0.1 ±1µA
data pins [2]
VCC = 3.6 V; VI=V
CC - 0.1 1 µA
VCC = 3.6 V; VI=0V −5−1−µA
IOFF power-off leakage current VCC = 0 V; VI or VO = 0 V to 4.5 V - 1 ±100 µA
IBHL bus hold LOW current VCC = 3 V; VI = 0.8 V [3] 75 150 - µA
IBHH bus hold HIGH current VCC = 3 V; VI = 2.0 V −−150 −75 µA
IBHLO bus hold LOW
overdrive current nAn input;
VCC = 0 V to 3.6 V; VI= 3.6 V 500 - - µA
IBHHO bus hold HIGH
overdrive current nAn input;
VCC = 0 V to 3.6 V; VI= 3.6 V --−500 µA
ILO output leakage current nYn output in HIGH-state when
VO>V
CC; VO = 5.5 V; VCC = 3.0 V - 60 125 µA
IO(pu/pd) power-up/power-down
output current VCC ≤1.2 V; VO= 0.5 V to VCC;
VI= GND or VCC; nOE = don’t care [4] -±1±100 µA
74LVT_LVTH244A_4 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 04 — 3 September 2008 6 of 15
NXP Semiconductors 74LVT244A; 74LVTH244A
3.3 V octal buffer/line driver; 3-state
[1] All typical values are at Tamb = 25 °C.
[2] Unused pins at VCC or GND.
[3] This is the bus hold overdrive current required to force the input to the opposite logic state.
[4] This parameter is valid for any VCC between 0 V and 1.2 V with a transition time of up to 10 ms. From VCC = 1.2 V to VCC = 3.3 V ±0.3 V
a transition time of 100 µs is permitted. This parameter is valid for Tamb = 25 °C only.
[5] ICC is measured with outputs pulled to VCC or GND.
[6] This is the increase in supply current for each input at the specified voltage level other than VCC or GND.
10. Dynamic characteristics
IOZ OFF-state output current VCC = 3.6 V; VI=V
IH or VIL
VO = 3.0 V - 1 5 µA
VO = 0.5 V −5−1−µA
ICC supply current VCC = 3.6 V; VI = GND or VCC;
IO=0A
output HIGH - 0.13 0.19 mA
output LOW - 3 12 mA
outputs disabled [5] - 0.13 0.19 mA
∆ICC additional supply current per input pin; VCC = 3.0 V to 3.6 V;
one input at VCC −0.6 V and other
inputs at VCC or GND
[6] - 0.1 0.2 mA
CIinput capacitance VI = 0 V or 3.0 V - 4 - pF
COoutput capacitance outputs disabled; VO= 0 V or 3.0 V - 8 - pF
Table 6. Static characteristics
…continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7.
Symbol Parameter Conditions Min Typ Max Unit
Tamb = −40 °C to +85 °C[1]
tPLH LOW to HIGH
propagation delay nAn to nYn; see Figure 5
VCC = 2.7 V - - 5.0 ns
VCC = 3.0 V to 3.6 V 1 2.5 4.1 ns
tPHL HIGH to LOW
propagation delay nAn to nYn; see Figure 5
VCC = 2.7 V - - 5.1 ns
VCC = 3.0 V to 3.6 V 1 2.6 4.1 ns
tPZH OFF-state to HIGH
propagation delay see Figure 6
VCC = 2.7 V - - 6.3 ns
VCC = 3.0 V to 3.6 V 1 3.2 5.2 ns
tPZL OFF-state to LOW
propagation delay see Figure 6
VCC = 2.7 V - - 6.7 ns
VCC = 3.0 V to 3.6 V 1.1 3.1 5.2 ns
tPHZ HIGH to OFF-state
propagation delay see Figure 6
VCC = 2.7 V - - 6.3 ns
VCC = 3.0 V to 3.6 V 1.9 3.3 5.6 ns
74LVT_LVTH244A_4 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 04 — 3 September 2008 7 of 15
NXP Semiconductors 74LVT244A; 74LVTH244A
3.3 V octal buffer/line driver; 3-state
[1] All typical values are at VCC = 3.3 V and Tamb = 25 °C.
11. Waveforms
tPLZ LOW to OFF-state
propagation delay see Figure 6
VCC = 2.7 V - - 5.6 ns
VCC = 3.0 V to 3.6 V 1.8 3.3 5.1 ns
Table 7. Dynamic characteristics
…continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7.
Symbol Parameter Conditions Min Typ Max Unit
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 5. Propagation delay input (nAn) to output (nYn) propagation delays
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 6. 3-state output enable and disable times
mna171
nAn input
nYn output
tPLH tPHL
GND
VI
VM
VM
VM
VM
VOH
VOL
001aae464
tPZL
nYn output
nYn output
nOE input
VOL
VOH
3.0 V
VI
VM
GND
0 V
tPLZ
tPZH tPHZ
VX
VY
VM
VM
Table 8. Measurement points
Input Output
VMVMVXVY
1.5 V 1.5 V VOL + 0.3 V VOH − 0.3 V
74LVT_LVTH244A_4 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 04 — 3 September 2008 8 of 15
NXP Semiconductors 74LVT244A; 74LVTH244A
3.3 V octal buffer/line driver; 3-state
Test data is given in Table 9.
Definitions test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = Test voltage for switching times.
Fig 7. Load circuitry for switching times
VMVM
tW
tW
10 %
90 %
0 V
VI
VI
negative
pulse
positive
pulse
0 V
VMVM
90 %
10 %
tf
tr
tr
tf
001aai546
VEXT
VDD
VIVO
DUT
CL
RT
RL
RL
G
Table 9. Test data
Input Load VEXT
VIfitWtr, tfCLRLtPHZ, tPZH tPLZ, tPZL tPLH, tPHL
2.7 V ≤ 10 MHz 500 ns ≤ 2.5 ns 50 pF 500 ΩGND 6 V open
74LVT_LVTH244A_4 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 04 — 3 September 2008 9 of 15
NXP Semiconductors 74LVT244A; 74LVTH244A
3.3 V octal buffer/line driver; 3-state
12. Package outline
Fig 8. Package outline SOT163-1 (SO20)
UNIT A
max. A1A2A3bpcD
(1) E(1) (1)
eH
ELL
pQZ
ywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
2.65 0.3
0.1 2.45
2.25 0.49
0.36 0.32
0.23 13.0
12.6 7.6
7.4 1.27 10.65
10.00 1.1
1.0 0.9
0.4 8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.1
0.4
SOT163-1
10
20
wM
bp
detail X
Z
e
11
1
D
y
0.25
075E04 MS-013
pin 1 index
0.1 0.012
0.004 0.096
0.089 0.019
0.014 0.013
0.009 0.51
0.49 0.30
0.29 0.05
1.4
0.055
0.419
0.394 0.043
0.039 0.035
0.016
0.01
0.25
0.01 0.004
0.043
0.016
0.01
0 5 10 mm
scale
X
θ
A
A1
A2
HE
Lp
Q
E
c
L
vMA
(A )
3
A
SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1
99-12-27
03-02-19
74LVT_LVTH244A_4 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 04 — 3 September 2008 10 of 15
NXP Semiconductors 74LVT244A; 74LVTH244A
3.3 V octal buffer/line driver; 3-state
Fig 9. Package outline SOT339-1 (SSOP20)
UNIT A1A2A3bpcD
(1) E(1) eH
ELL
pQ(1)
Zywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.21
0.05 1.80
1.65 0.38
0.25 0.20
0.09 7.4
7.0 5.4
5.2 0.65 7.9
7.6 0.9
0.7 0.9
0.5 8
0
o
o
0.131.25 0.2 0.1
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
1.03
0.63
SOT339-1 MO-150 99-12-27
03-02-19
X
wM
θ
A
A1
A2
bp
D
HE
Lp
Q
detail X
E
Z
e
c
L
vMA
(A )
3
A
110
20 11
y
0.25
pin 1 index
0 2.5 5 mm
scale
SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1
A
max.
2
74LVT_LVTH244A_4 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 04 — 3 September 2008 11 of 15
NXP Semiconductors 74LVT244A; 74LVTH244A
3.3 V octal buffer/line driver; 3-state
Fig 10. Package outline SOT360-1 (TSSOP20)
UNIT A1A2A3bpcD
(1) E(2) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05 0.95
0.80 0.30
0.19 0.2
0.1 6.6
6.4 4.5
4.3 0.65 6.6
6.2 0.4
0.3 0.5
0.2 8
0
o
o
0.13 0.10.21
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT360-1 MO-153 99-12-27
03-02-19
wM
bp
D
Z
e
0.25
110
20 11
pin 1 index
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
HE
E
c
vMA
X
A
y
0 2.5 5 mm
scale
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1
A
max.
1.1
74LVT_LVTH244A_4 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 04 — 3 September 2008 12 of 15
NXP Semiconductors 74LVT244A; 74LVTH244A
3.3 V octal buffer/line driver; 3-state
Fig 11. Package outline SOT764-1 (DHVQFN20)
terminal 1
index area
0.51
A1Eh
b
UNIT ye
0.2
c
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 4.6
4.4
Dh
3.15
2.85
y1
2.6
2.4 1.15
0.85
e1
3.5
0.30
0.18
0.05
0.00 0.05 0.1
DIMENSIONS (mm are the original dimensions)
SOT764-1 MO-241 - - -- - -
0.5
0.3
L
0.1
v
0.05
w
0 2.5 5 mm
scale
SOT764-1
DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
20 terminals; body 2.5 x 4.5 x 0.85 mm
A(1)
max.
AA1c
detail X
y
y1C
e
L
Eh
Dh
e
e1
b
29
19 12
11
10
1
20
X
D
E
C
BA
terminal 1
index area
AC
CB
vM
wM
E(1)
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
D(1)
02-10-17
03-01-27
74LVT_LVTH244A_4 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 04 — 3 September 2008 13 of 15
NXP Semiconductors 74LVT244A; 74LVTH244A
3.3 V octal buffer/line driver; 3-state
13. Abbreviations
14. Revision history
Table 10. Abbreviations
Acronym Description
BiCMOS BIpolar Complementary Metal Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
TTL Transistor-Transistor Logic
Table 11. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74LVT_LVTH244A_4 20080903 Product data sheet - 74LVT_LVTH244A_3
Modifications: •The format of this data sheet has been redesigned to comply with the new identity guidelines of
NXP Semiconductors.
•Legal texts have been adapted to the new company name where appropriate.
•Section 3 “Ordering information” and Section 12 “Package outline” DHVQFN20 package
added.
74LVT_LVTH244A_3 20060315 Product specification - 74LVT244A_2
74LVT244A_2 19980219 Product specification - 74LVT244A_1
74LVT_LVTH244A_4 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 04 — 3 September 2008 14 of 15
NXP Semiconductors 74LVT244A; 74LVTH244A
3.3 V octal buffer/line driver; 3-state
15. Legal information
15.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
15.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
NXP Semiconductors 74LVT244A; 74LVTH244A
3.3 V octal buffer/line driver; 3-state
© NXP B.V. 2008. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 3 September 2008
Document identifier: 74LVT_LVTH244A_4
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
17. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 1
4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
6 Functional description . . . . . . . . . . . . . . . . . . . 4
6.1 Function table. . . . . . . . . . . . . . . . . . . . . . . . . . 4
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
8 Recommended operating conditions. . . . . . . . 4
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 13
14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 13
15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 14
15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14
15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
16 Contact information. . . . . . . . . . . . . . . . . . . . . 14
17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
