TSC695E Rad-Hard Rad-Hard 32-bit SPARC SPARC 32-bit Embedded Processor Processor Embedded Data Sheet Rev.D - August 2000 1 TSC695E Data Sheet Information Foreword Atmel Nantes S.A. reserves the right to make changes in the products or specifications contained in this document in order to improve design or performance and to supply the best possible products. Atmel Nantes S.A. also assumes no responsibility for the use of any circuits described herein, conveys no license under any patents or other rights, and makes no representations that the circuits are free from patent infringement. Applications for any integrated circuits contained in this publication are for illustration purposes only and Atmel Nantes S.A. makes no representation or warranty that such applications will be suitable for the use specified without further testing or modification. Reproduction of any portion hereof without the prior written consent of Atmel Nantes S.A. is prohibited. Definition of Terms The product Data Sheet contained in this document is referring to the following possible status: Data Sheet Identification Preview Definition This Data Sheet contains the targeted specifications, all electrical parameters correspond to either targeted or simulated values. Specifications may change in any manner without notice. Preliminary This Data Sheet contains final functional specification. The electrical parameters given are based either on simulated values or on preliminary product characterization results. Specifications may change in any manner without notice. No Indication (blank) This Data Sheet contains final specifications. Atmel Wireless & Microcontrollers reserves the right to make changes at any time, according to Atmel Wireless & Microcontrollers Quality Assurance procedures, in order to improve design and supply the best possible product. Atmel Wireless & Microcontrollers on Line Information World Wide Web: http://www.atmel-wm.com Contact Atmel Nantes S.A. La Chantrerie Route de Gachet, BP 70602 44306 NANTES Cedex 03 France Tel: +33 2 40 18 18 18 Fax: +33 2 40 18 19 20 2 Rev.D - August 2000 TSC695E 1. Overview The TSC695E (ERC32 Single-Chip) is a highly integrated, high-performance 32-bit RISC embedded processor implementing the SPARC architecture V7 specification. It has been developed with the support of the ESA (European Space Agency), and is offering a full development environment for embedded space applications. The processor is manufactured using the Atmel Wireless & C 0.5 m radiation tolerant ( 300 KRADs (Si)) CMOS enhanced process (RTP). It can operate at a low voltage for optimized power consumption. It has been especially designed for space, as it has on-chip concurrent transient and permanent error detection. The TSC695E includes on chip an Integer Unit (IU), a Floating Point Unit (FPU), a Memory Controller and a DMA Arbiter. For Real Time applications, the TSC695E offers a high security Watch Dog, two Timer's, an Interrupt Controller, Parallel and Serial interfaces. Fault tolerance is supported using parity on internal/external buses and an EDAC on the external data bus. The design is highly testable with the support of an On-Chip Debugger (OCD), an internal and boundary scan through JTAG interface. 2. Features Integer Unit based on SPARC V7 high performance RISC architecture Optimized integrated 32/64-bit floating-point unit On-chip peripherals: * EDAC and parity generator and checker * Memory interface: - Chip select generator - Waitstate generation - Memory protection * DMA arbiter * Timers: - General purpose timer (GPT) - Real time clock timer (RTCT) - Watch dog timer (WDT) * Interrupt controller with 5 external inputs * General purpose interface (GPI) * Dual UART Speed optimized code RAM interface 8 or 40-bit boot-PROM (Flash) interface IEEE 1149.1 test access port (TAP) for debugging and test purposes Fully static design Performance: 20 MIPs / 5 MFlops (double precision) @ SYSCLK = 25 MHz Core consumption: 1.0 W typ. @ 20 MIPs / 0.7 W typ. @ 10 MIPs Operating range: 4.5 V to 5.5 V (3 V capability) -55 C to +125 C Total dose radiation capability (parametric & functional): 300 KRADs (Si) SEU event rate better than 1E-8 error/component/day (worst case) Latch up immunity better than (LET) 100 MeV-cm2/mg Quality grades: ESA SCC, QML Q or V Package: 256 MQFPF; KGD Rev.D - August 2000 3 TSC695E 4 Rev.D - August 2000 TSC695E 3. Product Organization 3.1 Block Diagram DMA TAP Clock & Resett Manag 32-bit Integer Unit Arbiter 32/64-bit Floating-Point Unit Parity Access Controller Parity Gen./Chk. Gen./Chk. Wait State Controller Address Error t Manag General Purpose Timer Real Time Clock Timer Watch Dog General Purpose Interface UART B UART A Interrupt Controller GPI bits RxD, TxD Interrupts DMA Ctrl Mem Ctrl Ready/Busy Interface Add.+Size+ASI EDAC Data+Check bits Parity Gen./Check. Parities Figure 1. TSC695E Block Diagram 3.2 Signals Descriptions Table 1. TSC695E External Signals Summary Signal Type RA[31:0] RAPAR RASI[3:0] RSIZE[1:0] RASPAR CPAR D[31:0] CB[6:0] DPAR RLDSTO ALE DXFER LOCK RD WE WRT I/O, I/O I/O I/O I/O I/O I/O I/O I/O I/O O I/O I/O I/O I/O I/O MHOLD MDS MEXC PROM8 BA[1:0] ROMCS ROMWRT MEMCS[9:0] MEMWR OE BUFFEN Rev.D - August 2000 Active Description High High Low High High High Low High 32-bit registered address bus Registered address bus parity 4-bit registered address space identifier 2-bit registered bus transaction size Registered ASI and SIZE parity Control bus parity 32-bit data bus 7-bit check-bit bus Data bus parity Registered atomic load-store Address latch enable Data transfer Bus lock Read access Write enable Advanced write O Low Memory bus hold O O I O O I O O O O Low Low Low Memory data strobe Memory exception Select 8-bit wide PROM Latched address used for 8-bit wide boot PROM PROM chip select ROM write enable Memory chip select Memory write strobe Memory output enable Data buffer enable High High High Low Low Low Low Low Low Output buffer: 400pF MHOLD+FHOLD +BHOLD+FCCV Output buffer: 400pF Output buffer: 400pF Output buffer: 400pF 5 TSC695E Table 1. TSC695E External Signals Summary Signal Type Active DDIR DDIR IOSEL[3:0] IOWR EXMCS BUSRDY BUSERR DMAREQ DMAGNT DMAAS DRDY IUERR CPUHALT SYSERR SYSHALT SYSAV NOPAR INULL INST FLUSH DIA RTC RxA/RxB TxA/TxB GPI[7:0] GPIINT EXTINT[4:0] EXTINTACK IWDE EWDINT WDCLK CLK2 SYSCLK RESET SYSRESET TMODE[1:0] DEBUG TCK TRST TMS TDI TDO VCCI/VSSI VCCO/VSSO O O O O O I I I O I O O O O I O I O O O O O I O I/O O I O I I I I O O I I I I I I I O High Low Low Low Low Low Low Low Low High Low Low Low Low Low High Low High High High High High High High High High Low Low High Low Description Data buffer direction Data buffer direction I/O chip select I/O and exchange memory write strobe Exchange memory chip select Bus ready Bus error DMA request DMA grant DMA address strobe Data ready during DMA access IU error Processor (IU & FPU) halt and freeze System error System halt System availability No parity Integer unit nullify cycle Instruction fetch FPU instruction flush Delay instruction annulled Real Time Clock Counter output Receive data UART "A" and "B" Transmit data UART "A" and "B" GPI input/output GPI interrupt External interrupt External interrupt acknowledge Internal watch dog enable External watch dog input interrupt Watch dog clock Double frequency clock System clock Output reset System input reset Factory test mode Software debug mode Test (JTAG) clock Test (JTAG) reset Test (JTAG) mode select Test (JTAG) data input Test (JTAG) data output Main internal power Output driver power Used to check the execute stage of IU instruction pipeline Input trigger Input trigger Input trigger Input trigger Input trigger Functional mode=00 pull-up 37 k pull-up 37 k pull-up 37 k Note: If not specified, the output buffer type is 150 pF, the input buffertype is TTL. 6 Rev.D - August 2000 TSC695E 3.3 System Architecture The TSC695E is to be used as an embedded processor requiring only memory and application specific peripherals to be added to form a complete on-board computer. All other system support functions are provided by the core. DMA Unit Boot PROM Ax[31:0] Xtd PROM master Xchg Mem Glue logic local memory Xtd RAM I/O 0 to I/O 3 DMAREQ DMAGNT DMAAS DPAR Xtd I/O (BUFFEN, DDIR) Xtd general Memory Interface CB[6:0] FPU RA[31:0] MEMCtrl (ROMCS, EXMCS, IOSEL[3:0], MEMWR, IOWR, OE, BUSRDY, ...) DMA A[31:0] IU DMA Peripherals RAM Memory (0 ws) D[31:0] SYSCLK ALE RAMCtrl (MEMCS[9:0], MEMWR, OE) User Application TSC695E Figure 2. TSC695E System Architecture Rev.D - August 2000 7 TSC695E 8 Rev.D - August 2000 TSC695E 4. Product Description 4.1 Integer Unit The IU is designed for highly dependable space and military applications, and includes support for error detection. The RISC architecture makes possible the creation of a processor that can execute instructions at a rate approaching one instruction per processor clock. To achieve that rate of execution, the IU employs a four-stage instruction pipeline that permits parallel execution of multiple instructions. * Fetch- The processor outputs the instruction address to fetch the instruction. * Decode- The instruction is placed in the instruction register and is decoded. The processor reads the operands from the register file and computes the next instruction address. * Execute- The processor executes the instruction and saves the results in temporary registers. Pending traps are prioritized and internal traps are taken during this stage. * Write- If no trap is taken, the processor writes the result to the destination register. All four stages operate in parallel, working on up to four different instructions at a time. A basic "single-cycle" instruction enters the pipeline and completes in four cycles. By the time it reaches the write stage, three more instructions have entered and are moving through the pipeline behind it. So, after the first four cycles, a single-cycle instruction exits the pipeline and a single-cycle instruction enters the pipeline on every cycle. Of course, a "single-cycle" instruction actually takes four cycles to complete, but they are called single cycle because with this type of instruction the processor can complete one instruction per cycle after the initial four-cycle delay. 4.2 Floating-Point Unit The FPU is designed to provide execution of single and double-precision floating-point instructions concurrently with execution of integer instructions by the IU. The FPU is compliant to the ANSI/IEEE-754 (1985) floatingpoint standard. The FPU is designed for highly dependable space and military applications, and includes support for concurrent error detection and testability. The FPU uses a four stage instruction pipeline consisting of fetch, decode, execute and write stages (F, D, E and W). The fetch unit captures instructions and their addresses from the data and address busses. The decode unit contains logic to decode the floating-point instruction opcodes. The execution unit handles all instruction execution. The execution unit includes a floating-point queue (FP queue), which contains stored floating-point operate (FPop) instructions under execution and their addresses. The execution unit controls the load unit, the store unit, and the datapath unit. The FPU depends upon the IU to access all addresses and control signals for memory access. Floatingpoint loads and stores are executed in conjunction with the IU, which provides addresses and control signals while the FPU supplies or stores the data. Instruction fetch for integer and floating-point instructions is provided by the IU. The FPU provides three types of registers: f registers, FSR, and the FP queue. The FSR is a 32-bit status and control register. It keeps track of rounding modes, floating-point trap types, queue status, condition codes, and various IEEE exception information. The floating-point queue contains the floating-point instruction currently under execution, along with its corresponding address. 4.3 Instruction Set TSC695E instructions fall into six functional categories: load/store, arithmetic/logical/shift, control transfer, read/ write control register, floating-point-operate-operate, and miscellaneous. Note: The execution of IFLUSH will cause an illegal instruction trap. Rev.D - August 2000 9 TSC695E 4.4 On-Chip Peripherals 4.4.1 Memory Interface 4.4.1.1 Memory Mapping The TSC695E is design to allow an easy interfacing to internal/external memory resources. Table 2. Memory Mapping Memory contents Start Address Boot PROM 0x 0000 0000 Extended PROM 0x 0100 0000 Exchange Memory System Registers RAM (8 blocks) Extended RAM I/O Area 0 I/O Area 1 I/O Area 2 I/O Area 3 Extended I/O Area Extended General 0x 01F0 0000 0x 01F8 0000 0x 0200 0000 0x 0400 0000 0x 1000 0000 0x 1100 0000 0x 1200 0000 0x 1300 0000 0x 1400 0000 0x 8000 0000 Size (bytes) Data size and parity options 8-bit mode -No parity / -No EDAC / -Only byte write 128K 16M 40-bit mode -Parity + EDAC mandatory / -Only word write 8-bit mode -No parity / -No EDAC / -Only byte write Max: 15M 40-bit mode -Parity + EDAC mandatory / -Only word write 4k 512k -Parity + EDAC option / -Only word write 512K (124 used) -Parity / -Only word read/write access 8*32K 8*4M -Parity + EDAC option / -All data sizes allowed Max: 192M 0 16M 0 16M 0 16M -Parity option / -All data sizes allowed 0 16M Max: 1728M Max: 2G -No parity / -All data sizes allowed 4.4.1.2 System Registers The system registers are only writeable by IU in the supervisor mode or by DMA during halt mode. Table 3. System Registers Address Map System Register Name System Control Register Software Reset Power Down System Fault Status Register Failing Address Register Error & Reset Status Register Test Control Register Memory Configuration Register I/O Configuration Register Waitstate Configuration Register Access Protection Segment 1 Base Register Access Protection Segment 1 End Register Access Protection Segment 2 Base Register Access Protection Segment 2 End Register Interrupt Shape Register Interrupt Pending Register Interrupt Mask Register Interrupt Clear Register Interrupt Force Register Watchdog Timer Register Watchdog Timer Trap Door Set Real Time Clock Timer <Counter> Register 10 Address SYSCTR SWRST PDOWN SYSFSR FAILAR ERRRSR TESCTR MCNFR IOCNFR WSCNFR APS1BR APS1ER APS2BR APS2ER INTSHR INTPDR INTMKR INTCLR INTFCR WDOGTR WDOGST RTCCR 0x 01F8 0000 0x 01F8 0004 0x 01F8 0008 0x 01F8 00A0 0x 01F8 00A4 0x 01F8 00B0 0x 01F8 00D0 0x 01F8 0010 0x 01F8 0014 0x 01F8 0018 0x 01F8 0020 0x 01F8 0024 0x 01F8 0028 0x 01F8 002C 0x 01F8 0044 0x 01F8 0048 0x 01F8 004C 0x 01F8 0050 0x 01F8 0054 0x 01F8 0060 0x 01F8 0064 0x 01F8 0080 Rev.D - August 2000 TSC695E Table 3. System Registers Address Map System Register Name Real Time Clock Timer <Scaler> Register General Purpose Timer <Counter> Register General Purpose Timer <Scaler> Register Timers Control Register General Purpose Interface Configuration Register General Purpose Interface Data Register UART "A" Rx & Tx Register UART "B" Rx & Tx Register UART Status Register Address RTCSR GPTCR GPTSR TIMCTR GPICNFR GPIDATR UARTAR UARTBR UARTSR 0x 01F8 0084 0x 01F8 0088 0x 01F8 008C 0x 01F8 0098 0x 01F8 00A8 0x 01F8 00AC 0x 01F8 00E0 0x 01F8 00E4 0x 01F8 00E8 4.4.1.3 Wait-State and Time-out Generator It is possible to control the wait state generation by programming a Waitstate Configuration Register. The maximum programmable number of wait-states is applied by default at reset. It is possible to program the number of wait states for the following combinations: - RAM read and write - PROM read and write (i.e. EEPROM or FLASH write) - Exchange Memory read/write - Four individual I/O peripherals read/write A bus time-out function of 256 system clock cycles is provided for the bus ready controlled memory areas, i.e the Extended PROM, Exchange Memory, Extended RAM, Extended I/O and the Extended General areas. 4.4.1.4 EDAC The TSC695E includes a 32-bit EDAC (Error Detection And Correction). Seven bits (CB[6:0]) are used as check bits over the data bus. The Data Bus Parity signal (DPAR) is used to check and generate the odd parity over the 32-bit data bus. This means that altogether 40 bits are used when the EDAC is enabled. The TSC695E EDAC uses a seven bit Hamming code which detects any double bit error on the 40-bit bus as a non-correctable error. In addition, the EDAC detects all bits stuck-at-one and stuck-at-zero failure for any nibble in the data word as a non-correctable error. Stuck-at-one and stuck-at-zero for all 32 bits of the data word is also detected as a non-correctable error. 4.4.1.5 Memory and I/O Parity The TSC695E handles parity towards memory and I/O in a special way. The processor can be programmed to use no parity, only parity or parity and EDAC protection towards memory and to use parity or no towards I/O. The signal used for the parity bit is DPAR. 4.4.1.6 Memory Redundancy Programming the Memory Configuration Register, the TSC695E provides chip selects for two redundant memory banks for replacement of faulty banks. 4.4.1.7 Memory Access Protection * Unimplemented Areas - Accesses to all unimplemented memory areas are handled by the TSC695E and detected as illegal. * RAM Write Access Protection - The TSC695E can be programmed to detect and mask write accesses in any part of the RAM. The protection scheme is enabled only for data area, not for the instruction area. The programmable write access protection is based on two segments. * Boot PROM Write Protection - The TSC695E supports a qualified PROM write for an 8-bit wide PROM and/or for a 40-bit wide PROM. Rev.D - August 2000 11 TSC695E 4.4.2 DMA 4.4.2.1 DMA Interface The TSC695E supports Direct Memory Access (DMA). The DMA unit requests access to the processor bus by asserting the DMA request signal (DMAREQ). When the DMA unit receives the DMAGNT signal in response, the processor bus is granted. In case the processor is in the power down mode the processor is permanent tristated, and a DMAREQ will directly give a DMAGNT. The TSC695E includes a DMA session time-out function. 4.4.2.2 Bus Arbiter The TSC695E always has the lowest priority on the system bus. 4.4.3 Traps A trap is a vectored transfer of control to the supervisor through a special trap table that contains the first four instructions of each trap handler. The base address of the table is established by supervisor and the displacement, within the table, is determined by the trap type. Two categories of traps can appear. 4.4.3.1 Synchronous Traps Table 4. Synchronous Traps Trap Priority Hardware Error Reset 1 Non-restartable, imprecise error Non-restartable, precise error - 2.1 64h 2.2 62h 2.3 65h Restartable, late error 2.4 63h Restartable, precise error 2.5 61h Register file error Instruction access (Error on instruction fetch) Illegal Instruction Privileged instruction FPU disabled Overflow Window Underflow Memory address not aligned 12 Trap Type (tt) 2 3 01h 4 5 6 02h 03h 04h 05h 06h 07h 7 8 Comments Sources: - SYSRESET* pin - software reset - watchdog reset - IU or System error reset Severe error requiring a re-boot TSC695E enters (if not masked) in halt or reset mode. Error not removable, PC & nPC OK TSC695E enters (if not masked) in halt or reset mode. Special case of non -restartable, precise error. TSC695E enters (if not masked) in halt or reset mode. Retrying instruction but PC & nPC have to be re-adjusted TSC695E enters (if not masked) in halt or reset mode. Retrying instruction TSC695E enters (if not masked) in halt or reset mode. - Parity error on control bus - Parity error on data bus - Parity error on address bus - Access to protected or unimplemented area - Uncorrectable error in memory - Bus time out - Bus error During SAVE instruction or trap taken During RESTORE instruction or RETT instruction Rev.D - August 2000 TSC695E FPU exception Trap Priority Non-restartable error Data bus error Restartable error Sequence error Unimplemented FPop IEEE exceptions: Data access exception (Error on data load) Tag overflow Trap instructions 9 9.1 9.2 9.3 9.4 9.5 9.6 10 11 12 Trap Type (tt) Comments Severe error, cannot restarting the instruction. Parity error on FPU data bus. Can be removed restarting the instruction. 08h - Invalid operation - Division by zero - Overflow - Underflow - Inexact - Idem "instruction access" 09h - System register access violation 0Ah TADDccTV and TSUBccTV instructions 80h to FFh Trap on integer condition codes (Ticc) 4.4.3.2 Interrupts or Asynchronous Traps Table 5. Interrupts or Asynchronous Traps Priority Trap Type (tt) Watchdog time-out External INT 4 Real time clock timer General purpose timer External INT 3 External INT 2 DMA time-out DMA access error UART Error Correctable error in memory - Data ready UART B - Transmitter ready - Data ready UART A - Transmitter ready External INT 1 External INT 0 13 14 15 16 17 18 19 20 21 22 1Fh 1Eh 1Dh 1Ch 1Bh 1Ah 19h 18h 17h 16h 23 15h 24 14h 25 26 13h 12h Masked hardware errors 27 11h Trap Comments Internal or external (EWDINT pin) EXTINTAK on only one of EXTINT[4:0] EXTINTAK on only one of EXTINT[4:0] EXTINTAK on only one of EXTINT[4:0] Data read OK but source not updated EXTINTAK on only one of EXTINT[4:0] EXTINTAK on only one of EXTINT[4:0] Logical OR of: - IU hardware error masked - IU error mode masked - System hardware error masked It is possible to mask each individual interrupt (except Watchdog time-out). The interrupts in the Interrupt Pending Register are cleared automatically when the interrupt is acknowledged. By programming the Interrupt Shape Register, it is possible to define the external interrupts to be either active low or active high and to define the external interrupts to be either edge or level sensitive. 4.4.4 Timers In software debug mode the timers are controlled by a system register bit and the external pin DEBUG. Rev.D - August 2000 13 TSC695E 4.4.4.1 General Purpose Timer The General Purpose Timer (GPT) provides, in addition to a generalized counter function, a mechanism for setting the step size in which actual time counts are performed. GPT is clocked by the internal system clock. They are possible to program to be either of single-shot type or periodical type and in both cases generate an interrupt when the delay time has elapsed. The current value of the scaler and counter of the GPT can be read. 4.4.4.2 Real Time Clock Timer The only functional differences between the two timers are that the Real Time Clock Timer (RTCT) has an 8-bit scaler (16-bit scaler for GPT) and that the RTCT interrupt has higher priority than the GPT interrupt. RTCT information is available on RTC output pin. 4.4.4.3 Watchdog Timer Setting the external pin IWDE to Vcc enables the internal watchdog timer. Otherwise the watchdog function must be externally provided. The watchdog is supplied from a separate external input (WDCLK). After reset, the timer is enabled and starts running with the maximum range. If the timer is not refreshed (reprogrammed) before the counter reaches zero value, an interrupt is sent. Simultaneously, the timer starts counting a reset time-out period. If the timer is not acknowledged before the reset time-out period elapses, a reset is applied to TSC695E. 4.4.5 UART's Two full duplex asynchronous receiver transmitters (UART) are included. In software debug mode the UART's are controlled by system register bits. The data format of the UART's is eight bits. It is possible to choose between even or odd parity, or no parity, and between one and two stop bits. The UART's provide double buffering, i.e. each UART consists of a transmitter holding register, a receiver holding register, a transmitter shift register, and a receiver shift register. Each of these registers are 8-bit wide. For each UART a RX and TX Register is provided. The UART's generate an interrupt each time a byte has been received or a byte has been sent. There is another interrupt to indicate errors. The baud rate of both the UART's is programmable. The clock is derived either from the system clock or can use the watchdog clock. 4.4.6 General Purpose Interface The General Purpose Interface (GPI) is an 8-bit parallel I/O port. Each pin can be configured as an input or an output. A falling or rising edge detection is made on each selected GPI inputs. Every input transition on GPI generates an external positive pulse on GPIINT pin of two SYSCLK width. 4.4.7 Execution Modes 4.4.7.1 Reset Mode Reset mode is entered when: - The SYSRES input is asserted, - Software reset which is caused by the software writing to a Software Reset Register, - Watchdog reset which is caused by a Watchdog counter time-out, - Error reset which is caused by a hardware parity error, EDAC uncorrectable error. This RESET output have a minimum of 1024 SYSCLK width to allow the usage of flash memories. Error and Reset Status Register contains the source of the last processor reset. 4.4.7.2 Run Mode In this mode the IU/FPU is executing, all peripherals are running (if software enabled). 14 Rev.D - August 2000 TSC695E 4.4.7.3 System Halt Mode System Halt mode is entered when the SYSHALT input is asserted. In this mode, the IU and FPU are frozen, the timers (included internal watchdog timer) and UART's are stopped. 4.4.7.4 Power Down Mode This mode is entered by writing to the Power Down Register. In this mode, the IU and FPU are frozen. The TSC695E leaves the power-down mode if an external interrupt is asserted. 4.4.7.5 Error Halt Mode Error Halt mode is entered under the following circumstances: - A internal hardware parity error. - The IU enters error mode. The only way to exit Error Halt Mode is through Cold Reset by asserting SYSRESET. 4.4.8 Error Handler The TSC695E has one error output signal (SYSERR) which indicates that an unmasked error has occurred. Any error signalled on the error inputs from the IU and the FPU is latched and reflected in the Error and Reset Status Register. As default, an error leads to a processor halt. 4.4.9 Parity Checking The TSC695E includes: - Parity checking and generation (if required) on the external data bus, - Parity checking on the external address bus, - Parity checking on ASI and SIZE, - Parity checking and generation on all system registers, - Parity generation and checking on the internal control bus to the IU, All external parity checking can be disabled using the NOPAR signal. 4.4.10 System Clock The TSC695E uses CLK2 clock input directly and creates a system clock signal by dividing CLK2 by two. It drives SYSCLK pin with a nominal 50% duty cycle for the application. It is highly recommended that only SYSCLK rising edge is used as reference as far as possible. 4.4.11 System Availability The SYSAV bit in the Error and Reset Status Register can be used by software to indicate system availability. 4.4.12 Test Mode The TSC695E includes a number of software test facilities such as EDAC test, Parity test, Interrupt test, Error test and a simple Test Access Port. These test functions are controlled using the Test Control Register. 5. Test and Diagnostic Hardware Functions A variety of TSC695E test and diagnostic hardware functions, including boundary scan, internal scan, clock control and On-Chip Debugger, are controlled through an IEEE 1149.1 (JTAG) standard Test Access Port (TAP). 5.1 Test Access Port The TAP interfaces to the JTAG bus via 5 dedicated pins on the TSC695E chip. These pins are: - TCK (input): Test Clock, Rev.D - August 2000 15 TSC695E - TMS (input): Test Mode Select, TDI (input): Test Data Input, TDO (output): Test Data Output, TRST (input): Test Reset 5.2 The Instruction Register Five standard instructions are supported by the TSC695E TAP. Table 6. JTAG Instructions Binary Value Name of Instruction Data Register Scan Chain Accessed 00 . 0000 EXTEST Boundary Scan Register Boundary scan chain 00 . 0001 SAMPLE/PRELOAD Boundary Scan Register Boundary scan chain 00 . 0011 INTEST Boundary Scan Register Boundary scan chain 11 . 1111 BYPASS Bypass Register Bypass register 10 . 0000 IDCODE Device ID Register ID register scan chain 5.3 Debugging The design is highly testable with the support of an On-Chip Debugger (OCD), an internal and boundary scan through JTAG interface. 16 Rev.D - August 2000 TSC695E 6. Electrical and Mechanical Specification 6.1 Maximum Rating and DC Characteristics 6.1.1 Maximum Ratings * Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 C to +150 C * Ambient Temperature with Power Applied . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 C to +125 C * Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to +7.0 V * Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to +7.0 V 6.1.2 Operating Range Range Ambient Temperature Vcc Military -55 C to +125 C +5 V 10% 6.1.3 DC Characteristics Over the Operating Range Symbol Parameter VIL trigger Input Low Voltage for trigger input VIH trigger Input High Voltage for trigger input VT Input Hysteresis for trigger input VIL TTL Input Low Voltage for TTL input VIH TTL Input High Voltage for TTL input VOL400pF Output Low Voltage for 400pf buffer VOH400pF Output High Voltage for 400pf buffer VOL150pF Output Low Voltage for 150pf buffer VOH150pF Output High Voltage for 150pf buffer IccOP Operating Supply Current for core processor min Typ MAX Unit Test Conditions 0.8 V Vcc = 4.5 to 5.5 V V Vcc = 4.5 to 5.5 V V Vcc = 4.5 to 5.5 V V Vcc = 4.5 to 5.5 V V Vcc = 4.5 to 5.5 V V Vcc = 4.5 to 5.5 V IOL = 12 mA V Vcc = 4.5 to 5.5 V IOH = - 16 mA V Vcc = 4.5 to 5.5 V IOL = 4 mA V Vcc = 4.5 to 5.5 V IOH = - 6 mA 3.0 0.9 0.8 2.2 0.3 2.4 0.3 0.3 2.4 0.4 0.4 4.3 230 210 Vcc = 5.5 V, f = 25 MHz mA 170 Vcc = 5.5 V, f = 10 MHz 41 IccPD Power Down Supply Current for core processor 38 30 Rev.D - August 2000 Vcc = 5.5 V, f = 20 MHz Vcc = 5.5 V, f = 25 MHz mA Vcc = 5.5 V, f = 20 MHz Vcc = 5.5 V, f = 10 MHz 17 TSC695E 6.1.4 Capacitance Ratings Parameter Description MAX CIN Input Capacitance 7 pF COUT Output Capacitance 8 pF CIO Input/Output Capacitance 8 pF 6.2 AC Characteristics 6.2.1 AC Characteristics (SYSCLK Freq. = 25 MHz - 5V 10 %) Param. t1 t2 t3 t4 t5 t6 min (ns) 20 40 9.75 6.5 12.5 15 t7 23.5 t8 20.5 t9 t10 9 5 t11 t12 28 8 t13 t14 19 13 t15 21 t17 t20 t21 t22 t23 t24 t25 15 15 10 3 13 12 0 t27 18 Max (ns) 15 t28 12 20 t29 0 20 t30 t31 t32 t33 t36 t37 12 15 10 3 100 10 Comment CLK2 period SYSCLK period CLK2 high and low pulse width RA(31:0) RAPAR RSIZE output delay MEMCS*(9:0) ROMCS* EXMCS* output delay DDIR DDIR* output delay MEMWR* output delay formula: 13.5 ns + 1/4 t2 OE* HL output delay formula: 10.5 ns + 1/4 t2 Data setup time during load Data hold time during load Data output delay formula: 18 ns + 1/4 t2 Data output valid guaranteed by design CB output delay ALE* output delay BUFFEN* HL output delay formula: 11 ns + 1/4 t2 MDS* DRDY* output delay MEXC* output delay RASI(3:0) RSIZE(1:0) RASPAR setup time RASI(3:0) RSIZE(1:0) RASPAR hold time BOOT PROM address output delay BUSRDY* setup time BUSRDY* hold time IOSEL output delay DMAAS setup time formula of max: 1/2 t2 DMAAS hold time formula of max: 1/2 t2 DMAREQ* setup time DMAGNT* output delay RA(31:0) RAPAR CPAR setup time RA(31:0) RAPAR CPAR hold time TCK period TMS setup time Reference edge SYSCLK+ SYSCLK+ SYSCLK+ SYSCLK- or SYSCLK+ SYSCLK+ SYSCLK+ SYSCLK+ SYSCLKSYSCLK+ SYSCLK+ SYSCLKSYSCLK+ SYSCLK+ SYSCLKSYSCLK+ SYSCLK+ SYSCLK+ SYSCLK+ SYSCLK+ SYSCLK+ HL SYSCLK+ HL SYSCLK+ SYSCLKSYSCLK+ SYSCLK+ SYSCLK+ SYSCLK+ TCK+ Rev.D - August 2000 TSC695E Param. min (ns) t38 t39 t40 t41 t46 t48 t49 t50 t52 t53 t54 t56 t57 t60 4 10 10 t61 20 Max (ns) 20 22 22 20 20 12 0 15 8.5 9 22 Rev.D - August 2000 Comment TMS hold time TDI setup time TDI hold time TDO output delay INULL output delay RESET* CPUHALT* output delay SYSERR* SYSAV output delay IUERR* output delay EXTINT(4:0) setup time EXTINT(4:0) hold time EXTINTACK output delay OE* LH output delay (no DMA mode) BUFFEN* LH output delay INST output delay Data output delay to low-Z guaranteed by design formula: 10 ns + 1/4 t2 Reference edge TCK+ TCK+ TCK+ TCKSYSCLK+ SYSCLK+ SYSCLK+ SYSCLK+ SYSCLKSYSCLK+ SYSCLK+ SYSCLK+ SYSCLK+ SYSCLK+ SYSCLK+ 19 3 (ram fetch) 4 (ram store) t1 t3 5 (ram fetch) t3 CLK2 t2 SYSCLK ALE t4 RA [31:0] FA1 t4 LA1 t4 t4 FA2 SA1 FA3 t5 t5 t5 t5 MEMCS* [0] MEMCS* [1] ROMCS* t6 t6 DDIR t7 t7 MEMWR* BUFFEN* t8 t56 t56 t8 OE* t10 D [31:0] t9 FD1 t10 t9 LD1 t61 t11 t12 FD2 SD1 FD3 previous stored data t10 DPAR t9 FP1 t10 t9 LP1 t61 t11 t12 FP2 SP1 FP3 previous stored parity t10 Rev.D - August 2000 CB [6:0] FC1 t9 t10 LC1 t9 t61 t13 FC2 t12 SC1 FC3 previous stored checkbyte t60 t60 t60 INST MHOLD* MDS* RAM fetch, RAM load, RAM fetch and RAM store sequence - 0 waitstate t60 TSC695E 2 (ram load) 6.2.2 Timing Diagrams 20 1 (ram fetch) Rev.D - August 2000 1 (ram fetch) 2 (ram load) 3 (ram fetch) t1 4 (ram store) 5 (ram fetch) t3 t3 CLK2 n ws n ws n ws m ws n ws t2 SYSCLK t4 RA [31:0] t4 FA1 t4 LA1 t14 t4 FA2 SA1 FA3 t14 ALE t5 t5 t5 t5 MEMCS* [0] MEMCS* [1] ROMCS* t6 t6 DDIR t7 t7 MEMWR* BUFFEN* t8 t56 t56 t8 OE* t10 t11 t61 t9 D [31:0] FD1 LD1 t12 FD2 SD1 FD3 previous stored data t10 t11 t61 t9 DPAR FP1 LP1 t12 FP2 SP1 FP3 previous stored parity t10 t9 FC1 t61 LC1 t13 FC2 t12 SC1 FC3 previous stored checkbyte t60 t60 t60 t60 INST t16 t16 MHOLD* t17 t17 t17 t17 t17 t17 MDS* 21 RAM fetch, RAM load and RAM store sequence - n waitstates for read, m waitstates for write t17 TSC695E CB [6:0] 2 (ram atomic load store) 3 (ram fetch) t2 SYSCLK t4 RA [31:0] t4 FA1 FA5 ALSA ALE* t5 t5 t5 t5 MEMCS* [0] MEMCS* [1] t6 t6 t6 t6 DDIR t7 t7 MEMWR* BUFFEN* t8 t56 t8 t56 t8 OE* t10 t61 t10 t9 D [31:0] t9 t11 t12 FD5 FD1 byte from ram word from ram t10 t9 DPAR word to ram t10 t61 t9 t11 t12 FP1 FP5 parity from ram parity from ram t10 t61 t9 t10 t9 CB [6:0] parity to ram t13 t12 FC1 FC5 checkbyte from ram checkbyte from ram t60 checkbyte to ram t60 INST t16 MHOLD* t16 held to update the full word Rev.D - August 2000 MDS* t46 t46 INULL t4 t4 RLDSTO t4 t4 LOCK RAM atomic-load-store byte sequence- 0 waitstate TSC695E 22 1 (ram fetch) Rev.D - August 2000 1 (ram fetch) 2 (ram double load) 3 (ram fetch) 4 (ram double store) 5 (ram fetch) t2 SYSCLK t4 RA [31:0] t4 FA1 LA1 t4 t4 LA2 t4 FA2 t4 SA1 SA2 FA3 ALE* t5 t5 t5 t5 t5 t5 t5 t5 MEMCS* [0] MEMCS* [1] t6 t6 DDIR t7 t7 t7 t7 MEMWR* BUFFEN* t8 t56 t8 t56 t8 OE* t9 D [31:0] FD1 LD1 t9 DPAR FP1 LP1 t9 CB [6:0] FC1 LC1 t10 LD2 t61 t11 t11 FD2 t10 LP2 t61 t11 t10 t61 SD2 t11 FP2 LC2 t12 SD1 t12 SP1 t13 FC2 FD3 SP2 t13 SC1 FP3 t12 SC2 t60 FC3 t60 INST t16 t16 MDS* t46 t46 INULL t4 t4 LOCK 23 RAM load-double and RAM store-double sequence - 0 waitstate TSC695E MHOLD* 2 (ram load correctable data) load 3 (ram fetch) 4 (ram fetch) internal error correction t2 SYSCLK t14 t14 ALE* t4 RA[31-0] FA1 t4 t4 LA1 FA2 t5 t5 t5 t5 FA3 MEMCS*[0] MEMCS*[1] DDIR MEMWR* IOWR* t8 t56 t56 t8 OE* BUFFEN* D[31-0] t9 t10 FD1 CB[6-0] DPAR t9 t10 LD1 FD2 FD2 FD3 FC1 LC1 FC2 FC2 FC3 FP1 LP1 1-bit error on 40-bit data FP2 FP2 FP3 t16 t16 MHOLD* MEXC* Rev.D - August 2000 t17 t17 MDS* t60 t60 INST INULL RAM load with correctable error - 0 waitstate TSC695E 24 1 (ram fetch) Rev.D - August 2000 1 (ram fetch) 2 (ram load) load 3 (ram fetch) internal error detection 4 (null cycle) 5 (ram fetch) exception 6 (ram fetch) trap t2 SYSCLK t14 t14 ALE* t4 RA[31-0] FA1 t4 t4 LD1 FA2 t5 t5 t5 t5 t4 FA3 TA1 TA2 MEMCS*[0] MEMCS*[1] DDIR MEMWR* IOWR* t8 t56 t8 t56 OE* BUFFEN* t10 D[31-0] FD1 LD1 FD2 FD2 t10 t9 FD2 CB[6-0] FC1 LC1 FC2 FC2 FC2 FC3 TC1 TC2 DPAR FP1 LP1 FP2 2-bit error on 40-bit data FP2 FP2 FP3 TP1 TP2 t9 FD3 TD1 TD2 t16 t16 MHOLD* t20 t20 t17 t17 MDS* t60 t60 t60 t60 t46 t46 INST INULL 25 RAM load with uncorrectable error - 0 waitstate TSC695E MEXC* 2 (ram load) 3 (ram fetch) internal error 4 (null cycle) 5 (ram fetch) fetch 6 (ram fetch) trap t2 SYSCLK ALE* RA[31-0] t4 unimplemented address LA1 FA1 t5 FA2 t4 FA3 TA1 TA2 t5 MEMCS*[0] MEMCS*[1] DDIR MEMWR* IOWR* BUFFEN* t56 t8 t8 t56 OE* t9 D[31-0] t10 FD1 t9 no data t16 t10 FD2 FD3 TD1 t16 MHOLD* t20 t20 MEXC* t17 t17 Rev.D - August 2000 MDS* t60 t60 t60 t60 t46 t46 INST INULL RAM load with unimplemented area access - 0 waitstate TD2 TSC695E 26 1 (ram fetch) Rev.D - August 2000 1 (ram fetch) 2 (i/o store) start of cycle (n-2) ws 3 (ram fetch) rdy waiting end of cycle t2 SYSCLK ALE* t4 RA[31-0] t4 t4 FA1 SA1 FA2 t5 t5 MEMCS*[0] t27 t27 IOSEL*[0] t25 t24 t24 BUSRDY* t6 t6 DDIR MEMWR* t7 t7 IOWR* t15 t57 BUFFEN* t56 t8 OE* t10 t61 t9 t11 FD1 t12 SD1 FD2 previous stored data t60 t60 INST t16 t16 MHOLD* MDS* 27 I/O store sequence with BUSRDY* and n waitstates (timing for 0 or 1 waitstate = timing for 2 waitstates) TSC695E D[31-0] 2 (i/o load) start of cycle (n-2) ws 3 (ram fetch) rdy waiting end of cycle t2 SYSCLK t14 t14 ALE* t4 RA[31-0] t4 FA1 LA1 FA2 t5 t5 MEMCS*[0] t27 t27 IOSEL*[0] t25 t24 t24 BUSRDY* DDIR MEMWR* IOWR* t15 t57 t8 t56 BUFFEN* t56 t8 OE* t10 data driven by external buffers (c.f BUFFEN*) t9 D[31-0] FD1 t9 t10 LD1 t60 FD2 t60 Rev.D - August 2000 INST t16 t16 MHOLD* t17 MDS* I/O load sequence with BUSRDY* and n waitstates (timing for 0 or 1 ws = timing for 2 ws) t17 TSC695E 28 1 (ram fetch) Rev.D - August 2000 1 (ram fetch) 2 (xchgram store) start of cycle rdy waiting 3 (ram fetch) in between n ws end of cycle t2 SYSCLK ALE* t4 RA[31-0] t4 FA1 SA1 FA2 t5 t5 t5 t5 t6 t6 MEMCS*[0] EXMCS* DDIR t7 t7 MEMWR* t7 t7 IOWR* t15 t57 BUFFEN* t56 t8 OE* t25 t24 t24 BUSRDY* t61 FD1 t11 t12 SD1 FD2 previous stored data t60 t60 INST t16 t16 MHOLD* MDS* 29 EXCHANGE RAM store with BUSDRY* and n waitstates TSC695E D[31-0] 2 (xchgram load) start of cycle 3 (ram fetch) rdy waiting n ws end of cycle t2 SYSCLK t14 t14 ALE* t4 RA[31-0] t4 FA1 LA1 FA2 t5 t5 t5 t5 MEMCS*[0] EXMCS* DDIR MEMWR* IOWR* t15 t57 BUFFEN* t56 t8 OE* t24 t24 t25 BUSRDY* t9 D[31-0] t10 LD1 FD1 FD2 data driven by external buffers (c.f BUFFEN*) t60 t60 Rev.D - August 2000 INST t16 t16 MHOLD* t17 MDS* EXCHANGE RAM load with BUSDRY* and n waitstates t17 TSC695E 30 1 (ram fetch) Rev.D - August 2000 1 (rom fetch) 2 (8-bit rom fetch or load word) byte 0 (n-1) ws start of cycle byte 1 (n-1) ws 3 (rom fetch) byte 2 (n-1) ws byte 3 (n-1) ws t2 end of cycle SYSCLK t14 t4 ALE* t4 t4 RSIZE[0,1] 10 t4 RA[31-0] t4 FA1 (address mod. 4) FA2 t23 BA[0,1] 0 t5 t23 1 t23 2 3 FA2 t23 0 t5 t5 ROMCS* MEMCS*[0] DDIR MEMWR* t15 t57 t15 BUFFEN* t8 t56 t8 OE* data driven by external buffers (c.f BUFFEN*) D[31-8] t10 t9 D[7-0] t10 t9 FD2-0 t10 t9 FD2-1 FD2-2 t10 t9 FD2-3 t60 (1 = fetch, t16 0 = load word) t16 t16 MHOLD* t17 t17 MDS* 31 8-bit BOOT PROM fetch (or load word) - n waitstates t17 TSC695E t60 INST 2 (8-bit rom write) start of cycle 3 (ram fetch) (n-1) ws 4 (8-bit rom write) start of cycle t2 5 (ram fetch) (n-1) ws SYSCLK ALE* t4 RA[31-0] t4 FA1 t4 addr.=mod. 4 SA1 t4 FA2 addr.=mod. 4 +1 SA2 t23 BA[0,1] 00 t4 10 t23 00 01 t4 RSIZE[0,1] t4 00 t4 00 10 t5 FA3 t5 10 t5 t5 MEMCS*[0] t5 t5 t5 t5 ROMCS* t6 t6 t6 t6 DDIR t7 t7 t7 t7 MEMWR* IOWR* t15 t57 t15 t57 BUFFEN* t56 t8 t56 OE* t61 D[31-0] t61 t9 FD1 t11 byte D[7:0] SD1 Rev.D - August 2000 t60 t12 t60 t9 FD2 t11 byte D[7:0] SD2 t60 INST t16 t16 t16 MHOLD* MDS* 8-bit BOOT PROM 2x Store byte - n waitstate t16 t12 TSC695E 32 1 (ram fetch) TSC695E 6.3 Package Description 6.3.1 256-pin MQFP-F Package Rev.D - August 2000 33 TSC695E 6.3.2 256-pin MQFP-F Pin Assignments Pin Signal Pin Signal Pin Signal Pin Signal 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 GPIINT GPI[7] VCCO VSSO GPI[6] GPI[5] GPI[4] GPI[3] VCCO VSSO GPI[2] GPI[1] GPI[0] D[31] D[30] VCCO VSSO D[29] D[28] VCCI VSSI D[27] D[26] VCCO VSSO D[25] D[24] D[23] D[22] VCCO VSSO D[21] D[20] D[19] D[18] VCCO VSSO D[17] D[16] VCCI VSSI D[15] D[14] VCCO VSSO D[13] D[12] D[11] D[10] VCCO VSSO D[9] D[8] D[7] D[6] VCCO VSSO D[5] D[4] D[3] D[2] VCCO VSSO D[1] 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 D[0] RSIZE[1] RSIZE[0] RASI[3] VCCO VSSO RASI[2] RASI[1] RASI[0] RA[31] RA[30] VCCO VSSO RA[29] RA[28] RA[27] VCCO VSSO RA[26] RA[25] RA[24] VCCI VSSI VCCO VSSO RA[23] RA[22] RA[21] VCCO VSSO RA[20] RA[19] RA[18] VCCO VSSO RA[17] RA[16] RA[15] VCCO VSSO RA[14] VCCI VSSI RA[13] RA[12] VCCO VSSO RA[11] RA[10] RA[9] VCCO VSSO RA[8] RA[7] RA[6] VCCO VSSO RA[5] RA[4] RA[3] VCCO VSSO RA[2] RA[1] 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 RA[0] VCCO VSSO RAPAR RASPAR DPAR VCCO VSSO SYSCLK TDO TRST TMS TDI TCK CLK2 DRDY DMAAS VCCO VSSO DMAGNT EXMCS VCCI VSSI DMAREQ BUSERR BUSRDY ROMWRT NOPAR SYSHALT CPUHALT VCCO VSSO SYSERR SYSAV EXTINT[4] EXTINT[3] EXTINT[2] EXTINT[1] EXTINT[0] VCCI VSSI EXTINTACK IUERR VCCO VSSO CPAR TXA RXA RXB TXB IOWR IOSEL[3] VCCO VSSO IOSEL[2] IOSEL[1] IOSEL[0] WRT WE VCCO VSSO RD RLDSTO LOCK 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 DXFER MEXC VCCO VSSO RESET SYSRESET BA[1] BA[0] CB[6] CB[5] VCCO VSSO CB[4] CB[3] CB[2] CB[1] VCCO VSSO CB[0] ALE VCCI VSSI PROM8 ROMCS MEMCS[9] VCCO VSSO MEMCS[8] MEMCS[7] MEMCS[6] MEMCS[5] MEMCS[4] MEMCS[3] VCCO VSSO MEMCS[2] MEMCS[1] MEMCS[0] VCCI VSSI OE VCCO VSSO MEMWR BUFFEN DDIR VCCO VSSO DDIR MHOLD MDS WDCLK IWDE EWDINT TMODE[1] TMODE[0] DEBUG INULL DIA VCCO VSSO FLUSH INST RTC Note: XYZ 34 XYZ, signal active low Rev.D - August 2000 TSC695E Rev.D - August 2000 35