MAX6323DUT29-T - Maxim Integrated

General Description

The MAX6323/MAX6324 microprocessor (µP) supervi-

sory circuits monitor power supplies and µP activity in

digital systems. A watchdog timer looks for activity out-

side an expected window of operation. Six laser-trimmed

reset thresholds are available with ±2.5% accuracy from

+2.32V to +4.63V. Valid RESET output is guaranteed

down to VCC = +1.2V.

The RESET output is either push-pull (MAX6323) or

open-drain (MAX6324). RESET is asserted low when

VCC falls below the reset threshold, or when the manual

reset input (MR) is asserted low. RESET remains assert-

ed for at least 100ms after VCC rises above the reset

threshold and MR is deasserted.

The watchdog pulse output (WDPO) utilizes an open-

drain configuration. It can be triggered either by a fast

timeout fault (watchdog input pulses are too close to each

other) or a slow timeout fault (no watchdog input pulse is

observed within the timeout period). The watchdog time-

out is measured from the last falling edge of watchdog

input (WDI) with a minimum pulse width of 300ns. WDPO

is asserted for 1ms when a fault is observed. Eight laser-

trimmed timeout periods are available.

The MAX6323/MAX6324 are offered in a 6-pin SOT23

package and operate over the extended temperature

range (-40°C to +125°C).

Applications

●Automotive

●Industrial

●Medical

●Embedded Control Systems

Features

●Min/Max (Windowed) Watchdog,

8 Factory-Trimmed Timing Options

●Pulsed Open-Drain, Active-Low Watchdog Output

●Power-On Reset

●Precision Monitoring of +2.5V, +3.0V, +3.3V,

and +5.0V Power Supplies

●Open-Drain or Push-Pull RESET Outputs

●Low-Power Operation (23µA typ)

●Debounced Manual Reset Input

●Guaranteed Reset Valid to VCC = +1.2V

●AEC-Q100 Qualified MAX6324HUT44/V+T

Ordering Information continued at end of data sheet.

Typical Operating Circuit appears at end of data sheet.

19-1838; Rev 8; 12/18

*See Figure 1 for operation.

*These devices are factory trimmed to one of eight watchdog-

timeout windows and one of six reset voltage thresholds. Insert

the letter corresponding to the desired watchdog-timeout window

(A, B, C, D, E, F, G, or H) into the blank following the number

6323 or 6324 (see Watchdog Timeout table). Insert the two-

digit code (46, 44, 31, 29, 26, or 23) after the letters UT for the

desired nominal reset threshold (see Reset Threshold Range

table at end of data sheet).

/V denotes an automotive qualified part.

Devices are available in both leaded and lead-free packaging.

Specify lead-free by replacing “-T” with “+T” when ordering.

Note: There are eight standard versions of each device available

(see Standard Versions table). Sample stock is generally held on

standard versions only. Standard versions have an order

increment requirement of 2500 pieces. Nonstandard versions

have an order increment requirement of 10,000 pieces. Contact

factory for availability of nonstandard versions.

PART TEMP

RANGE

PIN-

PACKAGE

RESET

OUTPUT

MAX6323_UT_ _-T -40°C to +125°C 6 SOT23 Push-Pull

WATCHDOG TIMEOUT*

SUFFIX FAST SLOW

MAX UNITS MIN UNITS

A 1.5 ms 10

B 15 ms 100

C 15 ms 300

D 15 ms 10 s

E 15 ms 60

F 23 ms 47 ms

G 39 ms 82

H 719 ms 1.3 s

Watchdog Timeout

Pin Conguration

Ordering Information

GND

VCC

WDI

1 6

MAX6323

MAX6324

SOT23

TOP VIEW

3 4

RESET

WDPO

Click here for production status of specic part numbers.

MAX6323/MAX6324 μP Supervisory Circuits with Windowed

(Min/Max) Watchdog and Manual Reset

Terminal Voltage (with respect to GND)

VCC ................................................................... -0.3V to +6.0V

MR, RESET (MAX6323), WDI .............. -0.3V to (VCC + 0.3V)

WDPO, RESET (MAX6324) .............................-0.3V to +6.0V

Input Current, VCC, WDI, MR .............................................20mA

Output Current, RESET, WDPO ........................................20mA

Rate of Rise, VCC ..........................................................100V/µs

Continuous Power Dissipation (TA = +70°C)

6-Pin SOT23 (derate 8.7mW/°C above +70°C) ..........696mW

Operating Temperature Range ......................... -40°C to +125°C

Junction Temperature ...................................................... +150°C

Storage Temperature Range ............................ -65°C to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

Soldering Temperature (reflow)

Lead(Pb)-Free .............................................................+260°C

Containing Lead ..........................................................+240°C

6 SOT23

PACKAGE CODE U6+1/U6+1A

Outline Number 21-0058

Land Pattern Number 90-0175

Thermal Resistance, Single-Layer Board:

Junction to Case (θJC) 80°C/W

Thermal Resistance, Multi-Layer Board:

Junction to Ambient (θJA) 115°C/W

Junction to Case (θJC) 80°C/W

Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board.

For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.

For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,

“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing

pertains to the package regardless of RoHS status.

Package Information

Absolute Maximum Ratings

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these

or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect

device reliability.

MAX6323/MAX6324 μP Supervisory Circuits with Windowed

(Min/Max) Watchdog and Manual Reset

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(VCC = full range, TA = -40°C to +125°C, unless otherwise noted. Typical values are at VCC = 3V, TA = +25°C.) (Note 1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Operating Voltage Range VCC 1.2 5.5 V

Supply Current ICC

No load, RESET

deasserted

VCC = 2.5V or 3.3V 23 45 µA

VCC = 5.5 27 57

Reset Threshold Voltage VTH

MAX632_ _UT46 4.50 4.63 4.75

MAX632_ _UT44 4.25 4.38 4.50

MAX632_ _UT31 3.00 3.08 3.15

MAX632_ _UT29 2.85 2.93 3.00

MAX632_ _UT26 2.55 2.63 2.70

MAX632_ _UT23 2.25 2.32 2.38

Reset Timeout Delay tRP RESET deasserted 100 180 280 ms

VCC to RESET Delay 10mV/ms, VTH +100mV to VTH - 100mV 20 µs

WDPO, RESET Output Voltage VOL

ISINK = 1.2mA, VCC = 2.25V

(MAX632_ _UT23, MAX632_ _UT26,

MAX632_ _UT29, MAX632_ _UT31)

0.4

ISINK = 3.2mA, VCC = 4.25V

(MAX632_ _UT44, MAX632_ _UT46) 0.4

ISINK = 100μA, VCC > 1.2V,

RESET asserted 0.4

RESET Output Voltage

(MAX6323) VOH

ISOURCE = 500μA, VCC = 3.15V,

RESET deasserted (MAX632_ _UT23,

MAX632_ _UT26, MAX632_ _UT29,

MAX632_ _UT31)

0.8 x VCC

ISOURCE = 800μA, VCC = 4.75V, RESET

deasserted, (MAX632_ _UT44,

MAX632_ _UT46)

VCC - 1.5

WDPO, RESET Output Leakage ILKG

VRESET = VWDPO = +5.5V, RESET,

WDPO deasserted 1 µA

Electrical Characteristics

MAX6323/MAX6324 μP Supervisory Circuits with Windowed

(Min/Max) Watchdog and Manual Reset

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(VCC = full range, TA = -40°C to +125°C, unless otherwise noted. Typical values are at VCC = 3V, TA = +25°C.) (Note 1)

Note 1: Devices are tested at TA = +25°C and guaranteed by design for TA = TMIN to TMAX, as specified.

Note 2: WDPO will pulse low if a falling edge is detected on WDI before this timeout period expires.

Note 3: To avoid a potential fake fault, the first WDI pulse after the rising edge of RESET or WDPO will not create a fast watchdog

timeout fault.

Note 4: WDPO will pulse low if no falling edge is detected on WDI after this timeout period expires.

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

WATCHDOG INPUT AND OUTPUT

Watchdog Timeout (Fast)

(Notes 2, 3) tWD1

MAX632_AUT_ _ 1 1.5

MAX632_BUT_ _ 10 15

MAX632_CUT_ _ 10 15

MAX632_DUT_ _ 10 15

MAX632_EUT_ _ 10 15

MAX632_FUT_ _ 17 23

MAX632_GUT_ _ 29 39

MAX632_HUT_ _ 543 719

Watchdog Timeout (Slow)

(Note 4) tWD2

MAX632_AUT_ _ 10 15

msMAX632_BUT_ _ 100 150

MAX632_CUT_ _ 300 450

MAX632_DUT_ _ 10 15 s

MAX632_EUT_ _ 60 90

MAX632_FUT_ _ 47 63 ms

MAX632_GUT_ _ 82 108

MAX632_HUT_ _ 1.3 1.8 s

Minimum Watchdog Input

Pulse Width 300 ns

WDI Glitch Immunity VCC = 5.5V 100 ns

WDI Input Voltage VIH 0.75 x VCC V

VIL 0.8

WDI Input Current VWDI = 0V -1.5 -1 µA

VWDI = VCC 1 1.5

WDPO Pulse Width VIL = 0.8V, VIH = 0.75V x VCC 0.5 1 3 ms

MANUAL RESET INPUT

MR Input Voltage VIH 0.7 x VCC V

VIL 0.3 x VCC

MR Minimum Pulse Width 1 µs

MR Glitch Immunity VCC = 2.5V 100 ns

MR to Reset Delay VCC = 2.5V 120 ns

MR Pullup Resistance 50 85 kΩ

Electrical Characteristics (continued)

MAX6323/MAX6324 μP Supervisory Circuits with Windowed

(Min/Max) Watchdog and Manual Reset

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(VCC = full range, TA = +25°C, unless otherwise noted.)

Typical Operating Characteristics

-40 200-20 40 60 80

MAX6323/24-01

TEMPERATURE (°C)

SUPPLY CURRENT vs. TEMPERATURE

SUPPLY CURRENT (µA)

VCC = 5.5V

VCC = 3.3V

VCC = 1.0V

0.9985

0.9990

0.9995

1.0000

1.0005

-40 200-20 40 60 80

MAX6323/24-04

TEMPERATURE (°C)

RESET THRESHOLD

NORMALIZED RESET THRESHOLD

vs. TEMPERATURE

0.9980

0.995

1.000

1.001

0.999

0.997

0.998

0.996

1.002

1.003

-40 200-20 40 60 80

MAX6323/24-07

TEMPERATURE (°C)

NORMALIZED WATCHDOG TIMEOUT

PERIOD (SLOW) vs. TEMPERATURE

NORMALIZED WATCHDOG TIMEOUT PERIOD (SLOW)

-40 200-20 40 60 80

MAX6323/24-02

TEMPERATURE (°C)

POWER-DOWN RESET DELAY (µs)

POWER-DOWN RESET DELAY

vs. TEMPERATURE

VOD = 20mV

VOD = 100mV

0.994

1.004

1.006

1.008

-40 200-20 40 60 80

MAX6323/24-05

TEMPERATURE (°C)

POWER-UP RESET TIMEOUT

NORMALIZED POWER-UP RESET TIMEOUT

vs. TEMPERATURE

1.002

1.000

0.998

0.996

0.992

1.004

1.002

1.000

1.006

1.008

-40 200-20 40 60 80

MAX6323/24-08

TEMPERATURE (°C)

NORMALIZED WATCHDOG OUTPUT PULSE WIDTH (µs)

NORMALIZED WATCHDOG OUTPUT

PULSE WIDTH vs. TEMPERATURE

0.998

0.996

0.994

120

100

140

160

-40 200-20 40 60 80

MAX6323/24-03

TEMPERATURE (°C)

MR TO RESET DELAY (ns)

MR TO RESET DELAY

vs. TEMPERATURE

0.992

1.004

1.002

1.000

0.998

1.006

1.008

-40 200-20 40 60 80

MAX6323/24-06

TEMPERATURE (°C)

NORMALIZED WATCHDOG TIMEOUT

PERIOD (FAST) vs. TEMPERATURE

NORMALIZED WATCHDOG TIMEOUT PERIOD (FAST)

0.996

0.994

VOD = VTH - VCC

400

1 100 1000

MAXIMUM TRANSIENT DURATION

vs. RESET THRESHOLD OVERDRIVE

100

150

200

250

300

350

MAX6323/24-09

RESET COMPARATOR OVERDRIVE (mV)

MAXIMUM TRANSIENT DURATION (µs)

MAX632_AUT23

RESET ASSERTED

ABOVE THIS LINE

MAX6323/MAX6324 μP Supervisory Circuits with Windowed

(Min/Max) Watchdog and Manual Reset

Maxim Integrated

│

www.maximintegrated.com

(VCC = full range, TA = +25°C, unless otherwise noted.)

PIN NAME FUNCTION

1MR

Active-Low, Manual Reset Input. When MR is asserted low, RESET is asserted low, the internal watchdog

timer is reset to zero, and WDPO is reset to high impedance (open drain). After the rising edge of MR,

RESET is asserted for at least 100ms. Leave MR unconnected or connect to VCC if unused.

2 GND Ground

3 WDI

Watchdog Input. The internal watchdog timer clears to zero on the falling edge of WDI or when RESET goes

high. If WDI sees another falling edge within the factory-trimmed watchdog window, WDPO will

remain unasserted. Transitions outside this window, either faster or slower, will cause WDPO to pulse

low for 1ms (typ).

4 VCC

Supply Voltage for the Device. Input for VCC reset monitor. For noisy systems, bypass VCC with a 500pF

(min) capacitor.

5WDPO Watchdog Pulse Output. The open-drain WDPO output is pulsed low for 1ms (typ) upon detection of a fast

or slow watchdog fault. WDPO is only active when RESET is high.

6RESET

Active-Low. Reset is asserted when VCC drops below VTH and remains asserted until VCC rises above

VTH for the duration of the reset timeout period. The MAX6323 has a push-pull output and the MAX6324

has an open-drain output. Connect a pullup resistor from RESET to any supply voltage up to +6V.

Typical Operating Characteristics (continued)

500µs/div

MAX6323/24-10

WDI 2V/div

2V/div

WDPO

FAST WATCHDOG TIMEOUT PERIOD

MAX6323AUT23

5ms/div

MAX6323/24-11

WDI 2V/div

2V/div

WDPO

SLOW WATCHDOG TIMEOUT PERIOD

MAX6323AUT23

Pin Description

MAX6323/MAX6324 μP Supervisory Circuits with Windowed

(Min/Max) Watchdog and Manual Reset

Maxim Integrated

│

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Detailed Description

The MAX6323/MAX6324 μP supervisory circuits maintain

system integrity by alerting the μP to fault conditions. In

addition to a standard VCC monitor (for power-on reset,

brownout detect, and power-down reset), the devices

include a sophisticated watchdog timer that detects when

the processor is running outside an expected window of

operation for a specific application. The watchdog signals

a fault when the input pulses arrive too early (faster than

the selected tWD1 timeout period) or too late (slower than

the selected tWD2 timeout period) (Figure 1). Incorrect

timing can lead to poor or dangerous system performance

in tightly controlled operating environments. Incorrect

timing could be the result of improper μP clocking or code

execution errors. If a timing error occurs, the MAX6323/

MAX6324 issue a watchdog pulse output, independent

from the reset output, indicating that system maintenance

may be required.

Watchdog Function

A pulse on the watchdog output WDPO can be triggered

by a fast fault or a slow fault. If the watchdog input (WDI)

has two falling edges too close to each other (faster

than tWD1) (Figure 2) or falling edges that are too far

apart (slower than tWD2) (Figure 3), WDPO is pulsed

low. Normal watchdog operation is displayed in Figure 4

(WDPO is not asserted). The internal watchdog timer is

cleared when a WDI falling edge is detected within the

valid watchdog window or when the device’s RESET or

WDPO outputs are deasserted. All WDI input pulses are

ignored while either RESET or WDPO is asserted. Figure

1 identifies the input timing regions where WDPO fault

outputs will be observed with respect to tWD1 and tWD2.

After RESET or WDPO deasserts, the first WDI falling

edge is ignored for the fast fault condition (Figure 2).

Upon detecting a watchdog fault, the WDPO output

will pulse low for 1ms. WDPO is an open-drain output.

Connect a pullup resistor on WDPO to any supply up to

+6V.

VCC Reset

The MAX6323/MAX6324 also include a standard VCC

reset monitor to ensure that the μP is started in a

known state and to prevent code execution errors

during power-up, power-down, or brownout conditions.

RESET is asserted whenever the VCC supply voltage

Figure 1. Detailed Watchdog Input Timing Relationship

*UNDETERMINED STATES MAY OR MAY NOT GENERATE A FAULT CONDITION.

POSSIBLE STATES

GUARANTEED TO

ASSERT WDPO

GUARANTEED TO

ASSERT WDPO

GUARANTEED NOT TO

ASSERT WDPO

FAST FAULTCONDITION 1

SLOW FAULTCONDITION 3

NORMAL OPERATIONCONDITION 2

tWD1 (min)

)

tWD1 (max) tWD2 (min) tWD2 (max)

*UNDETERMINED *UNDETERMINED

MAX6323/MAX6324 μP Supervisory Circuits with Windowed

(Min/Max) Watchdog and Manual Reset

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Figure 2. Fast Fault Timing

Figure 3. Slow Fault Timing

Figure 4. Normal Operation, WDPO Not Asserted

RESET

WDPO

WDI

FAST FAULT

tWDI < tWD1 (min)

RESET

WDPO

WDI

SLOW FAULT

tWDI < tWD2 (max)

RESET

WDPO

WDI

NORMAL OPERATION (NO PULSING, OUTPUT STAYS HIGH)

tWD1 (max) < tWDI < tWD2 (min)

MAX6323/MAX6324 μP Supervisory Circuits with Windowed

(Min/Max) Watchdog and Manual Reset

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falls below the preset threshold or when the manual

reset input (MR) is asserted. The RESET output remains

asserted for at least 100ms after VCC has risen above

the reset threshold and MR is deasserted (Figure 5).

For noisy environments, bybass VCC with a 500pF (min)

capacitor to ensure correct operation.

The MAX6323 has a push-pull output stage, and the

MAX6324 utilizes an open-drain output. Connect a

pullup resistor on the RESET output of the MAX6324 to

any supply up to +6V. Select a resistor value large enough

to register a logic low (see Electrical Characteristics) and

small enough to register a logic high while supplying all

input leakage currents and leakage paths connected

to the RESET line. A 10kΩ pullup is sufficient in most

applications.

Manual Reset Input

Many μP-based products require manual reset capability

to allow an operator or external logic circuitry to initiate a

reset. The manual reset input (MR) can connect directly to

a switch without an external pullup resistor or debouncing

network. MR is internally pulled up to VCC and, there-

fore, can be left unconnected if unused. MR is designed

to reject fast, negative-going transients (typically 100ns

pulses), and it must be held low for a minimum of 1μs

to assert the reset output (Figure 5). A 0.1μF capacitor

from MR to ground provides additional noise immunity.

After MR transitions from low to high, reset will remain

asserted for the duration of the reset timeout period, at

least 100ms.

Applications Information

Negative-Going VCC Transients

The MAX6323/MAX6324 are relatively immune to short-

duration negative-going VCC transients (glitches), which

usually do not require the entire system to shut down.

Typically, 200ns large-amplitude pulses (from ground

to VCC) on the supply will not cause a reset. Lower

amplitude pulses result in greater immunity. Typically,

a VCC transient that falls 100mV below the reset

threshold and lasts less than 20μs will not trigger a

reset (see Typical Operating Characteristics). An optional

0.1μF bypass capacitor mounted close to VCC provides

additional transient immunity.

Ensuring a Valid Reset Output

Down to VCC = 0V

When VCC falls below +1.2V, the MAX6323 RESET out-

put no longer sinks current; it becomes an open circuit.

Therefore, high-impedance CMOS logic inputs connected

to RESET can drift to undetermined voltages. This does

not present a problem in most applications, since most

μPs and other circuitry are inoperative with VCC below

+1.2V. However, in applications where RESET must be

valid down to 0, adding a pulldown resistor to RESET

causes any stray leakage currents to flow to ground, hold-

ing RESET low (Figure 6). R1’s value is not critical; 100kΩ

is large enough not to load RESET and small enough to

pull RESET to ground. This scheme does not work with

the open-drain output of the MAX6324.

Figure 5. RESET Timing Relationship

RESET

VCC

VTH

100ms (min)

120ns (typ) 20µs (typ)

1µs (min)

100ms (min)

MAX6323/MAX6324 μP Supervisory Circuits with Windowed

(Min/Max) Watchdog and Manual Reset

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Interfacing to μPs with

Bidirectional Reset Pins

Since the RESET output on the MAX6324 is open-

drain, this device easily interfaces with μPs that have

bidirectional reset pins, such as the Motorola 68HC11.

Connecting the μP supervisor’s RESET output directly

to the microcontroller’s (μC’s) RESET pin with a single

pullup resistor allows either device to assert reset

(Figure 7).

MAX6324 Open-Drain RESET Output

Allows Use with Multiple Supplies

Generally, the pullup resistor connected to the MAX6324

will connect to the supply voltage that is being monitored

at the IC’s VCC pin. However, some systems may use

the open-drain output to level-shift from the monitored

supply to reset circuitry powered by some other supply

(Figure 8). Keep in mind that as the MAX6324’s VCC

decreases below +1.2V, so does the IC’s ability to sink

current at RESET. Also, with any pullup resistor, RESET

will be pulled high as VCC decays toward 0. The voltage

where this occurs depends on the pullup resistor value

and the voltage to which it is connected.

Watchdog Software Considerations

To help the watchdog timer monitor software execution

more closely, set and reset the watchdog input at different

points in the program, rather than “pulsing” the watchdog

input high-low-high or low-high-low. This technique avoids

a “stuck” loop in which the watchdog time would continue

to be reset within the loop, keeping the watchdog from

timing out.

Figure 9 shows an example of a flow diagram where the

I/O driving the watchdog input is set high at the beginning

of the program, set low at the beginning of every subrou-

tine or loop, then set high again when the program returns

to the beginning. If the program should “hang” in any sub-

routine, the problem would be quickly corrected, since the

I/O is continually set low and the watchdog time is allowed

to time out, causing a reset or interrupt to be issued.

Figure 6. RESET Valid to VCC = Ground Circuit Figure 7. Interfacing to μPs with Bidirectional Reset Pins

Figure 8. MAX6324 Open-Drain RESET Output Allows Use

with Multiple Supplies

MAX6323

GND

VCC

RESET

100k

MAX6324

GND GND

VCC

VCC VCC

µP

RESET RESET

INPUT

MAX6324

GND GND

VCC

+3.3V +5.0V

VCC

5V SYSTEM

RESET RESET

INPUT

RPULLUP

MAX6323/MAX6324 μP Supervisory Circuits with Windowed

(Min/Max) Watchdog and Manual Reset

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WDPO to MR Loopback

An error detected by the watchdog often indicates that

a problem has occurred in the μP code execution.

This could be a stalled instruction or a loop from which

the processor cannot free itself. If the μP will still respond

to a nonmaskable input (NMI), the processor can be

redirected to the proper code sequence by connecting the

WDPO output to an NMI input. Internal RAM data should

not be lost, but it may have been contaminated by the

same error that caused the watchdog to time out.

If the processor will not recognize NMI inputs, or if the

internal data is considered potentially corrupted when a

watchdog error occurs, the processor should be restarted

with a reset function. To obtain proper reset timing

characteristics, the WDPO output should be connected

to the MR input, and the RESET output should drive the

μP RESET input (Figure 10). The short 1ms WDPO pulse

output will assert the manual reset input and force the

RESET output to assert for the full reset timeout period

(100ms min). All internal RAM data is lost during the reset

period, but the processor is guaranteed to begin in the

proper operating state.

Figure 9. Watchdog Flow Diagram

Figure 10. WDPO to MR Loopback Circuit

START

SET WDI

LOW

SUBROUTINE OR

PROGRAM LOOP

SET WDI HIGH

RETURN

END

MAX6323

MAX6324

RESET

WDPO

µP

RESET

*MAX6324 ONLY

MR WDI I/O

GND

VCC VCC

VCC

*RPULLUP

500pF

MAX6323/MAX6324 μP Supervisory Circuits with Windowed

(Min/Max) Watchdog and Manual Reset

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*These devices are factory trimmed to one of eight watchdog-

timeout windows and one of six reset voltage thresholds. Insert

the letter corresponding to the desired watchdog-timeout window

(A, B, C, D, E, F, G, or H) into the blank following the number

6323 or 6324 (see Watchdog Timeout table). Insert the two-

digit code (46, 44, 31, 29, 26, or 23) after the letters UT for the

desired nominal reset threshold (see Reset Threshold Range

table at end of data sheet).

/V denotes an automotive qualified part.

Devices are available in both leaded and lead-free packaging.

Specify lead-free by replacing “-T” with “+T” when ordering.

Note: There are eight standard versions of each device available

(see Standard Versions table). Sample stock is generally held on

standard versions only. Standard versions have an order

increment requirement of 2500 pieces. Nonstandard versions

have an order increment requirement of 10,000 pieces. Contact

factory for availability of nonstandard versions.

PART TEMP

RANGE

PIN-

PACKAGE

RESET

OUTPUT

MAX6324_UT_ _-T -40°C to +125°C 6 SOT23 Open

Drain

MAX6324_UT_ _/V+T -40°C to +125°C 6 SOT23 Open

Drain

MAX6324HUT44/V+T -40°C to +125°C 6 SOT23 Open

Drain

MAX6323AUT29 MAX6324AUT29

MAX6323AUT46 MAX6324AUT46

MAX6323CUT29 MAX6324BUT29

MAX6323CUT46 MAX6324BUT46

MAX6323DUT29 MAX6324EUT29

MAX6323DUT46 MAX6324EUT46

MAX6323HUT29 MAX6324HUT29

MAX6323HUT46 MAX6324HUT46

SUFFIX MIN TYP MAX UNITS

46 4.50 4.63 4.75

44 4.25 4.38 4.50

31 3.00 3.08 3.15

29 2.85 2.93 3.00

26 2.55 2.63 2.70

23 2.25 2.32 2.38

Standard Versions Reset Threshold Range

(-40°C to +125°C)

Ordering Information (continued) Chip Information

TRANSISTOR COUNT: 1371

PROCESS: BiCMOS

MAX6323/MAX6324 μP Supervisory Circuits with Windowed

(Min/Max) Watchdog and Manual Reset

www.maximintegrated.com Maxim Integrated

│

Typical Operating Circuit

MAX6323

MAX6324

RESET

WDPO NMI

µP

RESET

*MAX6324 ONLY

MR WDI I/O

GND

VCC VCC

VCC

*RPULLUP

500pF

MAX6323/MAX6324 μP Supervisory Circuits with Windowed

(Min/Max) Watchdog and Manual Reset

www.maximintegrated.com Maxim Integrated

│

REVISION

NUMBER

REVISION

DATE DESCRIPTION PAGES

CHANGED

0 10/00 Initial release —

5 5/10 Updated the Ordering Information and Absolute Maximum Ratings. 1, 2, 10

6 1/11 Corrected placement of /V in the Ordering Information section 11

7 3/18 Updated Features section and Ordering Information table 1, 12

8 12/18 Updated Package Information 2, 12

Revision History

Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses

are implied. Maxim Integrated reserves the right to change the circuitry and specications without notice at any time. The parametric values (min and max limits)

shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.

Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.

MAX6323/MAX6324 μP Supervisory Circuits with Windowed

(Min/Max) Watchdog and Manual Reset

│

For pricing, delivery, and ordering information, please visit Maxim Integrated’s online storefront at https://www.maximintegrated.com/en/storefront/storefront.html.