S1R72801F00A MF1385-04 Technical Manual IEEE1394 Controller S1R72801F00A Technical Manual S1R72801F00A Technical Manual ELECTRONIC DEVICES MARKETING DIVISION EPSON Electronic Devices Website http://www.epson.co.jp/device/ This manual was made with recycle paper, and printed using soy-based inks. First issue December,2000 Printed March,2001 in Japan H A 4.5mm In pursuit of "Saving" Technology, Epson electronic devices. Our lineup of semiconductors, liquid crystal displays and quartz devices assists in creating the products of our customers' dreams. Epson IS energy savings. NOTICE No parts of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind aristing out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export licence from teh Ministry of International Trade and Industry or other approval from another government agency. (c) SEIKO EPSON CORPORATION 2001, All rights reserved. All other product names mentioned herein are trademarks and/or registered trademarkes of their respective companies. 4.5mm The information of the product number change Starting April 1, 2001 the product number will be changed as listed below. To order from April 1, 2001 please use the new product number. For further information, please contact Epson sales representative. Configuration of product number DEVICES S1 R 72801 F 00A1 00 Packing specification Specifications Shape (F:QFP) Model number Model name (R:Exclusive use controller, Peripheral) Product classification (S1:Semiconductors) Comparison table between new and previous number Previous number SPC7281F0A E0C33000 New number S1R72801F00A S1C33000 SPC7281F0A Contents 1. DESCRIPTION .................................................................................................................................................. 1 2. FEATURES ........................................................................................................................................................ 1 3. INTERNAL BLOCK DESCRIPTION .................................................................................................................. 3 3.1 BLOCK DIAGRAM ..................................................................................................................................... 3 3.2 BLOCK DIAGRAM DESCRIPTION ............................................................................................................ 3 4. INTERNAL CONNECTION DIAGRAM .............................................................................................................. 4 5. PIN ASSIGNMENT DIAGRAM .......................................................................................................................... 5 6. PIN DESCRIPTION ........................................................................................................................................... 6 7. FUNCTIONAL DESCRIPTION ........................................................................................................................ 10 7.1 MEMORY MAP ........................................................................................................................................ 10 7.1.1 All Memory Space .......................................................................................................................... 10 7.1.2 IEEE1394LINK/Transaction Controller xCSBUF Area (SRAM) ..................................................... 11 7.2 IEEE1394 PACKET FORMAT ................................................................................................................. 12 7.2.1 Transmit Packet Format ................................................................................................................ 12 7.2.2 Receive Packet Format.................................................................................................................. 14 7.3 IEEE1394 HARDWARE SBP-2 CONTROL ............................................................................................. 17 7.4 IDE INTERFACE CONTROL ................................................................................................................... 17 7.5 BUILT-IN CPU .......................................................................................................................................... 17 7.6 FLASH CONTROLLER ............................................................................................................................ 18 8. INTERNAL REGISTER .................................................................................................................................... 19 8.1 IEEE1394 LINK CONTROLLER REGISTER MAPPING ......................................................................... 19 8.1.1 Register Table ............................................................................................................................... 19 8.1.2 Register/Bit Table .......................................................................................................................... 22 8.1.3 Register Map ................................................................................................................................. 26 8.1.4 Detail Description of Register ........................................................................................................ 42 8.2 FLASH ROM CONTROL REGISTER ...................................................................................................... 88 9. ELECTRICAL CHARACTERISTICS ................................................................................................................ 91 9.1 ABSOLUTE MAXIMUM RATINGS ........................................................................................................... 91 9.2 RECOMMENDED OPERATING CONDITION ......................................................................................... 91 9.3 DC CHARACTERISTICS (ACCORDING TO RECOMMENDED OPERATING CONDITION) ................ 92 9.4 AC CHARACTERISTICS ......................................................................................................................... 94 9.4.1 Clock Timing .................................................................................................................................. 94 9.4.2 PHY-LINK Interface Timing ........................................................................................................... 95 9.4.3 IDE Interface Timing ...................................................................................................................... 96 9.4.4 CPU Interface Timing .................................................................................................................. 102 10. EXAMPLES OF EXTERNAL CONNECTION FOR REFERENCE PURPOSES ........................................... 103 11. SHAPE OF PACKAGE .................................................................................................................................. 106 EPSON i S1R72801F00A 1. DESCRIPTION 2. FEATURES The S1R72801F00A is a LINK/Transaction controller based on the IEEE Std. 1394-1955, P1394a Draft 2.0. It integrates a built-in CPU and Flash ROM, and also integrates a part of transaction functions into hardware. If you set a PageTable address and its size, it can automatically fetch subsequent PageTables and transmit data. It can offer a 1394 interface optimum to computer peripherals in combination with the Cable PHY Transceiver Arbiter based on the above standard. LINK/Transaction Controller LINK Layer Ready for all two-way data transfer in Asynchronous and Isochronous modes. The built-in SRAM realized stable two-way data transfer up to max. payload of 100Mbps, 200Mbps, and 400Mbps. Can automatically detect the Isochronous Resource Manager by hardware. Transaction Layer Integrates a part of transaction functions into hardware to prevent deterioration of actual data transmission rate due to the overhead of firmware (assure a special area). A header area is distinguished from a data area to simplify communications with a higher rank layer. Furthermore, it segments a data area to a stream area and ORB area. Adopts a ring buffer to the receive header area, receive data area (receive stream area, receive ORB area) and transmit data area (transmit stream area). Can arbitrarily set the size of each area. Automatically controls the Busy when hardware receives data. SBP-2 Support Can set an PageTable address and its size for the SBP-2 to automatically perform subsequent Page Table fetches and data transfers. PHY/LINK Interface Ready for the P1394a. Ready for the data transfer rate of 100/200/400Mbps. Ready for isolation (bus holder integrated) IDE Interface Ready for the PIO mode 0/1/2/3/4, multi-word DMA mode 0/1/2, Ultra-DMA mode 0/1/2. Usable as a general port interface as well. EPSON 1 S1R72801F00A Built-in CPU Integration of a CPU eliminated the necessity of an external CPU to control this IC. CPU core: 32-bit RISC CPU S1C33000 Harvard architecture (Concurrency of a fetch and load/store) High speed/high performance: Ready for operation with 50MHz Command set: 16-bit fixed length, 105 types of basic commands Execution cycle: Execution at one cycle/command regarding a main command AND/OR (MAC) operation: 16 bits x 16 bits + 64 bits, 2 clocks/ MAC (25 MOPS at 50MHz) CPU Register: 16 32-bit general registers and 5 32bit special registers Memory space:Linear space where 256-Mbyte (28bit) code, data, and I/O can be mapped. External bus interface: Directly connects the external memory of the memory area. Programmable wait cycle (7 cycles, Max.) Enables handshake through the XWAIT terminal. Interrupt: Ready for reset, NMI, max. 128 external interrupts, 4 software interrupts, and 2 exceptions Reset, boot: Cold reset, hot reset Built-in RAM: 8Kbytes 2 Flash ROM Integration of a Flash ROM eliminated the necessity of a ROM to externally store programs. * Memory structure: Memory size 512K (32K x 16) bits * Sector size: 512 words/sector * Unit of erase: Per chip or sector * Unit of write: Writing with words * Erase/write time: Chip erase time 100ms (Standard) Sector erase time 20ms (Standard) Write time: 15s (Standard) * Access time: 90nsec. (Max.) * Reliability: No. of erase/write 1,000 times Data retention: 10 years Others A Boot ROM (4MBbytes, Max.) is connectable to outside of this IC. Supply voltage, 5.0V 10% and 3.3V 0.3V 184PinQFP (0.4mm pitch) Not radiation resistant. The CPU core built into this IC is an original 32-bit RISC CPU from SEIKO EPSON. Regarding the CPU core, refer to the E0C33208/204/202 TECHNICAL MANUAL. The built-in RAM is 8Kbytes. Note: In the built-in CPU core, a DMA controller and A/D converter are not integrated; this part is different from the description on the DMA controller and A/D converter given in TECHNICAL MANUAL (and Macro Manual). A low speed oscillation circuit (OSC1) is not available. EPSON S1R72801F00A 3. INTERNAL BLOCK DESCRIPTION 3.1 BLOCK DIAGRAM Intenal Packet Memory (8KByte) D [7:0] CTL [1:0] LREQ Buffer I/F Maneger LPS HDD [15:0] HDMARQ XHIOR XHIOW XHDMACK HIORDY HINTRQ IDE I/F TRAN & SBP2 Control XHPDIAG HDA [2:0] XCS [1:0] DMA for ATF IDE FIFO IsoTx FIFO SCLK 1394 LINK & TRAN Core 1394 PHY/LINK I/F Rx FIFO DMA for RF XHDASP BHEN XISO DMA for ITF IDE DMA LINKON AsyncTx FIFO XHRST ICEMD DSIO X2SPD XNMI XREST TVEP FLASH ROM 64KByte (32KWord X 16bit) CORE PAD Register for LINK&TRAN Register for 1394Tx/Rx C33_CORE (CPU, BCU, ITC, CLG, DBG) C33_SBUS Internal RAM (8KByte) C33 Core Block C33_PERI (Prescaaler, 8-bit timer, 16bit timer, Clock timer, Serial interface, Ports) PERI PAD OSC4 OSC3 PLLS1 PLLS0 Register for TRAN&SBP2 C33 Internal Memory Block Register for IDE C33 peripheral Block C33 Macro Block AD [23:0] DT [15:0] XCE10_EX XCE [9:4] EA10MD [1:0] XWAIT EXT_MD XRD XWR XWRH BCLK P[14:04] SRDY SCLK SOUT SIN Fig. 3.1 Block diagram 3.2 BLOCK DIAGRAM DESCRIPTION C33 CORE Block The C33 CORE Block consists of the function blockC33_CORE- that includes the CPU, BCU (bus control unit), ITC (interrupt controller), CLG (clock generator), and DBG (debug unit), the external interface I/O pad block-PAD_CORE, PAD_CORE_OPTION-, and the block to interface with the peripheral circuits on the chip -SBUS-. Internal RAM Block SRAM for the built-in memory area (Area 0). C33_PERI Block (C33 peripheral circuit block) The C33_PERI Block consists of the PSC (prescaler), Internal Flash Block Flash for the built-in memory area (Area 10). 6-channel T8 (8-bit programmable timer), WDT (watch dog timer), 6-channel T16 with an event counter (16-bit programmable timer), 4-channel SIO (serial interface), input and I/O ports, and CTM (clock timer). EPSON 3 S1R72801F00A BHEN XISO LINKON LPS LREQ CTL<1:0> D<7:0> SCLK MonxInt MonxWait P20 P21 P22 P23 LPS(P35) PD(P34) CNA(K64) K66 K67 4. INTERNAL CONNECTION DIAGRAM XRESET U_AD<23:0> U_DT<15:0> xCSREG<XCE4> xCSBUF<XCE7> xCSFREG<XCE5> xCSFLS<XCE10> xWRL xRD xWait xRST xINT(K65) SLEEP(P33) AD<23:00> DT<15:00> XCE10EX XCE9 XCE8 XCE6 U_AD<12:0> U_DT<7:0> xCSREG xCSBUF xWRL xRD xWait xRST xINT SLEEP 1394LINK Core XRD XWRL XWRH C33 Core BCLK XNMI X2SPDX ICEMD U_AD<14:0> U_DT<15:0> xCSFREG xWRL xRD DSIO OSC3 OSC4 PLLC PLLS1 PLLS0 U_AD<14:0> U_DT<15:0> xCS xRD EA10MD2 EA10MD1 FLASH Controller Flash ROM (64KB) P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 EA10MD0 Fig. 4.1 Internal connection diagram 4 EPSON HDD<15:0> HDA<2:0> XHCS<1:0> XHRST XHIOW XHIOR HDMARQ XHDMACK HIORDY XHPDIAG XHDASP HINTRQ S1R72801F00A 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 VSS N.C. P21 P20 XCE10EX XCE9 MonxWait XCE6 HVDD TO0 TO1 TO2 TO3 TO4 TO5 TO6 TO7 TI8 MonxInt VSS VSS VSS VSS LREQ LVDD SCLK VSS CNA XISO BHEN CTL0 CTL1 D0 D1 D2 LVDD D3 D4 D5 D6 D7 PD LPS LINKON N.C. LVDD 5. PIN ASSIGNMENT DIAGRAM EPSON S1R72801F00A TOP View INDEX 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 VSS N.C. XHRST HDD7 HDD8 HDD6 HDD9 HDD5 HDD10 HVDD HDD4 HDD11 HDD3 HDD12 HDD2 HDD13 HDD1 VSS HDD14 HDD0 HDD15 HDMARQ XHIOW XHIOR HIORDY HVDD XHDMACK HINTRQ HDA1 XHPDIAG HDA0 HDA2 XHCS0 XHCS1 TVEP VSS XHDASP FLSTST AD23 AD22 AD21 AD20 AD19 AD18 N.C. LVDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 LVDD N.C. DT0 DT1 HVDD DT2 DT3 DT4 DT5 DT6 DT7 DT8 VSS DT9 DT10 DT11 DT12 DT13 DT14 DT15 HVDD XWRH XWRL XRD AD0 AD1 AD2 AD3 VSS AD4 AD5 AD6 AD7 AD8 AD9 AD10 HVDD AD11 AD12 AD13 AD14 AD15 AD16 AD17 N.C. VSS LVDD N.C. P22 P23 K66 K67 XWAIT P00 P01 VSS P02 P03 P04 P05 P06 P07 X2SPDX RAMTST VSS PLLC VSS PLLS0 PLLS1 EA10MD0 EA10MD1 EA10MD2 HVDD P14 P13 P12 P11 VSS OSC3 OSC4 VSS P10 DSIO HVDD XNMI XRESET ICEMD VSS HCLK BCLK N.C. VSS EPSON 5 S1R72801F00A 6. PIN DESCRIPTION Control signals with an "X" as the first character of a pin name are low active. (Excluding X2SPD) Pin Name PIN I/O Reset Pin Function 1394PHY interface (LVDD ) D7 98 B Hi-Z (MSB) D6 99 B Hi-Z D5 100 B Hi-Z D4 101 B Hi-Z Data Bus with PHY D3 102 B Hi-Z D2 104 B Hi-Z D1 105 B Hi-Z D0 106 B Hi-Z (LSB) CTL1 107 B Hi-Z CTL0 108 B Hi-Z LREQ LPS LINKON XISO 115 96 95 110 O O I I BHEN 109 I CNA 111 I PD 97 O SCLK 113 I IDE Interface (HVDD) HDD15 72 B HDD14 74 B HDD13 77 B HDD12 79 B HDD11 81 B HDD10 84 B HDD9 86 B HDD8 88 B HDD7 89 B HDD6 87 B HDD5 85 B HDD4 82 B HDD3 80 B HDD2 78 B HDD1 76 B HDD0 73 B HDMARQ 71 B XHIOW 70 B XHIOR 69 B HIORDY 68 I XHDMACK 66 B HINTRQ 65 I XHPDIAG 63 I 6 Lo Lo - - - - Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z - Hi-Z - - Remarks Try State Output Drive ability 12mA Schmitt Input (Bus Holder) Tray State Output Drive Ability 12mA Schmitt Input (Bus Holder) Drive Ability 12mA Drive Ability 12mA Schmitt Input (Bus Holder) CMOS Input LINK Request Signal to PHY LINK Power Status Signal to PHY LINK ON Signal from PHY Selects Connection to PHY (L: Annex-J Isolarion) Bus Holder Enable Signal (H: Enable) CMOS Schmitt Input Cabele Not Active Power Down Enable Clock Signal from PHY (49.152MHz) Schmitt Input (Bus Holder) (MSB) IDE Data Bus (LSB) IDE DMA Request Signal IDE Write Signal IDE Read Signal IDE IORDY Signal IDE DMA Acknowledge Signal IDE Interrupt Signal IDE PDIAG Signal EPSON Drive Ability 3mA Drive Ability 6mA Drive Ability 3mA Drive Ability 3mA S1R72801F00A Pin Name PIN I/O Reset IDE Interface (HVDD ) HDA2 61 Otr Hi-Z HDA1 64 Otr Hi-Z HDA0 62 Otr Hi-Z XHCS1 59 Otr Hi-Z XHCS0 60 Otr Hi-Z XHDASP 56 I - XHRST 90 Otr Hi-Z C33 External Interface (HVDD) AD23 54 O Lo AD22 53 O Lo AD21 52 O Lo AD20 51 O Lo AD19 50 O Lo AD18 49 O Lo AD17 44 O Lo AD16 43 O Lo AD15 42 O Lo AD14 41 O Lo AD13 40 O Lo AD12 39 O Lo AD11 38 O Lo AD10 36 O Lo AD9 35 O Lo AD8 34 O Lo AD7 33 O Lo AD6 32 O Lo AD5 31 O Lo AD4 30 O Lo AD3 28 O Lo AD2 27 O Lo AD1 26 O Lo AD0 25 O Lo DT15 20 B Hi-Z DT14 19 B Hi-Z DT13 18 B Hi-Z DT12 17 B Hi-Z DT11 16 B Hi-Z DT10 15 B Hi-Z DT9 14 B Hi-Z DT8 12 B Hi-Z DT7 11 B Hi-Z DT6 10 B Hi-Z DT5 9 B Hi-Z DT4 8 B Hi-Z DT3 7 B Hi-Z DT2 6 B Hi-Z DT1 4 B Hi-Z DT0 3 B Hi-Z Pin Function (MSB) IDE Address Signal (LSB) IDE Chip Select Signal IDE Chip Select Signal IDE DASP Signal IDE Reset Signal Remarks Drive Ability 3mA Drive Ability 6mA (MSB) CPU Address Bus (LSB) (MSB) CPU Data Buss (LSB) EPSON 7 S1R72801F00A Pin Name PIN I/O Reset C33 External Interface (HVDD) P07 154 B P06 153 B P05 152 B P04 151 B SRDY(P03) 150 B SCLK(P02) 149 B SOUT(P01) 147 B SIN(P00) 146 B K67 144 I K66 143 I P23 142 B P22 141 B P21 136 B P20 135 B XCE10_EX 134 O Hi XCE9 133 O Hi XCE6 131 O Hi EA10M2 164 I EA10M1 163 I EA10M0 162 I XWAIT 145 I XRD 24 O Hi XWRH 22 O Hi XWRL 23 O Hi BCLK 182 O Hi C33 External Interface (LV DD) P14 166 B Lo P13 167 B Lo P12 168 B Lo P11 169 B Lo P10 174 B Lo DSIO 175 B Clock Generator Pin OSC4 172 O OSC3 171 I PLLS1 PLLS0 PLLC 8 161 160 158 I I - Pin Function General I/O Port 07 General I/O Port 06 General I/O Port 05 General I/O Port 04 Serial I/F Ready Signal Input Pin-cum-General I/O Port 03 Serial I/F Clock Input Pin-cum-General I/O Port 02 Serial I/F Data Output Pin-cum-General I/O Port 01 Serial I/F Data Input Pin-cum-General I/O Port 00 Remarks Pull Up Resistor Integrated Pull Up Resistor Integrated Pull Up Resistor Integrated Pull Up Resistor Integrated Pull Up Resistor Integrated Pull Up Resistor Integrated Pull Up Resistor Integrated Pull Up Resistor Integrated Pull Up Resistor Integrated Pull Up Resistor Integrated Pull Up Resistor Integrated Pull Up Resistor Integrated Pull Up Resistor Integrated Pull Up Resistor Integrated External Memory Area 10 Chip Enable Area 9 Chip Enable Area 6 Chip Enable Area 10 Boot Mode Select 2 Area 10 Boot Mode Select 1 Area 10 Boot Mode Select 0 Wait Cycle Input Read Signal Higher Order Byte Write Signal Lower Order Byte Write Signal Bus Clock Signal General I/O Port 14 (For ICD) General I/O Port 13 (For ICD) General I/O Port 12 (For ICD) General I/O Port 11 (For ICD) General I/O Port 10 (For ICD) Serial I/O Pin for Debug: Use for communication with ICD33. Pull Up Resister Integrated High Speed Oscillation Output High Speed Oscillation Output (XTAL/Ceramic Oscillation or External Clock Input) PLL Set Pin 1 PLL Circuit is not usable. PLL Set Pin 0 Connect to GND. Capacitor Connection Pin for PLL Non-Connect Pin EPSON S1R72801F00A Pin Name Other Pins ICEMD PIN I/O Reset 179 I X2PSDX 155 I XNMI XRESET HCLK TVEP Test Pin TI8 TO7 TO6 TO5 TO4 TO3 TO2 TO1 TO0 FLSTST RAMTST MonxWait MonxInt Power Pin HVDD 177 178 181 58 I I O - 121 122 123 124 125 126 127 128 129 55 156 132 120 I O O O O O O O O I I O O - P LV DD - P VSS - P N.C. Pin N.C. - - Pin Function Remarks Pull Down Resistor Integrated Hi-Impedance Control: Set Hi-Z for all outputs. Bus Speed Mode Set Pin HIGH : BCLK = CPU Clock LOW : BCLK = Half CPU Clock NMIInput Pin Initial Reset Half SCLK Frequency Division Output Flash Test Pin Connect to HV DDwhen it is mounted. Schmitt Input (Bus Holder) - - - - - - - - - - - - (MSB) (LSB) Built-in Flash Test Pin Built-in SRAM Test Pin Internal Logic xWait Monitor Pin Internal Logic xINT Monitor Pin Pull Down Resistor Integrated Pull Down Resistor Integrated HIGH HIGH Power (5V) 5,21,37,67,83,130,165,176 (8 Pins) LOW LOW Power (3.3V) 1,47,93,103,114,139 (6 Pins) GND 148,157,159,170,173,180,184 13,29,46,57,75,92,112,116,117, 118,119,138 (19 Pins) 2,45,48,91,94,137,140,183 (8 Pins) Table 6.1 Settings of EA10M2, EA10M1, and EA10M0 (Area 10 Boot Mode) P_EA10M2 P_EA10M1 P_EA10M0 Function 1 1 1 Built-in Flash Boot Mode 0 1 1 External ROM Mode Note) Other settings are not available on this IC. EPSON 9 S1R72801F00A 7. FUNCTIONAL DESCRIPTION 7.1 MEMORY MAP 7.1.1 All Memory Space Area Area 0 Address 0x000000 CPU-integrated RAM (8KB) 0x002000 (Mirror of CPU-integrated RAM) 0x030000 (Mirror of CPU-integrated Peripheral Circuit Control Register) 0x040000 CPU-integrated Peripheral Circuit Control Register 0x050000 (Mirror of CPU-integrated Peripheral Circuit Control Register) Area 2 0x060000 Reserved Area 3 Area 4 0x080000 0x100000 Reserved IEEE1394LINK/Transaction Controller Area 1 x CSREG Area (Control Register) 0x100080 Reserved 0x200000 Flash ROM Control Register 0x200008 Reserved Area 6 0x300000 Reserved Area 7 0x400000 IEEE1394LINK/Transaction Controller xCSBUF Area (SRAM: 8KB) 0x402000 Reserved Area 8 0x600000 Reserved Area 9 0x800000 Reserved Area 10 0xC00000 Area 5 Internal Flash ROM (64KB) 0xC10000 External ROM Reserved 0xFFFFFF 10 EPSON (4MB) S1R72801F00A 7.1.2 IEEE1394LINK/Transaction Controller xCSBUF Area (SRAM) 8KBytes 0x400000 HW_PageTableArea 0x4000C0 HW_RxHeaderArea 0x4000E0 HW_TxHeaderArea 0x400100 (RxHeaderAreaStart) HW_RxHeaderArea RxORBAreaStart RxHeaderArea (RingBuffer) TxHeaderAreaStart RxORBArea (RingBuffer) (TxHeaderAreaStart + 0x0040) TxHeaderArea (2 Headers) TxStreamAreaStart IDE -> 1394 DMA Area TxORBArea (RingBuffer) TxStreamAreaEnd NotUsed RxStreamAreaStart 1394 -> IDE DMA Area RxStreamArea (RingBuffer) 0x401FFF TxHeaderArea used Isocronouse used Asyncronouse only TxAreaStart + 0x20 TxAreaStart AsyTxPktHdr 0 + 0x20 + 0x30 + 0x40 AsyTxPktHdr 1 + 0x40 AsyTxPktHdr 0 IsoTxPktHdr 0 IsoTxPktHdr 1 * All RAM areas are accessible from the CPU by direct addressing. TxStreamAreaStart, TxStreamAreaEnd, and RxStreamAreaStart.) * Hardware DMA is possible to the IDE I/F for the RxStreamArea and TXStreamArea. * The TxStreamArea and RxStreamArea is usable as one StreamArea by overlaying them. * HW_PageTableArea (the equivalent of 24 pages) and HW_RxHeaderArea and HW_TXHeaderArea (the equivalent of 1 header, respectively) are assured. The RxORB and TxORB areas are usable by firmware alone. * The Post**Ptr and Used**Ptr of the RxHeaderArea, RxORBArea, TxStreamArea, and RxStreamArea monitor the used condition in each Area. (In the case of the Rx of 1394, the free space of the above two is monitored and the busy_A, B, X is controlled by hardware.) * The RxHeaderArea, RxORBArea, TxORB, TXStreamArea and RxStreamArea are RingBuffers. Even at the time of execution of data transmission/ reception according to 1394 or IDE DMA, data among the areas are guaranteed by hardware . (The size of each RingBuffer is variable by settings on the * By controlling the above functions from the TRAN & SBP2 Control Block, a PageTable fetch and data transfer according to SBP-2 are executable by hardware. EPSON 11 S1R72801F00A 7.2 IEEE1394 PACKET FORMAT 7.2.1 Transmit Packet Format (1) TxAsyncronousePacket <3> QuadReadReq, WriteResp b.31 24 23 - 0 1 2 3 4 5 6 7 Sbid 16 15 - 87 speed tl rt b.0 tcode (MSB) PacketTypeSpecInfo DestinationID pri (LSB) reserved - 1 QuadReadReq (tcode : 0x4) DestinationID 1 2 2 WriteResp 1 2 ACK (MSB) DestinationOffset (tcode : 0x2) DestinationID (LSB) rcode reserved (2) TxAsyncronousePacket <4> QuadWriteReq, QuadReadResp, BlockReadReq b.31 0 1 2 3 4 5 6 7 1 QuadWriteReq 1 2 3 2 QuadReadResp 1 2 3 3 BlockReadReq 1 2 3 12 24 23 - Sbid 16 15 - DestinationID speed tl (MSB) PacketTypeSpecInfo PacketTypeSpecQuadletData 87 rt b.0 tcode pri (LSB) reserved - (tcode : 0x0) DestinationID (tcode : 0x6) DestinationID (tcode : 0x5) DestinationID ACK (MSB) DestinationOffset QuadletData (LSB) rcode reserved QuadletData (MSB) DestinationOffset DataLength (LSB) ExtendedTcode EPSON S1R72801F00A (3) TxAsyncronousePacket <5> BlockWriteReq, BlockReadResp, LockReq, LockResp b.31 24 23 - 0 1 2 3 4 5 6 7 16 15 - Sbid 87 speed tl rt b.0 tcode pri (MSB) PacketTypeSpecInfo DestinationID (LSB) DataLength ExtendedTcode *DataPointer reserved - 1 BlockWriteReq LockReq 1 2 (tcode : 0x1) (tcode : 0x9) DestinationID 2 BlockReadResp LockResp 1 2 (tcode : 0x7) (tcode : 0xB) DestinationID ACK (MSB) DestinationOffset (LSB) rcode reserved (4) TxAsyncronousePhyPacket (tcode : 0xE) b.31 24 23 - 0 1 2 3 4 5 6 7 Sbid 16 15 - 0x0 PhyPacket 87 reserved tcode (0xE) b.0 reserved reserved (5) TxIsocoronousePacket (tcode : 0xA) b.31 24 23 - 0 1 2 3 Sbid 16 15 - speed tag DataLength 87 channel tcode (0xA) reserved b.0 sy *DataPointer reserved Transmit Packet Common Format Name speed Sbid Name ACK Bit count 3 1 Bit count 4 Description Speed Code 3'b000 3'b001 3'b010 All Other Value Souce Bus ID S100 S200 S400 Reserved 0:3FFh, 1:Source ID Description Received AckCode 4'h1 4'h2 4'h4 4'h5 4'h6 4'hB 4'hC 4'hD 4'hE 4'hF All Other Value ask_complete ask_pending ask_busy_X ask_busy_A ask_busy_B ask_tardy ask_confilict_error ask_data_error ask_type_error ask_address_error Reserved EPSON 13 S1R72801F00A 7.2.2 Receive Packet Format (1) RxAsyncronousePacket <4> QuadReadReq, WriteResp b.31 24 23 - DestinationID SourceID 0 1 2 3 4 5 6 7 16 15 87 - speed tl AS BT 0 rt b.0 BC 0 tcode (MSB) PacketTypeSpecInfo ACK pri (LSB) reserved 1 QuadReadReq 2 3 2 WriteResp 2 3 (tcode : 0x4) SourceID (MSB) DestinationOffset (tcode : 0x2) SourceID (LSB) rcode reserved (2) RxAsyncronousePacket <5> QuadWriteReq, QuadReadResp, BlockReadReq b.31 0 1 2 3 4 5 6 7 24 23 - DestinationID SourceID speed 87 - tl AS BT 0 rt b.0 BC 0 tcode (MSB) PacketTypeSpecInfo PacketTypeSpecQuadData ACK pri (LSB) reserved 1 QuadWriteReq 2 3 4 (tcode : 0x0) SourceID 2 QuadReadResp 2 3 4 (tcode : 0x6) SourceID 3 BlockReadReq 2 3 4 (tcode : 0x5) SourceID 14 16 15 (MSB) DestinationOffset QuadletData (LSB) rcode reserved QuadletData (MSB) DestinationOffset DataLength (LSB) ExtendedTcode EPSON S1R72801F00A (3) RxAsyncronousePacket <6> BlockWriteReq, BlockReadResp, LockReq, LockResp b.31 24 23 16 15 - DestinationID SourceID 0 1 2 3 4 5 6 7 87 - speed tl AS BT 0 rt b.0 BC 0 tcode (MSB) PacketTypeSpecInfo DataLength ACK pri (LSB) ExtendedTcode *DataPointer reserved 1 BlockWriteReq LockReq (tcode : 0x1) (tcode : 0x9) SourceID 2 3 2 BlockReadResp LockResp 2 3 (MSB) DestinationOffset (tcode : 0x7) (tcode : 0xB) SourceID (LSB) rcode reserved (4) RxAsyncronousePhyPacket Normal (tcode : 0xE) b.31 24 23 16 15 - 0 1 2 3 4 5 6 7 87 - 0x0 reserved b.0 - AS BT 0 1 0 tcode (0xE) ACK reserved PhyPacket reserved (5) SelfIDPacket Received SelfID packets between BusReset and 1st-ArbRstGap (tcode : 0xE) b.31 0 1 2 3 4 5 6 7 24 23 16 15 DataLength 87 - reserved AS BT 1 1 0 - tcode (0xE) b.0 ACK reserved *DataPointer reserved EPSON 15 S1R72801F00A (6) RxIsocronousePacket (tcode : 0xA) b.31 0 1 2 3 4 5 6 7 24 23 16 15 speed - DataLength 87 - tag *DataPointer AS BT 0 channel b.0 1 0 - tcode (0xA) ACK sy reserved Receive Packet Common Format b.31 0 24 23 - Name speed AS BT SI BC HC ACK PSTS Bit count 3 1 1 1 1 1 4 4 16 15 speed 87 - - BC HC ACK Description Speed Code (Note 1) AreaStatus bit (1: StreamArea, 0: ORBArea) Bit which toggles during the BusReset period. Whether the received packet is a Self ID packet Whether the received packet is a Broadcast packet. Presence/absence of the Header CRC error (1: Packet disabled) Transmitted AckCode (Note 2) AckCode which was scheduled to be transmitted (Note 2) (Note 1) Refer to the Transmit Packet Common spd (speed code). (Note 2) Refer to the Transmit Packet Common Ack (AckCode). 16 AS BT SI b.0 EPSON S1R72801F00A 7.3 IEEE1394 HARDWARE SBP-2 CONTROL The hardware SBP2 of this IC automatically executes a PageTable fetch and data transfer according to the Serial Bus Protocol 2 after receiving specifications of its PageTable Size and Address. The control of the SBP2 is performed by accessing the internal register. Data transfer is controlled by the transmission and reception of signals to and from the PHY-LINK interface and the transmission/reception of a series of packets are automatically executed by having access to the internal SRAM area. The functions of this block are as follows. This Block, (1) Receives specifications of a Page Table Size, Page Table Address, Speed Code, and Max Payload Size, etc. to automatically execute a PageTable fetch and data transfer according to the Serial Bus Protocol 2. (3) Allows you to perform the pause, resume, or reset during data transfer. Though the register value is retained even after the reset, the state machine is restored to the initial state. You can check transfer condition through the register any time. (4) Immediately enters the error pause when an error arises during data transfer by which you can check an error cause through the register. The resume from the error pause will pick up the transaction where the error arose. (5) Allows you to transfer data if you specify the omission of the PageTable fetch or Page Element No. to start data. (2) Can transfer data the equivalent of max. 24-page elements at one time. If no PageTable exists, you can transfer data by directly specifying a data length as a Page Table Size. 7.4 IDE INTERFACE CONTROL 7.5 BUILT-IN CPU This IC contains a block to control the IDE interface. Its functions are as follows. Regarding the built-in CPU, refer to the E0C33208/204/ 202 TECHNICAL MANUAL (and E0C33 Family ASIC Macro Manual). This block, (1) Accesses the IDE bus by having access to the Program mode of the CPU. The access to the data port of the CPU is available only in PIO mode. (2) Can monitor various kinds of signals of the IDE interface. In the built-in CPU core, however, a DMA controller and A/D converter are not integrated; this part is different from the description on the DMA controller and A/D converter given in TECHNICAL MANUAL (and Macro Manual). A low speed oscillation circuit (OSC1) is not available. (3) Controls the link-up of function blocks in accordance with the control signals and operation end signal from the DMA control circuit. (4) Manages the condition of data transfer in DMA mode of the IDE by the HDMARQ/XHDMACK signal. (5) Reads and writes the data of data bus DD15-0 of IDE from and to the FIFO in the 1394LINKCORE by the XHIOR/XHIOW signal. If the FIFO becomes full or empty to disable data transfer, this block suspends data transfer with specified timing. EPSON 17 S1R72801F00A 7.6 FLASH CONTROLLER This IC is provided with a function to perform Erase and Write to the Flash ROM. (1) Chip Erase According to a specified sequence, you can erase all memory cells in the built-in Flash ROM to put them in "1" status. After erasing the chip, check that the data of all memory cells is "1". (2) Sector Erase This IC is ready for the Sector Erase in the unit of 512 words/sector. According to a specified sequence, you can erase all 18 memory cells in the built-in Flash ROM to put them in "1" status. After erasing the chip, check that the data of all memory cells is "1". (3) Write Write is complete if you continue writing Write data in the unit of word until writing of all sectors (512 words) finishes. On completion of the Sector Write, compare all data in the sectors with original data for confirmation. You cannot change the data of the memory cell from "0" to "1" by writing. EPSON S1R72801F00A 8. INTERNAL REGISTER 8.1 IEEE1394 LINK CONTROLLER REGISTER MAPPING 8.1.1 Register Table (The base address of this register is 0x100000.) Address Register Name R/W Function 0x00 0x01 MainIntStat SubIntStat R(W) R(W) Main Interrupt Status Register Sub-Interrupt Status Register 0x02 0x03 (Reserved) DmaIntStat R(W) DMA Interrupt Status Register 0x04 0x05 LinkIntStat1 LinkIntStat0 R(W) R(W) LINK Core Interrupt Status Register 1 LINK Core Interrupt Status Register 0 0x06 0x07 PhyIntStat (Reserved) R(W) PHY Interrupt Status Register 0x08 0x09 MainIntEnb SubIntEnb R/W R/W Main Interrupt Enable Flag Register Sub-Interrupt Enable Flag Register 0x0A 0x0B (Reserved) DmaIntEnb R/W DMA Interrupt Enable Flag Register 0x0C 0x0D 0x0E LinkIntEnb1 LinkIntEnb0 PhyIntEnb R/W R/W R/W LINK Core Interrupt Enable Flag Register 1 LINK Core Interrupt Enable Flag Register 0 PHY Interrupt Enable Flag Register 0x0F 0x10 (Reserved) ChipCtl 0x11 0x12 HW_Revision (Reserved) 0x13 0x14 (Reserved) (Reserved) 0x15 0x16 (Reserved) (Reserved) 0x17 0x18 Relation R/W Chip Control Register R/W Hardware Revision Register (Reserved) LinkCtl_H R/W LINK Core Control Register Higher Rank 0x19 0x1A LinkCtl_L LinkStat R/W R LINK Core Control Register LINK Core Status Read Register Lower Rank 0x1B 0x1C PriReqCnt RetryLimit_H R R/W Priority Request Count Register Dual Retry Time Set Register 0x1D 0x1E RetryLimit_L MaxRetry R/W R/W Dual Retry Time Set Register Single Retry Number Set Register 0x1F 0x20 IRM_Stat NODE_IDS_H R/W R/W IRM Status Register Node IDS Status Register Higher Rank 0x21 0x22 NODE_IDS_L (Reserved) R/W Node IDS Status Register Lower Rank 0x23 0x24 (Reserved) PhyAccCtl_H R/W LINK Core Control Register Middle Rank 0x25 0x26 PhyAccCtl_L PhyRdstat_H R/W R LINK Core Control Register LINK Core Status Read Register Lower Rank 0x27 0x28 PhyRdstat_L ChnlIndex R/W R/W Priority Request Count Register ISO Async Stream Channel Index Register 0x29 0x2A ChnlWindow CmprIndex R/W R/W ISO Async Stream Channel Window Register Compare Offset Address Index Register 0x2B 0x2C CmpRW indow CYCLE_TIME_H R/W R/W Compare Offset Address Window Register Cycle Time Register EPSON Higher Rank Lower Rank Higher Rank 19 S1R72801F00A Address 20 Register Name R/W Function 0x2D 0x2E CYCLE_TIME_MH CYCLE_TIME_ML R/W R/W Cycle Time Register Cycle Time Register 0x2F 0x30 CYCLE_TIME_L HwSBP2Ctl R/W R/W Cycle Time Register Hardware SBP2 Control Register 0x31 0x32 HwSBP2Stat HwSBP2IntStat R/W R(W) Hardware SBP2 Status Read Register Hardware SBP2 Interrupt Status Register 0x33 0x34 HwSBP2Index HwSBP2Window_H R/W R/W Hardware SBP2 Index Register Hardware SBP2 Window Register Higher Rank 0x35 0x36 HwSBP2Window_L PayloadSize_H R/W R/W Hardware SBP2 Window Register Hardware SBP2 Payload Size Set Register Lower Rank Higher Rank 0x37 0x38 PayloadSize_L PageTableSize_H R/W R/W Hardware SBP2 Payload Size Set Register Hardware PageTable Size Set Register Lower Rank Higher Rank 0x39 0x3A PageTableSize_L PageTableAdrs0 R/W R/W Hardware PageTable Size Set Register Hardware SBP2 PageTable Address Set Register Lower Rank Higher Rank 0x3B 0x3C PageTableAdrs1 PageTableAdrs2 R/W R/W Hardware SBP2 PageTable Address Set Register Hardware SBP2 PageTable Address Set Register 0x3D 0x3E PaqeTableAdrs3 PageTableAdrs4 R/W R/W Hardware SBP2 PageTable Address Set Register Hardware SBP2 PageTable Address Set Register 0x3F 0x40 PageTableAdrs5 LinkRxHdrPtr_H R/W R/W Hardware SBP2 PageTable Address Set Register Receive Header LINK Pointer Register Lower Rank Higher Rank 0x41 0x42 LinkRxHdrPtr_L LinkRxORBPtr_H R/W R/W Receive Header LINK Pointer Register Receive ORB Data LINK Pointer Register Lower Rank Higher Rank 0x43 0x44 LinkRxORBPtr_L LinkRxStreamPtr_H R/W R/W Receive ORB Data LINK Pointer Register Receive Stream Data LINK Pointer Register Lower Rank Higher Rank 0x45 0x46 LinkRxStreamPtr_L LinkTxStreamPtr_H R/W R Receive Stream Data LINK Pointer Register Receive Stream Data LINK Pointer Register Lower Rank Higher Rank 0x47 0x48 0x49 LinkTxStreamPtr_L UsedRxHdrPtr_H UsedRxHdrPtr_L R R/W R/W Receive Stream Data LINK Pointer Register Used Receive Header Pointer Register Used Receive Header Pointer Register Lower Rank Higher Rank Lower Rank 0x4A 0x4B UsedRxORBPtr_H UsedRxORBPtr_L R/W R/W Used Receive ORB Data Pointer Register Used Receive ORB Data Pointer Register Higher Rank Lower Rank 0x4C 0x4D IDE_RxStreamPtr_H IDE_RxStreamPtr_L R/W R/W Receive Stream Data IDE Pointer Register Receive Stream Data IDE Pointer Register Higher Rank Lower Rank 0x4E 0x4F IDE_TxStreamPtr_H IDE_TxStreamPtr_L R/W R/W Receive Stream Data IDE Pointer Register Receive Stream Data IDE Pointer Register Higher Rank Lower Rank 0x50 0x51 BufControl BufMonitor R/W R Buffer Control Register Buffer Monitor Register 0x52 0x53 AsyDmaCtl IsoDmaCtl R/W R/W Async TxDMA Control Register ISO TxDMA Control Register 0x54 0x55 RxDmaCtl AreaIndex R/W R/W RxDMA Control Register Memory Map Area Set Index Register 0x56 0x57 AreaWindow_H AreaWindow_L R/W R/W Memory Map Area Set Window Register Memory Map Area Set Window Register Higher Rank Lower Rank 0x58 0x59 BRstHdrPtr_H BRstHdrPtr_L R R Bus Reset Header Pointer Register Bus Reset Header Pointer Register Higher Rank Lower Rank 0x5A 0x5B BRstORBPtr_H BRstORBPtr_L R R Bus Reset ORB Pointer Register Bus Reset ORB Pointer Register Higher Rank Lower Rank 0x5C 0x5D (Reserved) (Reserved) 0x5E 0x5F MaintCtl_H MaintCtl_L Maintenance Control Register Maintenance Control Register Higher Rank Lower Rank R/W R/W EPSON Relation Lower Rank S1R72801F00A Address Register Name R/W Function 0x60 0x61 IDE_Config0 IDE_Config1 R/W R/W IDE Configuration Register IDE Configuration Register 0x62 0x63 IDE_RegAccCyc IDE_PioDmaCyc R/W R/W IDE Register Access Cycle Register IDE PIO/DMA Cycle Register 0x64 0x65 IDE_UltraDmaCyc IDE_DmaCtl R/W R/W IDE Ultra DMA Cycle Register IDE DMA Control Register 0x66 0x67 IDE_BusStat IDE_DmaStat R/W R/W IDE Bus Status Read Register IDE DMA Status Register 0x68 0x69 IDE_ByteCount0 IDE_ByteCount1 R/W R/W IDE Byte Count Set Register IDE Byte Count Set Register 0x6A 0x6B IDE_ByteCount2 IDE_ByteCount3 R/W R/W IDE Byte Count Set Register IDE Byte Count Set Register Lower Rank 0x6C 0x6D IDE_CRC0 IDE_CRC1 CRC Read Register CRC Read Register Higher Rank Lower Rank 0x6E 0x6F (Reserved) (Reserved) 0x70 0x71 IDE_CS00 IDE_CS01 R/W R/W IDE Command Block Register IDE Command Block Register 0x72 0x73 IDE_CS02 IDE_CS03 R/W R/W IDE Command Block Register IDE Command Block Register 0x74 0x75 IDE_CS04 IDE_CS05 R/W R/W IDE Command Block Register IDE Command Block Register 0x76 0x77 IDE_CS06 IDE_CS07 R/W R/W IDE Command Block Register IDE Command Block Register 0x78 0x79 IDE_CS10 IDE_CS11 R/W R/W IDE Command Control Register IDE Command Control Register 0x7A 0x7B 0x7C IDE_CS12 IDE_CS13 IDE_CS14 R/W R/W R/W IDE Command Control Register IDE Command Control Register IDE Command Control Register 0x7D 0x7E IDE_CS15 IDE_CS16 R/W R/W IDE Command Control Register IDE Command Control Register 0x7F IDE_CS17 R/W IDE Command Control Register R R EPSON Relation Higher Rank 21 S1R72801F00A 8.1.2 Register/Bit Table The base address of this register is 0x100000. Address 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 22 Register Name MainIntStat SubIntStat (Reserved) DmaIntStat LinkIntStat1 LinkIntStat0 PhyIntStat (Reserved) MainIntEnb SubIntEnb (Reserved) DmaIntEnb LinkIntEnb1 UltraDmaMode PhyIntEnb (Reserved) ChipCtl HW_Revision ApetusTestOutPut_H ApetusTestOutPut_L LCTestIndex LCTestWindow SBP2TestIndex SBP2TestWindow LinkCtl_H LinkCtl_L LinkStat PriReqCnt RetryLimit_H RetryLimit_L MaxRetry IRM_Stat NODE_IDS_H NODE_IDS_L (Reserved) (Reserved) PhyAccCtl_H PhyAccCtl_L PhyRdstat_H PhyRdstat_L ChnlIndex ChnlWindow CmprIndex CmprWindow CYCLE_TIME_H CYCLE_TIME_MH CYCLE_TIME_ML CYCLE_TIME_L bit7 SubIntStat SelfIDdone bit6 TxIsoCmp SelfIDerr bit5 bit4 bit3 bit2 RxDmaCmp TxAsyCmp HwSBP2Cmp IDE_DmaCm HwSBP2Err HwSBP2BRs LinkIntStat1 LinkIntStat0 TxAsyRtyGo TxAsyBCSent RxDmaFaild UnExpCh SubGap DupliCh ArbGap IsoArbFaild CycTooLong TxAsyFaild RxOnTardy CycOverFlw TxIsoFaild RxHcrcErr CycEvent Phy_int bit1 IDE_INTRQ PhyIntStat bit0 BusReset DmaIntStat TxAsyBRAbort RxUnkTcode CycLost PhyWrDone TxAsyMiss TxRtyExced CycArbFail PhyRdDone EnSubIntStat EnTxIsoCmp EnRxDmaCmp EnTxAsyCmp EnHwSBP2Cm EnIDE_DmaC EnIDE_INTRQ EnBusReset EnSelfIDdone EnSelfIDerr EnHwSBP2Err EnHwSBP2BRst EnLinkIntStat1 EnLinkIntStat0 EnPhyIntStat EnDmaIntStat EnTxAsyRtyGo EnTxAsyBCSe EnRxDmaFaild EnTxAsyFaild EnTxIsoFaild EnTxAsyBRAb EnTxAsyMiss EnRxOnTardy EnRxHcrcErr EnRxUnkTcod EnTxRtyExced EnUnExpCh EnDupliCh EnIsoArbFaild EnCycTooLon EnCycOverFlw EnCycEvent EnCycLost EnCycArbFail EnSubGap EnArbGap EnPhy_int EnPhyWrDone EnPhyRdDone Suspend IDE_MdlRst SendTardy SoftReset HW_Revision[7:0] Chip Test Register PassSelfID EnLink PassPhyPkt PassBrPkt PLIFrst EnPosWB IgnrBChdr APHY EnAcc RxBusyMode DualRtyEnb ID_Valid Root Priority Budget Request Count [5:0] CycLimit[12:8] CycLimit[7:0] MaxRetry[3:0] IRM_ID[5:0] BusID[9:2] Physical ID[5:0] SecLimit[2:0] NoIRM WonIRM BusID[1:0] RdReq EnPosWQ IgnrBCdata WrReq Cmstr SinglRtyEnb CablPwSts Request Address[3:0] Write Data[7:0] Read Address[3:0] Read Data[7:0] Channel Index Channel Window Compare Address Index Compare Address Window Cycle Second[6:0] Cycle Count[11:4] Cycle Count[3:0] Cycle Offset[11:8] Cycle Offset[7:0] EPSON CycCnt[12] S1R72801F00A Address 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F Register Name HwSBP2Ctl HwSBP2Stat HwSBP2IntStat HwSBP2Index HwSBP2Window_H HwSBP2Window_L PayloadSize_H PayloadSize_L PageTableSize_H PageTableSize_L PageTableAdrs0 PageTableAdrs1 PageTableAdrs2 PaqeTableAdrs3 PageTableAdrs4 PageTableAdrs5 LinkRxHdrPtr_H LinkRxHdrPtr_L LinkRxORBPtr_H LinkRxORBPtr_L LinkRxStreamPtr_H LinkRxStreamPtr_L LinkTxStreamPtr_H LinkTxStreamPtr_L UsedRxHdrPtr_H UsedRxHdrPtr_L UsedRxORBPtr_H UsedRxORBPtr_L IDE_RxStreamPtr_H IDE_RxStreamPtr_L IDE_TxStreamPtr_H IDE_TxStreamPtr_L BufControl BufMonitor AsyDmaCtl IsoDmaCtl RxDmaCtl AreaIndex AreaWindow_H AreaWindow_L BRstHdrPtr_H BRstHdrPtr_L BRstORBPtr_H BRstORBPtr_L (Reserved) (Reserved) MaintCtl_H MaintCtl_L bit7 bit6 PtNotPresen HOSTtoDev FwPause ErrPause SplitTimeOut TxAckedIlleg bit5 FromStream TxAckMiss (MSB) (MSB) (MSB) bit4 bit3 bit2 bit1 bit0 HwSBP2Rst HwSBP2Rsu HwSBP2Pau HwSBP2Star WaitPLRead HwSBP2Exe PTaskExec StTaskExec TranExec BRAbort RxNotRespCm RxBroadCast RxAckDataErr HwSBP2 Index HwSBP2 Window (LSB) Payload Size (LSB) Page Table Size (LSB) (MSB) Page Table Offset Address (LSB) LinkRxHdrPtr[12:8] LinkRxHdrPtr[7:5] LinkORBPointer[12:8] LinkRxORBPtr[7:2] LinkRxStreamPtr[12:8] LinkRxStreamPtr[7:2] LinkTxStreamPtr[12:8] LinkTxStreamPtr[7:2] UsedRxHdrPtr[12] UsedRxHdrPtr[7:5] UsedRxORBPtr[12:8] UsedRxORBPtr[7:2] IDE_RxStreamPtr[12:8] IDE_RxStreamPtr[7:2] IDE_TxStreamPtr[12:8] TxStreamClr RxStreamClr RxPayldRdy TxPayldRdy AsyChnlSel IsoChnlSel IDE_TxStreamPtr[7:2] RxORBClr RxHdrClr UpdLinkTxStrm RxHdrRemain RxORBFull RxStreamFull RxHdrFull BlkWrAreaSel AsyFIFOEpty AsyFIFOClr AsyTxMon AsyStart SelTxPtr IsoFIFOEpty IsoFIFOClr IsoTxMon IsoStart RxFIFOEpty RxFIFOClr RxMon ForceBusy Memory Map Area Index Memory Map Area Window (LSB) BusReset Header Pointer[12:8] (MSB) BusResetHeaderPointer[7:5] BusResetORBPointer[12:8] BusResetORBPointer[7:2] E_Hcrc E_Dcrc No_Pkt F_Ack N_ack Ack[7:0] EPSON 23 S1R72801F00A Address 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F Register Name bit7 bit6 bit5 IDE_Config0 UltraDmaMode DmaMode ActPort IDE_Config1 IDE_Reset IDE_RegAccCyc Assert Pulse[3:0] IDE_PioDmaCyc Assert Pulse[3:0] IDE_UltraDmaCyc IDE_DmaCtl IDE_BusStat DMARQ DMACK INTRQ IDE_DmaStat IDE_ByteCount0 (MSB) IDE_ByteCount1 IDE_ByteCount2 IDE_ByteCount3 IDE_CRC0 (MSB) IDE_CRC1 IDE_TestIndex IDE_TestWindow IDE_CS00 Command Block register IDE_CS01 Command Block register IDE_CS02 Command Block register IDE_CS03 Command Block register IDE_CS04 Command Block register IDE_CS05 Command Block register IDE_CS06 Command Block register IDE_CS07 Command Block register IDE_CS10 Control Block Register IDE_CS11 Control Block Register IDE_CS12 Control Block Register IDE_CS13 Control Block Register IDE_CS14 Control Block Register IDE_CS15 Control Block Register IDE_CS16 Control Block Register IDE_CS17 Control Block Register bit4 IDE_Slave CRC_Clear IORDY bit3 DMARQ_Leve FIFO_Clear bit2 Swap bit1 Negate Pulse[3:0] Negate Pulse[3:0] Cycle Time[3:0] IDE_Abort IDE_Directio DIAG DmaPause bit0 DmaStart DASP DmaRun IDE DMA xfer Byte Count (LSB) Ultra DMA CRC Value (LSB) Chip Test Register R- Data R- Error R- Sector Count R- Sector Number/LBA[bit0-7] R- Cylinder Low/LBA[bit8-15] R- Cylinder High/LBA[bit[16-23] R- Device/Head,LBA[bit24-27] R- Status R- Data Bus Hi-Impedence R- Data Bus Hi-Impedence R- Data Bus Hi-Impedence R- Data Bus Hi-Impedence R- Data Bus Hi-Impedence R- Data Bus Hi-Impedence R- Alternate Status R- (obsolete) W- Data W- Features W- Sector Count W- Sector Number/LBA[bit0-7] W- Cylinder Low/LBA[bit8-15] W- Cylinder High/LBA[bit[16-23] W- Device/Head,LBA[bit24-27] W- Command W- Not Used W- Not Used W- Not Used W- Not Used W- Not Used W- Not Used W- Device Control W- Not Used LinkChnnel Index/Window Register ChnlIndex ChnlWindow 0x00 ChannelAvailableH0 0x01 ChannelAvailableH1 0x02 ChannelAvailableH2 0x03 ChannelAvailableH3 0x04 ChannelAvailableL0 0x05 ChannelAvailableL1 0x06 ChannelAvailableL2 0x07 ChannelAvailableL3 0x08 ReceiveChannel0 0x09 ReceiveChannel1 0x0A ReceiveChannel2 0x0B ReceiveChannel3 0x0C ReceiveChannel4 0x0D ReceiveChannel5 0x0E ReceiveChannel6 0x0F ReceiveChannel7 24 bit7 ch08 ch16 ch24 ch32 ch40 ch48 ch56 ch00 ch08 ch16 ch24 ch32 ch40 ch48 ch56 bit6 ch01 ch09 ch17 ch25 ch33 ch41 ch49 ch57 ch01 ch09 ch17 ch25 ch33 ch41 ch49 ch57 bit5 ch02 ch10 ch18 ch26 ch34 ch42 ch50 ch58 ch02 ch10 ch18 ch26 ch34 ch42 ch50 ch58 bit4 ch03 ch11 ch19 ch27 ch35 ch43 ch51 ch59 ch03 ch11 ch19 ch27 ch35 ch43 ch51 ch59 EPSON bit3 ch04 ch12 ch20 ch28 ch36 ch44 ch52 ch60 ch04 ch12 ch20 ch28 ch36 ch44 ch52 ch60 bit2 ch05 ch13 ch21 ch29 ch37 ch45 ch53 ch61 ch05 ch13 ch21 ch29 ch37 ch45 ch53 ch61 bit1 ch06 ch14 ch22 ch30 ch38 ch46 ch54 ch62 ch06 ch14 ch22 ch30 ch38 ch46 ch54 ch62 bit0 ch07 ch15 ch23 ch31 ch39 ch47 ch55 ch63 ch07 ch15 ch23 ch31 ch39 ch47 ch55 ch63 S1R72801F00A Compare Address Index/Window Register CmprIndex 0x00 0x01 0x02 0x03 0x04 0x05 0x06 : 0x0F ChnlWindow CompareDOffset0 CompareDOffset1 CompareDOffset2 CompareDOffset3 CompareDOffset4 CompareDOffset5 (Reserved) (Reserved) (Reserved) bit7 (MSB) bit6 bit5 bit4 bit3 bit2 bit1 bit0 Compare Destination Offset Address[47:0] (LSB) H/W SBP2 Index Chnnel/Window Register SBP2Index SBP2Window_H/L 0x00 PageBoundary PageElementNunber 0x01 PgElmentRemain_H PgElmentRemain_L 0x02 SpeedCode MaxPayload 0x03 DestinationID_H DestinationID_L 0x04 SplitTime_H SplitTime_L 0x05 (Reserved) : (Reserved) 0x0F (Reserved) bit7 bit6 bit5 (MSB) bit4 bit3 bit2 bit1 bit0 PageBoundary[2:0] PageElementNumber[4:0] Page Element Remain Length (Bytes) (LSB) SpeedCode[2:0] MaxPayload[3:0] (MSB) Destination_ID Value Second[2:0] (LSB) Cycle Count[12:8] Cycle Count[7:0] Memory Map Area Index/Window Register AreaIndex AreaWindow_H/L 0x00 RxORBAreaStart_H RxORBAreaStart_L 0x01 TxHdrAreaStart_H TxHdrAreaStart_L 0x02 TxStreamAreaStart_H TxStreamAreaStart_L 0x03 TxStreamAreaEnd_H TxStreamAreaEnd_L 0x04 RxStreamAreaStart_H RxStreamAreaStart_L 0x05 (Reserved) : (Reserved) 0x0F (Reserved) bit7 bit6 bit5 bit4 (MSB) RxORBAreaStart[7:2] (MSB) TxHdrAreaStart[7:2] (MSB) TxStreamAreaStart[7:2] (MSB) TxStreamAreaEnd[7:2] (MSB) RxStreamAreaStart[7:2] EPSON bit3 bit2 bit1 RxORBAreaStart[12:8] (LSB) TxHdrAreaStart[12:8] (LSB) TxStreamAreaStart[12:8] (LSB) TxStreamAreaEnd[12:8] (LSB) RxStreamAreaStart[12:8] (LSB) bit0 25 S1R72801F00A 8.1.3 Register Map (The base address of this register is 0x100000.) Address Register Name 0x00 0x01 MainIntStat SubIntStat UltraDmaMode 0x02 0x03 0x04 0x05 0x06 0x07 26 (Reserved) DmaIntStat LinkIntStat1 LinkIntStat0 PhyIntStat (Reserved) Bit Symbol R/W 7:SubIntStat 6: TxIsoCmp 5: RxDmaCmp 4: TxAsyCmp 3: HwSBP2Cmp 2: IDE_DmaCmp 1: IDE_INTRQ 0: BusReset R(W) R(W) R(W) R(W) R(W) R(W) R(W) R(W) 0: None 0: None 0: None 0: None 0: None 0: None 0: None 0: None 1: Sub Interrupt Occurred 1: ISO Pkt Transmit Done 1: Packet Reception 1: AckCode Reception 1: HwSBP2 Process Complete 1: IDE DMA Transmit Complete 1: IDE Interface Interrupt 1: Bas Reset Detected 7: SelfIDdone 6: SelfIDerr 5: HwSBP2Err 4: HwSBP2BRst 3: LinkIntStat1 2: LinkIntStat0 1: PhyIntStat 0: DmaIntStat R(W) R(W) R(W) R(W) R(W) R(W) R(W) R(W) 0: None 0: None 0: None 0: None 0: None 0: None 0: None 0: None 1: Self-ID Phase Done 1: Self-ID Packet Error 1: Hw SBP2 Error 1: BusReset in process HwSBP 1: Link1 Interrupt Occurred 1: Link0 Interrupt Occurred 1: PHY Interrupt Occurred 1: Dma Interrupt Occurred 0: 0: 0: 0: 0: 0: 0: 0: 1: 1: 1: 1: 1: 1: 1: 1: 0: 0: None 0: None 0: None 0: None 0: None 0: None 0: None 1: 1: Async Tx Retry Go 1: AsyncTxBroadcast Sent 1: Rx DMA Failed 1: Async Tx Failed 1: ISO Tx Failed 1: Async Tx BusReset Abort 1: AsyncTxAckCodeMissing 0: 0: 0: 7: 6: 5: 4: 3: 2: 1: 0: 7: 6: TxAsyRtyGo 5: TxAsyBCSent 4: RxDmaFaild 3: TxAsyFaild 2: TxIsoFaild 1: TxAsyBRAbort 0: TxAsyMiss R(W) R(W) R(W) R(W) R(W) R(W) R(W) Description 7: 6: 5: 4: 3: RxOnTardy 2: RxHcrcErr 1: RxUnkTcode 0: TxRtyExced R(W) R(W) R(W) R(W) 0: None 0: None 0: None 0: None 1: 1: 1: 1: 1: Ack_tardy Sent 1: Rx Packet Header CRC Err 1: Rx Packet Tcode Unknown 1: Tx Retry Exceeded 7: UnExpCh 6: DupliCh 5: IsoArbFaild 4: CycTooLong 3: CycOverFlw 2: CycEvent 1: CycLost 0: CycArbFail R(W) R(W) R(W) R(W) R(W) R(W) R(W) R(W) 0: None 0: None 0: None 0: None 0: None 0: None 0: None 0: None 1: Unknown Expected Channel 1: DuplicateChannelDetected 1: Iso Arbtration Failed 1: ISO Arbitration Failed 1: Cycle Timer Over Fullow 1: Local Cycle Event Occured 1: Cycle Start Packet Lost 1: CycleStartPkt Arbtration Fail 7: SubGap 6: ArbGap 5: 4: 3: 2: Phy_int 1: PhyWrDone 0: PhyRdDone R(W) R(W) 0: None 0: None 0: 0: 0: 0: None 0: None 0: None 1: Sub Action Gap Detected 1: ArbtrationResetGapDetected 1: 1: 1: 1: PHY Interrupt Detected 1: PHY Register Write Done 1: PHY Register Read Done 0: 0: 0: 0: 0: 0: 0: 0: 1: 1: 1: 1: 1: 1: 1: 1: 7: 6: 5: 4: 3: 2: 1: 0: R(W) R(W) R(W) EPSON H.Rst S.Rst B.Rst 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - S1R72801F00A Address 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F Register Name MainIntEnb SubIntEnb (Reserved) DmaIntEnb LinkIntEnb1 LinkIntEnb0 PhyIntEnb (Reserved) Bit Symbol R/W 7: EnSubIntStat 6: EnTxIsoCmp 5: EnRxDmaCmp 4: EnTxAsyCmp 3: EnHwSBP2Cmp 2: EnIDE_DmaCmp 1: EnIDE_INTRQ 0: EnBusReset R/W R/W R/W R/W R/W R/W R/W R/W 0: Disable 0: Disable 0: Disable 0: Disable 0: Disable 0: Disable 0: Disable 0: Disable 1: Enable 1: Enable 1: Enable 1: Enable 1: Enable 1: Enable 1: Enable 1: Enable 7: EnSelfIDdone 6: EnSelfIDerr 5: EnHwSBP2Err 4: EnHwSBP2BRst 3: EnLinkIntStat1 2: EnLinkIntStat0 1: EnPhyIntStat 0: EnDmaIntStat R/W R/W R/W R/W R/W R/W R/W R/W 0: Disable 0: Disable 0: Disable 0: Disable 0: Disable 0: Disable 0: Disable 0: Disable 1: Enable 1: Enable 1: Enable 1: Enable 1: Enable 1: Enable 1: Enable 1: Enable 0: 0: 0: 0: 0: 0: 0: 0: 1: 1: 1: 1: 1: 1: 1: 1: R/W R/W R/W R/W R/W R/W R/W 0: 0: Disable 0: Disable 0: Disable 0: Disable 0: Disable 0: Disable 0: Disable 1: 1: Enable 1: Enable 1: Enable 1: Enable 1: Enable 1: Enable 1: Enable 7: 6: 5: 4: 3: EnRxOnTardy 2: EnRxHcrcErr 1: EnRxUnkTcode 0: EnTxRtyExced R/W R/W R/W R/W 0: 0: 0: 0: 0: Disable 0: Disable 0: Disable 0: Disable 1: 1: 1: 1: 1: Enable 1: Enable 1: Enable 1: Enable 7: EnUnExpCh 6: EnDupliCh 5: EnIsoArbFaild 4: EnCycTooLong 3: EnCycOverFlw 2: EnCycEvent 1: EnCycLost 0: EnCycArbFail R/W R/W R/W R/W R/W R/W R/W R/W 0: Disable 0: Disable 0: Disable 0: Disable 0: Disable 0: Disable 0: Disable 0: Disable 1: Enable 1: Enable 1: Enable 1: Enable 1: Enable 1: Enable 1: Enable 1: Enable 7: EnSubGap 6: EnArbGap 5: 4: 3: 2: EnPhy_int 1: EnPhyWrDone 0: EnPhyRdDone R/W 0: Disable R/W 0: Disable 0: 0: 0: R/W 0: Disable R/W 0: Disable R/W 0: Disable 1: Enable 1: Enable 1: 1: 1: 1: Enable 1: Enable 1: Enable 7: 6: 5: 4: 3: 2: 1: 0: 7: 6: EnTxAsyRtyGo 5: EnTxAsyBCSent 4: EnRxDmaFaild 3: EnTxAsyFaild 2: EnTxIsoFaild 1: EnTxAsyBRAbort 0: EnTxAsyMiss 7: 6: 5: 4: 3: 2: 1: 0: Description 0: 0: 0: 0: 0: 0: 0: 0: EPSON 1: 1: 1: 1: 1: 1: 1: 1: H.Rst S.Rst B.Rst 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - 27 S1R72801F00A Address 0x10 0x11 Register Name ChipCtl HW_Revision UltraDmaMode 0x12 0x13 0x14 0x15 0x16 0x17 28 (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) Bit Symbol 7: Suspend 6: 5: 4: 3: 2: IDE_MdlRst 1: SendTardy 0: SoftReset 7: HW_Revision[7] 6: HW_Revision[6] 5: HW_Revision[5] 4: HW_Revision[4] 3: HW_Revision[3] 2: HW_Revision[2] 1: HW_Revision[1] 0: HW_Revision[0] 7: 6: 5: 4: 3: 2: 1: 0: R/W Description H.Rst R/W 0: Resume 1: Suspend 0: 1: 0: 1: 0: 1: 0x00 0: 1: W 0: None 1: IDE_Module Reset R/W 0: None 1: Send Ack_tardy W 0: None 1: Reset Start R Indicate Hard Ware Revison Number 0: 0: 0: 0: 0: 0: 0: 0: 1: 1: 1: 1: 1: 1: 1: 1: 7: 6: 5: 4: 3: 2: 1: 0: 7: 6: 5: 4: 3: 2: 1: 0: 0: 0: 0: 0: 0: 0: 0: 0: 0: 0: 0: 0: 0: 0: 0: 0: 1: 1: 1: 1: 1: 1: 1: 1: 1: 1: 1: 1: 1: 1: 1: 1: 7: 6: 5: 4: 3: 2: 1: 0: 7: 6: 5: 4: 3: 2: 1: 0: 0: 0: 0: 0: 0: 0: 0: 0: 0: 0: 0: 0: 0: 0: 0: 0: 1: 1: 1: 1: 1: 1: 1: 1: 1: 1: 1: 1: 1: 1: 1: 1: 7: 6: 5: 4: 3: 2: 1: 0: 0: 0: 0: 0: 0: 0: 0: 0: 1: 1: 1: 1: 1: 1: 1: 1: EPSON S.Rst B.Rst 0x00 - 0x03 0x03 0x03 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - S1R72801F00A Address Register Name Bit Symbol 0x18 LinkCtl_H 7: PassSelfID 6: PassPhyPkt 5: PassBrPkt 4: EnPosWB 3: EnPosWQ 2: APHY 1: EnAcc 0: Cmstr 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F LinkCtl_L LinkStat PriReqCnt RetryLimit_H RetryLimit_L MaxRetry IRM_Stat 7: EnLink 6: 5: PLIFrst 4: IgnrBChdr 3: IgnrBCdata 2: RxBusyMode 1: DualRtyEnb 0: SinglRtyEnb 7: 6: 5: 4: 3: 2: ID_Valid 1: Root 0: CablPwSts 7: 6: 5: PriReq[5] 4: PriReq[4] 3: PriReq[3] 2: PriReq[2] 1: PriReq[1] 0: PriReq[0] 7: SecLimit[2] 6: SecLimit[1] 5: SecLimit[0] 4: CycLimt[12] 3: CycLimt[11] 2: CycLimt[10] 1: CycLimt[9] 0: CycLimt[8] 7: CycLimt[7] 6: CycLimt[6] 5: CycLimt[5] 4: CycLimt[4] 3: CycLimt[3] 2: CycLimt[2] 1: CycLimt[1] 0: CycLimt[0] 7: 6: 5: 4: 3: maxRty[3] 2: maxRty[2] 1: maxRty[1] 0: maxRty[0] 7: NoIRM 6: WonIRM 5: IRMID[5] 4: IRMID[4] 3: IRMID[3] 2: IRMID[2] 1: IRMID[1] 0: IRMID[0] R/W R/W R/W W R/W R/W R/W R/W R/W R R R Description H.Rst 0: Non PassSelfID 1: Self-ID to DMA FIFO 0: Non Pass PHY Packet 1: PHY Pkt to DMA FIFO 0: Non Pass BusRst Packet 1: BusRst Pkt to DMA FIFO 0: Disable Posted WB 1: Enable Posted WB 0x00 0: Disable Poosted WQ 1: Enable Posted WQ 0: PHY 1394.a uncorrespond 1: PHY 1394.a correspond 0: Ack Acceleration Disable 1: Ack Acceleration Enable 0: Cycle Master Not Capabl 1: Cycle Master Capable 0: Disable Link 0: 0: NONE 0: BC Pkt to DMA FIFO 0: BC Data to DMA FIFO 0: Dual 0: Dual Retry Disable 0: Single Retry Disable 0: 0: 0: 0: 0: 0: PhyID Invalid 0: Self Node = Not Root 0: Cable Power Status NG 1: Enable Link 1: 1: Reset PHY/Link I/F 1: Ignore BC Packet 1: Ignore BC-Data 1: Single 1: Dual Retry Enable 1: Single Retry Enable 1: 1: 1: 1: 1: 1: PhyID Valid 1: Self Node = Root 1: Cable Power Status OK 0: 0: 1: 1: R/W Maximum Number of certain Priority Arb Request R/W Dual Phase Retry Limit Second Limit R/W R R(W) R B.Rst 0x00 - - - 0 0 0 0 0 0 - - - - - - 0x00 - - 0x00 0x00 0x00 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - 0x3F - 0x3F 0x00 Cycle Limit If (SecLimit == 0 and CycLimit==0) Dual Phase is ignore R/W S.Rst 0: 1: 0: 1: 0: 1: 0: 1: Single Phase Retry Limit Max Retry Count Value If maxRty == 0, Single Phase Retry is ignore 0: Exist IRM Node 0: Other Node 1: None IRM Node 1: Self Node Physical ID of IRM Node No exist IRM Node then IRMID= 0x3F EPSON 29 S1R72801F00A Address 0x20 0x21 Register Name NODE_IDS_H NODE_IDS_L UltraDmaMode 0x22 (Reserved) Bit Symbol 7: BusID[9] 6: BusID[8] 5: BusID[7] 4: BusID[6] 3: BusID[5] 2: BusID[4] 1: BusID[3] 0: BusID[2] 7: BusID[1] 6: BusID[0] 5: PhyID[5] 4: PhyID[4] 3: PhyID[3] 2: PhyID[2] 1: PhyID[1] 0: PhyID[0] R/W Description R/W Serial Bus ID Number Single Bus, Bus ID = 0x3FF Multiple Bus, Bus ID is uniquely specifying R 7: 6: 5: 4: 3: 2: 1: 0: 0x23 (Reserved) 7: 6: 5: 4: 3: 2: 1: 0: 0x24 0x25 0x26 0x27 30 PhyAccCtl_H PhyAccCtl_L PhyRdstat_H PhyRdstat_L 7: RdReq 6: WrReq 5: 4: 3: ReqAdd[3] 2: ReqAdd[2] 1: ReqAdd[1] 0: ReqAdd[0] 7: WrDat[7] 6: WrDAt[6] 5: WrDat[5] 4: WrDat[4] 3: WrDat[3] 2: WrDat[2] 1: WrDat[1] 0: WrDat[0] 7: 6: 5: 4: 3: RdAdd[3] 2: RdAdd[2] 1: RdAdd[1] 0: RdAdd[0] 7: RdDat[7] 6: RdDat[6] 5: RdDat[5] 4: RdDat[4] 3: RdDat[3] 2: RdDat[2] 1: RdDat[1] 0: RdDat[0] R/W R/W H.Rst S.Rst B.Rst 0xFF - 1: 1: 1: 1: 1: 1: 1: 1: 0: 0: 0: 0: 0: 0: 0: 0: 1: 1: 1: 1: 1: 1: 1: 1: 0: Normal 0: Normal 0: 0: 1: PHY Reg Rd Request 1: PHY Reg Wr Request 1: 1: - - 1 1 1 1 1 1 0xFF - 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - Self Node's Physical ID Number 0: 0: 0: 0: 0: 0: 0: 0: - R/W PHY Register Read/Write Request Address R/W PHY Register Write Data 0x00 0x00 - 0: 0: 0: 0: 0x00 0x00 - 0x00 0x00 - 1: 1: 1: 1: R PHY Register Read Address R PHY Register Read Data EPSON S1R72801F00A Address 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F Register Name ChnlIndex ChnlWindow CmprIndex CmprWindow CYCLE_TIME_H CYCLE_TIME_MH CYCLE_TIME_ML CYCLE_TIME_L Bit Symbol 7: 6: 5: 4: 3: Channel Index[3] 2: Channel Index[2] 1: Channel Index[1] 0: Channel Index[0] 7: Channel Window[7] 6: Channel Window[6] 5: Channel Window[5] 4: Channel Window[4] 3: Channel Window[3] 2: Channel Window[2] 1: Channel Window[1] 0: Channel Window[0] 7: 6: 5: 4: 3: Compare Index[3] 2: Compare Index[2] 1: Compare Index[1] 0: Compare Index[0] 7: Compare Window[7] 6: Compare Window[6] 5: Compare Window[5] 4: Compare Window[4] 3: Compare Window[3] 2: Compare Window[2] 1: Compare Window[1] 0: Compare Window[0] 7: Cycle Second[6] 6: Cycle Second[5] 5: Cycle Second[4] 4: Cycle Second[3] 3: Cycle Second[2] 2: Cycle Second[1] 1: Cycle Second[0] 0: Cycle Count[12] 7: Cycle Count[11] 6: Cycle Count[10] 5: Cycle Count[9] 4: Cycle Count[8] 3: Cycle Count[7] 2: Cycle Count[6] 1: Cycle Count[5] 0: Cycle Count[4] R/W Description 0: 0: 0: 0: 1: 1: 1: 1: R/W ISO (Async Stream) Channel Index R/W ISO (Async Stream) Cahnnel Window 0: 0: 0: 0: 1: 1: 1: 1: 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - R/W Compare Address Index R/W Compare Address Window 0x00 0x00 - R/W CYCLE_TIME.second_count 0x00 - - 0x00 - - 0x00 - - 0x00 - - R/W CYCLE_TIME.cycle_count 7: Cycle Count[3] 6: Cycle Count[2] 5: Cycle Count[1] 4: Cycle Count[0] 3: Cycle Offset[11] 2: Cycle Offset[10] 1: Cycle Offset[9] 0: Cycle Offset[8] 7: Cycle Offset[7] 6: Cycle Offset[6] 5: Cycle Offset[5] 4: Cycle Offset[4] 3: Cycle Offset[3] 2: Cycle Offset[2] 1: Cycle Offset[1] 0: Cycle Offset[0] H.Rst S.Rst B.Rst R/W CYCLE_TIME.cycle_offset EPSON 31 S1R72801F00A Address 0x30 0x31 Register Name HwSBP2Ctl HwSBP2Stat UltraDmaMode 0x32 0x33 0x34 0x35 0x36 0x37 32 HwSBP2IntStat HwSBP2Index Bit Symbol R/W 7: PtNotPresent 6: HOSTtoDev 5: FromStream 4: 3: HwSBP2Rst 2: HwSBP2Rsum 1: HwSBP2Pause 0: HwSBP2Start R/W R/W R/W 7: FwPause 6: ErrPause 5: 4: WaitPLReady 3: HwSBP2Exec 2: PTaskExec 1: StTaskExec 0: TranExec 7: SplitTimeOut 6: TxAckedIllegal 5: TxAckMiss 4: BrAbort 3: 2: RxNotRespCmp 1: RxBroadCast 0: RxAckDataErr 7: 6: 5: 4: 3: HwSBP2 Index[3] 2: HwSBP2 Index[2] 1: HwSBP2 Index[1] 0: HwSBP2 Index[0] W W W W R R R R R R R R(W) R(W) R(W) R(W) R(W) R(W) R(W) R/W HwSBP2Window_H 7: HwSBP2 Window[15] 6: HwSBP2 Window[14] 5: HwSBP2 Window[13] 4: HwSBP2 Window[12] 3: HwSBP2 Window[11] 2: HwSBP2 Window[10] 1: HwSBP2 Window[9] 0: HwSBP2 Window[8] R/W Description 1: Not Present 1: Host -> Device 1: FromStream 1: 1: Reset 1: Resume 1: Pause 1: Start 0: Not Firmware Pause 0: Not Error Pause 0: 0: Not Ready 0: Stop 0: Stop 0: Stop 0: Stop 1: FirmWre Pause 1: Error Pause 1: 1: Ready 0x00 1: Execute 1: Execute 1: Execute 1: Execute 0: None 0: None 0: None 0: None 0: 0: None 0: None 0: None 1: SplitTimeOut 1: TxAckedIllegal 1: TxAsyMiss 1: BrAbort 0x00 1: 1: RxNotRespCmp 1: RxBroadCast 1: RxAckDataErr 0: 0: 0: 0: 1: 1: 1: 1: PayloadSize_L 7: Payload Size[15] 6: Payload Size[14] 5: Payload Size[13] 4: Payload Size[12] 3: Payload Size[11] 2: Payload Size[10] 1: Payload Size[9] 0: Payload Size[8] 7: Payload Size[7] 6: Payload Size[6] 5: Payload Size[5] 4: Payload Size[4] 3: Payload Size[3] 2: Payload Size[2] 1: Payload Size[1] 0: Payload Size[0] R/W 0x00 0x00 - 0x00 - 0x00 - 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - HwSBP2 Index HwSBP2 Window HwSBP2Window_L 7: HwSBP2 Window[7] 6: HwSBP2 Window[6] 5: HwSBP2 Window[5] 4: HwSBP2 Window[4] 3: HwSBP2 Window[3] 2: HwSBP2 Window[2] 1: HwSBP2 Window[1] 0: HwSBP2 Window[0] PayloadSize_H H.Rst S.Rst B.Rst 0: Present 0: Host <- Device 0: From PageTable 0: 0: None 0: None 0: None 0: None Set Payload Size (Bytes) If (HwSBP2Ctl.HwSBP2Exec ==0) { Write is valid. } else { Write is invalid. } EPSON S1R72801F00A Address Register Name 0x38 PageTableSize_H 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F Bit Symbol R/W Description 7: Page Table Size[15] 6: Page Table Size[14] 5: Page Table Size[13] 4: Page Table Size[12] If (HwSBP2Ctl.PtNotPresent == 0) { 3: Page Table Size[11] Write:Set PageElement *8 (bytes) 2: Page Table Size[10] Read :Indicate Page Table Size 1: Page Table Size[9] } else { 0: Page Table Size[8] R/W Write:Set Data Length (bytes) PageTableSize_L 7: Page Table Size[7] 6: Page Table Size[6] 5: Page Table Size[5] 4: Page Table Size[4] 3: Page Table Size[3] 2: Page Table Size[2] 1: Page Table Size[1] 0: Page Table Size[0] 0x00 - 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - Read :Indicate Create PageElement *8 (bytes) PageTableAdrs1 7: PtAdress[39] 6: PtAdress[38] 5: PtAdress[37] 4: PtAdress[36] 3: PtAdress[35] 2: PtAdress[34] 1: PtAdress[33] 0: PtAdress[32] PaqeTableAdrs3 7: PtAdress[23] 6: PtAdress[22] 5: PtAdress[21] 4: PtAdress[20] 3: PtAdress[19] 2: PtAdress[18] 1: PtAdress[17] 0: PtAdress[16] 0x00 } PageTableAdrs0 7: PtAdress[47] 6: PtAdress[46] 5: PtAdress[45] 4: PtAdress[44] 3: PtAdress[43] 2: PtAdress[42] 1: PtAdress[41] 0: PtAdress[40] PageTableAdrs2 7: PtAdress[31] 6: PtAdress[30] 5: PtAdress[29] 4: PtAdress[28] 3: PtAdress[27] 2: PtAdress[26] 1: PtAdress[25] 0: PtAdress[24] H.Rst S.Rst B.Rst R/W Write: Set PageTable Offset Address Read: Indicate NextPageTable Offset Address PageTableAdrs4 7: PtAdress[15] 6: PtAdress[14] 5: PtAdress[13] 4: PtAdress[12] 3: PtAdress[11] 2: PtAdress[10] 1: PtAdress[9] 0: PtAdress[8] PageTableAdrs5 7: PtAdress[7] 6: PtAdress[6] 5: PtAdress[5] 4: PtAdress[4] 3: PtAdress[3] 2: PtAdress[2] 1: PtAdress[1] 0: PtAdress[0] EPSON 33 S1R72801F00A Address 0x40 0x41 Register Name LinkRxHdrPtr_H LinkRxHdrPtr_L UltraDmaMode 0x42 0x43 0x44 0x45 0x46 0x47 34 LinkRxORBPtr_H LinkRxORBPtr_L Bit Symbol 7: 6: 5: 4: LRHP[12] 3: LRHP[11] 2: LRHP[10] 1: LRHP[9] 0: LRHP[8] R/W 0x00 - 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - 0x00 0x00 0x00 0x00 Write is ignore Read is always zero R/W Current Received Packet ORB Data Area Pointer Write is ignore Read is always zero LinkRxStreamPtr_H 7: 6: 5: 4: PSP[12] 3: PSP[11] 2: PSP[10] 1: PSP[9] 0: PSP[8] Write is ignore Read is always zero R/W Current Received Packet Stream Data Area Pointer Write is ignore Read is always zero LinkTxStreamPtr_H 7: 6: 5: 4: PTDP[12] 3: PTDP[11] 2: PTDP[10] 1: PTDP[9] 0: PTDP[8] LinkTxStreamPtr_L 7: PTDP[7] 6: PTDP[6] 5: PTDP[5] 4: PTDP[4] 3: PTDP[3] 2: PTDP[2] 1: 0: 0x00 Write is ignore Read is always zero 7: 6: 5: 4: POP[12] 3: POP[11] 2: POP[10] 1: POP[9] 0: POP[8] LinkRxStreamPtr_L 7: PSP[7] 6: PSP[6] 5: PSP[5] 4: PSP[4] 3: PSP[3] 2: PSP[2] 1: 0: H.Rst S.Rst B.Rst R/W Current Received Packet Header Area Pointer 7: LRHP[7] 6: LRHP[6] 5: LRHP[5] 4: 3: 2: 1: 0: 7: POP[7] 6: POP[6] 5: POP[5] 4: POP[4] 3: POP[3] 2: POP[2] 1: 0: Description Write is ignore Read is always zero Write is ignore Read is always zero R Current Transmit Packet Data Area Pointer Write is ignore Read is always zero EPSON S1R72801F00A Address 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F Register Name UsedRxHdrPtr_H UsedRxHdrPtr_L UsedRxORBPtr_H UsedRxORBPtr_L IDE_RxStreamPtr_H IDE_RxStreamPtr_L IDE_TxStreamPtr_H IDE_TxStreamPtr_L Bit Symbol R/W 7: 6: 5: 4: URHP[12] 3: URHP[11] 2: URHP[10] 1: URHP[9] R/W 0: URHP[8] 7: URHP[7] 6: URHP[6] 5: URHP[5] 4: 3: 2: 1: 0: R/W 0x00 - 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - Received Packet Header Area Used Pointer Received Packet ORB Data Area Used Pointer Write is ignore Read is always zero Write is ignore Read is always zero R/W Received Packet Stream Data Area IDE Pointer Write is ignore Read is always zero 7: 6: 5: 4: ITSP[12] 3: ITSP[11] 2: ITSP[10] 1: ITSP[9] 0: ITSP[8] 7: ITSP[7] 6: ITSP[6] 5: ITSP[5] 4: ITSP[4] 3: ITSP[3] 2: ITSP[2] 1: 0: 0x00 Write is ignore Read is always zero 7: 6: 5: 4: IRSP[12] 3: IRSP[11] 2: IRSP[10] 1: IRSP[9] 0: IRSP[8] 7: IRSP[7] 6: IRSP[6] 5: IRSP[5] 4: IRSP[4] 3: IRSP[3] 2: IRSP[2] 1: 0: H.Rst S.Rst B.Rst Write is ignore Read is always zero 7: 6: 5: 4: UOP[12] 3: UOP[11] 2: UOP[10] 1: UOP[9] 0: UOP[8] 7: UOP[7] 6: UOP[6] 5: UOP[5] 4: UOP[4] 3: UOP[3] 2: UOP[2] 1: 0: Description Write is ignore Read always zero Write is ignore Read is always zero R/W Transmit Packet Stream Data Area IDE Pointer Write is ignore Read is always zero EPSON 35 S1R72801F00A Address Register Name 0x50 0x51 BufControl BufMonitor UltraDmaMode 0x52 0x53 0x54 0x55 0x56 0x57 36 AsyDmaCtl IsoDmaCtl RxDmaCtl AreaIndex AreaWindow_H AreaWindow_L Bit Symbol 7: TxStreamClr 6: RxStreamClr 5: RxORBClr 4: RxHdrClr 3: 2: 1: 0: UpdLinkTxStrm 7: RxPayldRdy 6: TxPayldRdy 5: 4: 3: RxHdrRemain 2: RxORBFull 1: RxStreamFull 0: RxHdrFull R/W W W W W W R R R R R R Description 1: Tx Stream Data Clear 1: Rx Stream Data Clear 1: Rx ORB Dat Clear 1: Rx Header Clear 1: 1: 1: 1: Update Link Tx Stream Ptr 0: Rx Payld Capa not Ready 0: Tx Payld Capa not Ready 0: 0: 0: Rx Header Area Empty 0: Rx ORB Area not Full 0: Rx Stream Area not Full 0: Rx Header Area not Full 1: Rx Payload Capa Ready 1: Tx Payload Capa Ready 1: 1: 0x00 1: Rx Header not Empty 1: Rx ORB Data Area Full 1: Rx Stream Data Area Full 1: Rx Header Area Full 7: AsyChnlSel 6: 5: 4: BlkWrAreaSel 3: AsyFIFOEpty 2: AsyFIFOClr 1: AsyTxMon 0: AsyStart R/W 0: AsyTxPktHdr0 0: 0: R/W 0: Rx ORB Area R 0: AsyFIFO Empty W 0: Normal R 0: Async Tx Stop W 0: normal 1: AsyTxPktHdr1 1: 1: 1: Rx Stream Area 1: Non Empty 1: AsyFIFO Clear 1: Async Tx Run 1: Async Start 7: IsoChnlSel 6: 5: 4: SelTxPtr 3: IsoFIFOEpty 2: IsoFIFOClr 1: IsoTxMon 0: IsoStart R/W 0: IsoTxPktHdr0 0: 0: R/W 0: Async Tx Pointer Select R 0: IsoFIFO Empty W 0: Normal R 0: Iso Tx Stop W 0: normal 1: IsoTxPktHdr1 1: 1: 1: ISO Tx Pointer Select 1: Non Empty 1: IsoFIFO Clear 1: Iso Tx Run 1: Start 7: 6: 5: 4: 3: RxFIFOEpty 2: RxFIFOClr 1: RxMon 0: ForceBusy 0: 0: 0: 0: R 0: Rx FIFO Empty W 0: Normal R 0: Rx Stop R/W 0: Normal 1: 1: 1: 1: 1: Non Empty 1: Rx FIFO Clear 1: Rx Run 1: Busy 7: 6: 5: 4: 3: MemMapIndex[3] 2: MemMapIndex[2] 1: MemMapIndex[1] 0: MemMapIndex[0] H.Rst S.Rst B.Rst 0: None Affect 0: None Affect 0: None Affect 0: None Affect 0: 0: 0: 0: None Affect 0: 0: 0: 0: 1: 1: 1: 1: 0x00 0x00 - 0x00 - 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - R/W Memory Map Area Index 7: MemMapWindow[15] 6: MemMapWindow[14] 5: MemMapWindow[13] 4: MemMapWindow[12] 3: MemMapWindow[11] 2: MemMapWindow[10] 1: MemMapWindow[9] 0: MemMapWindow[8] R/W Memory Map Area Window 7: MemMapWindow[7] 6: MemMapWindow[6] 5: MemMapWindow[5] 4: MemMapWindow[4] 3: MemMapWindow[3] 2: MemMapWindow[2] 1: MemMapWindow[1] 0: MemMapWindow[0] EPSON S1R72801F00A Address Register Name 0x58 BRstHdrPtr_H 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F BRstHdrPtr_L Bit Symbol 7: 6: 5: 4: BusResetPtr[12] 3: BusResetPtr[11] 2: BusResetPtr[10] 1: BusResetPtr[9] 0: BusResetPtr[8] R/W R 7: BusResetPtr[7] 6: BusResetPtr[6] 5: BusResetPtr[5] 4: 3: 2: 1: 0: (Reserved) (Reserved) MaintCtl_H MaintCtl_L 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - Write is ignore Read is always zero Write is ignore Read is always zero R Bus Reset ORB-Data Area Pointer This register indicates Address in Rx ORB Data Area when BusRest detected. Write is ignore Read is always zero 0: 0: 0: 0: 0: 0: 0: 0: 1: 1: 1: 1: 1: 1: 1: 1: 7: 6: 5: 4: 3: 2: 1: 0: 0: 0: 0: 0: 0: 0: 0: 0: 1: 1: 1: 1: 1: 1: 1: 1: 0: 0: 0: 0: 0: 0: 0: 0: 1: Add Header CRC Error 1: Add Data CRC Error 1: No Transmit Next Packet 1: Tx Optional AckCode 1: No Transmit AckPacket 1: 1: 1: 7: Ack[7] 6: Ack[6] 5: Ack[5] 4: Ack[4] 3: Ack[3] 2: Ack[2] 1: Ack[1] 0: Ack[0] S.Rst B.Rst Bus Reset Header Area Pointer This register indicates Address in Rx Header Area 7: 6: 5: 4: 3: 2: 1: 0: 7: E_Hcrc 6: E_Dcrc 5: No_Pkt 4: F_Ack 3: N_ack 2: 1: 0: H.Rst when BusRest detected. BRstORBPtr_H 7: 6: 5: 4: BusRstORBPtr[12] 3: BusRstORBPtr[11] 2: BusRstORBPtr[10] 1: BusRstORBPtr[9] 0: BusRstORBPtr[8] BRstORBPtr_L 7: BusRstORBPtr[7] 6: BusRstORBPtr[6] 5: BusRstORBPtr[5] 4: BusRstORBPtr[4] 3: BusRstORBPtr[3] 2: BusRstORBPtr[2] 1: 0: Description Write is ignore Read is always zero R/W R/W R/W R/W R/W R/W Optional AckCode EPSON 37 S1R72801F00A Address 0x60 0x61 Register Name IDE_Config0 IDE_Config1 UltraDmaMode 0x62 0x63 0x64 0x65 0x66 0x67 38 Bit Symbol R/W Description H.Rst S.Rst B.Rst 7: UltraDmaMode 6: DmaMode 5: ActPort 4: IDE_Slave 3: DMARQ_Level 2: Swap 1: 0: 0: DMA Mode 0: PIO Mode 0: None R/W 0: Master 0: Positive Logic 0: Nomal 0: 0: 1: Ultra DMA Mode 1: DMA Mode 1: Active 1: Slave 0x00 1: Negative Logic 1: Swap IDE Port Hi & Lo 1: 1: 7: IDE_Reset 6: 5: 4: 3: 2: 1: 0: R/W R/W 0: None 0: 0: 0: 0: 0: 0: 0: 1: IDE Reset 1: 1: 1: 1: 1: 1: 1: 0x00 - 0x00 - 0x00 - 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - 0x00 IDE_RegAccCyc 7: Assert Pulse[3] 6: Assert Pulse[2] R/W IDE Register Access Strobe Signal Assert Pulse 5: Assert Pulse[1] Width Minimum Value 4: Assert Pulse[0] 0x00 3: Negate Pulse[3] 2: Negate Pulse[2] R/W IDE Register Access Strobe Signal Negate Pulse 1: Negate Pulse[1] Width Minimum Value 0: Negate Pulse[0] IDE_PioDmaCyc 7: Assert Pulse[3] 6: Assert Pulse[2] R/W IDE Transfer Mode Strobe Signal Assert Pulse 5: Assert Pulse[1] Width Minimum Value 4: Assert Pulse[0] 3: Negate Pulse[3] 2: Negate Pulse[2] R/W IDE Transfer Mode Strobe Signal Negate Pulse 1: Negate Pulse[1] Width Minimum Value 0: Negate Pulse[0] IDE_UltraDmaCyc 7: 6: 5: 4: 3: Cycle Time[3] 2: Cycle Time[2] 1: Cycle Time[1] 0: Cycle Time[0] IDE_DmaCtl IDE_BusStat IDE_DmaStat 7: 6: 5: 4: CRC_Clear 3: FIFO_Clear 2: IDE_Abort 1: IDE_Direction 0: DmaStart 7: DMARQ 6: DMACK 5: INTRQ 4: IORDY 3: 2: 1: DIAG 0: DASP 7: 6: 5: 4: 3: 2: 1: DmaPause 0: DmaRun 0: 0: 0: 0: 1: 1: 1: 1: R/W IDE Ultra DMA Transfer Mode Strobe Signal Minimum Cycle Time 0: 0: 0: W 0: None W 0: None W 0: None R/W 0: SRAM -> IDE W 0: None 1: 1: 1: 1: CRC Clear 1: FIFO Clear 1: IDE Transfer Abort 1: IDE -> SRAM 1: IDE DMA Start R Indicate IDE I/F Signals State R W 0: 0: 0: 0: 0: 0: 0: IDE DMA not Pause 0: Not DMA EPSON 1: 1: 1: 1: 1: 1: 1: IDE DMA Pause 1: IDE DMA Running S1R72801F00A Address Register Name Bit Symbol 0x68 IDE_ByteCount0 7: ByteCount[31] 6: ByteCount[30] 5: ByteCount[29] 4: ByteCount[28] 3: ByteCount[27] 2: ByteCount[26] 1: ByteCount[25] 0: ByteCount[24] 0x69 IDE_ByteCount1 7: ByteCount[23] 6: ByteCount[22] 5: ByteCount[21] 4: ByteCount[20] 3: ByteCount[19] 2: ByteCount[18] 1: ByteCount[17] 0: ByteCount[16] 0x6A IDE_ByteCount2 7: ByteCount[15] 6: ByteCount[14] 5: ByteCount[13] 4: ByteCount[12] 3: ByteCount[11] 2: ByteCount[10] 1: ByteCount[9] 0: ByteCount[8] 0x6B IDE_ByteCount3 7: ByteCount[7] 6: ByteCount[6] 5: ByteCount[5] 4: ByteCount[4] 3: ByteCount[3] 2: ByteCount[2] 1: ByteCount[1] 0: ByteCount[0] 0x6C IDE_CRC0 7: CRC[15] 6: CRC[14] 5: CRC[13] 4: CRC[12] 3: CRC[11] 2: CRC[10] 1: CRC[9] 0: CRC[8] 0x6D IDE_CRC1 7: CRC[7] 6: CRC[6] 5: CRC[5] 4: CRC[4] 3: CRC[3] 2: CRC[2] 1: CRC[1] 0: CRC[0] 0x6E IDE_TestIndex 7: 6: 5: 4: 3: 2: 1: 0: 0x6F IDE_TestWindow 7: 6: 5: 4: 3: 2: 1: 0: R/W R/W R Description H.Rst S.Rst B.Rst 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - IDE Data Transfer Byte Count Register Read: Indicate Remain Byte Count Write: Set Total Transfer Byte Count IDE CRC Data Register 0: 0: 0: 0: 0: 0: 0: 0: 1: 1: 1: 1: 1: 1: 1: 1: 0: 0: 0: 0: 0: 0: 0: 0: 1: 1: 1: 1: 1: 1: 1: 1: EPSON 39 S1R72801F00A Address Register Name Bit Symbol 0x70 IDE_CS00 7: 6: 5: 4: 3: 2: 1: 0: 0x71 IDE_CS01 7: 6: 5: 4: 3: 2: UltraDmaMode 1: 0: 0x72 IDE_CS02 7: 6: 5: 4: 3: 2: 1: 0: 0x73 IDE_CS03 7: 6: 5: 4: 3: 2: 1: 0: 0x74 IDE_CS04 7: 6: 5: 4: 3: 2: 1: 0: 0x75 IDE_CS05 7: 6: 5: 4: 3: 2: 1: 0: 0x76 IDE_CS06 7: 6: 5: 4: 3: 2: 1: 0: 0x77 IDE_CS07 7: 6: 5: 4: 3: 2: 1: 0: 40 R/W Description H.Rst S.Rst B.Rst Command Block Register R/W Data Register 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - Command Block Register R/W Read : Error Register Write: Features Register Command Block Register R/W Sector Count Register Command Block Register R/W Sector Number Register or Logical Block Address(LBA) bit 0 - 7 Command Block Register R/W Cylinder Low Register or Logical Block Address(LBA) bit 8 - 15 Command Block Register R/W Cylinder High Register or Logical Block Address(LBA) bit 16 - 23 Command Block Register R/W Device/Head Register 0x00 Logical Block Address(LBA) bit 24 - 27 Command Block Register R/W Read : Status Register 0x00 Write: Command Register EPSON S1R72801F00A Address Register Name Bit Symbol 0x78 IDE_CS10 7: 6: 5: 4: 3: 2: 1: 0: 0x79 IDE_CS11 7: 6: 5: 4: 3: 2: 1: 0: 0x7A IDE_CS12 7: 6: 5: 4: 3: 2: 1: 0: 0x7B IDE_CS13 7: 6: 5: 4: 3: 2: 1: 0: 0x7C IDE_CS14 7: 6: 5: 4: 3: 2: 1: 0: 0x7D IDE_CS15 7: 6: 5: 4: 3: 2: 1: 0: 0x7E IDE_CS16 7: 6: 5: 4: 3: 2: 1: 0: 0x7F IDE_CS17 7: 6: 5: 4: 3: 2: 1: 0: R/W Description H.Rst S.Rst B.Rst Control Block Register R/W Read : Data Bus Hi - Impedance Write: Not Used 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - Control Block Register R/W Read : Data Bus Hi - Impedance Write: Not Used Control Block Register R/W Read : Data Bus Hi - Impedance Write: Not Used Control Block Register R/W Read : Data Bus Hi - Impedance Write: Not Used Control Block Register R/W Read : Data Bus Hi - Impedance Write: Not Used Control Block Register R/W Read : Data Bus Hi - Impedance Write: Not Used Control Block Register R/W Read : Alternate Status Write: Device Control Control Block Register R/W Read : (obsolete) Write: Not Used EPSON 41 S1R72801F00A 8.1.4 Detail Description of Register (The base address of this register is 0x100000.) Address Register Name 0x00 MainIntStat Bit Symbol 7:SubIntStat 6: TxIsoCmp 5: RxDmaCmp 4: TxAsyCmp 3: HwSBP2Cmp 2: IDE_DmaCmp 1: IDE_INTRQ 0: BusReset R/W R(W) R(W) R(W) R(W) R(W) R(W) R(W) R(W) Description 0: None 0: None 0: None 0: None 0: None 0: None 0: None 0: None 1: Sub Interrupt Occurred 1: ISO Pkt Transmit Done 1: Packet Reception 1: AckCode Reception 1: HwSBP2 Process Complete 1: IDE DMA Transmit Complete 1: IDE Interface Interrupt 1: Bas Reset Detected H.Rst S.Rst B.Rst 0x00 0x00 - Main Interrupt Status Register When this IC interrupts the CPU, the CPU first reads this register to handle it, indicating which Interrupt Status Register is a factor of this interrupt. Subsequent to reading this register, the SubIntStat (Bit 7) reads an Interrupt Status Register associated with each bit to confirm which bit is an interrupt source and appropriately handle it. After that, it writes the read value to the Interrupt Status Register to clear the bit. In the case the interrupt factor still remains, however, the bit is not cleared. When one of 7 bits of the TxIsoCmp, RxDmaCmp, TxAsyCmp, HwSBP2Cmp, IDE_DmaCmp, IDE_INTRQ, and BusReset other than above is an interrupt source, this register clears the bit by writing the read value. Note) The bits of this register control the XInt of output pin. Writing to this register negates the XInt once even if the interrupt factor remains, asserting the XInt after a certain period. (Ready for a timer or edge interrupt). Bit7 Sub Interrupt Status When an interrupt factor exists at each bit shown at the SubIntStat Register, this bit becomes "1". Bit 6 Isochronous Packet Transmit Complete When an ISO Packet Transmit is complete, this bit becomes "1". Bit5 Receive Packet DMA Complete When a received packet is written to the Receive Buffer Area, this bit becomes "1". Bit4 Asynchronous Packet Transmit Complete When an Ack packet to an Async Transmit packet is received, this bit becomes "1". The Ack code is written to the footer area of the Transmit Packet Header. Bit 3 HwSBP2 Process Complete When a HwSBP2 processing is complete, this bit becomes "1". Bit2 IDE DMA Transmit Complete When an IDE I/F DMA Transmit is complete, this bit becomes "1". Bit1 IDE Interface Interrupt When the INTRQ signal is asserted to the IDE I/F, this bit becomes "1". Bit0 BusReset Detected When a BusReset signal is detected on the 1394 Serial Bus, this bit becomes "1". When it issues a BusReset, this bit becomes "1" as well. 42 EPSON S1R72801F00A Address Register Name 0x01 SubIntStat Bit Symbol 7: SelfIDdone 6: SelfIDerr 5: HwSBP2Err 4: HwSBP2BRst 3: LinkIntStat1 2: LinkIntStat0 1: PhyIntStat 0: DmaIntStat R/W R(W) R(W) R(W) R(W) R(W) R(W) R(W) R(W) Description 0: None 0: None 0: None 0: None 0: None 0: None 0: None 0: None 1: Self-ID Phase Done 1: Self-ID Packet Error 1: Hw SBP2 Error 1: BusReset in process HwSBP 1: Link1 Interrupt Occurred 1: Link0 Interrupt Occurred 1: PHY Interrupt Occurred 1: Dma Interrupt Occurred H.Rst S.Rst B.Rst 0x00 0x00 - Sub-Interrupt Status Register The value of each bit of this register indicates the status of a corresponding interrupt source. If these bits become "1" when the associated bit of the SubIntEnb Register is "1", this register asserts an interrupt signal to the CPU. The CPU reads this register after receiving the interrupt signal to locate an interrupt source. By writing the read value again, it clears these bits. Subsequent to reading this register, the lower order 4 bits reads the Interrupt Status Register associated with each bit to confirm which bit is an interrupt source and appropriately handle it. After that, it writes the read value to the Interrupt Status Register to clear the bit. In the case that the interrupt factor still remains, however, the bit is not cleared. Bit7 Self Identify Period Complete When a Self ID period finishes, this bit becomes "1". Bit6 Self Identify Packet Error When a Self-ID packet with an error is received during the Self-ID period or when the Self-ID period finishes due to an error, this bit becomes "1". Bit5 HwSBP2Err When an interrupt factor from the HwSBP2 indicated on the HwSBP2IntStat Register exists, this bit becomes "1". Bit4 BusReset in process HwSBP2 When a BusReset occurs in the HwSBP2 processing, this bit becomes "1". Bit3 LINK Core Interrupt Status1 When an interrupt factor from the LINK core indicated on the LinkIntStat1 Register exists, this bit becomes "1". Bit2 LINK Core Interrupt Status0 When an interrupt factor from the LINK core indicated on the LinkIntStat0 Register exists, this bit becomes "1". Bit1 PHY/LINK Interrupt Status When an interrupt factor from the PHY status indicated on the PHYIntStat Register exists, this bit becomes "1". Bit0 LINK DMA Interrupt Status When an interrupt factor exists in the internal DMA operation indicated on the DmaIntStat Register, this bit becomes "1". Address Register Name 0x02 (Reserved) Bit Symbol 7: 6: 5: 4: 3: 2: 1: 0: R/W Description 0: 0: 0: 0: 0: 0: 0: 0: EPSON 1: 1: 1: 1: 1: 1: 1: 1: H.Rst S.Rst B.Rst 0x00 0x00 - 43 S1R72801F00A Address Register Name 0x03 DmaIntStat Bit Symbol 7: 6: TxAsyRtyGo 5: TxAsyBCSent 4: RxDmaFaild 3: TxAsyFaild 2: TxIsoFaild 1: TxAsyBRAbort 0: TxAsyMiss R/W R(W) R(W) R(W) R(W) R(W) R(W) R(W) Description 0: 0: None 0: None 0: None 0: None 0: None 0: None 0: None 1: 1: Async Tx Retry Go 1: AsyncTxBroadcast Sent 1: Rx DMA Failed 1: Async Tx Failed 1: ISO Tx Failed 1: Async Tx BusReset Abort 1: AsyncTxAckCodeMissing H.Rst S.Rst B.Rst 0x00 0x00 - DMA Interrupt Status Register The value of each bit of this register indicates the status of a corresponding interrupt source. If these bits become "H" when the associated bit of the DMAIntEnb Register is "1", this register asserts the interrupt signal to the CPU. The CPU reads this register after receiving the interrupt signal to locate an interrupt source. By writing the read value again, it clears these bits. Bit7 Reserved When a Sub Action Gap is detected in PHY status of PHY/LINK interface, this bit becomes "1". Bit6 Transmit Async Packet Retry Go When an auto retry is performed after transmitting an Async packet and receiving an Ack_busy, this bit becomes "1". Bit5 Transmit Async Broadcast Packet Sent After a transmission of a Broadcast packet of Async or a PHY packet finishes, this bit becomes "1". Bit4 Receive Packet LINK DMA Failed When a received packet cannot be written to the buffer due to the following reasons, this bit becomes "1". 1) DMA was too late. 2) A packet was received when the ForceBusy bit is on. Bit3 Transmit Async Packet LINKDMA Failed When data cannot be transferred from the buffer to the LINK core at the time of Async packet transmission (DMA FIFO is Under Flow), this bit becomes "1". Bit2 Transmit ISO Packet LINKDMA Failed When data cannot be transferred from the buffer to the LINK core at the time of ISO packet transmission (DMA FIFO is Under Flow), this bit becomes "1". Bit 1 Transmit Async Packet BusReset Abort When a Transmit packet is disabled by a BusReset before an Ack packet is returned at the time of Async packet transmission, this bit becomes "1". Bit0 Transmit Async Packet Ack-code Missing When a Ack packet is not returned at the time of Async packet transmission, this bit becomes "1". 44 EPSON S1R72801F00A Address Register Name 0x04 LinkIntStat1 Bit Symbol 7: 6: 5: 4: 3: RxOnTardy 2: RxHcrcErr 1: RxUnkTcode 0: TxRtyExced R/W R(W) R(W) R(W) R(W) Description 0: 0: 0: 0: 0: None 0: None 0: None 0: None 1: 1: 1: 1: 1: Ack_tardy Sent 1: Rx Packet Header CRC Err 1: Rx Packet Tcode Unknown 1: Tx Retry Exceeded H.Rst S.Rst B.Rst 0x00 0x00 - LINK Core Interrupt Status Register 1 The value of each bit of this register indicates the status of a corresponding interrupt source. If these bits become "1" when the associated bit of the LINKIntEnb1 Register is "1", this register asserts the interrupt signal to the CPU. The CPU reads this register after receiving the interrupt signal to locate an interrupt source. By writing the read value again, it clears these bits. Bit7 Reserved Bit6 Reserved Bit5 Reserved Bit4 Reserved Bit3 RxOnTardy When a packet is received when the ChipCtl. SendTardy bit is "1", an Ack_tardy is returned to the party of the other end and this bit becomes "1". Bit2 Receive Packet Header CRC Error When an error exists in the header CRC of a received packet, this bit becomes "1". Bit1 Receive Packet Tcode Unknown When the Tcode in a received packet is invalid, this bit becomes "1". Bit0 transmit Retry Exceeded If a transmit retry fails since the set value of the MaxRetry Register is exceeded when the RetryLimit Register is not zero or the MaxRetry Register is not 0 and this bit becomes "1". EPSON 45 S1R72801F00A Address Register Name 0x05 LinkIntStat0 Bit Symbol R/W 7: UnExpCh 6: DupliCh 5: IsoArbFaild 4: CycTooLong 3: CycOverFlw 2: CycEvent 1: CycLost 0: CycArbFail R(W) R(W) R(W) R(W) R(W) R(W) R(W) R(W) Description 0: None 0: None 0: None 0: None 0: None 0: None 0: None 0: None 1: Unknown Expected Channel 1: DuplicateChannelDetected 1: Iso Arbtration Failed 1: ISO Arbitration Failed 1: Cycle Timer Over Fullow 1: Local Cycle Event Occured 1: Cycle Start Packet Lost 1: CycleStartPkt Arbtration Fail H.Rst S.Rst B.Rst 0x00 0x00 - LINK Core Interrupt Status Register 0 The value of each bit of this register indicates the status of a corresponding interrupt source. If these bits become "1" when the associated bit of the LINKIntEnb0 Register is "1", this register asserts the interrupt signal to the CPU. The CPU reads this register after receiving the interrupt signal to locate an interrupt source. By writing the read value again, it clears these bits. Bit7 Unknown Expected Channel When a packet of ISO channel not set in the CHANNEL_AVAILABLE Register is detected, this bit becomes "1". It is enabled when the WonIRM = "1" of IRM IDStat Register (the self node is IRM). Bit6 DuplicateChannelDetected When a packet of a same channel is detected in the ISO period of 1 cycle, this bit becomes "1". It is enabled when the WonIRM = "1" of IRM IDStat Register (the self node is IRM). Bit5 ISO Arbitration Failed When an ISO packet transmit request is received but a SubAction Gap is detected before it is transmitted, this bit becomes "1". Bit4 ISO Arbitration Failed When a Cycle_START packet is received but a SubAction Gap cannot be detected even after the ISOCHRONOUS_CYCLE_TIME has passed, this bit becomes "1". Bit3 Cycle Timer Over Flow When the CYCLE_TIMER overflows, this bit becomes "1". Bit2 Local Cycle Event Occurred When an local cycle event occurs, this bit becomes "1". Bit1 Cycle Start Packet Lost When the CYCLE_START_PACKET does not exist over two local cycle events, this bit becomes "1". Bit0 CycleStartPkt Arbitration Failed When a CYCLE_START_PACKET cannot be transmitted before the SubActionGap after a local cycle event occurs, this bit becomes "1". This bit is enabled when cmstr = "1". 46 EPSON S1R72801F00A Address Register Name 0x06 PhyIntStat Bit Symbol 7: SubGap 6: ArbGap 5: 4: 3: 2: Phy_int 1: PhyWrDone 0: PhyRdDone R/W Description R(W) 0: None R(W) 0: None 0: 0: 0: R(W) 0: None R(W) 0: None R(W) 0: None 1: Sub Action Gap Detected 1: ArbtrationResetGapDetected 1: 1: 1: 1: PHY Interrupt Detected 1: PHY Register Write Done 1: PHY Register Read Done H.Rst S.Rst B.Rst 0x00 0x00 - PHY Interrupt Status Register The value of each bit of this register indicates the status of a corresponding interrupt source. If these bits become "1" when the associated bit of the PHYIntEnb Register is "1", this register asserts the interrupt signal to the CPU. The CPU reads this register after receiving the interrupt signal to locate an interrupt source. By writing the read value again, it clears these bits. Bit 7 Sub Action Gap Detected When a Transmit Action Gap is detected in the PHY status of the PHY/LINK interface, this bit becomes "1". Bit6 Arbitration Reset Gap Detected When an Arbitration Reset Gap is detected in the PHY status of the PHY/LINK interface, this bit becomes "1". Bit5 Reserved Bit4 Reserved Bit3 Reserved Bit2 PHY/LINK Interface Interrupt Detected When a PHY_Interrupt is detected in the PHY status of the PHY/LINK interface, this bit becomes "1". This status indicates the PHY is put under one of the following. 1) In most instances, a loop is created in the cable topology. 2) Cable power is insufficient. 3) A bias change is detected. Bit1 PHY Register Write Done When the write access of the PHY Register is complete, this bit becomes "1". Bit0 PHY Register Read Done When read data is stored in the PHYRdStat Register at the time of read access of the PHY Register, this bit becomes "1". Address Register Name 0x07 (Reserved) Bit Symbol 7: 6: 5: 4: 3: 2: 1: 0: R/W Description 0: 0: 0: 0: 0: 0: 0: 0: EPSON 1: 1: 1: 1: 1: 1: 1: 1: H.Rst S.Rst B.Rst 0x00 0x00 - 47 S1R72801F00A Address Register Name 0x08 MainIntEnb Bit Symbol R/W 7: EnSubIntStat 6: EnTxIsoCmp 5: EnRxDmaCmp 4: EnTxAsyCmp 3: EnHwSBP2Cmp 2: EnIDE_DmaCmp 1: EnIDE_INTRQ 0: EnBusReset R/W R/W R/W R/W R/W R/W R/W R/W Description 0: Disable 0: Disable 0: Disable 0: Disable 0: Disable 0: Disable 0: Disable 0: Disable 1: Enable 1: Enable 1: Enable 1: Enable 1: Enable 1: Enable 1: Enable 1: Enable H.Rst S.Rst B.Rst 0x00 0x00 - Main Interrupt Enable Flag Register This register enables/disables an interrupt factor of the MainIntStat Register. Setting the corresponding bit to "1" enables an interrupt to the CPU. Address Register Name 0x09 SubIntEnb Bit Symbol R/W 7: EnSelfIDdone 6: EnSelfIDerr 5: EnHwSBP2Err 4: EnHwSBP2BRst 3: EnLinkIntStat1 2: EnLinkIntStat0 1: EnPhyIntStat 0: EnDmaIntStat R/W R/W R/W R/W R/W R/W R/W R/W Description 0: Disable 0: Disable 0: Disable 0: Disable 0: Disable 0: Disable 0: Disable 0: Disable 1: Enable 1: Enable 1: Enable 1: Enable 1: Enable 1: Enable 1: Enable 1: Enable H.Rst S.Rst B.Rst 0x00 0x00 - Sub-Interrupt Enable Flag Register This register enables/disables an interrupt factor of the SubIntStat Register. Setting the corresponding bit to "1" enables an interrupt to the CPU. Address Register Name 0x0A 48 (Reserved) Bit Symbol 7: 6: 5: 4: 3: 2: 1: 0: R/W Description 0: 0: 0: 0: 0: 0: 0: 0: EPSON 1: 1: 1: 1: 1: 1: 1: 1: H.Rst S.Rst B.Rst 0x00 0x00 - S1R72801F00A Address Register Name 0x0B DmaIntEnb Bit Symbol 7: 6: EnTxAsyRtyGo 5: EnTxAsyBCSent 4: EnRxDmaFaild 3: EnTxAsyFaild 2: EnTxIsoFaild 1: EnTxAsyBRAbort 0: EnTxAsyMiss R/W R/W R/W R/W R/W R/W R/W R/W Description 0: 0: Disable 0: Disable 0: Disable 0: Disable 0: Disable 0: Disable 0: Disable 1: 1: Enable 1: Enable 1: Enable 1: Enable 1: Enable 1: Enable 1: Enable H.Rst S.Rst B.Rst 0x00 0x00 - DMA Interrupt Enable Flag Register This register enables/disables an interrupt factor of the DMAIntStat Register. Setting the corresponding bit to "1" enables an interrupt to the CPU. Address Register Name 0x0C LinkIntEnb1 Bit Symbol 7: 6: 5: 4: 3: EnRxOnTardy 2: EnRxHcrcErr 1: EnRxUnkTcode 0: EnTxRtyExced R/W R/W R/W R/W R/W Description 0: 0: 0: 0: 0: Disable 0: Disable 0: Disable 0: Disable 1: 1: 1: 1: 1: Enable 1: Enable 1: Enable 1: Enable H.Rst S.Rst B.Rst 0x00 0x00 - LINK Core Interrupt Enable Flag Register 1 This register enables/disables an interrupt factor of the LINKIntStat1 Register. Setting the corresponding bit to "1" enables an interrupt to the CPU. Address Register Name 0x0D LinkIntEnb0 Bit Symbol 7: EnUnExpCh 6: EnDupliCh 5: EnIsoArbFaild 4: EnCycTooLong 3: EnCycOverFlw 2: EnCycEvent 1: EnCycLost 0: EnCycArbFail R/W R/W R/W R/W R/W R/W R/W R/W R/W Description 0: Disable 0: Disable 0: Disable 0: Disable 0: Disable 0: Disable 0: Disable 0: Disable 1: Enable 1: Enable 1: Enable 1: Enable 1: Enable 1: Enable 1: Enable 1: Enable H.Rst S.Rst B.Rst 0x00 0x00 - LINK Core Interrupt Enable Flag Register 0 This register enables/disables an interrupt factor of the LINKIntStat0 Register. Setting the corresponding bit to "1" enables an interrupt to the CPU. EPSON 49 S1R72801F00A Address Register Name 0x0E PhyIntEnb Bit Symbol 7: EnSubGap 6: EnArbGap 5: 4: 3: 2: EnPhy_int 1: EnPhyWrDone 0: EnPhyRdDone R/W Description R/W 0: Disable R/W 0: Disable 0: 0: 0: R/W 0: Disable R/W 0: Disable R/W 0: Disable 1: Enable 1: Enable 1: 1: 1: 1: Enable 1: Enable 1: Enable H.Rst S.Rst B.Rst 0x00 0x00 - PHY Core Interrupt Enable Flag Register This register enables/disables an interrupt factor of the PHYIntStat Register. Setting the corresponding bit to "1" enables an interrupt to the CPU. Address Register Name 0x0F (Reserved) Address Register Name 0x10 ChipCtl Bit Symbol R/W 7: 6: 5: 4: 3: 2: 1: 0: Description 0: 0: 0: 0: 0: 0: 0: 0: Bit Symbol 7: Suspend 6: 5: 4: 3: 2: IDE_MdlRst 1: SendTardy 0: SoftReset R/W 1: 1: 1: 1: 1: 1: 1: 1: Description R/W 0: Resume 0: 0: 0: 0: W 0: None R/W 0: None W 0: None H.Rst S.Rst B.Rst 0x00 0x00 - H.Rst S.Rst B.Rst 1: Suspend 1: 1: 1: 0x00 1: 1: IDE_Module Reset 1: Send Ack_tardy 1: Reset Start 0x00 - Chip Control Register The Chip Ctl Register controls the internal circuit of a chip. Bit7 Suspend Setting this bit to "1" stops the Sclk supplied from the PHY to this IC. At that time, the LPS signal must be negated as well. When a LINKOn packet is received, the CPU asserts the xINT. After asserting it, the firmware asserts the LPS signal to the PHY and resume it by the Sclk supplied from the PHY. At that time, this bit must be set to "0". Bit6 Reserved Bit5 Reserved Bit4 Reserved Bit3 Reserved Bit2 IDE_MdlRst Setting this bit to "1" resets IDE-related registers (0x60 - 0x7F) to restore them to the initial state. Bit1 Send Ack_tardy Enable Makes setting to return an Ack_tardy as a Ack code when receiving an Async packet. 0: Usual Ack code 1: ack_tardy Bit0 Soft Reset Setting this bit to "1" initializes the interiors of the circuit. After initializing it, it is restored to "0". 50 EPSON S1R72801F00A Address Register Name 0x11 HW_Revision Bit Symbol 7: HW_Revision[7] 6: HW_Revision[6] 5: HW_Revision[5] 4: HW_Revision[4] 3: HW_Revision[3] 2: HW_Revision[2] 1: HW_Revision[1] 0: HW_Revision[0] R/W Description R Indicate Hard Ware Revison Number H.Rst S.Rst B.Rst 0x03 0x03 0x03 Hardware Revision Register The HW_Revision Register indicates the revision number of a chip. Address Register Name 0x18 LinkCtl_H Bit Symbol R/W Description 7: PassSelfID 0: Non PassSelfID 6: PassPhyPkt 0: Non Pass PHY Packet 5: PassBrPkt 0: Non Pass BusRst Packet 4: EnPosWB R/W 0: Disable Posted WB 3: EnPosWQ 0: Disable Poosted WQ 2: APHY 0: PHY 1394.a uncorrespond 1: EnAcc 0: Ack Acceleration Disable 0: Cmstr 0: Cycle Master Not Capabl 1: Self-ID to DMA FIFO 1: PHY Pkt to DMA FIFO 1: BusRst Pkt to DMA FIFO 1: Enable Posted WB 1: Enable Posted WQ 1: PHY 1394.a correspond 1: Ack Acceleration Enable 1: Cycle Master Capable H.Rst S.Rst B.Rst 0x00 0x00 - LINK Core Control Register Higher Rank This register controls the functions of the LINK core. Bit7 Pass Self-ID Packet Setting this bit to "1" captures a Self-ID packet received by the LINK core into the buffer. Bit6 Pass PHY Packet When requesting the PHY Register for a register write, this bit is set to "1". After the execution, this bit is cleared. Bit5 Pass BusReset Packet Setting this bit to "1" captures a BusReset packet received by the LINK core into the buffer. Bit4 Enable Posted Block Write Setting this bit to "1" enables the Posted Write function for a Block Write Request. Bit3 Enable Posted Quadlet Write Setting this bit to "1" enables the Posted Write function for a Quadlet Write Request. Bit2 APHY Indicates whether the PHY conforms to 1394.a or not. 1: Conforms to PHY 1394.a 0: Does not conform to PHY 1394.a Bit1 Enable Ack Acceleration Indicates the setting of Ack Acceleration. 1: Ack Acceleration enable 0: Ack Acceleration disable Bit0 cmstr When the self node is Cycle Master capable and a root, this bit becomes "1". If the self node does not become a root in the Self-ID processing when this bit is set after the Bus Reset, this bit is cleared. EPSON 51 S1R72801F00A Address Register Name 0x19 LinkCtl_L Bit Symbol R/W 7: EnLink 6: 5: PLIFrst 4: IgnrBChdr 3: IgnrBCdata 2: RxBusyMode 1: DualRtyEnb 0: SinglRtyEnb R/W W R/W R/W R/W R/W R/W Description 0: Disable Link 0: 0: None 0: BC Pkt to DMA FIFO 0: BC Data to DMA FIFO 0: Dual 0: Dual Retry Disable 0: Single Retry Disable H.Rst S.Rst B.Rst 1: Enable Link 1: 1: Reset PHY/Link I/F 1: Ignore BC Packet 0x00 1: Ignore BC - Data 1: Single 1: Dual Retry Enable 1: Single Retry Enable - - 0 0 0 0 0 0 - - - - - - - - LINK Core Control Register Lower Rank This register controls the functions of the LINK core. Bit7 Enable LINK Controls whether communications with other nodes are enabled. When this bit is "0", no response is given to a received packet. When it is "1", the transmission/reception of a packet becomes possible. Even if you set the EnLINK to "1" when the LPS bit is "0", it is ignored. Before setting it to "1", set the LPS bit to "1" and wait 10ms. Bit6 Reserved Bit5 PHY/LINK Interface Reset Writing "1" to this bit resets the PHY/LINK interface. After resetting it, this bit is automatically restored to "0". Bit4 Ignore Broadcast Packet Setting this bit to "1" abandons a Broadcast packet received by the LINK core. Bit3 Ignore Broadcast Packet Data Setting this bit to "1" abandons a Broadcast data received by he LINK core. Bit2 Rx Busy Mode Sets a Busy type, the Dual Phase mode or Single Phase mode, for a received packet when returning a Busy. When this is "1", an ack_busy_X is returned. When it is "0", an ack_busy_A or ack_busy_B is returned. Bit1 Dual Phase Retry Enable Controls whether the Dual Phase retry protocol is enabled. When this bit is "1", a retry processing is done until a time set on the Retry Limit Register is exceeded. When it is "0", no retry is done. When the value of the Retry Limit Register is "0", a retry processing is ignored. Bit0 Single Phase Retry Enable Controls whether the Single Phase retry protocol is enabled. When this bit is "1", a retry processing is done until the number set on the Retry Limit Register is exceeded. When it is "0", a retry processing is disabled. When the value of the MaxRetry Register is "0", a retry processing is ignored. Address Register Name 0x1A LinkStart Bit Symbol 7: 6: 5: 4: 3: 2: ID_Valid 1: Root 0: CablPwSts R/W R R R Description 0: 0: 0: 0: 0: 0: PhyID Invalid 0: Self Node =Not Root 0: Cable Power Status NG H.Rst S.Rst B.Rst 1: 1: 1: 1: 0x00 1: 1: PhyID Valid 1: Self Node =Root 1: Cable Power Status OK - - Link Core Status Read Register Bit 7..3 Reserved Bit2 ID_Valid When this bit is set to "1," the Physical_ID of the NodeID register becomes valid, and when this bit is set to "0," the Physical_ID becomes invalid. Bit1 Root This bit is set to "1" when the self node comes to Root in the Self-ID process after the bus is reset. Bit 0 Cable Power Status This bit indicates the status of Cable Power, which is updated in the PHY Status. "1" : Cable Power Status OK "0" : Cable Power Status NG 52 EPSON S1R72801F00A Address Register Name 0x1B PriReqCnt Bit Symbol 7: 6: 5: PriReq[5] 4: PriReq[4] 3: PriReq[3] 2: PriReq[2] 1: PriReq[1] 0: PriReq[0] R/W Description 0: 0: H.Rst S.Rst B.Rst 1: 1: 0x00 R/W 0x00 0x00 Maximum Number of certain Priority Arb Request Priority Request Count Register This register shows registers in the pri-req field shown in the PRIORITY_BUDGET(CSR) register. This register can precede the Priority Request as often as it is set to PriReq in a uniform section. But this register can only be set by the node suitable for the bus manager. Bit7..6 Reserved Bit5..0 pri_req[9:0] This bit is for setting the value of pri_req designated by the bus manager. Any value exceeding the value of pri_max to be packaged with the firmware cannot be set. The value is cleared to zero when a uniform section ends. Address Register Name 0x1C 0x1D RetryLimit_H RetryLimit_L Bit Symbol 7: SecLimit[2] 6: SecLimit[1] 5: SecLimit[0] 4: CycLimt[12] 3: CycLimt[11] 2: CycLimt[10] 1: CycLimt[9] 0: CycLimt[8] 7: CycLimt[7] 6: CycLimt[6] 5: CycLimt[5] 4: CycLimt[4] 3: CycLimt[3] 2: CycLimt[2] 1: CycLimt[1] 0: CycLimt[0] R/W R/W R/W Description H.Rst S.Rst B.Rst Dual Phase Retry Limit Second Limit 0x00 0x00 - 0x00 0x00 - Cycle Limit If (SecLimit == 0 and CycLimit==0) Dual Phase is ignore Dual Retry Time Set Register (Higher Rank, Lower Rank) This register is used for the Dual Phase Retry protocol to set a retransmit retry time limit when an Async Transmit packet is transmitted and a Busy is returned. When this register is "0", the Dual Phase retry is ignored. 0x1C Bit7..5 Second_Limit[2:0] Set a Dual Phase Retry Time (Unit: second). 0x1C, 0x1D Cycle Limit[12:0] Sets a retry time at Cycle Limit [12:0] (Unit: 125s). EPSON 53 S1R72801F00A Address Register Name 0x1E MaxRetry Bit Symbol 7: 6: 5: 4: 3: maxRty[3] 2: maxRty[2] 1: maxRty[1] 0: maxRty[0] R/W R/W Description H.Rst S.Rst B.Rst 0: 1: 0: 1: 0: 1: 0: 1: 0x00 Single Phase Retry Limit Max Retry Count Value If maxRty == 0, Single Phase Retry is ignore 0x00 - Single Retry Limit Set Register This register sets the number of retries of the Single Phase Retry protocol. When its value is "0", the Single Phase Retry is ignored. Bit7..4 Reserved Bit3..0 Single Retry Limit[3:0] Sets the number of retries in the Single Phase at maxRtry[3:0] Address Register Name 0x1F IRM_Stat Bit Symbol 7: NoIRM 6: WonIRM 5: IRMID[5] 4: IRMID[4] 3: IRMID[3] 2: IRMID[2] 1: IRMID[1] 0: IRMID[0] R/W Description R 0: Exist IRM Node R(W) 0: Other Node R H.Rst S.Rst B.Rst 1: None IRM Node 1: Self Node Physical ID of IRM Node No exist IRM Node then IRMID=0x3F 0x3F - 0x3F IRM Status Register This IRM Status Register controls detection of the Isochronous Resource Manager. Bit7 No IRM Sets whether an Isochronous Resource Manager exists on the serial bus. "1" indicates the IRM node does not exist and "0" indicates the IRM node exists. Bit6 WonIRM Sets whether the Isochronous Resource Manager is self node or other node. "1" indicates it is the self node and "0" indicates it is other node. Usually, this bit is read-only. When a valid IRM is not detectable due to hardware bugs, however, the firmware sets this bit through a Self-ID packet or topology map. Bit5..0 IRM ID[5:0] When the EnLrmDetect bit is "1", the node ID of the Isochronous Resource Manager detected in the Self-ID period is set. When no node corresponding to the IRM exists, it indicates the 0x3F value. 54 EPSON S1R72801F00A Address Register Name 0x20 0x21 NODE_IDS_H NODE_IDS_L UltraDmaMode Bit Symbol 7: BusID[9] 6: BusID[8] 5: BusID[7] 4: BusID[6] 3: BusID[5] 2: BusID[4] 1: BusID[3] 0: BusID[2] 7: BusID[1] 6: BusID[0] 5: PhyID[5] 4: PhyID[4] 3: PhyID[3] 2: PhyID[2] 1: PhyID[1] 0: PhyID[0] R/W R/W Description Serial Bus ID Number Single Bus, Bus ID = 0x3FF Multiple Bus, Bus ID is uniquely specifying H.Rst S.Rst B.Rst 0xFF 0xFF R - - Self Node's Physical ID Number - - - 1 1 1 1 1 1 Node IDS Status Register (Higher Rank, Lower Rank) This register indicates the bus ID of topology connected through the serial bus. At the time of BusReset, the BusID does not change. When the self node is a bus manager, this register is writable. If you write when it is not a bus manager, the bus goes out of control. Never write when it is not a bus manager. The PHY ID becomes a value of the 0x3F at the time of BusReset and is automatically stored on completion of the Self-ID processing. 0x20, 0x21 .Bit7..6 Bus ID These bits are areas to store the Bus_ID value of the serial bus. 0x21 Bit5:0 PHY ID Indicates the Physical ID of a node established by the PHY in the Self-ID phase. Address Register Name 0x24 PhyAccCtl_H Bit Symbol 7: RdReq 6: WrReq 5: 4: 3: ReqAdd[3] 2: ReqAdd[2] 1: ReqAdd[1] 0: ReqAdd[0] R/W R/W R/W R/W Description 0: Normal 0: Normal 0: 0: 1: PHY Reg Rd Request 1: PHY Reg Wr Request 1: 1: H.Rst S.Rst B.Rst 0x00 0x00 - PHY Register Read/Write Request Address PHY Register Access Control Register (Higher Rank) Bit7 PHY Register Read Request When requesting the PHY Register for a register read, this bit is set to "1". After the execution, it is automatically cleared. Bit6 PHY Register Write Request When requesting the PHY Register for a register write, this bit is set to "1". After the execution, it is automatically cleared. Bit5 Reserved Bit4 Reserved Bit3..0 PHY Access Register Set a register address to access the PHY Register. EPSON 55 S1R72801F00A Address Register Name 0x25 PhyAccCtl_L Bit Symbol 7: WrDat[7] 6: WrDAt[6] 5: WrDat[5] 4: WrDat[4] 3: WrDat[3] 2: WrDat[2] 1: WrDat[1] 0: WrDat[0] R/W R/W Description PHY Register Write Data H.Rst S.Rst B.Rst 0x00 0x00 - PHY Register Access Control Register (Lower Rank) Bit7..0 PHY Write Data Set data to write to the PHY Register. Address Register Name 0x26 PhyRdstat_H Bit Symbol 7: 6: 5: 4: 3: RdAdd[3] 2: RdAdd[2] 1: RdAdd[1] 0: RdAdd[0] R/W Description 0: 0: 0: 0: R 1: 1: 1: 1: H.Rst S.Rst B.Rst 0x00 0x00 - PHY Register Read Address PHY Register Read Status Register (Higher Rank) Bit7 Reserved Bit6 Reserved Bit5 Reserved Bit4 Reserved Bit3..0 PHY Read Address Indicate a register address indicated in the PHY status. Address Register Name 0x27 PhyRdstat_L Bit Symbol 7: RdDat[7] 6: RdDat[6] 5: RdDat[5] 4: RdDat[4] 3: RdDat[3] 2: RdDat[2] 1: RdDat[1] 0: RdDat[0] R/W R Description PHY Register Read Data PHY Register Read Status Register (Lower Rank) Bit7..0 PHY Read Data Indicate register data indicated in the PHY status. 56 EPSON H.Rst S.Rst B.Rst 0x00 0x00 - S1R72801F00A Address Register Name 0x28 0x29 ChnlIndex ChnlWindow Bit Symbol 7: 6: 5: 4: 3: Channel Index[3] 2: Channel Index[2] 1: Channel Index[1] 0: Channel Index[0] 7: Channel Window[7] 6: Channel Window[6] 5: Channel Window[5] 4: Channel Window[4] 3: Channel Window[3] 2: Channel Window[2] 1: Channel Window[1] 0: Channel Window[0] R/W Description 0: 0: 0: 0: H.Rst S.Rst B.Rst 1: 1: 1: 1: R/W ISO (Async Stream) Channel Index R/W ISO (Async Stream) Cahnnel Window 0x00 0x00 - 0x00 0x00 - ISO-Asyno Stream Channel Index Window Register This register selects an ISO channel and Async Stream channel. The Channel Available Register is available when the Isochronous Resource Manager is used. 0x28 Channel Index Sets an index number to select a channel. 0x29 Channel Window Indicates a window specified by the Channel Index. ChnlIndex ChnlWindow bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ch01 ch02 ch03 ch04 ch05 ch06 ch07 0x00 ChannelAvailableH0 0x01 ChannelAvailableH1 ch08 ch09 ch10 ch11 ch12 ch13 ch14 ch15 0x02 ChannelAvailableH2 ch16 ch17 ch18 ch19 ch20 ch21 ch22 ch23 0x03 ChannelAvailableH3 ch24 ch25 ch26 ch27 ch28 ch29 ch30 ch31 0x04 ChannelAvailableL0 ch32 ch33 ch34 ch35 ch36 ch37 ch38 ch39 0x05 ChannelAvailableL1 ch40 ch41 ch42 ch43 ch44 ch45 ch46 ch47 0x06 ChannelAvailableL2 ch48 ch49 ch50 ch51 ch52 ch53 ch54 ch55 0x07 ChannelAvailableL3 ch56 ch57 ch58 ch59 ch60 ch61 ch62 ch63 0x08 ReceiveChannel0 ch00 ch01 ch02 ch03 ch04 ch05 ch06 ch07 0x09 ReceiveChannel1 ch08 ch09 ch10 ch11 ch12 ch13 ch14 ch15 0x0A ReceiveChannel2 ch16 ch17 ch18 ch19 ch20 ch21 ch22 ch23 0x0B ReceiveChannel3 ch24 ch25 ch26 ch27 ch28 ch29 ch30 ch31 0x0C ReceiveChannel4 ch32 ch33 ch34 ch35 ch36 ch37 ch38 ch39 0x0D ReceiveChannel5 ch40 ch41 ch42 ch43 ch44 ch45 ch46 ch47 0x0E ReceiveChannel6 ch48 ch49 ch50 ch51 ch52 ch53 ch54 ch55 0x0F ReceiveChannel7 ch56 ch57 ch58 ch59 ch60 ch61 ch62 ch63 ChannelAvailable This is a register to provide a channel number resource to be used when transferring isochronous and asynchronous stream. ReceiveChannel This is a register to set an ISO channel number to be received by this IC. EPSON 57 S1R72801F00A Address Register Name 0x2A 0x2B CmprIndex CmprWindow Bit Symbol 7: 6: 5: 4: 3: Compare Index[3] 2: Compare Index[2] 1: Compare Index[1] 0: Compare Index[0] 7: Compare Window[7] 6: Compare Window[6] 5: Compare Window[5] 4: Compare Window[4] 3: Compare Window[3] 2: Compare Window[2] 1: Compare Window[1] 0: Compare Window[0] R/W Description 0: 0: 0: 0: H.Rst S.Rst B.Rst 1: 1: 1: 1: R/W Compare Address Index R/W Compare Address Window 0x00 0x00 - 0x00 0x00 - Compare Offset Address Index Window Register This register sets a compare offset address. When the BlkWrAreaSet bit is "1" and a BlockWriteRequest packet having an Destination_Offset address same as a value set to this register is received, the received data of payload is received by the RxStreamArea. 0x2A Compare Index This is a register to set an index number to select a channel. 0x2B Compare Window This is a register to view a window specified by the Compare Index. Compare Address Index/Window Register ChnlIndex ChnlWindow bit7 0x00 CompareDOffset0 (MSB) 0x01 CompareDOffset1 0x02 CompareDOffset2 0x03 CompareDOffset3 0x04 CompareDOffset4 0x05 CompareDOffset5 0x06 (Reserved) : (Reserved) 0x0F (Reserved) bit6 bit5 bit4 bit3 bit2 bit1 bit0 Compare Destination Offset Address[47:0] (LSB) Compare Destination Offset Address When the BlkWrAreaSet bit is "1" and a BlockWriteRequest packet having an Destination_Offset address same as a value set to this register is received, the received data of payload is received by the RxStreamArea. This address is valid when the BlkWrAreaSel bit of the AsyDmaCtl Register is "1". 58 EPSON S1R72801F00A Address 0x2C 0x2D 0x2E 0x2F Register Name CYCLE_TIME_H CYCLE_TIME_MH CYCLE_TIME_ML CYCLE_TIME_L Bit Symbol 7: Cycle Second[6] 6: Cycle Second[5] 5: Cycle Second[4] 4: Cycle Second[3] 3: Cycle Second[2] 2: Cycle Second[1] 1: Cycle Second[0] 0: Cycle Count[12] 7: Cycle Count[11] 6: Cycle Count[10] 5: Cycle Count[9] 4: Cycle Count[8] 3: Cycle Count[7] 2: Cycle Count[6] 1: Cycle Count[5] 0: Cycle Count[4] R/W R/W R/W Description CYCLE_TIME.second_count R/W 0x00 - - 0x00 - - 0x00 - - 0x00 - - CYCLE_TIME.cycle_count 7: Cycle Count[3] 6: Cycle Count[2] 5: Cycle Count[1] 4: Cycle Count[0] 3: Cycle Offset[11] 2: Cycle Offset[10] 1: Cycle Offset[9] 0: Cycle Offset8[] 7: Cycle Offset[7] 6: Cycle Offset[6] 5: Cycle Offset[5] 4: Cycle Offset[4] 3: Cycle Offset[3] 2: Cycle Offset[2] 1: Cycle Offset[1] 0: Cycle Offset[0] H.Rst S.Rst B.Rst CYCLE_TIME.cycle_offset Cycle Time Register Each of CycSecond, CycCount, and CycOffset Registers updates the timer by updating the current value of the cycle timer used for isochronous transfer. When the self node is a CYCLE MASTER, set the value of each register in the CYCLE START PACKET. When the self node is not a CYCLE MASTER, set the cycle_time_data of a received CYCLE START PACKET on each register. This register is enabled when LINKCtl(Hi). DisCycTimer="0". Reserve this register as a CycSecond(Hi) for WORD access. CYCLE_TIME.second_count This bit field indicates an integer at the place of Second of the cycle timer. It is enabled when the LINKCtl(H).DisCycTimer= "0" and the Cycle Second is incremented every time the CycleCount reaches 8000. When the Cycle Second exceeds 127, it is restored to 0. CYCLE_TIME.cycle_count When the self node is a CYCLE MASTER and the DisCycTimer="0", it is incremented every time the Cycle Offset reached 3072. When the Cycle Count reaches 8000, it is restored to 0. CYCLE_TIME. cycle.offset When the self node is a CYCLE TIMER and the DisCycTimer="0", it is incremented in a cycle of 24.576MHz. When the Cycle Offset reaches 3072, it is restored to 0 and then the Cycle Count is incremented. EPSON 59 S1R72801F00A Address Register Name 0x30 HwSBP2Ctl Bit Symbol R/W 7: PtNotPresent 6: HOSTtoDev 5: FromStream 4: 3: HwSBP2Rst 2: HwSBP2Rsum 1: HwSBP2Pause 0: HwSBP2Start R/W R/W R/W W W W W Description 0: Present 0: Host <- Device 0: From PageTable 0: 0: None 0: None 0: None 0: None 1: Not Present 1: Host -> Device 1: FromStream 1: 1: Reset 1: Resume 1: Pause 1: Start Hardware SBP2 Control Register This register controls the SBP2 processing of this IC. Bit7 UltraDmaMode PtNotPresent:0 (Present) Set => PageTable exists. PtNotPresent:1 (Not Present) Set => PageTable does not exist. Bit6 HOSTtoDev HOSTtoDev:0 (Host<-Device) Set => Transfers data from Device to Host. HOSTtoDev:1 (Host->Device) Set => Transfers data from Host to Device. Bit5 FromStream FromStream:0 (FromPt) Set => Starts with the PageTable Processing. FromStream:1 (FromStream) Set => Starts with the Stream processing. Bit4 Reserved Bit3 HwSBP2Rst SBP2Reset:1 (Reset) Set => Resets the hwSBP2. If you read it, it indicates 0. Bit2 HwSBP2Rsum SBP2Resume:1 (Reset) Set => Resumes the hwSBP2 processing in pause. If you read it, it indicates 0. Bit1 HwSBP2Pause SBP2Pause:1 (Pause) Set => Pauses the hwSBP2 processing in execution. If you read it, it indicates 0. Bit0 HwSBP2Start SBP2Start:1 (Start) Set => Starts the hWSBP2 processing. If you read it, it indicates 0. 60 EPSON H.Rst S.Rst B.Rst 0x00 0x00 - S1R72801F00A Address Register Name 0x31 HwSBP2Stat Bit Symbol R/W 7: FwPause 6: ErrPause 5: 4: WaitPLReady 3: HwSBP2Exec 2: PTaskExec 1: StTaskExec 0: TranExec R R R R R R R Description 0: Not Firmware Pause 0: Not Error Pause 0: 0: Not Ready 0: Stop 0: Stop 0: Stop 0: Stop 1: FirmWre Pause 1: Error Pause 1: 1: Ready 1: Execute 1: Execute 1: Execute 1: Execute H.Rst S.Rst B.Rst 0x00 0x00 - Hardware SBP2 Status Read Register This register indicates the execution condition of the hardware SBP2. Bit7 F/W Pause When the firmware writes "1" at the HwSBP2Ctl. HwSBP2Pause bit during the execution of the HwSBP2Pause:1 (Pause) HwSBP2, this bit becomes "1". When the firmware writes "1" at the HwSBP2Ctl.HwSBP2Rsum bit or resets it, it is cleared. Writing to this bit is ignored. Bit6 Error Pause When firmware enters the pause state without writing "1" at the HwSBP2Ctl.HwSBP2Pause bit during the execution of the HwSBP2Pause:1 (Pause) HwSBP2, this bit becomes "1". It is cleared at the time of Reset. Writing to this bit is ignored. Bit5 Reserved Bit4 Wait Payload Ready * WaitPLReady:0 (Not Ready) => Payload Domain Not Ready * WaitPLReady:1 (Ready) => Payload Domain Ready When the IDE interface has a problem, the payload may not be ready. At that time, perform a recovery processing by the firmware. Bit3 HwSBP2Exec * HwSBP2Exec:0 (Stop) => Indicates the HwSBP2 processing is completed. * HwSBP2Exec:1 (Execute) => Indicates the HwSBP2 processing is in execution. It is cleared at the time of Reset. Writing to this bit is ignored.. Bit2 PageTaskExec * PageTaskExec:0 (Stop) => Indicates a PageTask is completed. * PageTaskExec:1 (Execute) => Indicates a PageTask is in execution. It is cleared at the time of Reset. Writing to this bit is ignored.. Bit1 StreamTaskExec * StreamTaskExec:0 (Stop) => Indicates a StreamTask is completed. * StreamTaskExec:1 (Execute) => Indicates a StreamTask is in execution. It is cleared at the time of Reset. Writing to this bit is ignored.. Bit0 TranExec. * TranExec:0 (Stop) => Indicates a Transaction is completed. * TranExec:1 (Execute) => Indicates a Transaction is in execution. It is cleared at the time of Reset. Writing to this bit is ignored.. EPSON 61 S1R72801F00A Address Register Name 0x32 Bit Symbol HwSBP2IntStat 7: SplitTimeOut 6: TxAckedIllegal 5: TxAckMiss 4: BrAbort 3: 2: RxNotRespCmp 1: RxBroadCast 0: RxAckDataErr R/W Description R(W) R(W) R(W) R(W) 0: None 0: None 0: None 0: None 0: R(W) 0: None R(W) 0: None R(W) 0: None 1: SplitTimeOut 1: TxAckedIllegal 1: TxAsyMiss 1: BrAbort 1: 1: RxNotRespCmp 1: RxBroadCast 1: RxAckDataErr H.Rst S.Rst B.Rst 0x00 0x00 - Hardware SBP2 Interrupt Status Register This register indicates error information when an error arises in execution of the hardware SBP2 processing. At the same time, it asserts the HwSBP2Err bit of the SubIntStat Register. When clearing it, write "1" to a bit to clear. This register is automatically cleared when setting HwSBP2Ctl.HwSBP2Start or the HWSBP2Ctl. HwSBP2Rst. Bit7 Split Timeout * SplitTimeOut:1 => During the HwSBP2 processing, an SPLIT TIMEOUT error arose. Bit6 Tx Acked Illegal TxAckedIllegal:1 => Though a transmission was completed, a response other than ack_pending was given to a BlkRdReq and a response other than ack_completed was given to a BlkWrReq. Bit5 Tx Ack Miss * TxAsyMiss:1 => Though a transmission was completed, no Ack was returned. Bit4 BRAbort * When the HwSBP2Ctl.HwSBP2Start bit is set to "1" or HWSBP2Ctl.Resume bit is set to "1" during the BusReset period, this bit becomes "1", Bit3 Reserved Bit2 RxNotRespCmp * RxNotRespCmp:1 => Though a response packet receive was completed, its code was other than resp_complete. Bit1 RxBroadcast * RxBroadCast:1 => Though a response packet receive was completed, it was a broadcast packet. Bit0 RxAckDataError * RxAckDataErr:1 => Though a response packet was received, it was a DataCRCError. It does not assert the interrupt signal SBP2Err. It is automatically cleared on completion of the Transaction. 62 EPSON S1R72801F00A Address 0x33 0x34 0x35 Register Name HwSBP2Index Bit Symbol R/W 7: 6: 5: 4: 3: HwSBP2 Index[3] 2: HwSBP2 Index[2] 1: HwSBP2 Index[1] 0: HwSBP2 Index[0] R/W HwSBP2Window_H 7: HwSBP2 Window[15] 6: HwSBP2 Window[14] 5: HwSBP2 Window[13] 4: HwSBP2 Window[12] 3: HwSBP2 Window[11] 2: HwSBP2 Window[10] 1: HwSBP2 Window[9] 0: HwSBP2 Window[8] HwSBP2Window_L Description 0: 0: 0: 0: R/W 1: 1: 1: 1: H.Rst S.Rst B.Rst 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - HwSBP2 Index HwSBP2 Window 7: HwSBP2 Window[7] 6: HwSBP2 Window[6] 5: HwSBP2 Window[5] 4: HwSBP2 Window[4] 3: HwSBP2 Window[3] 2: HwSBP2 Window[2] 1: HwSBP2 Window[1] 0: HwSBP2 Window[0] Hardware SBP2 Index Window Register This register functions as an Index Register and Window Register to set a register to use for the HwSBP2 processing. HwSBP2Index This register sets an index number to select a channel. HwSBP2Window This register indicates a window specified by the HwSBP2Index. EPSON 63 S1R72801F00A H/W SBP2 Index Chnnel/Window Register SBP2Index SBP2Window_H/L 0x00 bit7 bit6 bit5 bit4 PageBoundary PgElmentRemain_H bit2 bit1 PageElementNumber[4:0] (MSB) Page Element Remain Length (Bytes) PgElmentRemain_L 0x02 (LSB) SpeedCode SpeedCode[2:0] MaxPayload 0x03 DestinationID_H MaxPayload[3:0] (MSB) DestinationID_L 0x04 SplitTime_H SplitTime_L 0x05 (Reserved) : (Reserved) 0x0F (Reserved) bit0 PageBoundary[2:0] PageElementNunber 0x01 bit3 Destination_ID Value Second[2:0] (LSB) Cycle Count[12:8] Cycle Count[7:0] PageBoundary Set a value of page boundary to use for the HwSBP2. The actual page boundary is as follows. PageBoundary =2 (PageBoundary +8) Bytes PageElementNumber Sets a page element number with which the HwSBP2 starts a processing. When the HwSBP2Ctl.PtPresent:1, set a value equal to or less. than 0x17 When the HwSBP2Ctl.PtPresent:0, set a value equal to or less than 0x02. If you read it, the page element number currently in process is indicated. PgElementRemain Indicates the number of remaining data bytes of the page element currently being processed by the HwSBP2. This register is read-only. SpeedCode Sets the speed code of 1394 bus to be used for data transfer by the HwSBP2. SpeedCode:0 100Mbps SpeedCode:1 200Mbps SpeedCode:2 400Mbps SpeedCode:3 Reserved MaxPayload Sets the max. payload value to be used by the HwSBP2. The actual payload size is as follows. Payload = 2 (MaxPayload+2) Bytes Since the max. payload size transferable at 400Mbps is 2048 bytes, set "9" or less for this register. Destination_ID This is a register to set a transmit destination of the HwSBP2. Set a Bus ID (10 bits) and Node ID (6 bits). SplitTime Set a split timeout time of a transaction of the HwSBP2. SplitTime.Second: Set a value in second. SplitTime.CycleCount: Set a value in 125s. (Set range: 0 to 0x1F3F) Setting of a value exceeding 0x1F3F is not possible. 64 EPSON S1R72801F00A Address Register Name 0x36 0x37 Bit Symbol PayloadSize_H 7: 6: 5: 4: 3: Payload Size[11] 2: Payload Size[10] 1: Payload Size[9] 0: Payload Size[8] PayloadSize_L R/W Description H.Rst S.Rst B.Rst 0x00 0x00 - 0x00 0x00 - Set Payload Size (Bytes) If (HwSBP2Ctl.HwSBP2Exec ==0) { Write is valid. } else { R/W 7: Payload Size[7] 6: Payload Size[6] 5: Payload Size[5] 4: Payload Size[4] 3: Payload Size[3] 2: Payload Size[2] 1: Payload Size[1] 0: Payload Size[0] Write is invalid. } Hardware SBP2 Payload Size Set Register Set this register when the firmware handles data to a StreamArea to be used by the HwSBP2. When the HwSBP2Stat.Exec.:"1" (in execution of HwSBP2), writing to this register is ignored. When the RxStreamArea receives data the equivalent of this size, the BufMoniter.RxPayldRdy bit becomes "1". If free space the equivalent of a size set here exists in the TxStreamArea, the BufMoniter. TxPayldRdy bit becomes "1". Payload Size [11:0] Set a payload size to use for data transfer in byte. The settable size is 2^n (n:2 to 11) bytes. Address Register Name 0x38 0x39 Bit Symbol R/W PageTableSize_H 7: Page Table Size[15] 6: Page Table Size[14] 5: Page Table Size[13] 4: Page Table Size[12] 3: Page Table Size[11] 2: Page Table Size[10] 1: Page Table Size[9] 0: Page Table Size[8] R/W PageTableSize_L 7: Page Table Size[7] 6: Page Table Size[6] 5: Page Table Size[5] 4: Page Table Size[4] 3: Page Table Size[3] 2: Page Table Size[2] 1: Page Table Size[1] 0: Page Table Size[0] Description If (HwSBP2Ctl.PtNotPresent == 0) { Write:Set PageElement *8 (bytes) Read :Indicate Page Table Size } else { Write:Set Data Length (bytes) H.Rst S.Rst B.Rst 0x00 0x00 - 0x00 0x00 - Read :Indicate Create PageElement *8 (bytes) } Hardware Page Table Size Set Register The Write and Read of this register have different meanings depending on whether a PageTable is present (setting of HwSBP2Ctl.PtNotPresent bit). * When a PageTable is present Write: Set a PageTable size in byte. (The number of pages x 8 bytes) Read: Indicates the remaining PageTable size. * When a PageTable is not present Write: Set a data length. Read: Indicates a new PageTable size based on the written data size. (The number of pages x 8 bytes) When it is not written, zero can be read if the HwSBP2 correctly finishes. The remaining table size can be read when it is in execution or it finishes incorrectly. EPSON 65 S1R72801F00A Address Register Name 0x3A PageTableAdrs0 0x3B 0x3C 0x3D 0x3E 0x3F PageTableAdrs1 PageTableAdrs2 PaqeTableAdrs3 PageTableAdrs4 PageTableAdrs5 Bit Symbol 7: PtAdress[47] 6: PtAdress[46] 5: PtAdress[45] 4: PtAdress[44] 3: PtAdress[43] 2: PtAdress[42] 1: PtAdress[41] 0: PtAdress[40] R/W Description 7: PtAdress[39] 6: PtAdress[38] 5: PtAdress[37] 4: PtAdress[36] 3: PtAdress[35] 2: PtAdress[34] 1: PtAdress[33] 0: PtAdress[32] 7: PtAdress[31] 6: PtAdress[30] 5: PtAdress[29] 4: PtAdress[28] 3: PtAdress[27] 2: PtAdress[26] 1: PtAdress[25] 0: PtAdress[24] 7: PtAdress[23] 6: PtAdress[22] 5: PtAdress[21] 4: PtAdress[20] 3: PtAdress[19] 2: PtAdress[18] 1: PtAdress[17] 0: PtAdress[16] H.Rst S.Rst B.Rst 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - R/W Write: Set PageTable Offset Address Read: Indicate NextPageTable Offset Address 7: PtAdress[15] 6: PtAdress[14] 5: PtAdress[13] 4: PtAdress[12] 3: PtAdress[11] 2: PtAdress[10] 1: PtAdress[9] 0: PtAdress[8] 7: PtAdress[7] 6: PtAdress[6] 5: PtAdress[5] 4: PtAdress[4] 3: PtAdress[3] 2: PtAdress[2] 1: PtAdress[1] 0: PtAdress[0] Hardware SBP2 Page Table Address Set Register This register specifies an address specified by the ORB of the SBP2. It is automatically updated in execution of the HwSBP2. Page Table Offset Address Write: Sets a Destination_Offset_Address accessed by the HwSBP2. It is ignored in execution of the HwSBP2. Read: Indicates the PageTable address following one being processed by the HwSBP2. 66 EPSON S1R72801F00A Address Register Name 0x40 0x41 Bit Symbol LinkRxHdrPtr_H 7: 6: 5: 4: LRHP[12] 3: LRHP[11] 2: LRHP[10] 1: LRHP[9] 0: LRHP[8] R/W Description H.Rst S.Rst B.Rst Write is ignore Read is always zero R/W LinkRxHdrPtr_L 7: LRHP[7] 6: LRHP[6] 5: LRHP[5] 4: 3: 2: UltraDmaMode 1: 0: 0x00 0x00 - 0x00 0x00 - Current Received Packet Header Area Pointer Write is ignore Read is always zero Receive Header LINK Pointer Register This Receive Header LINK Pointer Register indicates the starting address of the latest receive packet in the RxHeaderArea. Since the buffer pointer is given in 8Quadlet unit, the lower order 5 bits are always "0". Also, since the buffer size is 2 Kbytes, the higher order 3 bits are always "0". Reading the higher order bytes holds the lower order bytes. When writing to this register, write the higher order bytes-lower order bytes in order. (With timing of writing to the lower order bytes, the register is updated.) Address Register Name Bit Symbol 0x42 LinkRxORBPtr_H 7: 6: 5: 4: POP[12] 3: POP[11] 2: POP[10] 1: POP[9] 0: POP[8] 0x43 LinkRxORBPtr_L 7: POP[7] 6: POP[6] 5: POP[5] 4: POP[4] 3: POP[3] 2: POP[2] 1: 0: R/W Description H.Rst S.Rst B.Rst Write is ignore Read is always zero R/W 0x00 0x00 - 0x00 0x00 - Current Received Packet ORB Data Area Pointer Write is ignore Read is always zero Receive ORB Data LINK Pointer Register This Receive ORB Data LINK Pointer Register indicates the starting address of the latest receive ORB data in the RxORBdataArea. Since the buffer pointer is in Quadlet unit, the lower order 2 bits are always "0". Also, since the buffer size is 2 Kbytes, the higher order 3 bits are always "0". Reading the higher order bytes holds the lower order bytes. When writing to this register, write the higher order bytes and lower order bytes in order. (With timing of writing to the lower order bytes, the register is updated.) EPSON 67 S1R72801F00A Address 0x44 0x45 Register Name Bit Symbol R/W LinkRxStreamPtr_H 7: 6: 5: 4: PSP[12] 3: PSP[11] 2: PSP[10] 1: PSP[9] 0: PSP[8] LinkRxStreamPtr_L 7: PSP[7] 6: PSP[6] 5: PSP[5] 4: PSP[4] 3: PSP[3] 2: PSP[2] 1: 0: Description H.Rst S.Rst B.Rst Write is ignore Read is always zero R/W 0x00 0x00 - 0x00 0x00 - Current Received Packet Stream Data Area Pointer Write is ignore Read is always zero Receive Stream Data LINK Pointer Register This Receive Stream Data LINK Pointer Register indicates the starting address of the latest received stream data in the RxStreamdataArea. Since the buffer pointer is in Quadlet unit, the lower order 2 bits are always "0". Also, since the buffer size is 2 Kbytes, the higher order 3 bits are always "0". Reading the higher order bytes holds the lower order bytes. When writing to this register, write the higher order bytes and lower order bytes in order. (With timing of writing to the lower order bytes, the register is updated.) Address 0x46 0x47 Register Name Bit Symbol R/W LinkTxStreamPtr_H 7: 6: 5: 4: PTDP[12] 3: PTDP[11] 2: PTDP[10] 1: PTDP[9] 0: PTDP[8] LinkTxStreamPtr_L 7: PTDP[7] 6: PTDP[6] 5: PTDP[5] 4: PTDP[4] 3: PTDP[3] 2: PTDP[2] 1: 0: Description H.Rst S.Rst B.Rst Write is ignore Read is always zero R 0x00 0x00 0x00 0x00 Current Transmit Packet Data Area Pointer Write is ignore Read is always zero Transmit Stream Data LINK Pointer Register This Transmit Stream Data LINK Pointer Register indicates the starting address of unused area in the RxStreamArea. Since the buffer pointer is in Quadlet unit, the lower order 2 bits are always "0". Also, since the buffer size is 2 Kbytes, the higher order 3 bits are always "0". Reading the higher order bytes holds the lower order bytes. This register is read-only. Writing is ignored. 68 EPSON S1R72801F00A Address 0x48 0x49 Register Name Bit Symbol R/W UsedRxHdrPtr_H 7: 6: 5: 4: URHP[12] 3: URHP[11] 2: URHP[10] 1: URHP[9] R/W 0: URHP[8] UsedRxHdrPtr_L 7: URHP[7] 6: URHP[6] 5: URHP[5] 4: 3: 2: 1: 0: Description H.Rst S.Rst B.Rst Write is ignore Read always zero 0x00 0x00 - 0x00 0x00 - Received Packet Header Area Used Pointer Write is ignore Read is always zero Used Receive Header Pointer Register This Used Receive Header Pointer Register indicates the starting address of used header of a receive packet in the RxHdrArea. Since the buffer pointer is in 8Quadlet unit, the lower order 5 bits are always "0". Also, since the buffer size is 2 Kbytes, the higher order 3 bits are always "0". Reading the higher order bytes holds the lower order bytes. When writing to this register, write the higher order bytes and lower order bytes in order. (With timing of writing to the lower order bytes, the register is updated.) Address Register Name 0x4A UsedRxORBPtr_H 0x4B UsedRxORBPtr_L Bit Symbol R/W 7: 6: 5: 4: UOP[12] 3: UOP[11] 2: UOP[10] 1: UOP[9] 0: UOP[8] 7: UOP[7] 6: UOP[6] 5: UOP[5] 4: UOP[4] 3: UOP[3] 2: UOP[2] 1: 0: Description H.Rst S.Rst B.Rst Write is ignore Read is always zero R/W 0x00 0x00 - 0x00 0x00 - Received Packet ORB Data Area Used Pointer Write is ignore Read is always zero Used Receive ORB Data Pointer Register This Used Receive ORB Data Pointer Register indicates the starting address of used ORB data of receive packet in the RxORBArea. Since the buffer pointer is in Quadlet unit, the lower order 2 bits are always "0". Also, since the buffer size is 2 Kbytes, the higher order 3 bits are always "0". Reading the higher order bytes holds the lower order bytes. When writing to this register, write the higher order bytes and lower order bytes in order. (With timing of writing to the lower order bytes, the register is updated.) EPSON 69 S1R72801F00A Address Register Name Bit Symbol R/W 0x4C IDE_RxStreamPtr_H 7: 6: 5: 4: IRSP[12] 3: IRSP[11] 2: IRSP[10] 1: IRSP[9] 0: IRSP[8] 0x4D IDE_RxStreamPtr_L 7: IRSP[7] 6: IRSP[6] 5: IRSP[5] 4: IRSP[4] 3: IRSP[3] 2: IRSP[2] 1: 0: R/W Description Write is ignore Read is always zero H.Rst S.Rst B.Rst 0x00 0x00 - 0x00 0x00 - Received Packet Stream Data Area IDE Pointer Write is ignore Read is always zero Receive Stream Data IDE Pointer Register This Receive Stream Data IDE Pointer Register indicates the starting address of received stream data in the RxSTreamArea that is to be transmitted to the IDE side but not yet transmitted. Since the buffer pointer is in Quadlet unit, the lower order 2 bits are always "0". Also, since the buffer size is 2 Kbytes, the higher order 3 bits are always "0". Reading the higher order bytes holds the lower order bytes. When writing to this register, write the higher order bytes and lower order bytes in order. (With timing of writing to the lower order bytes, the register is updated.) Address 0x4E 0x4F Register Name Bit Symbol R/W IDE_TxStreamPtr_H 7: 6: 5: 4: ITSP[12] 3: ITSP[11] 2: ITSP[10] 1: ITSP[9] 0: ITSP[8] IDE_TxStreamPtr_L 7: ITSP[7] 6: ITSP[6] 5: ITSP[5] 4: ITSP[4] 3: ITSP[3] 2: ITSP[2] 1: 0: Description H.Rst S.Rst B.Rst Write is ignore Read is always zero 0x00 0x00 - 0x00 0x00 - R/W Transmit Packet Stream Data Area IDE Pointer Write is ignore Read is always zero Transmit Stream Data IDE Pointer Register This Transmit Stream Data IDE Pointer Register indicates the starting address of stream data in the RxStreamArea to be stored following the data that was transmitted from the IDE to the SRAM. Since the buffer pointer is in Quadlet unit, the lower order 2 bits are always "0". Also, since the buffer size is 2 Kbytes, the higher order 3 bits are always "0". Reading the higher order bytes holds the lower order bytes. When writing to this register, write the higher order bytes and lower order bytes in order. (With timing of writing to the lower order bytes, the register is updated.) 70 EPSON S1R72801F00A Address Register Name Bit Symbol R/W 0x50 BufControl 7: TxStreamClr W 6: RxStreamClr W 5: RxORBClr W 4: RxHdrClr W 3: 2: 1: 0: UpdLinkTxStrm W 0: None Affect 0: None Affect 0: None Affect 0: None Affect 0: 0: 0: 0: None Affect Description 1: Tx Stream Data Clear 1: Rx Stream Data Clear 1: Rx ORB Dat Clear 1: Rx Header Clear 1: 1: 1: 1: Update Link Tx Stream Ptr H.Rst S.Rst B.Rst 0x00 0x00 - Buffer Control Register This Buffer Control Register restores each pointer of the TxStreamArea, RxStreamArea, RxORBARea, and RxHeaderArea to the initial set pointer address. It also controls updates of the LINKTxStreamPtr. This register is read-only. If you read it, it always indicates zero. bit7 Tx Stream Clear Writing "1" to this bit changes the values of LINKTxStreamPtr and IDE_TxStreamPtr to ones set by the TxStreamAreaStart Register. bit6 Rx Stream Clear Writing "1" to this bit changes the values of LINKRxStreamPtr and IDE_RxStreamPtr to ones set by the RxStreamAreaStart Register. bit5 Rx ORB Clear Writing "1" to this bit changes the values of LINKRxORBPtr and IDE_RxORBPtr to ones set by the RxORBAreaStart Register. bit4 Rx Header Clear Writing "1" to this bit changes the values of LINKRxHdrPtr and UsedRxHdrPtr to the value of 0x0100. bit3::1 Reserved bit0 Update LINKTxStreamPtr Writing "1" to this bit updates the value of LINKTxStreamPtr to the latest value. When the firmware transmits data, this bit confirms that the transmit is normally completed as an error recovery to update the LINKTxStreamPtr. Do not use this bit in execution of the HwSBP2. EPSON 71 S1R72801F00A Address 0x51 Register Name BufMonitor Bit Symbol R/W 7: RxPayldRdy 6: TxPayldRdy 5: 4: 3: RxHdrRemain 2: RxORBFull 1: RxStreamFull 0: RxHdrFull R R R R R R Description 0: Rx Payld Capa not Ready 0: Tx Payld Capa not Ready 0: 0: 0: Rx Header Area Empty 0: Rx ORB Area not Full 0: Rx Stream Area not Full 0: Rx Header Area not Full 1: Rx Payload Capa Ready 1: Tx Payload Capa Ready 1: 1: 1: Rx Header not Empty 1: Rx ORB Data Area Full 1: Rx Stream Data Area Full 1: Rx Header Area Full H.Rst S.Rst B.Rst 0x00 0x00 - Buffer Monitor Register This Buffer Monitor Register indicates each buffer area status. This register is read-only. Writing to this register is ignored.. bit7 Rx Payload Ready When a free space the equivalent of the size set by the PyloadSize Register exists in the RxStreamArea, this bit becomes "1". When not, this bit becomes "0". bit6 Tx Payload Ready When transmit data the equivalent of the size set by the PayloadSize Register is accumulated in the RxStreamArea, this bit becomes "1". When not, this bit becomes "0". bit5::4 Reserved bit3 Received Header Remain When an unused packet header exists in the header area of a receive packet, this bit becomes "1". When the firmware rewrites the UsedRxHdrPtr to one same as LINKRxHdrPtr or when you write "1" to the BufControl.RxHdrCtr bit, this bit becomes "0". Bit2 Received ORB Data Full When the ORB buffer area of receive packet data is full of received data, this bit becomes "1". The firmware must turn on RxDMACtl.ForceBusy bit if this bit is turned on to give priority to the processing to free the buffer by starting a processing with the first received packet immediately. When the receive buffer area is freed, the RxDMACtl.ForceBusy is cleared. Bit1 Received Stream Data Full When the stream buffer area of receive packet data is full of received data, this bit becomes "1". The firmware must turn on the RxDMACtl.ForceBusy bit if this bit is turned on to give priority to the processing to free the buffer by starting a processing with the first received packet immediately. When the receive buffer area is freed, the RxDMACtl.ForceBusy is cleared. Bit0 Received Header Full When the header area of receive packet data is full, this bit becomes "1". The firmware must turn on the RxDMACtl.ForceBusy bit if this bit is turned on to give priority to the processing to free the buffer by starting a processing with the first received packet immediately. When the receive buffer area is freed, the RxDMACtl.ForceBusy is cleared. 72 EPSON S1R72801F00A Address Register Name Bit Symbol 0x52 AsyDmaCtl 7: AsyChnlSel 6: 5: 4: BlkWrAreaSel 3: AsyFIFOEpty 2: AsyFIFOClr 1: AsyTxMon 0: AsyStart R/W Description R/W 0: AsyTxPktHdr0 1: AsyTxPktHdr1 0: 1: 0: 1: R/W 0: Rx ORB Area 1: Rx Stream Area R 0: AsyFIFO Empty 1: Non Empty W 0: Normal 1: AsyFIFO Clear R 0: Async Tx Stop 1: Async Tx Run W 0: normal 1: Async Start H.Rst S.Rst B.Rst 0x00 0x00 - Async TxDMA Control Register Bit7 Async Transmit Packet Header Channel Select Selects the header area of an Async Transmit packet from DMA. You transmit send a transmit packet from the selected area. This bit selects "0": AsyncTxPktHdr0 or "1": AsyncTxPktHdr1. Since the AsyncTxPktHdr1 area overlaps the ISOTxPktHdr area, however, the firmware must decide how to use this area. Bit6 Reserved Bit5 Reserved Bit4 Block Write Request Packet Data Area Select Can divide the store area of the Block Write Request packet data between the RxORBArea and RxStreamArea. o:RxORBArea 1:RxStreamArea Bit3 Async FIFO Empty When the DMA-FIFO for Async is empty, this bit becomes "0". When it is not empty, it is "1". This bit is readonly and writing to this bit is ignored. Bit2 Async FIFO Clear Clears the DMA-FIFO for Async. Writing "1" to this bit clears the FIFO. After clearing it, this bit is automatically restored to "0". Bit1 Async Transmit Monitor Indicates the transmit status of Async. "1" indicates that an Async packet is in transmission and "0" indicates that no Async packet is in transmission. This bit is read-only and writing to this bit is ignored. Bit0 Async Transmit Start Transmits an Async packet. Writing "1" to this bit starts to transmit an Async packet. On completion of the transmission, it is automatically restored to "0". If you read this bit, it always indicates "0" regardless of presence/absence of transmit. EPSON 73 S1R72801F00A Address Register Name 0x53 IsoDmaCtl Bit Symbol 7: IsoChnlSel 6: 5: 4: SelTxPtr 3: IsoFIFOEpty 2: IsoFIFOClr 1: IsoTxMon 0: IsoStart R/W R/W R/W R W R W Description H.Rst S.Rst B.Rst 0: IsoTxPktHdr0 1: IsoTxPktHdr1 0: 1: 0: 1: - 0: Async Tx Pointer Select 1: ISO Tx Pointer Select 0x00 0x00 0: IsoFIFO Empty 1: Non Empty 0: Normal 1: IsoFIFO Clear 0: Iso Tx Stop 1: Iso Tx Run 0: normal 1: Start ISO TxDMA Control Register Bit7 ISO Transmit Packet Header Channel Select Selects the header area of an ISO Transmit packet from DMA. You can transmit a transmit packet from the selected area. This bit selects "0": ISOTxPktHdr0 or "1": ISOTxPktHdr1. Since the ISOAsyncTxPktHdr0 and ISOAsyncTxPktHdr1 areas overlap the AsyncTxPktHdr1 area, however, the firmware must decide how to use this area. Bit6..5 Reserved Bit4 Select Transmit Pointer Can switch the address pointed by the PostTxDataPtr of a transmit packet to one for Async or ISO. The PostTxData Ptr indicates a pointer of current transmit address; "0" indicates it is for Async and "1" indicates it is for ISO. Bit3 ISO FIFO Empty When the DMA-FIFO for ISO is empty, this bit becomes "0". When it is not empty, it is "1". This bit is readonly and writing to this bit is ignored. Bit2 ISO FIFO Clear Clears the DMA-FIFO for ISO. Writing "1" to this bit clears the FIFO. After clearing it, this bit is automatically restored to "0". Bit1 ISO Transmit Monitor Indicates the transmit status of ISO. "1" indicates that an ISO packet is in transmission and "0" indicates that no ISO packet is in transmission. This bit is read-only and writing to this bit is ignored. Bit0 ISO Transmit Start Transmits an ISO packet. Writing "1" to this bit starts to transmit an ISO packet. On completion of the transmission, it is automatically restored to "0". If you read this bit, it always indicates "0" regardless of presence/absence of transmit. 74 EPSON S1R72801F00A Address Register Name Bit Symbol 0x54 RxDmaCtl 7: 6: 5: 4: 3: RxFIFOEpty 2: RxFIFOClr 1: RxMon 0: ForceBusy R/W Description 0: 1: 0: 1: 0: 1: 0: 1: R 0: Rx FIFO Empty 1: Non Empty W 0: Normal 1: Rx FIFO Clear R 0: Rx Stop 1: Rx Run R/W 0: Normal 1: Busy H.Rst S.Rst B.Rst 0x00 0x00 - Rx DMA Control Register Bit7..4 Reserved Bit3 Receive FIFO Empty When the DMA-FIFO for reception is empty, this bit becomes "0". When it is not empty, it is "1". This bit is read-only and writing to this bit is ignored. Bit2 Receive FIFO Clear Clears the DMA-FIFO for reception. Writing "1" to this bit clears the FIFO. After clearing it, this bit is automatically restored to "0". Bit1 Reception Monitor Indicates the receive status of ISO. "1" indicates that a receive packet is in reception and "0" indicates that no receive packet is in reception. This bit is read-only and writing to this bit is ignored. Bit0 Force Busy Setting this bit to "1" can forcedly return an Ack_Busy to a receive packet. Before performing the RxData Clear or RxHdrClear, be sure to set this bit. If you set this bit during receiving a packet, the packet operates to complete the reception regardless of to what extent the packet has been received. It means that a RxDmaCmp interrupt occurs if this packet has been correctly received. The Ack_busy is continuously returned to the subsequent receive packets. EPSON 75 S1R72801F00A Address Register Name 0x55 0x56 0x57 AreaIndex AreaWindow_H AreaWindow_L Bit Symbol 7: 6: 5: 4: 3: MemMapIndex[3] 2: MemMapIndex[2] 1: MemMapIndex[1] 0: MemMapIndex[0] 7: MemMapWindow[15] 6: MemMapWindow[14] 5: MemMapWindow[13] 4: MemMapWindow[12] 3: MemMapWindow[11] 2: MemMapWindow[10] 1: MemMapWindow[9] 0: MemMapWindow[8] R/W Description 0: 0: 0: 0: R/W R/W 1: 1: 1: 1: H.Rst S.Rst B.Rst 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - Memory Map Area Index Memory Map Area Window 7: MemMapWindow[7] 6: MemMapWindow[6] 5: MemMapWindow[5] 4: MemMapWindow[4] 3: MemMapWindow[3] 2: MemMapWindow[2] 1: MemMapWindow[1] 0: MemMapWindow[0] Memory Map Area Set Index Window Register This register is an Index Register and Window Register to set each area of a memory map. MemMapIndex Sets an index number to select a register to set the starting address of each area of a memory map. MemMapWindow Indicates a window specified by the MemMapWindow. 76 EPSON S1R72801F00A Memory Map Area Index/Window Register AreaIndex AreaWindow_H/L 0x00 bit7 bit6 (MSB) TxHdrAreaStart_H TxStreamAreaStart_H (Reserved) : (Reserved) 0x0F (Reserved) (LSB) (MSB) TxStreamAreaStart[12:8] (LSB) TxStreamAreaEnd[12:8] TxStreamAreaEnd[7:2] (MSB) RxStreamAreaStart_L 0x05 TxHdrAreaStart[12:8] TxStreamAreaStart[7:2] RxStreamAreaStart_H bit0 (LSB) (MSB) TxStreamAreaEnd_H bit1 RxORBAreaStart[12:8] TxHdrAreaStart[7:2] TxStreamAreaEnd_L 0x04 bit2 (MSB) TxStreamAreaStart_L 0x03 bit3 RxORBAreaStart[7:2] TxHdrAreaStart_L 0x02 bit4 RxORBAreaStart_H RxORBAreaStart_L 0x01 bit5 (LSB) RxStreamAreaStart[12:8] RxStreamAreaStart[7:2] (LSB) RxORBAreaStart This register sets the starting address of a receive ORB data area. TxHeaderAreaStart This register sets the starting address of a transmit header area. TxStreamAreaStart This register sets the starting address of a transmit stream data area. TxStreamAreaEnd This register sets the ending address of a transmit stream data area. The actual data store area is up to immediately before this specified address. RxStreamAreaStart This register sets the starting address of a receive stream data area. Address Register Name 0x58 0x59 BRstHdrPtr_H BRstHdrPtr_L Bit Symbol 7: 6: 5: 4: BusResetPtr[12] 3: BusResetPtr[11] 2: BusResetPtr[10] 1: BusResetPtr[9] 0: BusResetPtr[8] 7: BusResetPtr[7] 6: BusResetPtr[6] 5: BusResetPtr[5] 4: 3: 2: 1: 0: R/W Description H.Rst S.Rst B.Rst Write is ignore Read is always zero R 0x00 0x00 - 0x00 0x00 - Bus Reset Header Area Pointer This register indicates Address in Rx Header Area when BusRest detected. Write is ignore Read is always zero Bus Reset Header Pointer Register This Bus Reset Header Pointer Register holds the value of a PostRxHdrPtr when a bus reset occurs. When several bus resets occur, it is updated to the latest PostRxHdrPtr. This register is read-only and writing to this register is ignored. EPSON 77 S1R72801F00A Address Register Name 0x5A 0x5B Bit Symbol R/W BRstORBPtr_H 7: 6: 5: 4: BusRstORBPtr[12] 3: BusRstORBPtr[11] 2: BusRstORBPtr[10] 1: BusRstORBPtr[9] 0: BusRstORBPtr[8] BRstORBPtr_L 7: BusRstORBPtr[7] 6: BusRstORBPtr[6] 5: BusRstORBPtr[5] 4: BusRstORBPtr[4] 3: BusRstORBPtr[3] 2: BusRstORBPtr[2] 1: 0: Description H.Rst S.Rst B.Rst Write is ignore Read is always zero 0x00 0x00 - 0x00 0x00 - Bus Reset ORB-Data Area Pointer R This register indicates Address in Rx ORB Data Area when BusRest detected. Write is ignore Read is always zero Bus Reset ORB Pointer Register This Bus Reset Header Pointer Register holds the value of a PostRxORBPtr when a bus reset occurs. When several bus resets occur, it is updated to the latest PostRxORBPtr. This register is read-only and writing to this register is ignored. Address Register Name 0x5E MaintCtl_H Bit Symbol 7: E_Hcrc 6: E_Dcrc 5: No_Pkt 4: F_Ack 3: N_ack 2: 1: 0: R/W R/W R/W R/W R/W R/W Description 0: 0: 0: 0: 0: 0: 0: 0: 1: Add Header CRC Error 1: Add Data CRC Error 1: No Transmit Next Packet 1: Tx Optional AckCode 1: No Transmit AckPacket 1: 1: 1: H.Rst S.Rst B.Rst 0x00 0x00 - Maintenance Control Register This Maintenance Control Register enables intentional generation of a serial bus error. Bit7 Error Header CRC Writing "1" to this bit sets an invalid value for the Header CRC of a transmit packet to be generated next. After transmitting it, this bit is cleared to "0". Bit6 Error Data CRC Writing "1" to this bit sets an invalid value for the Data CRC of a transmit packet to be generated next. After transmitting it, this bit is cleared to "0". Bit5 No Packet Writing "1" to this bit abandons a transmit packet to be generated next. Immediately after abandoning it, this bit is cleared. Bit4 F_Ack Writing "1" to this bit transmits the value in the MainCtl(Lo).Ack Register to the ACK packet to be generated next. Immediately after transmitting it, this bit is cleared to "0". Bit3 No_Ack Writing "1" to this bit abandons the ACK packet to be generated next without transmitting it. Immediately after abandoning it, this bit is cleared to "0". Bit2..0 Reserved 78 EPSON S1R72801F00A Address Register Name 0x5F MaintCtl_L Bit Symbol 7: Ack[7] 6: Ack[6] 5: Ack[5] 4: Ack[4] 3: Ack[3] 2: Ack[2] 1: Ack[1] 0: Ack[0] R/W R/W Description Optional AckCode H.Rst S.Rst B.Rst 0x00 0x00 - Maintenance Control Register When the F_Ack bit is "1", this register is enabled. When the F_Ack bit is set, an Ack_Code (Ack[7::4]) and Ack_Parity(Ack[3::0]) specified on this register are transmitted. Bit7..4 Ack Code Set an arbitrary Ack code. Bit3..0 Ack_Parity Set a parity bit for the Ack_Code. Address Register Name 0x60 IDE_Config0 Bit Symbol R/W Description 7: UltraDmaMode 0: DMA Mode 6: DmaMode 0: PIO Mode 5: ActPort 0: None 4: IDE_Slave R/W 0: Master 3: DMARQ_Level 0: Positive Logic 2: Swap 0: Nomal 1: 0: 0: 0: H.Rst S.Rst B.Rst 1: Ultra DMA Mode 1: DMA Mode 1: Active 1: Slave 0x00 1: Negative Logic 1: Swap IDE Port Hi & Lo 1: 1: 0x00 - IDE Configuration Register This register sets the mode of operation of the IDE interface of this IC. Bit7 UltraDmaMode When bit6:DmaMode is "1" and bit 7:Ultra Dma Mode is "1", this bit sets the DMA transfer mode at ULTRADMA. When bit6:DmaMode is "0", the setting of this bit is invalid. Bit6 DmaMode Sets the IDE interface transfer mode at DMA or PIO. DmaMode:1 DMA mode DmaMode:0 PIO mode Bit5 Activate IDE Port The IDE interface is in all-pin input mode after a reset. By setting this bit at "1", it is activated. Bit4 IDE PORT Slave Sets the mode of operation of the IDE interface. When using the IDE interface in IDE compatible mode, set "1". In the master mode, the DMA bit at Bit 6 is reflected. IDE_Slave:1 Slave mode (HDMACQ is output and XHDMACK/XHIOR/XHIOW is input.) IDE_Slave:0 Master mode (HDMACQ is input and XHDMACK/XHIOR/XHIOW is output.) Bit3 DMARQ_Level Decides the level of operation of the HDMARQ signal. Set "0" when using the IDE interface in IDE bus compatible mode. DMARQ_Level:1 Negative logic DMARQ_Level:0 Positive logic Bit2 Swap Swaps the higher order 8 bits and lower order 8 bits when using the interface at 16 bits width. The access order to an address of 0x70 of the IDE-CSO Register is reversed. SWAP:1 Transfers the higher order 8 bit data first. SWAP:0 Transfers the lower order 8 bit data first. Bit1::0 Reserved EPSON 79 S1R72801F00A Address Register Name 0x61 IDE_Config1 Bit Symbol 7: IDE_Reset 6: 5: 4: 3: 2: 1: 0: R/W R/W Description 0: None 0: 0: 0: 0: 0: 0: 0: 1: IDE Reset 1: 1: 1: 1: 1: 1: 1: H.Rst S.Rst B.Rst 0x00 0x00 - IDE Configuration Register This register sets the mode of operation of the IDE interface of this IC. Bit7 IDE_Reset Writing "1" to this bit asserts the RESET signal to the IDE interface for 50s. During asserting the XHRESET, this bit reads "1". If you reset it during the assertion, the XHRESET is output for 50s from that time. Bit6::0 Reserved Address 0x62 Register Name Bit Symbol R/W Description H.Rst S.Rst B.Rst IDE_RegAccCyc 7: Assert Pulse[3] 6: Assert Pulse[2] R/W IDE Register Access Strobe Signal Assert Pulse 5: Assert Pulse[1] Width Minimum Value 4: Assert Pulse[0] 0x00 3: Negate Pulse[3] 2: Negate Pulse[2] R/W IDE Register Access Strobe Signal Negate Pulse 1: Negate Pulse[1] Width Minimum Value 0: Negate Pulse[0] 0x00 - IDE Register Access Cycle Register This register sets a transfer mode when accessing the register area of the IDE interface. It is enabled for an access to 0x70 to 0x7F of the IDE-CS0/CS1 Register. Bit7::4 Assert Pulse Decides the minimum value of the assert period of the strobe signal when accessing the register area of the IDE interface. It is a value [Assert Pulse + 2] times the internal operation clock (50MHz) cycle. Bit3::0 Negate Pulse Decides the minimum value of the negate period of the strobe signal when accessing the register area of the IDE interface. It is a value [Assert Pulse + 2] times the internal operation clock (50MHz) cycle. Example: 0000: 2 x 20ns = 40ns 0001: 3 x 20s = 60ns 80 EPSON S1R72801F00A Address Register Name 0x63 Bit Symbol R/W IDE_PioDmaCyc 7: Assert Pulse[3] 6: Assert Pulse[2] R/W 5: Assert Pulse[1] 4: Assert Pulse[0] 3: Negate Pulse[3] 2: Negate Pulse[2] R/W 1: Negate Pulse[1] 0: Negate Pulse[0] Description H.Rst S.Rst B.Rst IDE Transfer Mode Strobe Signal Assert Pulse Width Minimum Value 0x00 0x00 - IDE Transfer Mode Strobe Signal Negate Pulse Width Minimum Value IDE PIO/DMA Cycle Register This register sets a transfer mode when transferring data through the IDE interface. It is enabled for an access to 0x70 of the IDE-CSO Register. It is common to both PIO/DMA modes. Bit7::4 Asset Pulse Decides the minimum value of the assert period of the strobe signal when transferring data through the IDE interface. It is a value [Assert Pulse + 2] times the internal operation clock (50MHz) cycle. Bit3::0 Negate Pulse Decides the minimum value of the negate period of the strobe signal when transferring data through the IDE interface. It is a value [Assert Pulse + 2] times the internal operation clock (50MHz) cycle. Example: 0000: 2 x 20ns = 40ns 0001: 3 x 20s = 60ns Address Register Name 0x64 Bit Symbol R/W Description H.Rst S.Rst B.Rst IDE_UltraDmaCyc 7: 0: 1: 6: 0: 1: 5: 0: 1: 4: 0: 1: 0x00 3: Cycle Time[3] 2: Cycle Time[2] R/W IDE Ultra DMA Transfer Mode Strobe Signal 1: Cycle Time[1] Minimum Cycle Time 0: Cycle Time[0] 0x00 - IDE UltraDMA Cycle Register This register sets a transfer mode when transferring data by the Ultra-DMA through the IDE interface. Bit7::4 Assert Pulse Decides the minimum value of the assert period of the strobe signal when transferring data through the IDE interface. It is a value [Assert Pulse + 2] times the internal operation clock (50MHz) cycle. Bit3::0 Cycle Pulse Decides the minimum cycle time of the strobe signal when transferring Ultra-DMA data through the IDE interface. It is a value [Assert Pulse + 2] times the internal operation clock (50MHz) cycle. Example: 0000: 2 x 20ns = 40ns 0001: 3 x 20s = 60ns EPSON 81 S1R72801F00A Address Register Name 0x65 IDE_DmaCtl Bit Symbol R/W 7: 6: 5: 4: CRC_Clear 3: FIFO_Clear 2: IDE_Abort 1: IDE_Direction 0: DmaStart W W W R/W W Description 0: 0: 0: 0: None 0: None 0: None 0: SRAM -> IDE 0: None 1: 1: 1: 1: CRC Clear 1: FIFO Clear 1: IDE Transfer Abort 1: IDE -> SRAM 1: IDE DMA Start H.Rst S.Rst B.Rst 0x00 0x00 - IDE DMA Control Register This register makes control when transferring data through the IDE interface. Bit7..5 Reserved Bit4 CRC_Clear Initializes the internal CRC calculation circuit. At start-up of the DMA, even the internal circuits are initialized . Writing "1" to this bit clears the IDE_CRC0 and IDE_CRC1 Registers. Bit3 FIFO_Clear Clears the FIFO for IDE data transfer. Writing "1" to this bit clears the FIFO. Bit2 IDE_Abort Use this bit to abort DMA data transfer in execution through the IDE interface. Writing "1" to this bit aborts the DMA transfer. Bit1 IDE_Direction Specifies a data flow direction for DMA data transfer in accordance with the IDE. IDE_Direction:1 IDE -> SRAM (Buffer) IDE_Direction:1 IDE <- SRAM (Buffer) Bit0 DmaStart Setting this bit to "1" starts DMA transfer between the buffer and the IDE interface. Address Register Name 0x66 IDE_BusStat Bit Symbol 7: DMARQ 6: DMACK 5: INTRQ 4: IORDY 3: 2: 1: DIAG 0: DASP R/W R Description Indicate IDE I/F Signals State IDE Bus Status Read Register This register indicates the status of the signal of the IDE interface. Bit7 DMARQ Indicates the state of the HDMARQ signal by positive logic. (The status of the DMARQ_Level bit of the CONFIG0 is reflected.) Bit6 DMACK Indicates the state of the XHDMACK signal by positive logic. Bit5 INTRQ Indicates the state of the HINTRQ signal by positive logic. Bit4 IORDY Indicates the state of the HIORDY signal by positive logic. Bit3::2 Reserved Bit1 DIAG Indicates the state of the XHPDIAG signal by positive logic. Bit0 DASP Indicates the state of the XHDASP signal by positive logic. 82 EPSON H.Rst S.Rst B.Rst 0x00 0x00 - S1R72801F00A Address Register Name 0x67 IDE_DmaStat Bit Symbol 7: 6: 5: 4: 3: 2: 1: DmaPause 0: DmaRun R/W R W Description 0: 0: 0: 0: 0: 0: 0: IDE DMA not Pause 0: Not DMA H.Rst S.Rst B.Rst 1: 1: 1: 1: 0x00 1: 1: 1: IDE DMA Pause 1: IDE DMA Running 0x00 - IDE DMA Status Register This register indicates the status of the DMA of the IDE interface. Bit7::2 Reserved Bit1 DmaPause Indicates whether the DMA mode in execution is in pause status or not. It is enabled when the DmaRun bit is "1". DmaPause:1 DMA is in pause. DmaPause:0 DMA is in execution. Bit0 DmaRun Indicates whether the DMA mode in execution is in execution or not. It is enabled when the DmaRun bit is "1". DmaPause:1 DMA is in execution. DmaPause:0 DMA is not in execution. EPSON 83 S1R72801F00A Address Register Name 0x68 0x69 0x6A 0x6B Bit Symbol R/W Description IDE_ByteCount0 7: ByteCount[31] 6: ByteCount[30] 5: ByteCount[29] 4: ByteCount[28] 3: ByteCount[27] 2: ByteCount[26] 1: ByteCount[25] 0: ByteCount[24] IDE_ByteCount1 7: ByteCount[23] 6: ByteCount[22] 5: ByteCount[21] 4: ByteCount[20] 3: ByteCount[19] 2: ByteCount[18] 1: ByteCount[17] 0: ByteCount[16] R/W H.Rst S.Rst B.Rst 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - IDE Data Transfer Byte Count Register Read: Indicate Remain Byte Count Write: Set Total Transfer Byte Count IDE_ByteCount2 7: ByteCount[15] 6: ByteCount[14] 5: ByteCount[13] 4: ByteCount[12] 3: ByteCount[11] 2: ByteCount[10] 1: ByteCount[9] 0: ByteCount[8] IDE_ByteCount3 7: ByteCount[7] 6: ByteCount[6] 5: ByteCount[5] 4: ByteCount[4] 3: ByteCount[3] 2: ByteCount[2] 1: ByteCount[1] 0: ByteCount[0] IDE Byte Count Set Register This register sets a total data length in DMA transfer in the unit of byte. By setting each register of IDE_ByteCount0 to 3, setting up to max. 0xFFFFFFFF is possible. If you set an odd byte to this register or the OddStart bit of the CONFIG0 Register when using the data port of the IDE bus based on word size, 1 byte is short at the first or last transfer. It is automatically padded by the IC (data is undefined). 84 EPSON S1R72801F00A Address Register Name 0x6C 0x6D IDE_CRC0 IDE_CRC1 Bit Symbol 7: CRC[15] 6: CRC[14] 5: CRC[13] 4: CRC[12] 3: CRC[11] 2: CRC[10] 1: CRC[9] 0: CRC[8] R/W R Description H.Rst S.Rst B.Rst 0x00 0x00 - 0x00 0x00 - IDE CRC Data Register 7: CRC[7] 6: CRC[6] 5: CRC[5] 4: CRC[4] 3: CRC[3] 2: CRC[2] 1: CRC[1] 0: CRC[0] CRC Read Register This register indicates CRC calculation results when transferring data by the Ultra-DMA through the IDE interface. EPSON 85 S1R72801F00A Address 0x70 0x71 Register Name IDE_CS00 IDE_CS01 UltraDmaMode 0x72 0x73 0x74 0x75 0x76 0x77 IDE_CS02 IDE_CS03 IDE_CS04 IDE_CS05 IDE_CS06 IDE_CS07 Bit Symbol 7: 6: 5: 4: 3: 2: 1: 0: 7: 6: 5: 4: 3: 2: 1: 0: 7: 6: 5: 4: 3: 2: 1: 0: 7: 6: 5: 4: 3: 2: 1: 0: 7: 6: 5: 4: 3: 2: 1: 0: 7: 6: 5: 4: 3: 2: 1: 0: 7: 6: 5: 4: 3: 2: 1: 0: 7: 6: 5: 4: 3: 2: 1: 0: R/W Description H.Rst S.Rst B.Rst Command Block Register R/W Data Register 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - Command Block Register R/W Read : Error Register Write: Features Register Command Block Register R/W Sector Count Register Command Block Register R/W Sector Number Register or Logical Block Address(LBA) bit 0 - 7 Command Block Register R/W Cylinder Low Register or Logical Block Address(LBA) bit 8 - 15 Command Block Register R/W Cylinder High Register or Logical Block Address(LBA) bit 16 - 23 Command Block Register R/W Device/Head Register 0x00 Logical Block Address(LBA) bit 24 - 27 Command Block Register R/W Read : Status Register 0x00 Write: Command Register IDE Command Block Register This register is a Command Block Register that is the I/O port of the IDE interface. The transfer mode of the Data Register is PIO mode-fixed, having access based on conditions set on the IDE_PioDmaCyc Register. Since the setting at the BUS8/SWAP bit of the CONFIG Register is reflected, 16-bit access is possible by always accessing the Data Register twice if it is 16 bits wide. During DMA transfer, access to the Data Register is disabled. If you access the 0x71-0x77 in the DMA mode or when the InterLock bit is not on, the HDMARQ is negated once and CPU access is done. When the Interlock bit is on or at the time of UltraDMA, the XHDMACK is negated at the time of HDMAQR off or on completion of transfer. Note that, for this reason, the CPU access is put in wait state. 86 EPSON S1R72801F00A Address Register Name 0x78 IDE_CS10 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F IDE_CS11 IDE_CS12 IDE_CS13 IDE_CS14 IDE_CS15 IDE_CS16 IDE_CS17 Bit Symbol 7: 6: 5: 4: 3: 2: 1: 0: 7: 6: 5: 4: 3: 2: 1: 0: 7: 6: 5: 4: 3: 2: 1: 0: 7: 6: 5: 4: 3: 2: 1: 0: 7: 6: 5: 4: 3: 2: 1: 0: 7: 6: 5: 4: 3: 2: 1: 0: 7: 6: 5: 4: 3: 2: 1: 0: 7: 6: 5: 4: 3: 2: 1: 0: R/W Description H.Rst S.Rst B.Rst Control Block Register R/W Read : Data Bus Hi - Impedance Write: Not Used 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - Control Block Register R/W Read : Data Bus Hi - Impedance Write: Not Used Control Block Register R/W Read : Data Bus Hi - Impedance Write: Not Used Control Block Register R/W Read : Data Bus Hi - Impedance Write: Not Used Control Block Register R/W Read : Data Bus Hi - Impedance Write: Not Used Control Block Register R/W Read : Data Bus Hi - Impedance Write: Not Used Control Block Register R/W Read : Alternate Status Write: Device Control Control Block Register R/W Read : (obsolete) Write: Not Used IDE Command Control Register This register is a Command Block Register that is the I/O port of the IDE interface. EPSON 87 S1R72801F00A 8.2 FLASH ROM CONTROL REGISTER Address Register Name 0x200000 FlashCtl Bit Symbol 7: FlashCtlEnb 6: 5: 4: Erase 3: FlashStat 2: FlashChipErs 1: FlashSctErs 0: FlashWrEnb R/W Description R/W 0: Flash Control Disable 0: 0: W 0: None R 0: Write/Erase Complete R/W 0: Chip All Erase Disable R/W 0: Sector Erase Disable R/W 0: Flash Data Write Disable H.Rst S.Rst B.Rst 1: Flash Control Enable 1: 1: 1: Erase Execute 0x00 1: Write/Erase Run 1: Chip All Erase Enable 1: Sector Erase Enable 1: Flash Data Write Enable 0x00 - Flash Control Register This register controls the erase and write of the built-in Flash. Bit7 FlashCtlEnb Enables Flash control. Setting this bit to "1" enables the lower order 5 bits of this register. Setting "0" disables having access to the built-in Flash. Bit6 Reserved Bit5 Reserved Bit4 Erase Setting this bit to "1" starts to erase the built-in Flash. This bit is read-only. If you read it, it always indicates zero. Setting this bit to "1" at the time of FlashSctErs=1, the Flash Address is updated after erasing one sector. Bit3 FlashStat Indicates the operation of Write/Erase. "1": In execution "0": Processing finishes. Bit2 FlashChipErs Use this bit to erase all the built-in Flash. "1": All Erase is enabled.. "0": All Erase is disabled. Bit1 FlashSctErs Use this bit to erase the built-in Flash in the unit of sector. It enables the erase of the sector address set on the Flash Address. "1": Sector Erase is enabled.. "0": Sector Erase is disabled. Bit1 FlashWREnb Enables Data Write into the built-in Flash. "1": Data Write is enabled.. "0": Data Write is disabled. Sequence to set a default value on FlashCtlCnt_reg Turn on one of Bit0, Bit1 or Bit2 to select a desired operation. Next, turn on bit7. Sequence to set a value on FlashCtlCnt_reg Turn on Bit7 and one of Bit0, Bit1 and Bit2. Next, set a value on the FlashCtlCnt_reg. 88 EPSON S1R72801F00A Address Register Name 0x200001 FlashCtlCnt_H 0x200002 FlashCtlCnt_M 0x200003 FlashCtlCnt_L Bit Symbol R/W Description 7: 6: 5: FlashCtlCnt[21] 4: FlashCtlCnt[20] 3: FlashCtlCnt[19] 2: FlashCtlCnt[18] 1: FlashCtlCnt[17] 0: FlashCtlCnt[16] 0: 0: IF(FlashChipErs==1 && FlashSctErs==0 && FlashWrEnb==0){ R/W Enable; Default Value = 0x3FFFFF; } 7: FlashCtlCnt[15] 6: FlashCtlCnt[14] 5: FlashCtlCnt[13] 4: FlashCtlCnt[12] R/W 3: FlashCtlCnt[11] 2: FlashCtlCnt[10] 1: FlashCtlCnt[9] 0: FlashCtlCnt[8] erase if(FlashChipErs==0 && FlashSctErs==1 && FlashWrEnb==0){ R/W Enable; Default Value = 0x0FFFFF; } erase if(FlashChipErs==0 && FlashSctErs==0 && FlashWrEnb==1){ R/W Enable; 7: FlashCtlCnt[7] 6: FlashCtlCnt[6] 5: FlashCtlCnt[5] 4: FlashCtlCnt[4] 3: FlashCtlCnt[3] 2: FlashCtlCnt[2] 1: FlashCtlCnt[1] 0: FlashCtlCnt[0] Default Value = 0x000190; } else { Read is alway Zero; Write is Ignore; } H.Rst S.Rst B.Rst 1: 1: 0x00 0x00 - 0x00 0x00 - 0x00 0x00 - Flash Control Count Register This register is enabled when the FlashChipErs bit, FlashSctErs bit or FlashWrEnb bit of the FlashCtl Register is set alone. It is disabled when two or more bits are set. When setting them in the unit of byte, conform to the order of FlashCtlCnt_H (higher order byte), FlashCtlCnt_M, and FlashCtlCnt_L (lower order byte). On completion of writing to the lower order byte, setting of this register is enabled. Pulse width (Default value) FlashChipErs: 40ns x 0x3FFFFF = 167.8ms FlashSctErs: 40ns x 0x0FFFFF = 41.9ms FlashWrEnb: 40ns x 0x000190 = 16.0s EPSON 89 S1R72801F00A Address Register Name 0x200004 FlashAdrs_H 0x200005 FlashAdrs_M Bit Symbol R/W 7: Flash Address[15] 6: Flash Address[14] 5: Flash Address[13] 4: Flash Address[12] 3: Flash Address[11] 2: Flash Address[10] 1: Flash Address[9] 0: Flash Address[8] R/W 7: Flash Address[7] 6: Flash Address[6] 5: Flash Address[5] 4: Flash Address[4] 3: Flash Address[3] 2: Flash Address[2] 1: Flash Address[1] 0: Description Write: Flash Write/Erase Sector Address Set Read: Current Flash Sector Address H.Rst S.Rst B.Rst 0x00 0x00 - 0x00 0x00 - When All of Sector are erased, This Address is Ignored. When Data register's Low Byte is accessed, This Register is updated. Reserved(Always Zero) Flash Address Register This register specifies a write/erase address of the built-in Flash. In the Built-in Flash All Erase mode, the setting of this register is ignored. During writing operation, writing to the lower order byte of the Flash Data Register increments the address of this register. Address Register Name 0x200006 FlashData_H 0x200007 FlashData_L Bit Symbol R/W 7: Flash Address[15] 6: Flash Address[14] 5: Flash Address[13] 4: Flash Address[12] 3: Flash Address[11] 2: Flash Address[10] 1: Flash Address[9] 0: Flash Address[8] R/W Description Write: Flash Write Data Set Read: Flash Address's Word Data is read. H.Rst S.Rst B.Rst 0x00 0x00 - 0x00 0x00 - When operation is Write, It shall be set from high byte. Because when Data register's Low Byte is accessed, 7: Flash Address[7] 6: Flash Address[6] 5: Flash Address[5] 4: Flash Address[4] 3: Flash Address[3] 2: Flash Address[2] 1: Flash Address[1] 0: Flash Address[0] Flash Address is updated. Flash Write Data Register This register specifies write data of the built-in Flash. When setting it in the unit of byte, conform to the order of higher order byte - lower order byte. If you reverse the order, data cannot be correctly written. Writing to the lower order byte updates the Flash Address Register to the next write address. 90 EPSON S1R72801F00A 9. ELECTRICAL CHARACTERISTICS 9.1 ABSOLUTE MAXIMUM RATINGS Item Symbol Rating Unit HVDD -0.3 to 7.0 V LVDD -0.3 to 4.0 V HVIN -0.3 to HVDD + 0.5 V LVIN -0.3 to LVDD + 0.5 V HVOUT -0.3 to HVDD + 0.5 V LVOUT -0.3 to LVDD + 0.5 V Output current/pin IOUT -30 mA Storage temperature TSTG -65 to 150 C Supply voltage Input voltage Output voltage 9.2 RECOMMENDED OPERATING CONDITION Item Symbol Min. Typ. Max. Unit HVDD 4.5 5 5.5 V LVDD 3 3.3 3.6 V HVIN VSS - HVDD V LVIN VSS - LV DD V Operating temperature TOPr1 0 - 70 C Operating temperature when writing to FLASH ROM TOPr2 0 - 70 C Supply voltage Input voltage EPSON 91 S1R72801F00A 9.3 DC CHARACTERISTICS (ACCORDING TO RECOMMENDED OPERATING CONDITION) (1) (HVDD = 5.0V 0.5V, LVDD = 3.3V 0.3V, Ta = 0 to 70C) Item Symbol Condition Min. Typ. Max. Unit - - 150 mA - - 45 A Power supply current Power supply current IDD HVDD =5.5V LVDD =3.6V Static current (Static current between HVDD to VSS) Power supply current IDDSH VIN =HVDD or LVDD or VSS HVDD =5.5V LVDD =3.6V Static current (Static current between LV DD to VSS) IDDSL VIN =HVDD or LVDD or VSS HVDD =5.5V LVDD =3.6V - - 90 A IL HVDD =5.5V LVDD =3.6V HVIH =HVDD LVIH =LVDD VIL =VSS -1 - 1 A HIGH level input voltage VIH1H HVDD =5.5V 3.5 - - V LOW level input voltage VIL1H HVDD =4.5V - - 1 V HIGH level input voltage VIH2H HVDD =5.5V 2 - - V LOW level input voltage VIL2H HVDD =4.5V - - 0.8 V HIGH level input voltage VIH1L HVDD =3.6V 2 - - V LOW level input voltage VIL1L HVDD =3.0V - - 0.8 V HIGH level trigger voltage VT2+ HVDD =5.5V LVDD =3.6V 1.2 - 2.4 V LOW level trigger voltage VT2- HVDD =4.5V LVDD =3.0V 0.6 - 1,8 V Hysteresis voltage HVDD =4.5V LVDD =3.0V 0.1 - - V Power supply current Input leak Input leak current Input characteristics (CMOS) Input characteristics (TTL) Input characteristics (CMOS) Schmitt input characteristics (TTL) 92 dV2 EPSON S1R72801F00A DC CHARACTERISTICS (ACCORDING TO RECOMMENDED OPERATING CONDITION) (1) (HVDD = 5.0V 0.5V, LVDD = 3.3V 0.3V, Ta = 0 to 70C) Item Symbol Output characteristics OFF-STATE leak current IOZ Input characteristics (Bus hold) Condition Min. Typ. Max. Unit - 1 A Pin name: CTL0, CTL1, D0.. D7 HVDD =5.5V LVDD =3.6V HVOH =HVDD LVOH =LVDD VOL =VSS -1 Pin name: LINKON, SCLK, CTL0, CTL1, D0..D7, T18 LOW level HOLD current IBHL LVDD =3.0V VBHL =0.4V - - 0.3 mA HIGH level HOLD current IBHH LVDD =3.0V VBHH =2.6V -0.3 - - mA Output characteristics (Bus drive) Pin name: LINKON, SCLK, CTL0, CTL1, D0..D7, T18 LOW level output current VBHL LVDD =3.6V IBHL =0.9mA HIGH level output current VBHH LVDD =3.6V IBHH =-0.9mA EPSON LVDD-0.4 - - V - - VSS+0.4 V 93 S1R72801F00A 9.4 AC CHARACTERISTICS 9.4.1 Clock Timing 9.4.1.1 SCLK Timing T201 SCLK T202 9.4.1.2 HCLK Timing T202 T203 T204 HCLK T205 Symbol T201 T202 T203 T204 T205 94 Description SCLK frequency SCLK duty cycle SCLK start HCLK start delay time HCLK frequency HCLK duty cycle EPSON T205 Unit % ns MHz % Min. Max. 49.152MHz 100ppm 45 55 5 15 20 24.576 40 60 S1R72801F00A 9.4.2 PHY-LINK Interface Timing 9.4.2.1 Output timing SCLK T211 T212 T213 Ctl[0:1] D[0:7] LReq 9.4.2.2 Input timing SCLK T214 T212 Ctl[0:1] D[0:7] LReq Symbol T211 T212 T213 Symbol T214 T215 Description SCLK rising edge C, Ctl, LReq delay time (Hi-Z Output starts.) SCLK rising edge C, Ctl, LReq delay time (Outputting) SCLK rising edge C, Ctl, LReq delay time (When output ends.) Unit ns Min. 1 Max. 10 ns 1 10 ns 1 10 Description SCLK rising edge C, Ctl set-up time SCLK rising edge C, Ctl hold time Unit ns Min. 6 Max. ns 0 EPSON 95 S1R72801F00A 9.4.3 IDE Interface Timing 9.4.3.1 PIO Read Direction of DATA Transfer PORT S1R72801 HOST HDCSO(0) T321 T322 HDA<2:0>(0) T323 T324 T326 T325 XHIOR(0) T327 T328 HDD<15:0>(0) T329 XHIORDY(1) Symbol T321 T322 T323 T324 T325 T326 T327 T328 T329 96 Specification XHCS0 HDA HDA output delay time XHCS0 HDA HDA hold time XHCS0 XHIOR XHIOR set-up time XHIOR XHIOR XHIOR assert pulse time XHIOR XHIOR XHIOR negate pulse time XHIOR XHCS0 XHIOR hold time HDD XHIOR Data set-up time XHIOR HDD Data hold time HIORDY assert XHIOR XHDMACK set-up time Min. - Typ. 0 Max. - Unit ns - 0 - ns 60 - - ns - - ns - ns 20 IDEPIO (AP+2)x20 IDEPIO (NP+2)x20 - - ns 10 - - ns 0 - - ns - - 40 ns - EPSON S1R72801F00A 9.4.3.2 PIO Write Direction of DATA Transfer PORT S1R72801 HOST HDCSO(0) T331 T332 HDA<2:0>(0) T333 T334 T336 T335 XHIOW(0) T337 T338 HDD<15:0>(0) T339 XHIORDY(1) Symbol T331 T332 T333 T334 T335 T336 T337 T338 T339 Specification XHCS0 HDA HDA output delay time XHCS0 HDA HDA hold time XHCS0 XHIOW XHIOW set-up time XHIOW XHIOW XHIOW assert pulse width XHIOW XHIOW XHIOW negate pulse width XHIOW XHCS0 XHIOW hold time XHIOW HDD Data output delay time XHIOW HDD Data bus negate time HIORDY assert XHIOW XHDMACK set-up time Min. Typ. Max. Unit - 0 - ns - 0 - ns 60 - ns - ns - - IDEPIO (AP+2)x20 IDEPIO (NP+2)x20 - ns 20 - - ns 0 - 20 ns 40 - 60 ns - - 40 ns - EPSON 97 S1R72801F00A 9.4.3.3 DMA Read Direction of DATA Transfer PORT S1R72801 HOST XHCS<1:0>(0) HDA<2:0>(0) T342 HDMARQ(1) T341 T344 XHDAMCK(0) T343 T345 T346 T347 T348 XHIOR(0) T349 T34a HDD<15:0>(1) Symbol T341 T342 T343 T344 T345 T346 T347 T348 T349 T34a 98 Specification XHCS0,1 XHDMACK Address set-up time XHIOR XHCS0,1 Address hold time HDMARQ XHDMACK XHDMACK response time XHIOR HDMARQ negate HDMARQ hold time XHDMACK XHIOR XHIOR set-up time XHIOR XHIOR XHIOR assert pulse width XHIOR XHIOR XHIOR negate pulse width XHIOR XHDMACK XHIOR hold time HDD XHIOR Data set-up time XHIOR HDD Data bus hold time Min. Typ. Max. Unit 60 - - ns 25 - - ns 0 - - ns 0 - - ns 0 - - IDE (AP+2)x20 IDE (AP+2)x20 - - ns ns - ns 20 - - ns 10 - - ns 0 - - ns - EPSON S1R72801F00A 9.4.3.4 DMA Write Direction of DATA Transfer PORT S1R72801 HOST XHCS<1:0>(0) HDA<2:0>(0) T352 HDMARQ(1) T351 T354 XHDAMCK(0) T353 T355 T356 T357 T358 XHIOW(0) T359 T35a HDD<15:0>(0) Symbol T351 T352 T353 T354 T355 T356 T357 T358 T359 T35a Specification XHCS0,1 XHDMACK Address set-up time XHIOW XHCS0,1 Address hold time HDMARQ XHDMACK XHDMACK response time XHIOW HDMARQ negate HDMARQ hold time XHDMACK XHIOW XHIOR set-up time XHIOW XHIOW XHIOW assert pulse width XHIOW XHIOW XHIOW negate pulse width XHIOW XHDMACK XHIOW hold time XHIOW HDD Data output delay time XHIOR HDD Data bus negate time Min. Typ. Max. Unit 60 - - ns 20 - - ns 0 - - ns 0 - - ns 0 - ns - ns - - IDE (AP+2)x20 IDE (AP+2)x20 - ns 20 - - ns 0 - 20 ns 20 - 40 ns - EPSON 99 S1R72801F00A 9.4.3.5 Ultra-DMA Read Direction of DATA Transfer PORT S1R72801 HOST XHCS<1:0>(0) HDA<2:0>(0) T362 HDMARQ(1) T361 T366 XHDAMCK(0) T363 XHIOW(0) T367 T369 T364 T368 XHHIOR(0) HIORDY(0) T36f T36e T365 T36a T36c HDD<15:0>(1) CRC T36b Symbol T361 T362 T363 T364 T365 T366 T367 T368 T369 T36a T36b T36c T36d T36e T36f 100 Specification XHCS0,1 XHDMACK Address set-up time XHIOW XHCS0,1 Address hold time HDMARQ XHDMACK XHDMACK response time XHDMACK XHIOR,XHIOW envelop time XHIOR,XHIOW HIORDY First Strobe Time XHIOR,XHIOW HDMARQ Strobe Edge to negation DMARQ HDMARQ XHIOR,XHIOWATM Limited interlock time HIORDY XHIOR Ready-to-final strobe time XHIOR XHIOW Ready-to-Pause time HDDHIORDY Data set-up time HIORDY HDD Data hold time HIORDY HDD(CRC) Interlock time with minimum HDD(CRC) HDMACK CRC data set-up time HDMACK HDD(CRC) CRC data hold time HIORDY HIORDY HIORDY pulse width EPSON T36d Min. Typ. Max. Unit 20 - - ns 40 - - ns 20 - - ns 20 - - ns 0 - - ns 30 - - ns 40 - 90 ns 20 - 55 ns 170 - - ns 7 - - ns 5 - - ns 0 - - ns 75 - 95 ns 7 - - ns 55 - - ns S1R72801F00A 9.4.3.6 Ultra-DMA Write Direction of DATA Transfer PORT S1R72801 HOST XHCS<1:0>(0) HDA<2:0>(0) T372 HDMARQ(1) T371 XHDAMCK(0) T377 T378 T373 T37a T374 XHIOW(0) XHHIOR(0) T375 T379 T376 HIORDY(1) T37e T37f T37b T37c HDD<15:0>(0) CRC T37d Symbol T371 T372 T373 T374 T375 T376 T377 T378 T379 T37a T37b T37c T37d T37e T37f T37g Specification XHCS0,1 XHDMACK Address set-up time XHDMCK XHCS0,1 Address hold time HDMARQ XHDMACK XHDMACK response time XHDMACK XHIOW envelop time XHIOW HIORDY Limited interlock Time HIORDY XHIOR Unlimited interlock Time XHIOR HDMARQ Strobe Edge to negation DMARQ HDMARQ XHIOR Limited interlock time XHIOR HIORDY Strobe to DMARDY time XHIOR XHIOW Strobe edge to nagation STOP HDMACK HDD Data output delay time XHIOR HDD Data negate time HIORDY HDD(CRC) Interlock time with minimum HDD(CRC) HDMACK CRC data set-up time HDMACK HDD(CRC) CRC data hold time HIORDY HIORDY HIORDY pulse width EPSON Min. Typ. Max. Unit 20 - - ns 40 - - ns 20 - - ns 20 - - ns 40 - - ns - - - ns 30 - - ns 40 - 90 ns (CYC+2)x20 - 55 ns 50 - - ns - - - ns 20 - - ns - - - ns 75 - 95 ns 7 - - ns - - - ns 101 S1R72801F00A 9.4.4 CPU Interface Timing Regarding the built-in CPU, refer to the E0C33208/204/202 TECHNICAL MANUAL. In the built-in CPU core, however, a DMA controller and A/D converter are not integrated; this part is different from the description on the DMA controller and A/D converter given in TECHNICAL MANUAL. A low-speed oscillation circuit (OSC1) is not available. 102 EPSON 17,18PIN 16PIN socket VP VG TPB* TPB TPA* TPA shell CN2 socket PVDD C32 0.1u 0.1u 25 27PIN 1 2 3 4 5 6 1 2 3 4 5 6 1000p C14 (E5) (F3) VP VG TPB* TPB TPA* TPA shell CN1 CPS RST R40 390K C31 PVDD HRW0202A 2 C37 0.1u 3 1 1000p 32PIN 0.1u C33 PVDD 30,31PIN C15 RM5 56 1000p C16 RM6 56 (1%) 1000p C17 R35 R70 Pattern width and length should be equal VP (C6) 0.01u D1 220p 220p C9 8 7 6 5 1 2 3 4 5.1K R37 C10 + C25 PVDD 0.01u 42PIN 0.1u C34 PVDD 5.1K 1.2K PVDD AGNG TPB0- TPB0+ TPA0- TPA0+ TPBIAS0 AGND R0 R1 AVDD TPB1- TPB1+ TPA1- TPA1+ TPBIAS1 AGND 1000p C18 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 R44 1K R49 R50 R51 R52 4 3 2 1 OPS (H5) 10K 10K 10K 10K TSB41LV02 PVDD 49,50PIN 1000p C19 0.1u C35 PVDD 51,52PIN (H4) RST C13 1u C27 5.1K R38 C29 0.1u 0.1u C30 8 7 6 5 1 2 3 4 1u C28 + C25 CR16 1000p C20 24.576MHz X1 63,64PIN PG 0.1u C38 PVDD 61,62PIN 1000p C21 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 1000p C22 0 0 0 0 1000p C23 R75 R76 R77 R78 0.01u 0.1u DG LED1 HVDD PG PG TLR124 Bus holder with pull-down PD,LINKON,CNA,LPS C51 C50 CR13 CR14 CR1 CR2 CR3 CR4 CR5 CR6 CR7 CR8 CR9 CR10 CR11 +12V GND GND +6V R75 R76 R77 R78 R71 R72 R73 R74 1K 0 0 0 0 0 0 0 0 R45 POWER DG DG 12V F1 (G5) JP1 D3V C4 + PVDD 47u C5 + HMDD P5V 47u D5 HRF503A D2 HRF503A 1 JUMP-3 3 VP D5V SMD0302 LPS (2D3) CON4 1 2 3 4 CN3 CR1 `16 DMT7281D 0 mounted DMT7281I 1000pF mounted CR15 1000pF 0 (2D3) PD 1000pF LD7 (2D3) 1000pF LD6 (2D3) 1000pF LD5 (2D3) 100pF LD4 (2D3) 1000pF LD3 (2D3) 1000pF LD2 (2D3) 1000pF LD1 (2D3) 1000pF LD0 (2D3) 1000pF CTRL1 (2D3) 1000pF CTRL0 (2D3) CR12 0 CNA (2D4) 1000pF SCLK (2D4) 1000pF LREQ (2D4) PVDD LINKON(2D3) PVDD 1000pF Shortest pattern (100PPM) VDD-5V LPS PD D7 D6 D5 D4 D3 D2 D1 D0 CTL1 CTL0 CNA SYSCLK LREQ U2 SWDIP-4 10K R54 5 6 7 8 1000p 4.7K R43 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 AGND AVDD AVDD SM SE TESTM DVDD DVDD CPS xISO PC2 PC1 PC0 C/LKON DGND DGND AGNG AGND AVDD AVDD RESET FILTER0 FILTER1 PLLVDD PLLGND PLLGND XI XO DVDD DVDD DGND DGND 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 10P C11 EPSON 10P C12 10K 10K R56 R57 10K R55 PVDD 2 VIN U7 0.1u C36 1 VIN U8 Current New 1 VOUT BA033FP JP1 1-2 2-3 VOUT BA05FP GND 2 GND 2 DSW1 3 3 PSV 22u C3 + D3V 22u C2 + PSV CON2 1 2 CN6 Power supply connector for 2.5" HDD S1R72801F00A 10. EXAMPLES OF EXTERNAL CONNECTION FOR REFERENCE PURPOSES 103 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 1u C52 R79 D0 R80 D1 R81 D2 R82 D3 R83 D4 R84 D5 R85 D6 R86 D7 R87 D8 R88 D9 R89 D10 R90 D11 R91 D12 R92 D13 R93 D14 R94 D15 1 2 3 4 5 RST VSA VSB VCC A11 A12 A13 A14 A15 A16 A17 A4 A5 A6 A7 A8 A9 A10 A0 A1 A2 A3 D9 D10 D11 D12 D13 D14 D15 D2 D3 D4 D5 D6 D7 D8 D0 D1 8 7 6 5 UVDD LVDD MB3771PF CT VSC OUT GND U5 (3F4) XWRL (3F4) XRD (3F6) A[0:23] UVDD (3D6) D[0:15] GND OUT LVDD N.C DT0 DT1 HVDD DT2 DT3 DT4 DT5 DT6 DT7 DT8 VSS DT9 DT10 DT11 DT12 DT13 DT14 DT15 HVDD XWRH XWRL XRD AD0 AD1 AD2 AD3 VSS AD4 AD5 AD6 AD7 AD8 AD9 AD10 HVDD AD11 AD12 AD13 AD14 AD15 AD16 AD17 N.C VSS 0.1u C40 HVDD XRESET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 U1 BCLK XRESET (3F5)(G6) HVDD A18 A19 A20 A21 A22 A23 33K R41 4 DSO (B6) DS1O (B6) 1000p C24 D4 1 2 MA739 (C5) XHDASOP (B3) SG8002JC-25M-PCMB 100p C8 R42 5p C7 Shortest Pattern FA10MDP(C6) LED4 LED3 TLG124 TLG124 S1R72801F00A1 3 4 SW(SKHHAL) SW1 C42 C43 C44 0.1u 0.1u 0.1u 0.1u C41 UVDD XHCS1 XHCS0 HDA2 HDA0 XHPDAG HDA1 HINTRO XHDMACK 0.1u JUMP-3 JP3 2 (B6) (B6) (B5) (B6) DS11 DS12 DPCO DO1K 1 CPCP8 P21 3 0 XRESFT (G1) 4.7K PLLS1 (C6) PLLS0 (C6) (A3) (A3) (A3) (A3) (A3) (A3) (A3) (A3) 1 X2SPDX(C6) HIORDY XHOR XHOW HDMARO HDD15 HDDD0 HDD14 (A3) (A3) (A3) (A3) (A4) (A4) (A4) OE CP CP7 CP CP6 CP CP5 CP CP4 1 1 1 1 X2 8 V CC CP CP3 CP CP2 1 1 C46 C47 MSC ON 0.1u 0.1u 0.1u C45 LVDD 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 R47 1K VSS N.C P21 P20 XCE10EX XCE9 monxWait XCE6 HVDD TO0 TO1 TO2 TO3 TO4 TO5 TO6 TO7 TI8 Monxint VSS VSS VSS VSS LREQ LVDD SCLK VSS CNA XISO BHEN CTL0 CTL1 D0 D1 D2 LVDD D3 D4 D5 D6 D7 PD LPS LINKON N.C LVDD R46 1K Monxint TH TH5 (1D4) JUMPER JP5 1 2 JUMPER JP6 1 2 UVDD LVDD LD3 (1D4) LD4 (1D4) LD5 (1D4) LD6 (1D4) LD7 (1D4) PD (1D4) LPS (1C4) LINKON (1E6) CTRL0 (1D4) CTRL1 (1D4) LD0 (1D4) LD1 (1D4) LD2 (1D4) CNA SCLK (1D4) 1 2 D3V HVDD D3V CP CP1 TH TH1 TH TH2 (3G4) NC1 NC2 LREQ (1D4) 1 WAIT 1 1 XCE10EX 1 FT1D-2M 1 Toggle SW3 3 2 NC1 NC2 2 Momentary FT1F-2M 1 SW2 3 4 3 1 TLY124 LED3 GND CP CP9 (G2) XHDASP (F6) FA10MD2 (F6) PLLS1 (F6) PLLS0 (F6) X2SPDX SW DIP-2 DSW3 HVDD 10K 10K 10K 10K R60 R61 R62 R63 D3V TH TH4 TH TH3 1 1 HDD1 HDD13 HDD2 HDD12 HDD3 HDD11 HDD4 10K 10K R58 R59 CON40 RESET GND D07 D08 D06 D09 D05 D10 D04 D11 D03 D12 D02 D13 D01 D14 D0 D15 GND NC DMARQ GND DIDW GND DIDR GND IORDY CSEL DMACK GND INTRQ NC DA1 PDIAG DA0 DA2 CS0 CS1 DASP GND CN5 DSK LVDD 4 3 2 1 R48 SW DIP-4 DSW2 510 5 6 7 8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 33 (G6) DST0 (F6) DPCO (F6) DST1 (F6) DST2 HDA1 XHPDAG HDA0 HDA2 XHCS0 XHCS1 R27 HINTRO 33 R28 0 R29 33 R30 33 R31 33 R32 33 R33 XHDASP (G2) 82 22 82 (F2) (F2) (F2) (F2) (F2) (F2) (F2) (F2) R25 HIORDY (F2) R26 XHDMACK (F2) R24 XHOR 22 22 R22 HIDMARO (F2) R23 XHOW (F2) XHRST (E2) HDD7 HDD8 (E2) HDD6 (E2) HDD9 (E2) HDD5 (E2) HDD10 (E2) HDD4 (E2) HDD11 (E2) HDD3 (E2) HDD12 (E2) HDD2 (E2) HDD13 (E2) HDD1 (F2) HDD14 (F2) HDD0 (F2) HDD15 (F2) (F2) 82 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R79 (G6) DSO R34 33 Pattern Length is within 5cm (F6) DCLK RM1 8 7 33 6 5 RM2 8 7 33 6 5 RM3 8 7 33 6 5 RM4 8 7 33 6 5 HVDD 1K R64 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 (A4) (A4) (A4) (A4) (A4) (A4) (A4) Not mounted yet HVDD CON10 1 2 3 4 5 6 7 8 9 10 ICD I/F CN4 0 R69 VSS N.C BCLK HCLK VSS ICEMD XRESET XNMI HVDD DSIO P10 VSS OSC4 OSC3 VSS P11 P12 P13 P14 HVDD EA10MD2 EA10MD1 EA10MD0 PLLS1 PLLS0 VSS PLLC VSS RAMTST X2SPDX P07 P06 P05 P04 P03 P02 VSS P01 P00 XWAIT K67 K66 P23 P22 N.C LVDD LVDD N.C AD18 AD19 AD20 AD21 AD22 AD23 FLSTST XHDASP VSS TVEP XHCS1 XHCS0 HDA2 HDA0 XHPDIAG HDA1 HINTRQ XHDMACK HVDD HIORDY XHIOR XHIOW HDMARQ HDD15 HDD0 HDD14 VSS HDD1 HDD13 HDD2 HDD12 HDD3 HDD11 HDD4 HVDD HDD10 HDD5 HDD9 HDD8 HDD8 HDD7 XHRST N.C VSS 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 HDD10 HDD5 HDD9 HDD6 HDD8 HDD7 XHRST (A4) (A4) (A4) (A4) (A4) (A4) (A5) 5.6K R68 EPSON 0 104 R65 C39 S1R72801F00A S1R72801F00A (2H2) A[1:18] D[0:15] (2H5) U4 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 HVDD 25 24 23 22 21 20 19 18 8 7 6 5 4 3 2 1 48 17 HVDD R66 10K 29 29 (2G1) XRESET 29 D0 A0 D1 A1 D2 A2 D3 A3 D4 A4 D5 A5 D6 A6 D7 A7 D8 A8 D9 A9 D10 A10 D11 A11 D12 A12 D13 A13 D14 A14 A15 D55/A-1 A16 NC A17 NC NC NC NC CE 29 31 33 35 38 40 42 44 30 32 34 36 39 41 43 45 RY/BY RESET VCC BYTE 15 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 9 10 13 14 16 HVDD 37 C48 0.1u (2H4) (2H4) 29 29 XRD XWRL OE OE GND GND 46 27 1 MBM29F400TC-70PFTN JP4 JUMP-3 2 3 (2D5) XCE10EX HVDD R67 10K U3 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 5 4 3 2 1 44 43 42 27 26 25 24 21 20 19 18 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 40 39 6 17 41 xUB xLB xCS xWE xOE D0 D1 D2 D3 D4 D5 D6 D7 7 8 9 10 13 14 15 16 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 29 30 31 32 35 36 37 38 D9 D10 D11 D12 D13 D14 D15 D15 VCC VCC 11 33 VSS VSS 12 34 HVDD C49 0.1u TC551664BFT Note: The circuit of this sheet is an example of connection when an external ROM and SRAM are connected during the process of system development. This circuit is not required on a system of finished product. EPSON 105 S1R72801F00A 11. SHAPE OF PACKAGE Plastic QFP20-184 pin 220.4 200.1 138 93 200.1 220.4 92 139 INDEX 47 184 1.40.1 46 0.4 +0.05 0.16 -0.03 +0.05 0.125 -0.025 0 10 0.50.2 0.1 1.7Max. 1 1 106 EPSON International Sales Operations AMERICA ASIA EPSON ELECTRONICS AMERICA, INC. HEADQUARTERS EPSON (CHINA) CO., LTD. 1960 E. Grand Avenue El Segundo, CA 90245, U.S.A. Phone : +1-310-955-5300 Fax : +1-310-955-5400 28F, Beijing Silver Tower 2# North RD DongSanHuan ChaoYang District, Beijing, CHINA Phone : 64106655 Fax : 64107319 SHANGHAI BRANCH SALES OFFICES West 150 River Oaks Parkway San Jose, CA 95134, U.S.A. Phone : +1-408-922-0200 Fax : +1-408-922-0238 Central 101 Virginia Street, Suite 290 Crystal Lake, IL 60014, U.S.A. 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EPSON EUROPE ELECTRONICS GmbH HEADQUARTERS No. 1 Temasek Avenue, #36-00 Millenia Tower, SINGAPORE 039192 Phone : +65-337-7911 Fax : +65-334-2716 Riesstrasse 15 80992 Munich, GERMANY Phone : +49- (0) 89-14005-0 SEIKO EPSON CORPORATION KOREA OFFICE Fax : +49- (0) 89-14005-110 SALES OFFICE Altstadtstrasse 176 51379 Leverkusen, GERMANY Phone : +49- (0) 2171-5045-0 Fax : +49- (0) 2171-5045-10 50F, KLI 63 Bldg., 60 Yoido-dong Youngdeungpo-Ku, Seoul, 150-763, KOREA Phone : 02-784-6027 Fax : 02-767-3677 SEIKO EPSON CORPORATION ELECTRONIC DEVICES MARKETING DIVISION UK BRANCH OFFICE Unit 2.4, Doncastle House, Doncastle Road Bracknell, Berkshire RG12 8PE, ENGLAND Phone : +44- (0) 1344-381700 Fax : +44- (0) 1344-381701 FRENCH BRANCH OFFICE 1 Avenue de l' Atlantique, LP 915 Les Conquerants Z.A. de Courtaboeuf 2, F-91976 Les Ulis Cedex, FRANCE Phone : +33- (0) 1-64862350 Fax : +33- (0) 1-64862355 BARCELONA BRANCH OFFICE Barcelona Design Center Edificio Prima Sant Cugat Avda. Alcalde Barrils num. 64-68 SPAIN E-08190 Sant Cugat del Valles, Phone : +34-93-544-2490 Fax: +34-93-544-2491 Electronic Device Marketing Department IC Marketing & Engineering Group 421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN Phone: +81-(0)42-587-5816 Fax: +81-(0)42-587-5624 ED International Marketing Department Europe & U.S.A. 421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN Phone: +81-(0)42-587-5812 Fax: +81-(0)42-587-5564 ED International Marketing Department Asia 421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN Phone: +81-(0)42-587-5814 Fax: +81-(0)42-587-5110 In pursuit of "Saving" Technology, Epson electronic devices. Our lineup of semiconductors, liquid crystal displays and quartz devices assists in creating the products of our customers' dreams. Epson IS energy savings. NOTICE No parts of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind aristing out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export licence from teh Ministry of International Trade and Industry or other approval from another government agency. (c) SEIKO EPSON CORPORATION 2001, All rights reserved. All other product names mentioned herein are trademarks and/or registered trademarkes of their respective companies. 4.5mm MF1385-04 S1R72801F00A Technical Manual IEEE1394 Controller S1R72801F00A Technical Manual S1R72801F00A Technical Manual ELECTRONIC DEVICES MARKETING DIVISION EPSON Electronic Devices Website http://www.epson.co.jp/device/ This manual was made with recycle paper, and printed using soy-based inks. First issue December,2000 Printed March,2001 in Japan H A 4.5mm