4S29CD016GS29CD016_00_A4 November 5, 2004
Advance Information
Table of Contents
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . .7
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Block Diagram of Simultaneous Read/Write
Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 10
Special Package Handling Instructions . . . . . . . 11
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Logic Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 14
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 15
Table 1. Device Bus Operation . . . . . . . . . . . . . . . . . 15
VersatileI/O™ (V
IO
) Control .............................................................. 15
Requirements for Reading Array Data ........................................... 16
Simultaneous Read/Write
Operations Overview and Restrictions .......................................... 16
Overview ............................................................................................................................16
Restrictions ........................................................................................................................16
Table 2. Bank Assignment for Boot Bank
Sector Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Simultaneous Read/Write Operations With Zero Latency ..... 17
Table 3. Ordering Option 00 . . . . . . . . . . . . . . . . . . . 17
Table 4. Ordering Option 01 . . . . . . . . . . . . . . . . . . . 17
Writing Commands/Command Sequences ................................... 17
Accelerated Program and Erase Operations ..........................................................18
Autoselect Functions ......................................................................................................18
Automatic Sleep Mode (ASM) ...........................................................18
Standby Mode ...................................................................................................................18
RESET#: Hardware Reset Pin ............................................................ 19
Output Disable Mode ...........................................................................19
Autoselect Mode ................................................................................... 19
Table 5. S29CD016G Autoselect Codes (High Voltage Meth-
od) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Asynchronous Read Operation (Non-Burst) ...............................20
Figure 1. Asynchronous Read Operation . . . . . . . . . . 21
Synchronous (Burst) Read Operation ............................................. 21
Linear Burst Read Operations ........................................................... 21
Table 6. 32- Bit Linear and Burst Data Order . . . . . . . 22
CE# Control in Linear Mode ...................................................................................... 23
ADV# Control In Linear Mode .................................................................................. 23
RESET# Control in Linear Mode ............................................................................... 23
OE# Control in Linear Mode ..................................................................................... 23
IND/WAIT# Operation in Linear Mode ................................................................. 23
Table 7. Valid Configuration Register Bit Definition for IND/
WAIT# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 2. End of Burst Indicator (IND/WAIT#) Timing for
Linear 4-Double-Word Burst Operation . . . . . . . . . . . 24
Burst Access Timing Control ......................................................................................24
Initial Burst Access Delay Control ............................................................................24
Table 8. Burst Initial Access Delay . . . . . . . . . . . . . . 24
Figure 3. Burst Access Timing . . . . . . . . . . . . . . . . . 25
Burst CLK Edge Data Delivery ................................................................................... 25
Burst Data Hold Control ............................................................................................. 25
Asserting RESET# During A Burst Access .............................................................. 25
Configuration Register ........................................................................ 25
Table 9. Configuration Register Definitions . . . . . . . . . 26
Table 10. Configuration Register After Device Reset . . 28
Initial Access Delay Configuration .................................................. 28
Sector Protection . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Sector and Sector Groups ...........................................................................................28
Persistent Sector Protection .......................................................................................28
Password Sector Protection ........................................................................................28
WP# Hardware Protection .........................................................................................28
Persistent Sector Protection ............................................................ 29
Persistent Protection Bit (PPB) .................................................................................. 29
Persistent Protection Bit Lock (PPB Lock) .............................................................29
Dynamic Protection Bit (DYB) ...................................................................................29
Table 11. Sector Protection Schemes . . . . . . . . . . . . . 30
Persistent Sector Protection Mode Locking Bit ...........................31
Password Protection Mode .................................................................31
Password and Password Mode Locking Bit ...................................32
64-bit Password ............................................................................................................... 32
Write Protect (WP#) ..........................................................................33
SecSi™ (Secured Silicon) Sector Protection ..................................33
SecSi Sector Protection Bit ................................................................34
Persistent Protection Bit Lock ..........................................................34
Hardware Data Protection ................................................................34
Low V
CC
Write Inhibit .................................................................................................. 34
Write Pulse “Glitch” Protection ................................................................................ 34
Logical Inhibit ................................................................................................................... 35
Power-Up Write Inhibit ................................................................................................ 35
V
CC
and V
IO
Power-up And Power-down Sequencing ...................................... 35
Table 12. Sector Addresses for Ordering Option 00 . . . 35
Table 13. Sector Addresses for Ordering Option 01 . . . 37
Common Flash Memory Interface (CFI) . . . . . . . 39
Table 14. CFI Query Identification String . . . . . . . . . . 39
Table 15. CFI System Interface String . . . . . . . . . . . . 40
Table 16. Device Geometry Definition . . . . . . . . . . . . 41
Table 17. CFI Primary Vendor-Specific Extended Query 42
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 44
Reading Array Data in Non-burst Mode ...................................... 44
Reading Array Data in Burst Mode ................................................ 44
Read/Reset Command .........................................................................45
Autoselect Command ..........................................................................45
Program Command Sequence ...........................................................45
Accelerated Program Command ..................................................... 46
Unlock Bypass Command Sequence .............................................. 46
Figure 4. Program Operation . . . . . . . . . . . . . . . . . . 47
Unlock Bypass Entry Command .................................................................................47
Unlock Bypass Program Command ..........................................................................48
Unlock Bypass Chip Erase Command ......................................................................48
Unlock Bypass CFI Command ....................................................................................48
Unlock Bypass Reset Command ................................................................................48
Chip Erase Command ......................................................................... 48
Sector Erase Command ..................................................................... 49
Figure 5. Erase Operation . . . . . . . . . . . . . . . . . . . . 50
Sector Erase and Program Suspend Command .......................... 50
Sector Erase and Program Suspend Operation Mechanics .......51
Table 18. Allowed Operations During Erase/Program Sus-
pend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Sector Erase and Program Resume Command ............................52
Configuration Register Read Command ........................................52
Configuration Register Write Command ......................................52
Common Flash Interface (CFI) Command ....................................52
SecSi Sector Entry Command ............................................................53