19-2173; Rev 1; 7/06 Dual 10-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Parallel Outputs -40C to +85C 48 TQFP-EP* *EP = Exposed paddle. +Denotes lead-free package. 37 38 39 40 41 42 43 44 36 2 35 3 34 4 33 5 32 6 31 MAX1183 7 30 8 29 9 28 27 10 EP 11 26 25 24 23 22 21 12 D1A D0A OGND OVDD OVDD OGND D0B D1B D2B D3B D4B D5B GND VDD VDD GND T/B SLEEP PD OE D9B D8B D7B D6B Ultrasound 45 1 20 COM VDD GND INA+ INAVDD GND INBINB+ GND VDD CLK 46 REFN REFP REFIN REFOUT D9A D8A D7A D6A D5A D4A D3A D2A Pin Configuration 13 Video Application MAX1183ECM+ 19 Instrumentation 48 TQFP-EP* 18 Multichannel IF Sampling PIN-PACKAGE -40C to +85C 17 I/Q Channel Digitization PART 16 High-Resolution Imaging TEMP RANGE MAX1183ECM 15 Applications Ordering Information 47 The MAX1183 features parallel, CMOS-compatible three-state outputs. The digital output format can be set to two's complement or straight offset binary through a single control pin. The device provides for a separate output power supply of 1.7V to 3.6V for flexible interfacing. The MAX1183 is available in a 7mm 7mm, 48-pin TQFP package, and is specified for the extended industrial (-40C to +85C) temperature range. Pin-compatible lower and higher speed versions of the MAX1183 are also available. See Table 2 at end of data sheet for a list of pin-compatible versions. Refer to the MAX1180 data sheet for 105Msps, the MAX1181 data sheet for 80Msps, the MAX1182 data sheet for 65Msps, and the MAX1184 data sheet for 20Msps. In addition to these speed grades, this family includes a multiplexed output version, for which digital data is presented timeinterleaved and on a single, parallel 10-bit output port. 48 An internal 2.048V precision bandgap reference sets the full-scale range of the ADC. A flexible reference structure allows the use of this internal or an externally derived reference, if desired for applications requiring increased accuracy or a different input voltage range. Single 3V Operation Excellent Dynamic Performance: 59.6dB SNR at fIN = 20MHz 73dB SFDR at fIN = 20MHz Low Power: 40mA (Normal Operation) 2.8mA (Sleep Mode) 1A (Shutdown Mode) 0.02dB Gain and 0.25 Phase Matching Wide 1VP-P Differential Analog Input Voltage Range 400MHz -3dB Input Bandwidth On-Chip 2.048V Precision Bandgap Reference User-Selectable Output Format--Two's Complement or Offset Binary 48-Pin TQFP Package with Exposed Paddle for Improved Thermal Dissipation 14 The MAX1183 is a 3V, dual 10-bit analog-to-digital converter (ADC) featuring fully differential wideband trackand-hold (T/H) inputs, driving two pipelined, nine-stage ADCs. The MAX1183 is optimized for low-power, high dynamic performance applications in imaging, instrumentation, and digital communication applications. This ADC operates from a single 2.7V to 3.6V supply, consuming only 120mW while delivering a typical signal-to-noise ratio (SNR) of 59.6dB at an input frequency of 20MHz and a sampling rate of 40Msps. The T/H driven input stages incorporate 400MHz (-3dB) input amplifiers. The converters may also be operated with single-ended inputs. In addition to low operating power, the MAX1183 features a 2.8mA sleep mode as well as a 1A power-down mode to conserve power during idle periods. Features 48 TQFP-EP Functional Diagram appears at end of data sheet. NOTE: THE PIN 1 INDICATOR FOR LEAD-FREE PACKAGE IS REPLACED BY A "+" SIGN. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. 1 MAX1183 General Description MAX1183 Dual 10-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Parallel Outputs ABSOLUTE MAXIMUM RATINGS VDD, OVDD to GND .............................................. -0.3V to +3.6V OGND to GND.......................................................-0.3V to +0.3V INA+, INA-, INB+, INB- to GND ...............................-0.3V to VDD REFIN, REFOUT, REFP, REFN, COM, CLK to GND .................................-0.3V to (VDD + 0.3V) OE, PD, SLEEP, T/B D9A-D0A, D9B-D0B to OGND ...........-0.3V to (OVDD + 0.3V) Continuous Power Dissipation (TA = +70C) 48-Pin TQFP-EP (derate 30.4mW/C above +70C) ..........................2430mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-60C to +150C Lead Temperature (soldering, 10s) .................................+300C Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = 3V, OVDD = 2.5V, 0.1F and 1.0F capacitors from REFP, REFN, and COM to GND, REFOUT connected to REFIN through a 10k resistor, VIN = 2VP-P (differential with respect to COM), CL = 10pF at digital outputs (Note 1), fCLK = 40MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS LSB DC ACCURACY Resolution 10 Bits Integral Nonlinearity INL fIN = 7.51MHz 0.5 1.7 Differential Nonlinearity DNL fIN = 7.51MHz, no missing codes guaranteed 0.25 1.0 LSB Offset Error <1 1.8 % FS Gain Error 0 2 % FS ANALOG INPUT Differential Input Voltage Range VDIFF Common-Mode Input Voltage Range VCM Input Resistance RIN Input Capacitance CIN Differential or single-ended inputs Switched capacitor load 1.0 V VDD/2 0.5 V 50 k 5 pF 5 Clock Cycles CONVERSION RATE Maximum Clock Frequency fCLK 40 Data Latency MHz DYNAMIC CHARACTERISTICS Signal-to-Noise Ratio (Note 3) SNR Signal-to-Noise and Distortion (Note 3) SINAD Spurious-Free Dynamic Range (Note 3) SFDR Total Harmonic Distortion (First 4 harmonics) (Note 3) THD Third-Harmonic Distortion (Note 3) HD3 Intermodulation Distortion IMD 2 fINA or B = 7.51MHz, TA = +25C 57.3 59.6 fINA or B = 20MHz, TA = +25C 56.8 59.6 fINA or B = 7.51MHz, TA = +25C 57 59.4 56.5 59 fINA or B = 7.51MHz, TA = +25C 65 76 fINA or B = 20MHz, TA = +25C 65 73 fINA or B = 20MHz, TA = +25C dB dB dBc fINA or B = 7.51MHz, TA = +25C -73 -64 fINA or B = 20MHz, TA = +25C -73 -63 fINA or B = 7.51MHz -76 fINA or B = 20MHz -73 fINA or B = 11.6066MHz at -6.5dBFS, fINA or B = 13.3839MHz at -6.5dBFS (Note 4) -78 _______________________________________________________________________________________ dBc dB dBc Dual 10-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Parallel Outputs (VDD = 3V, OVDD = 2.5V, 0.1F and 1.0F capacitors from REFP, REFN, and COM to GND, REFOUT connected to REFIN through a 10k resistor, VIN = 2VP-P (differential with respect to COM), CL = 10pF at digital outputs (Note 1), fCLK = 40MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 2) PARAMETER SYMBOL Small-Signal Bandwidth Full-Power Bandwidth FPBW CONDITIONS MIN TYP MAX UNITS Input at -20dBFS, differential inputs 500 MHz Input at -0.5dBFS, differential inputs 400 MHz Aperture Delay tAD 1 ns Aperture Jitter tAJ 2 psRMS 2 ns Overdrive Recovery Time For 1.5 x full-scale input Differential Gain 1 % 0.25 Degrees 0.2 LSBRMS REFOUT 2.048 3% V TCREF 60 ppm/ C 1.25 mV/mA Differential Phase Output Noise INA+ = INA- = INB+ = INB- = COM INTERNAL REFERENCE Reference Output Voltage Reference Temperature Coefficient Load Regulation BUFFERED EXTERNAL REFERENCE (VREFIN = 2.048V) REFIN Input Voltage VREFIN 2.048 V Positive Reference Output Voltage VREFP 2.012 V Negative Reference Output Voltage VREFN 0.988 V Differential Reference Output Voltage Range VREF REFIN Resistance RREFIN >50 M Maximum REFP, COM Source Current ISOURCE 5 mA Maximum REFP, COM Sink Current ISINK -250 A ISOURCE 250 A ISINK -5 mA Maximum REFN Source Current Maximum REFN Sink Current VREF = VREFP - VREFN 0.95 1.024 1.10 V UNBUFFERED EXTERNAL REFERENCE (VREFIN = AGND, reference voltage applied to REFP, REFN, and COM) REFP, REFN Input Resistance RREFP, RREFN Measured between REFP and COM and REFN and COM Differential Reference Input Voltage Range VREF VREF = VREFP - VREFN COM Input Voltage Range 4 k 1.024 10% V VCOM VDD/2 10% V REFP Input Voltage VREFP VCOM + VREF/2 V REFN Input Voltage VREFN VCOM VREF/2 V _______________________________________________________________________________________ 3 MAX1183 ELECTRICAL CHARACTERISTICS (continued) MAX1183 Dual 10-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Parallel Outputs ELECTRICAL CHARACTERISTICS (continued) (VDD = 3V, OVDD = 2.5V, 0.1F and 1.0F capacitors from REFP, REFN, and COM to GND, REFOUT connected to REFIN through a 10k resistor, VIN = 2VP-P (differential with respect to COM), CL = 10pF at digital outputs (Note 1), fCLK = 40MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DIGITAL INPUTS (CLK, PD, OE, SLEEP, T/B) Input High Threshold Input Low Threshold Input Hysteresis Input Leakage Input Capacitance CLK 0.8 x VDD PD, OE, SLEEP, T/B 0.8 x OVDD VIH V CLK 0.2 x VDD PD, OE, SLEEP, T/B 0.2 x OVDD VIL VHYST 0.1 V IIH VIH = OVDD or VDD (CLK) 5 IIL VIL = 0V 5 CIN V 5 A pF DIGITAL OUTPUTS (D9A-D0A, D9B-D0B) Output Voltage Low VOL ISINK = -200A Output Voltage High VOH ISOURCE = 200A Three-State Leakage Current ILEAK OE = OVDD Three-State Leakage Capacitance COUT OE = OVDD 0.2 OVDD - 0.2 V V 10 5 A pF POWER REQUIREMENTS Analog Supply Voltage Range VDD 2.7 3 3.6 V Output Supply Voltage Range OVDD 1.7 2.5 3.6 V Operating, fINA or B = 20MHz at -0.5dBFS 40 60 Sleep mode 2.8 Analog Supply Current IVDD Shutdown, clock idle, PD = OE = OVDD Output Supply Current IOVDD 5.8 Sleep mode 100 Shutdown, clock idle, PD = OE = OVDD Power Dissipation PDISS PSRR 15 10 Operating, fINA or B = 20MHz at -0.5dBFS 120 180 Sleep mode 8.4 3 A mA 2 Shutdown, clock idle, PD = OE = OVDD Power-Supply Rejection Ratio 1 Operating, CL = 15pF, fINA or B = 20MHz at -0.5dBFS mA 45 A mW W Offset 0.2 mV/V Gain 0.1 %V TIMING CHARACTERISTICS CLK Rise to Output Data Valid tDO Figure 3 (Note 5) 5 8 ns Output Enable Time tENABLE Figure 4 10 ns Output Disable Time tDISABLE Figure 4 1.5 ns 4 _______________________________________________________________________________________ Dual 10-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Parallel Outputs (VDD = 3V, OVDD = 2.5V, 0.1F and 1.0F capacitors from REFP, REFN, and COM to GND, REFOUT connected to REFIN through a 10k resistor, VIN = 2VP-P (differential with respect to COM), CL = 10pF at digital outputs (Note 1), fCLK = 40MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP CLK Pulse Width High tCH Figure 3, clock period: 25ns 12.5 3.8 CLK Pulse Width Low tCL Figure 3, clock period: 25ns 12.5 3.8 Wake up from sleep mode (Note 6) 0.41 Wake up from shutdown (Note 6) 1.5 Wake-Up Time tWAKE MAX UNITS ns ns s CHANNEL-TO-CHANNEL MATCHING Crosstalk fINA or B = 20MHz at -0.5dBFS -70 Gain Matching fINA or B = 20MHz at -0.5dBFS 0.02 dB Phase Matching fINA or B = 20MHz at -0.5dBFS 0.25 0.2 dB Degrees Note 1: Equivalent dynamic performance is obtainable over full OVDD range with reduced CL. Note 2: Specifications at +25C are guaranteed by production test and < +25C are guaranteed by design and characterization. Note 3: SNR, SINAD, THD, SFDR, and HD3 are based on an analog input voltage of -0.5dBFS referenced to a 1.024V full-scale input voltage range. Note 4: Intermodulation distortion is the total power of the intermodulation products relative to the individual carrier. This number is 6dB better, if referenced to the two-tone envelope. Note 5: Digital outputs settle to VIH, VIL. Parameter guaranteed by design. Note 6: With REFIN driven externally, REFP, COM, and REFN are left floating while powered down. Typical Operating Characteristics (VDD = 3V, OVDD = 2.5V, VREFIN = 2.048V, differential input at -0.5dBFS, fCLK = 40.0006MHz, CL 10pF, TA = +25C, unless otherwise noted.) -30 -40 -50 -60 HD3 -70 HD2 -80 CHB -20 -30 -40 -50 -60 HD3 HD2 -70 0 -20 -30 -40 -50 -70 -90 -90 -90 -100 -100 4 6 8 10 12 14 16 18 20 ANALOG INPUT FREQUENCY (MHz) HD3 -60 -100 2 CHA HD2 -80 -80 0 fCLK = 40.0006MHz fINA = 24.9662MHz fINB = 19.888MHz AINA = -0.552dBFS -10 AMPLITUDE (dB) AMPLITUDE (dB) -20 fCLK = 40.0006MHz fINB = 6.1475MHz fINA = 7.5343MHz AINB = -0.534dBFS MAX1183 toc02 CHA 0 -10 AMPLITUDE (dB) fCLK = 40.0006MHz fINA = 7.5343MHz fINB = 6.1475MHz AINA = -0.498dBFS MAX1183 toc01 0 -10 FFT PLOT CHA (DIFFERENTIAL INPUT, 8192-POINT DATA RECORD) FFT PLOT CHB (DIFFERENTIAL INPUT, 8192-POINT DATA RECORD) MAX1183 toc03 FFT PLOT CHA (DIFFERENTIAL INPUT, 8192-POINT DATA RECORD) 0 2 4 6 8 10 12 14 16 18 20 ANALOG INPUT FREQUENCY (MHz) 0 2 4 6 8 10 12 14 16 18 20 ANALOG INPUT FREQUENCY (MHz) _______________________________________________________________________________________ 5 MAX1183 ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (continued) (VDD = 3V, OVDD = 2.5V, VREFIN = 2.048V, differential input at -0.5dBFS, fCLK = 40.0006MHz, CL 10pF, TA = +25C, unless otherwise noted.) FFT PLOT CHB (DIFFERENTIAL INPUT, 8192-POINT DATA RECORD) -50 HD3 -60 -70 59 fIN1 -60 -80 -90 IM2 2 4 6 8 10 12 14 16 18 20 58 CHB 57 IM3 IM2 IM3 56 55 -100 0 2 4 6 8 10 12 14 16 18 20 ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) 10 20 30 40 50 60 70 ANALOG INPUT FREQUENCY (MHz) SIGNAL-TO-NOISE PLUS DISTORTION vs. ANALOG INPUT FREQUENCY TOTAL HARMONIC DISTORTION vs. ANALOG INPUT FREQUENCY SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT FREQUENCY 60 CHA -60 80 90 MAX1183 toc09 -50 MAX1183 toc07 62 0 MAX1183 toc08 0 MAX1183 toc06 CHA -50 -90 60 fIN2 -40 -80 -100 CHB 80 CHA 58 CHB -70 -80 SFDR (dBc) THD (dBc) SINAD (dB) -30 -70 HD2 MAX1183 toc05 -20 61 SNR (dB) -40 fCLK = 40.0006MHz fIN1 = 11.6066MHz fIN2 = 13.3834MHz AIN1 = AIN2 = -6.5dBFS -10 AMPLITUDE (dB) -30 0 MAX1183 toc04 -20 AMPLITUDE (dB) CHB fCLK = 40.0006MHz fINA = 24.9662MHz fINB = 19.888MHz AINB = -0.525dBFS SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT FREQUENCY TWO-TONE IMD PLOT (DIFFERENTIAL INPUT, 8192-POINT DATA RECORD) 0 -10 CHB 70 60 CHA 56 -90 -100 0 10 20 30 40 50 60 70 ANALOG INPUT FREQUENCY (MHz) 80 40 0 10 20 30 40 50 60 70 ANALOG INPUT FREQUENCY (MHz) 80 6 6 VIN = 100mVP-P 4 2 0 60 0 -2 -4 -4 -6 -6 -8 55 SNR (dB) GAIN (dB) -2 10 100 ANALOG INPUT FREQUENCY (MHz) 1000 50 45 40 -8 1 80 65 2 0 10 20 30 40 50 60 70 ANALOG INPUT FREQUENCY (MHz) SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT POWER (fIN = 19.888MHz) MAX1183 toc11 SMALL-SIGNAL INPUT BANDWIDTH vs. ANALOG INPUT FREQUENCY, SINGLE-ENDED MAX1183 toc10 FULL-POWER INPUT BANDWIDTH vs. ANALOG INPUT FREQUENCY, SINGLE-ENDED 4 6 50 MAX1183 toc12 54 GAIN (dB) MAX1183 Dual 10-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Parallel Outputs 35 1 10 100 ANALOG INPUT FREQUENCY (MHz) 1000 -20 -16 -12 -8 -4 ANALOG INPUT POWER (dBFS) _______________________________________________________________________________________ 0 Dual 10-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Parallel Outputs -60 MAX1183 toc15 60 80 MAX1183 toc14 -55 MAX1183 toc13 65 SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT POWER (fIN = 19.888MHz) TOTAL HARMONIC DISTORTION vs. ANALOG INPUT POWER (fIN = 19.888MHz) SIGNAL-TO-NOISE PLUS DISTORTION vs. ANALOG INPUT POWER (fIN = 19.888MHz) 76 50 -65 SFDR (dBc) THD (dBc) SINAD (dB) 55 -70 72 68 45 -75 40 64 -80 35 -12 -8 -4 60 -20 0 ANALOG INPUT POWER (dBFS) INTEGRAL NONLINEARITY DNL (LSB) -0.1 -0.2 -0.2 -0.3 0.4 -0.3 0 128 256 384 512 640 768 896 1024 0.3 CHB 0.2 0.1 CHA 0 -0.1 0 128 256 384 512 640 768 896 1024 -40 -15 10 35 60 DIGITAL OUTPUT CODE DIGITAL OUTPUT CODE TEMPERATURE (C) OFFSET ERROR vs. TEMPERATURE ANALOG SUPPLY CURRENT vs. ANALOG SUPPLY VOLTAGE ANALOG SUPPLY CURRENT vs. TEMPERATURE 50 MAX1183 toc19 0.2 0.1 50 MAX1183 toc20 46 46 85 -0.1 IVDD (mA) 0 CHB 42 IVDD (mA) INL (LSB) 0 -0.1 0 GAIN ERROR vs. TEMPERATURE 0.1 0 -16 -12 -8 -4 ANALOG INPUT POWER (dBFS) 0.5 GAIN ERROR (% FS) 0.2 0.1 OFFSET ERROR (% FS) -20 MAX1183 toc17 0.2 0 DIFFERENTIAL NONLINEARITY 0.3 MAX1183 toc16 0.3 -16 -12 -8 -4 ANALOG INPUT POWER (dBFS) MAX1183 toc18 -16 MAX1183 toc21 -20 38 42 38 -0.2 34 34 -0.3 CHA -0.4 30 30 -40 -15 10 35 TEMPERATURE (C) 60 85 2.70 2.85 3.00 3.15 VDD (V) 3.30 3.45 3.60 -40 -15 10 35 60 85 TEMPERATURE (C) _______________________________________________________________________________________ 7 MAX1183 Typical Operating Characteristics (continued) (VDD = 3V, OVDD = 2.5V, VREFIN = 2.048V, differential input at -0.5dBFS, fCLK = 40.0006MHz, CL 10pF, TA = +25C, unless otherwise noted.) Typical Operating Characteristics (continued) (VDD = 3V, OVDD = 2.5V, VREFIN = 2.048V, differential input at -0.5dBFS, fCLK = 40.0006MHz, CL 10pF, TA = +25C, unless otherwise noted.) SNR/SINAD, -THD/SFDR vs. CLOCK DUTY CYCLE 0.3 0.2 0.1 80 70 SNR -THD 60 50 2.0020 2.0014 SINAD 2.70 2.85 3.00 3.15 3.30 3.45 VDD (V) 35 40 45 50 55 60 CLOCK DUTY CYCLE (%) 65 70 3.00 3.15 MAX1183 toc25 64,515 63,000 56,000 49,000 2.000 1.995 42,000 35,000 28,000 1.990 21,000 14,000 1.985 7,000 1.980 0 -40 -15 10 35 TEMPERATURE (C) 8 2.85 60 3.30 OUTPUT NOISE HISTOGRAM (DC INPUT) 70,000 COUNTS VREFOUT (V) 2.005 2.70 VDD (V) INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE 2.010 2.0002 1.9990 30 3.60 2.0008 1.9996 40 0 MAX1183 toc24 fINA = 7.5343MHz fINB = 6.1475MHz SFDR MAX1183 toc26 0.4 90 VREFOUT (V) OE = PD = OVDD SNR/SINAD, -THD/SFDR (dB, dBc) MAX1183 toc22 0.5 INTERNAL REFERENCE VOLTAGE vs. ANALOG SUPPLY VOLTAGE MAX1183 toc23 ANALOG POWER-DOWN CURRENT vs. ANALOG SUPPLY VOLTAGE IVDD (A) MAX1183 Dual 10-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Parallel Outputs 85 0 869 N-2 N-1 N 152 0 N+1 N+2 DIGITAL OUTPUT CODE _______________________________________________________________________________________ 3.45 3.60 Dual 10-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Parallel Outputs PIN NAME 1 FUNCTION COM Common-Mode Voltage Input/Output. Bypass to GND with a 0.1F capacitor. 2, 6, 11, 14, 15 VDD Analog Supply Voltage. Bypass each supply pin to GND with a 0.1F capacitor. The analog supply accepts an input range of 2.7V to 3.6V. 3, 7, 10, 13, 16 GND Analog Ground 4 INA+ Channel A Positive Analog Input. For single-ended operation connect signal source to INA+. 5 INA- Channel A Negative Analog Input. For single-ended operation connect INA- to COM. 8 INB- Channel B Negative Analog Input. For single-ended operation connect INB- to COM. 9 INB+ Channel B Positive Analog Input. For single-ended operation connect signal source to INB+. 12 CLK Converter Clock Input 17 T/B T/B selects the ADC digital output format. High: Two's complement. Low: Straight offset binary. 18 SLEEP 19 PD Power-Down Input. High: Power-down mode. Low: Normal operation. 20 OE Output Enable Input. High: Digital outputs disabled. Low: Digital outputs enabled. 21 D9B Three-State Digital Output, Bit 9 (MSB), Channel B 22 D8B Three-State Digital Output, Bit 8, Channel B 23 D7B Three-State Digital Output, Bit 7, Channel B 24 D6B Three-State Digital Output, Bit 6, Channel B 25 D5B Three-State Digital Output, Bit 5, Channel B 26 D4B Three-State Digital Output, Bit 4, Channel B 27 D3B Three-State Digital Output, Bit 3, Channel B 28 D2B Three-State Digital Output, Bit 2, Channel B 29 D1B Three-State Digital Output, Bit 1, Channel B 30 D0B Three-State Digital Output, Bit 0 (LSB), Channel B 31, 34 OGND Output Driver Ground 32, 33 OVDD Output Driver Supply Voltage. Bypass each supply pin to OGND with a 0.1F capacitor. The output driver supply accepts an input range of 1.7V to 3.6V. 35 D0A Three-State Digital Output, Bit 0 (LSB), Channel A 36 D1A Three-State Digital Output, Bit 1, Channel A 37 D2A Three-State Digital Output, Bit 2, Channel A 38 D3A Three-State Digital Output, Bit 3, Channel A 39 D4A Three-State Digital Output, Bit 4, Channel A 40 D5A Three-State Digital Output, Bit 5, Channel A Sleep Mode Input. High: Deactivates the two ADCs, but leaves the reference bias circuit active. Low: Normal operation. _______________________________________________________________________________________ 9 MAX1183 Pin Description Dual 10-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Parallel Outputs MAX1183 Pin Description (continued) PIN NAME 41 D6A Three-State Digital Output, Bit 6, Channel A FUNCTION 42 D7A Three-State Digital Output, Bit 7, Channel A 43 D8A Three-State Digital Output, Bit 8, Channel A 44 D9A Three-State Digital Output, Bit 9 (MSB), Channel A Internal Reference Voltage Output. May be connected to REFIN through a resistor or a resistor divider. 45 REFOUT 46 REFIN Reference Input. VREFIN = 2 x (VREFP - VREFN). Bypass to GND with a >1nF capacitor. 47 REFP Positive Reference Input/Output. Conversion range is (VREFP - VREFN). Bypass to GND with a > 0.1F capacitor. 48 REFN Negative Reference Input/Output. Conversion range is (VREFP - VREFN). Bypass to GND with a > 0.1F capacitor. -- EP Exposed Pad. Connect to analog ground. Detailed Description The MAX1183 uses a nine-stage, fully differential, pipelined architecture (Figure 1) that allows for highspeed conversion while minimizing power consumption. Samples taken at the inputs move progressively through the pipeline stages every half-clock cycle. Including the delay through the output latch, the total clock-cycle latency is five clock cycles. One-and-a-half bit (2-comparator) flash ADCs convert the held-input voltages into a digital code. The digitalVIN T/H FLASH ADC x2 to-analog converters (DACs) convert the digitized results back into analog voltages, which are then subtracted from the original held-input signals. The resulting error signals are then multiplied by two, and the residues are passed along to the next pipeline stages where the process is repeated until the signals have been processed by all nine stages. Digital error correction compensates for ADC comparator offsets in each of these pipeline stages and ensures no missing codes. VIN VOUT T/H FLASH ADC DAC 1.5 BITS x2 VOUT DAC 1.5 BITS 2-BIT FLASH ADC STAGE 1 STAGE 2 STAGE 8 2-BIT FLASH ADC STAGE 9 STAGE 1 DIGITAL CORRECTION LOGIC T/H VINA 10 D9A-D0A STAGE 2 STAGE 8 DIGITAL CORRECTION LOGIC T/H VINB 10 D9B-D0B VINA = INPUT VOLTAGE BETWEEN INA+ AND INA- (DIFFERENTIAL OR SINGLE ENDED) VINB = INPUT VOLTAGE BETWEEN INB+ AND INB- (DIFFERENTIAL OR SINGLE ENDED) Figure 1. Pipelined Architecture--Stage Blocks 10 ______________________________________________________________________________________ STAGE 9 Dual 10-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Parallel Outputs INTERNAL BIAS COM S5a S2a C1a S3a S4a INA+ OUT C2a S4c S1 OUT INAS4b C2b C1b S3b S5b S2b INTERNAL BIAS COM HOLD INTERNAL BIAS TRACK COM CLK HOLD TRACK C1a The full-scale range of the MAX1183 is determined by the internally generated voltage difference between REFP (V DD /2 + V REFIN /4) and REFN (V DD /2 VREFIN/4). The full-scale range for both on-chip ADCs is adjustable through the REFIN pin, which is provided for this purpose. REFOUT, REFP, COM (VDD/2), and REFN are internally buffered low-impedance outputs. The MAX1183 provides three modes of reference operation: * Internal reference mode * Buffered external reference mode * Unbuffered external reference mode In internal reference mode, connect the internal reference output REFOUT to REFIN through a resistor (e.g., 10k) or resistor divider, if an application requires a reduced full-scale range. For stability and noise filtering purposes, bypass REFIN with a >10nF capacitor to GND. In internal reference mode, REFOUT, COM, REFP, and REFN become low-impedance outputs. In buffered external reference mode, adjust the reference voltage levels externally by applying a stable and accurate voltage at REFIN. In this mode, COM, REFP, and REFN become outputs. REFOUT may be left open or connected to REFIN through a >10k resistor. In unbuffered external reference mode, connect REFIN to GND. This deactivates the on-chip reference buffers for REFP, COM, and REFN. With their buffers shut down, these nodes become high impedance and may be driven through separate external reference sources. Clock Input (CLK) S3a S4a INB+ OUT C2a S1 OUT INBS4b Analog Inputs and Reference Configurations S5a S2a S4c INTERNAL NONOVERLAPPING CLOCK SIGNALS The ADC inputs (INA+, INB+, INA- and INB-) can be driven either differentially or single-ended. Match the impedance of INA+ and INA-, as well as INB+ and INBand set the common-mode voltage to midsupply (VDD/2) for optimum performance. MAX1183 C2b C1b S3b S2b INTERNAL BIAS S5b The MAX1183's CLK input accepts CMOS-compatible clock signals. Since the interstage conversion of the device depends on the repeatability of the rising and falling edges of the external clock, use a clock with low jitter and fast rise and fall times (< 2ns). In particular, sampling occurs on the rising edge of the clock signal, requiring this edge to provide lowest possible jitter. Any significant aperture jitter would limit the SNR performance of the on-chip ADCs as follows: COM Figure 2. MAX1183 T/H Amplifiers 1 SNR = 20 x log 2 x x fIN x t AJ ______________________________________________________________________________________ 11 MAX1183 Input Track-and-Hold (T/H) Circuits Figure 2 displays a simplified functional diagram of the input track-and-hold (T/H) circuits in both track-and-hold mode. In track mode, switches S1, S2a, S2b, S4a, S4b, S5a, and S5b are closed. The fully differential circuits sample the input signals onto the two capacitors (C2a and C2b) through switches S4a and S4b. S2a and S2b set the common mode for the amplifier input, and open simultaneously with S1, sampling the input waveform. Switches S4a and S4b are then opened before switches S3a and S3b connect capacitors C1a and C1b to the output of the amplifier and switch S4c is closed. The resulting differential voltages are held on capacitors C2a and C2b. The amplifiers are used to charge capacitors C1a and C1b to the same values originally held on C2a and C2b. These values are then presented to the first-stage quantizers and isolate the pipelines from the fast-changing inputs. The wide input bandwidth T/H amplifiers allow the MAX1183 to track-and-sample/hold analog inputs of high frequencies (> Nyquist). MAX1183 Dual 10-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Parallel Outputs Digital Output Data, Output Data Format Selection (T/B), Output Enable (OE) where fIN represents the analog input frequency and tAJ is the time of the aperture jitter. Clock jitter is especially critical for undersampling applications. The clock input should always be considered as an analog input and routed away from any analog input or other digital signal lines. All digital outputs, D0A-D9A (Channel A) and D0B-D9B (Channel B) are TTL/CMOS logic-compatible. There is a five-clock-cycle latency between any particular sample and its corresponding output data. The output coding can be chosen to be either straight offset binary or two's complement (Table 1) controlled by a single pin (T/B). Pull T/B low to select offset binary and high to activate two's complement output coding. The capacitive load on the digital outputs D0A-D9A and D0B-D9B should be kept as low as possible (<15pF) to avoid large digital currents that could feed back into the analog portion of the MAX1183, thereby degrading its dynamic performance. Using buffers on the digital outputs of the ADCs can further isolate the digital outputs from heavy capacitive loads. To further improve the dynamic performance of the MAX1183, small-series resistors (e.g., 100) may be added to the digital output paths close to the MAX1183. The MAX1183 clock input operates with a voltage threshold set to VDD/2. Clock inputs with a duty cycle other than 50% must meet the specifications for high and low periods as stated in the Electrical Characteristics. System Timing Requirements Figure 3 depicts the relationship between the clock input, analog input, and data output. The MAX1183 samples at the rising edge of the input clock. Output data for channels A and B is valid on the next rising edge of the input clock. The output data has an internal latency of five clock cycles. Figure 4 also determines the relationship between the input clock parameters and the valid output data on channels A and B. 5-CLOCK-CYCLE LATENCY N N+1 N+2 N+3 N+4 N+5 N+6 ANALOG INPUT CLOCK INPUT tDO tCH tCL DATA OUTPUT D9A-D0A N-6 N-5 N-4 N-3 N-2 N-1 N N+1 DATA OUTPUT D9B-D0B N-6 N-5 N-4 N-3 N-2 N-1 N N+1 Figure 3. System Timing Diagram 12 ______________________________________________________________________________________ Dual 10-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Parallel Outputs tENABLE tDISABLE Using Transformer Coupling OUTPUT D9A-D0A HIGH-Z OUTPUT D9B-D0B HIGH-Z HIGH-Z VALID DATA HIGH-Z VALID DATA Figure 4. Output Timing Diagram Figure 4 displays the timing relationship between output enable and data output valid, as well as powerdown/wake-up and data output valid. Power-Down (PD) and Sleep (SLEEP) Modes The MAX1183 offers two power-save modes--sleep and full power-down modes. In sleep mode (SLEEP = 1), only the reference bias circuit is active (both ADCs are disabled), and current consumption is reduced to 2.8mA. To enter full power-down mode, pull PD high. With OE simultaneously low, all outputs are latched at the last value prior to the power down. Pulling OE high forces the digital outputs into a high-impedance state. Applications Information Figure 5 depicts a typical application circuit containing two single-ended to differential converters. The internal reference provides a VDD/2 output voltage for levelshifting purposes. The input is buffered and then split to a voltage follower and inverter. One lowpass filter per ADC suppresses some of the wideband noise associated with high-speed op amps follows the amplifiers. The user may select the RISO and CIN values to optimize the filter performance, to suit a particular application. An RF transformer (Figure 6) provides an excellent solution to convert a single-ended source signal to a fully differential signal, required by the MAX1183 for optimum performance. Connecting the center tap of the transformer to COM provides a VDD/2 DC level shift to the input. Although a 1:1 transformer is shown, a step-up transformer may be selected to reduce the drive requirements. A reduced signal swing from the input driver, such as an op amp, may also improve the overall distortion. In general, the MAX1183 provides better SFDR and THD with fully differential input signals than singleended drive, especially for very high input frequencies. In differential input mode, even-order harmonics are lower as both inputs (INA+, INA- and/or INB+, INB-) are balanced, and each of the ADC inputs only requires half the signal swing compared to single-ended mode. Single-Ended AC-Coupled Input Signal Figure 7 shows an AC-coupled, single-ended application. Amplifiers like the MAX4108 provide high speed, high bandwidth, low noise, and low distortion to maintain the integrity of the input signal. Typical QAM Demodulation Application The most frequently used modulation technique for digital communications applications is probably the quadrature amplitude modulation (QAM). Typically found in spread-spectrum-based systems, a QAM signal represents a carrier frequency modulated in both amplitude and phase. At the transmitter, modulating the baseband signal with quadrature outputs, a local oscillator followed by subsequent up-conversion can generate the QAM signal. The result is an in-phase (I) and a quadrature (Q) carrier component, where the Q Table 1. MAX1183 Output Codes for Differential Inputs DIFFERENTIAL INPUT VOLTAGE* DIFFERENTIAL INPUT STRAIGHT OFFSET BINARY T/B = 0 TWO'S COMPLEMENT T/B = 1 VREF x 511/512 +FULL SCALE - 1LSB 11 1111 1111 01 1111 1111 VREF x 1/512 + 1LSB 10 0000 0001 00 0000 0001 0 Bipolar Zero 10 0000 0000 00 0000 0000 11 1111 1111 - VREF x 1/512 - 1LSB 01 1111 1111 -VREF x 512/512 -FULL SCALE +1LSB 00 0000 0001 10 0000 0001 -VREF x 512/512 -FULL SCALE 00 0000 0000 10 0000 0000 *VREF = VREFP - VREFN ______________________________________________________________________________________ 13 MAX1183 For the application in Figure 5, a RISO of 50 is placed before the capacitive load to prevent ringing and oscillation. The 22pF C IN capacitor acts as a small bypassing capacitor. OE MAX1183 Dual 10-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Parallel Outputs +5V 0.1F LOWPASS FILTER INA+ MAX4108 RIS0 50 0.1F 300 CIN 22pF 0.1F -5V 600 600 300 COM 0.1F +5V +5V 0.1F 600 INPUT 0.1F LOWPASS FILTER MAX4108 300 -5V 0.1F INA- MAX4108 RIS0 50 300 CIN 22pF 0.1F -5V 300 300 +5V 600 MAX1183 0.1F LOWPASS FILTER INB+ MAX4108 RIS0 50 0.1F 300 CIN 22pF 0.1F -5V 600 600 300 0.1F +5V +5V 0.1F 600 INPUT 0.1F LOWPASS FILTER MAX4108 300 -5V 0.1F INB- MAX4108 RIS0 50 300 -5V CIN 22pF 0.1F 300 300 600 Figure 5. Typical Application for Single-Ended to Differential Conversion 14 ______________________________________________________________________________________ Dual 10-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Parallel Outputs MAX1183 REFP 25 INA+ 22pF VIN 0.1F 1 VIN N.C. T1 3 1k RISO 50 INA+ MAX4108 6 100 5 2 0.1F CIN 22pF 1k COM 2.2F 4 COM REFN 0.1F MINICIRCUITS TT1-6 0.1F RISO 50 INA- 100 CIN 22pF 25 INAREFP 22pF MAX1183 25 VIN 0.1F MAX1183 1k RISO 50 INB+ INB+ MAX4108 22pF 100 CIN 22pF 1k 0.1F 1 VIN N.C. T1 6 REFN 2 5 3 4 2.2F 100 0.1F 0.1F RISO 50 INBCIN 22pF MINICIRCUITS TT1-6 25 INB22pF Figure 6. Transformer-Coupled Input Drive component is 90 degree phase-shifted with respect to the in-phase component. At the receiver, the QAM signal is divided down into its I and Q components, essentially representing the modulation process reversed. Figure 8 displays the demodulation process performed in the analog domain, using the dual matched 3V, 10-bit ADC (MAX1183), and the MAX2451 quadrature demodulator to recover and digitize the I and Q baseband signals. Before being digitized by the MAX1183, the mixed-down signal components may be filtered by matched analog filters, such as Nyquist or pulse-shaping filters, which remove any unwanted images from the mixing process, thereby enhancing the overall signal-to-noise (SNR) performance and minimizing intersymbol interference. Figure 7. Using an Op Amp for Single-Ended, AC-Coupled Input Drive Grounding, Bypassing, and Board Layout The MAX1183 requires high-speed board layout design techniques. Locate all bypass capacitors as close to the device as possible, preferably on the same side as the ADC, using surface-mount devices for minimum inductance. Bypass VDD, REFP, REFN, and COM with two parallel 0.1F ceramic capacitors and a 2.2F bipolar capacitor to GND. Follow the same rules to bypass the digital supply (OVDD) to OGND. Multilayer boards with separated ground and power planes produce the highest level of signal integrity. Consider the use of a split ground plane arranged to match the physical location of the analog ground (GND) and the digital output driver ground (OGND) on the ADC's package. The two ground planes should be joined at a single point such that the noisy digital ground currents do not interfere with the analog ground plane. The ideal location of this connection can be determined experimentally at a point along the gap between the two ground planes, which produces optimum results. Make this connection with a low-value, surface-mount resistor ______________________________________________________________________________________ 15 MAX1183 Dual 10-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Parallel Outputs MAX2451 INA+ INA0 90 DSP POSTPROCESSING MAX1183 INB+ INB- DOWNCONVERTER /8 Figure 8. Typical QAM Application, Using the MAX1183 (1 to 5), a ferrite bead, or a direct short. Alternatively, all ground pins could share the same ground plane, if the ground plane is sufficiently isolated from any noisy, digital systems ground plane (e.g. downstream output buffer or DSP ground plane). Route high-speed digital signal traces away from the sensitive analog traces of either channel. Make sure to isolate the analog input lines to each respective converter to minimize channel-to-channel crosstalk. Keep all signal lines short and free of 90 degree turns. CLK ANALOG INPUT tAD tAJ SAMPLED DATA (T/H) Static Parameter Definitions Integral Nonlinearity (INL) Integral nonlinearity is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best straight-line fit or a line drawn between the endpoints of the transfer function, once offset and gain errors have been nullified. The static linearity parameters for the MAX1183 are measured using the best straight-line fit method. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between an actual step width and the ideal value of 1LSB. A DNL error specification of less than 1LSB guarantees no missing codes and a monotonic transfer function. Dynamic Parameter Definitions Aperture Jitter Figure 9 depicts the aperture jitter (tAJ), which is the sample-to-sample variation in the aperture delay. 16 T/H TRACK HOLD TRACK Figure 9. T/H Aperture Timing Aperture Delay Aperture delay (tAD) is the time defined between the falling edge of the sampling clock and the instant when an actual sample is taken (Figure 9). Signal-to-Noise Ratio (SNR) For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the fullscale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC's resolution (N-Bits): SNRdB[max] = 6.02 N + 1.76 In reality, there are other noise sources besides quantization noise (thermal noise, reference noise, clock jitter, etc.). SNR is computed by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first five harmonics, and the DC offset. ______________________________________________________________________________________ Dual 10-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Parallel Outputs Intermodulation Distortion (IMD) The two-tone IMD is the ratio expressed in decibels of either input tone to the worst 3rd-order (or higher) intermodulation products. The individual input tone levels are backed off by 6.5dB from full scale. Total Harmonic Distortion (THD) THD is typically the ratio of the RMS sum of the first four harmonics of the input signal to the fundamental itself. This is expressed as: Table 2. Pin-Compatible Versions 2 2 2 2 V2 + V3 + V4 + V5 THD = 20 x log10 V1 PART where V1 is the fundamental amplitude, and V2 through V5 are the amplitudes of the 2nd- through 5th-order harmonics. Spurious-Free Dynamic Range (SFDR) SFDR is the ratio expressed in decibels of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next largest spurious component, excluding DC offset. RESOLUTION (BITS) SPEED GRADE (Msps) OUTPUT BUS 10 10 10 10 10 10 10 10 8 8 8 8 120 105 80 65 40 40 20 20 100 60 40 40 Full-Duplex Full-Duplex Full-Duplex Full-Duplex Full-Duplex Half-Duplex Full-Duplex Half-Duplex Full-Duplex Full-Duplex Half-Duplex Full-Duplex MAX1190 MAX1180 MAX1181 MAX1182 MAX1183 MAX1186 MAX1184 MAX1185 MAX1198 MAX1197 MAX1196 MAX1195 Functional Diagram VDD OGND OVDD GND INA+ PIPELINE ADC T/H 10 DEC OUTPUT DRIVERS 10 D9A-D0A INA- CONTROL CLK OE INB+ T/H PIPELINE ADC 10 DEC OUTPUT DRIVERS 10 D9B-D0B INB- REFERENCE MAX1183 T/B PD SLEEP REFOUT REFN COM REFP REFIN ______________________________________________________________________________________ 17 MAX1183 Signal-to-Noise Plus Distortion (SINAD) SINAD is computed by taking the ratio of the RMS signal to all spectral components minus the fundamental and the DC offset. Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) 48L,TQFP.EPS MAX1183 Dual 10-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Parallel Outputs PACKAGE OUTLINE, 48L TQFP, 7x7x1.0mm EP OPTION 21-0065 G 1 2 PACKAGE OUTLINE, 48L TQFP, 7x7x1.0mm EP OPTION 21-0065 G 2 2 Revision History Pages changed at Rev 1: Title change--all pages, 1-13, 15-18 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2006 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.