General Description
The MAX1183 is a 3V, dual 10-bit analog-to-digital con-
verter (ADC) featuring fully differential wideband track-
and-hold (T/H) inputs, driving two pipelined, nine-stage
ADCs. The MAX1183 is optimized for low-power, high
dynamic performance applications in imaging, instrumen-
tation, and digital communication applications. This ADC
operates from a single 2.7V to 3.6V supply, consuming
only 120mW while delivering a typical signal-to-noise ratio
(SNR) of 59.6dB at an input frequency of 20MHz and a
sampling rate of 40Msps. The T/H driven input stages
incorporate 400MHz (-3dB) input amplifiers. The convert-
ers may also be operated with single-ended inputs. In
addition to low operating power, the MAX1183 features a
2.8mA sleep mode as well as a 1µA power-down mode to
conserve power during idle periods.
An internal 2.048V precision bandgap reference sets
the full-scale range of the ADC. A flexible reference
structure allows the use of this internal or an externally
derived reference, if desired for applications requiring
increased accuracy or a different input voltage range.
The MAX1183 features parallel, CMOS-compatible
three-state outputs. The digital output format can be set
to two’s complement or straight offset binary through a
single control pin. The device provides for a separate
output power supply of 1.7V to 3.6V for flexible interfac-
ing. The MAX1183 is available in a 7mm ✕7mm, 48-pin
TQFP package, and is specified for the extended
industrial (-40°C to +85°C) temperature range.
Pin-compatible lower and higher speed versions of the
MAX1183 are also available. See Table 2 at end of data
sheet for a list of pin-compatible versions. Refer to the
MAX1180 data sheet for 105Msps, the MAX1181 data
sheet for 80Msps, the MAX1182 data sheet for 65Msps,
and the MAX1184 data sheet for 20Msps. In addition to
these speed grades, this family includes a multiplexed
output version, for which digital data is presented time-
interleaved and on a single, parallel 10-bit output port.
Applications
High-Resolution Imaging
I/Q Channel Digitization
Multichannel IF Sampling
Instrumentation
Video Application
Ultrasound
Features
♦Single 3V Operation
♦Excellent Dynamic Performance:
59.6dB SNR at fIN = 20MHz
73dB SFDR at fIN = 20MHz
♦Low Power:
40mA (Normal Operation)
2.8mA (Sleep Mode)
1µA (Shutdown Mode)
♦0.02dB Gain and 0.25° Phase Matching
♦Wide ±1VP-P Differential Analog Input Voltage
Range
♦400MHz -3dB Input Bandwidth
♦On-Chip 2.048V Precision Bandgap Reference
♦User-Selectable Output Format—Two’s
Complement or Offset Binary
♦48-Pin TQFP Package with Exposed Paddle for
Improved Thermal Dissipation
MAX1183
Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs
________________________________________________________________ Maxim Integrated Products 1
D1A
D0A
OGND
OVDD
OVDD
OGND
D0B
D1B
D2B
D3B
D4B
D5B
COM
VDD
GND
INA+
INA-
VDD
GND
INB-
INB+
GND
VDD
CLK
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
48 TQFP-EP
MAX1183
GND
VDD
GND
VDD
T/B
SLEEP
PD
OE
D9B
D8B
D7B
D6B
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
REFN
REFP
REFIN
REFOUT
D9A
D8A
D7A
D6A
D5A
D4A
D3A
D2A
EP
Pin Configuration
Ordering Information
19-2173; Rev 1; 7/06
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Functional Diagram appears at end of data sheet.
PART TEMP RANGE PIN-PACKAGE
MAX1183ECM -40°C to +85°C 48 TQFP-EP*
MAX1183ECM+ -40°C to +85°C 48 TQFP-EP*
*EP = Exposed paddle.
+Denotes lead-free package.
NOTE: THE PIN 1 INDICATOR FOR LEAD-FREE PACKAGE IS REPLACED BY A “+” SIGN.
MAX1183
Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VDD = 3V, OVDD = 2.5V, 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND, REFOUT connected to REFIN through a
10kΩresistor, VIN = 2VP-P (differential with respect to COM), CL= 10pF at digital outputs (Note 1), fCLK = 40MHz, TA= TMIN to TMAX,
unless otherwise noted. Typical values are at TA= +25°C.) (Note 2)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDD, OVDD to GND .............................................. -0.3V to +3.6V
OGND to GND.......................................................-0.3V to +0.3V
INA+, INA-, INB+, INB- to GND ...............................-0.3V to VDD
REFIN, REFOUT, REFP, REFN,
COM, CLK to GND .................................-0.3V to (VDD + 0.3V)
OE, PD, SLEEP, T/B
D9A–D0A, D9B–D0B to OGND ...........-0.3V to (OVDD + 0.3V)
Continuous Power Dissipation (TA= +70°C)
48-Pin TQFP-EP
(derate 30.4mW/°C above +70°C)..........................2430mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DC ACCURACY
Resolution 10 Bits
Integral Nonlinearity INL fIN = 7.51MHz ±0.5 ±1.7 LSB
Differential Nonlinearity DNL fIN = 7.51MHz, no missing codes guaranteed ±0.25 ±1.0 LSB
Offset Error <±1 ±1.8 % FS
Gain Error 0±2% FS
ANALOG INPUT
Differential Input Voltage Range VDIFF Differential or single-ended inputs ±1.0 V
Common-Mode Input Voltage
Range VCM VDD/2
±0.5 V
Input Resistance RIN Switched capacitor load 50 kΩ
Input Capacitance CIN 5pF
CONVERSION RATE
Maximum Clock Frequency fCLK 40 MHz
Data Latency 5Clock
Cycles
DYNAMIC CHARACTERISTICS
fINA or B = 7.51MHz, TA = +25°C 57.3 59.6
Signal-to-Noise Ratio
(Note 3) SNR fINA or B = 20MHz, TA = +25°C 56.8 59.6 dB
fINA or B = 7.51MHz, TA = +25°C 57 59.4
Signal-to-Noise and Distortion
(Note 3) SINAD fINA or B = 20MHz, TA = +25°C 56.5 59 dB
fINA or B = 7.51MHz, TA = +25°C 65 76
Spurious-Free Dynamic Range
(Note 3) SFDR fINA or B = 20MHz, TA = +25°C 65 73 dBc
fINA or B = 7.51MHz, TA = +25°C -73 -64
Total Harmonic Distortion
(First 4 harmonics) (Note 3) THD fINA or B = 20MHz, TA = +25°C -73 -63 dBc
fINA or B = 7.51MHz -76
Third-Harmonic Distortion
(Note 3) HD3 fINA or B = 20MHz -73 dB
Intermodulation Distortion IMD
fINA or B = 11.6066MHz at -6.5dBFS,
fINA or B = 13.3839MHz at -6.5dBFS
(Note 4)
-78 dBc
MAX1183
Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3V, OVDD = 2.5V, 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND, REFOUT connected to REFIN through a
10kΩresistor, VIN = 2VP-P (differential with respect to COM), CL= 10pF at digital outputs (Note 1), fCLK = 40MHz, TA= TMIN to TMAX,
unless otherwise noted. Typical values are at TA= +25°C.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Small-Signal Bandwidth Input at -20dBFS, differential inputs 500 MHz
Full-Power Bandwidth FPBW Input at -0.5dBFS, differential inputs 400 MHz
Aperture Delay tAD 1ns
Aperture Jitter tAJ 2ps
RMS
Overdrive Recovery Time For 1.5 x full-scale input 2 ns
Differential Gain ±1 %
Differential Phase ±0.25 Degrees
Output Noise INA+ = INA- = INB+ = INB- = COM 0.2 LSBRMS
INTERNAL REFERENCE
Reference Output Voltage REFOUT 2.048
±3% V
Reference Temperature
Coefficient TCREF 60 ppm/
°C
Load Regulation 1.25 mV/mA
BUFFERED EXTERNAL REFERENCE (VREFIN = 2.048V)
REFIN Input Voltage VREFIN 2.048 V
Positive Reference Output
Voltage VREFP 2.012 V
Negative Reference Output
Voltage VREFN 0.988 V
Differential Reference Output
Voltage Range ∆VREF ∆VREF = VREFP - VREFN 0.95 1.024 1.10 V
REFIN Resistance RREFIN >50 MΩ
Maximum REFP, COM
Source Current ISOURCE 5mA
Maximum REFP, COM
Sink Current ISINK -250 µA
Maximum REFN Source Current ISOURCE 250 µA
Maximum REFN Sink Current ISINK -5 mA
UNBUFFERED EXTERNAL REFERENCE (VREFIN = AGND, reference voltage applied to REFP, REFN, and COM)
REFP, REFN Input Resistance RREFP,
RREFN
Measured between REFP and COM and
REFN and COM 4kΩ
Differential Reference Input
Voltage Range ∆VREF ∆VREF = VREFP - VREFN 1.024
±10% V
COM Input Voltage Range VCOM VDD/2
±10% V
REFP Input Voltage VREFP VCOM +
∆VREF/2 V
REFN Input Voltage VREFN VCOM -
∆VREF/2 V
MAX1183
Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3V, OVDD = 2.5V, 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND, REFOUT connected to REFIN through a
10kΩresistor, VIN = 2VP-P (differential with respect to COM), CL= 10pF at digital outputs (Note 1), fCLK = 40MHz, TA= TMIN to TMAX,
unless otherwise noted. Typical values are at TA= +25°C.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DIGITAL INPUTS (CLK, PD, OE, SLEEP, T/B)
CLK 0.8 x
VDD
Input High Threshold VIH
PD, OE, SLEEP, T/B 0.8 x
OVDD
V
CLK 0.2 x
VDD
Input Low Threshold VIL
PD, OE, SLEEP, T/B 0.2 x
OVDD
V
Input Hysteresis VHYST 0.1 V
IIH VIH = OVDD or VDD (CLK) ±5
Input Leakage IIL VIL = 0V ±5 µA
Input Capacitance CIN 5pF
DIGITAL OUTPUTS (D9A–D0A, D9B–D0B)
Output Voltage Low VOL ISINK = -200µA 0.2 V
Output Voltage High VOH ISOURCE = 200µA OVDD
- 0.2 V
Three-State Leakage Current ILEAK OE = OVDD ±10 µA
Three-State Leakage
Capacitance COUT OE = OVDD 5pF
POWER REQUIREMENTS
Analog Supply Voltage Range VDD 2.7 3 3.6 V
Output Supply Voltage Range OVDD 1.7 2.5 3.6 V
Operating, fINA or B = 20MHz at -0.5dBFS 40 60
Sleep mode 2.8 mA
Analog Supply Current IVDD
Shutdown, clock idle, PD = OE = OVDD 115µA
Operating, CL = 15pF,
fINA or B = 20MHz at -0.5dBFS 5.8 mA
Sleep mode 100
Output Supply Current IOVDD
Shutdown, clock idle, PD = OE = OVDD 210
µA
Operating, fINA or B = 20MHz at -0.5dBFS 120 180
Sleep mode 8.4 mW
Power Dissipation PDISS
Shutdown, clock idle, PD = OE = OVDD 345µW
Offset ±0.2 mV/V
Power-Supply Rejection Ratio PSRR Gain ±0.1 %V
TIMING CHARACTERISTICS
CLK Rise to Output Data Valid tDO Figure 3 (Note 5) 5 8 ns
Output Enable Time tENABLE Figure 4 10 ns
Output Disable Time tDISABLE Figure 4 1.5 ns
MAX1183
Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3V, OVDD = 2.5V, 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND, REFOUT connected to REFIN through a
10kΩresistor, VIN = 2VP-P (differential with respect to COM), CL= 10pF at digital outputs (Note 1), fCLK = 40MHz, TA= TMIN to TMAX,
unless otherwise noted. Typical values are at TA= +25°C.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
CLK Pulse Width High tCH Figure 3, clock period: 25ns 12.5
±3.8 ns
CLK Pulse Width Low tCL Figure 3, clock period: 25ns 12.5
±3.8 ns
Wake up from sleep mode (Note 6) 0.41
Wake-Up Time tWAKE Wake up from shutdown (Note 6) 1.5 µs
CHANNEL-TO-CHANNEL MATCHING
Crosstalk fINA or B = 20MHz at -0.5dBFS -70 dB
Gain Matching fINA or B = 20MHz at -0.5dBFS 0.02 ±0.2 dB
Phase Matching fINA or B = 20MHz at -0.5dBFS 0.25 Degrees
Note 1: Equivalent dynamic performance is obtainable over full OVDD range with reduced CL.
Note 2: Specifications at ≥+25°C are guaranteed by production test and < +25°C are guaranteed by design and characterization.
Note 3: SNR, SINAD, THD, SFDR, and HD3 are based on an analog input voltage of -0.5dBFS referenced to a 1.024V full-scale
input voltage range.
Note 4: Intermodulation distortion is the total power of the intermodulation products relative to the individual carrier. This number is
6dB better, if referenced to the two-tone envelope.
Note 5: Digital outputs settle to VIH, VIL. Parameter guaranteed by design.
Note 6: With REFIN driven externally, REFP, COM, and REFN are left floating while powered down.
Typical Operating Characteristics
(VDD = 3V, OVDD = 2.5V, VREFIN = 2.048V, differential input at -0.5dBFS, fCLK = 40.0006MHz, CL≈10pF, TA= +25°C, unless
otherwise noted.)
-100
-80
-90
-60
-70
-40
-50
-30
-10
-20
0
046821012141816 20
FFT PLOT CHA (DIFFERENTIAL INPUT,
8192-POINT DATA RECORD)
MAX1183 toc01
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
fCLK = 40.0006MHz
fINA = 7.5343MHz
fINB = 6.1475MHz
AINA = -0.498dBFS
HD3
HD2
CHA
-100
-80
-90
-60
-70
-40
-50
-30
-10
-20
0
0 46821012141816 20
FFT PLOT CHB (DIFFERENTIAL INPUT,
8192-POINT DATA RECORD)
MAX1183 toc02
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
fCLK = 40.0006MHz
fINB = 6.1475MHz
fINA = 7.5343MHz
AINB = -0.534dBFS
HD3
HD2
CHB
-100
-80
-90
-60
-70
-40
-50
-30
-10
-20
0
0 46821012141816 20
FFT PLOT CHA (DIFFERENTIAL INPUT,
8192-POINT DATA RECORD)
MAX1183 toc03
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
fCLK = 40.0006MHz
fINA = 24.9662MHz
fINB = 19.888MHz
AINA = -0.552dBFS
HD3
HD2
CHA
MAX1183
Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs
6 _______________________________________________________________________________________
-100
-80
-90
-60
-70
-40
-50
-30
-10
-20
0
046821012141816 20
FFT PLOT CHB (DIFFERENTIAL INPUT,
8192-POINT DATA RECORD)
MAX1183 toc04
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
CHB
fCLK = 40.0006MHz
fINA = 24.9662MHz
fINB = 19.888MHz
AINB = -0.525dBFS
HD3
HD2
-100
-80
-90
-60
-70
-40
-50
-30
-10
-20
0
0 46821012141816 20
TWO-TONE IMD PLOT (DIFFERENTIAL INPUT,
8192-POINT DATA RECORD)
MAX1183 toc05
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
IM2 IM3 IM3 IM2
fCLK = 40.0006MHz
fIN1 = 11.6066MHz
fIN2 = 13.3834MHz
AIN1 = AIN2 = -6.5dBFS fIN2
fIN1
SIGNAL-TO-NOISE RATIO vs.
ANALOG INPUT FREQUENCY
ANALOG INPUT FREQUENCY (MHz)
SNR (dB)
MAX1183 toc06
0 1020304050607080
55
56
57
58
59
60
61
CHB
CHA
SIGNAL-TO-NOISE PLUS DISTORTION
vs. ANALOG INPUT FREQUENCY
ANALOG INPUT FREQUENCY (MHz)
SINAD (dB)
MAX1183 toc07
0 1020304050607080
54
56
58
60
62
CHB
CHA
TOTAL HARMONIC DISTORTION vs.
ANALOG INPUT FREQUENCY
ANALOG INPUT FREQUENCY (MHz)
THD (dBc)
MAX1183 toc08
0 1020304050607080
-100
-90
-80
-70
-60
-50
CHA
CHB
SPURIOUS-FREE DYNAMIC RANGE vs.
ANALOG INPUT FREQUENCY
ANALOG INPUT FREQUENCY (MHz)
SFDR (dBc)
MAX1183 toc09
0 1020304050607080
40
50
60
70
80
90
CHA
CHB
-8
-4
-6
0
-2
4
2
6
1 10 100 1000
FULL-POWER INPUT BANDWIDTH vs.
ANALOG INPUT FREQUENCY, SINGLE-ENDED
MAX1183 toc10
ANALOG INPUT FREQUENCY (MHz)
GAIN (dB)
-8
-4
-6
0
-2
4
2
6
1 10 100 1000
SMALL-SIGNAL INPUT BANDWIDTH vs.
ANALOG INPUT FREQUENCY, SINGLE-ENDED
MAX1183 toc11
ANALOG INPUT FREQUENCY (MHz)
GAIN (dB)
VIN = 100mVP-P
35
45
40
55
50
60
65
-20 0
SIGNAL-TO-NOISE RATIO vs.
ANALOG INPUT POWER (fIN = 19.888MHz)
MAX1183 toc12
ANALOG INPUT POWER (dBFS)
SNR (dB)
-12-16 -8 -4
Typical Operating Characteristics (continued)
(VDD = 3V, OVDD = 2.5V, VREFIN = 2.048V, differential input at -0.5dBFS, fCLK = 40.0006MHz, CL≈10pF, TA= +25°C, unless
otherwise noted.)
MAX1183
Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs
_______________________________________________________________________________________ 7
35
45
40
55
50
60
65
-20 0
SIGNAL-TO-NOISE PLUS DISTORTION vs.
ANALOG INPUT POWER (fIN = 19.888MHz)
MAX1183 toc13
ANALOG INPUT POWER (dBFS)
SINAD (dB)
-12-16 -8 -4
TOTAL HARMONIC DISTORTION vs.
ANALOG INPUT POWER (fIN = 19.888MHz)
ANALOG INPUT POWER (dBFS)
THD (dBc)
MAX1183 toc14
-20 -16 -12 -8 -4 0
-80
-75
-70
-65
-60
-55
SPURIOUS-FREE DYNAMIC RANGE vs.
ANALOG INPUT POWER (fIN = 19.888MHz)
ANALOG INPUT POWER (dBFS)
SFDR (dBc)
MAX1183 toc15
-20 -16 -12 -8 -4 0
60
64
68
72
76
80
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0 256128 384 512 640 768 896 1024
INTEGRAL NONLINEARITY
MAX1183 toc16
DIGITAL OUTPUT CODE
INL (LSB)
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0256128 384 512 640 768 896 1024
DIFFERENTIAL NONLINEARITY
MAX1183 toc17
DIGITAL OUTPUT CODE
DNL (LSB)
-0.1
0.1
0
0.3
0.2
0.4
0.5
-40 85
GAIN ERROR vs. TEMPERATURE
MAX1183 toc18
TEMPERATURE (°C)
GAIN ERROR (% FS)
10-15 35 60
CHB
CHA
-0.4
-0.2
-0.3
0
-0.1
0.1
0.2
-40 85
OFFSET ERROR vs. TEMPERATURE
MAX1183 toc19
TEMPERATURE (°C)
OFFSET ERROR (% FS)
10-15 35 60
CHB
CHA
30
34
42
38
46
50
2.70 3.002.85 3.15 3.30 3.45 3.60
ANALOG SUPPLY CURRENT vs.
ANALOG SUPPLY VOLTAGE
MAX1183 toc20
VDD (V)
IVDD (mA)
30
34
42
38
46
50
-40 10-15 35 60 85
ANALOG SUPPLY CURRENT vs.
TEMPERATURE
MAX1183 toc21
TEMPERATURE (°C)
IVDD (mA)
Typical Operating Characteristics (continued)
(VDD = 3V, OVDD = 2.5V, VREFIN = 2.048V, differential input at -0.5dBFS, fCLK = 40.0006MHz, CL≈10pF, TA= +25°C, unless
otherwise noted.)
MAX1183
Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs
8 _______________________________________________________________________________________
0
0.1
0.3
0.2
0.4
0.5
2.70 3.002.85 3.15 3.30 3.45 3.60
ANALOG POWER-DOWN CURRENT vs.
ANALOG SUPPLY VOLTAGE
MAX1183 toc22
VDD (V)
IVDD (µA)
OE = PD = OVDD
SNR/SINAD, -THD/SFDR vs.
CLOCK DUTY CYCLE
CLOCK DUTY CYCLE (%)
SNR/SINAD, -THD/SFDR (dB, dBc)
MAX1183 toc23
30 35 40 45 50 55 60 65 70
40
50
60
70
80
90
SINAD
SNR
SFDR
-THD
fINA = 7.5343MHz
fINB = 6.1475MHz
1.9990
1.9996
2.0008
2.0002
2.0014
2.0020
2.70 3.002.85 3.15 3.30 3.45 3.60
INTERNAL REFERENCE VOLTAGE vs.
ANALOG SUPPLY VOLTAGE
MAX1183 toc24
VDD (V)
VREFOUT (V)
1.980
1.990
1.985
2.000
1.995
2.005
2.010
-40 85
INTERNAL REFERENCE VOLTAGE vs.
TEMPERATURE
MAX1183 toc25
TEMPERATURE (°C)
VREFOUT (V)
10-15 35 60
0
21,000
14,000
7,000
28,000
35,000
42,000
49,000
56,000
63,000
70,000
OUTPUT NOISE HISTOGRAM (DC INPUT)
MAX1183 toc26
DIGITAL OUTPUT CODE
COUNTS
64,515
N
869
N-1
152
N+1
0
N+2
0
N-2
Typical Operating Characteristics (continued)
(VDD = 3V, OVDD = 2.5V, VREFIN = 2.048V, differential input at -0.5dBFS, fCLK = 40.0006MHz, CL≈10pF, TA= +25°C, unless
otherwise noted.)
MAX1183
Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs
_______________________________________________________________________________________ 9
Pin Description
PIN NAME FUNCTION
1 COM Common-Mode Voltage Input/Output. Bypass to GND with a ≥ 0.1µF capacitor.
2, 6, 11,
14, 15 VDD Analog Supply Voltage. Bypass each supply pin to GND with a 0.1µF capacitor.
The analog supply accepts an input range of 2.7V to 3.6V.
3, 7, 10,
13, 16 GND Analog Ground
4 INA+ Channel A Positive Analog Input. For single-ended operation connect signal source to INA+.
5 INA- Channel A Negative Analog Input. For single-ended operation connect INA- to COM.
8 INB- Channel B Negative Analog Input. For single-ended operation connect INB- to COM.
9 INB+ Channel B Positive Analog Input. For single-ended operation connect signal source to INB+.
12 CLK Converter Clock Input
17 T/B
T/B selects the ADC digital output format.
High: Two’s complement.
Low: Straight offset binary.
18 SLEEP
Sleep Mode Input.
High: Deactivates the two ADCs, but leaves the reference bias circuit active.
Low: Normal operation.
19 PD
Power-Down Input.
High: Power-down mode.
Low: Normal operation.
20 OE
Output Enable Input.
High: Digital outputs disabled.
Low: Digital outputs enabled.
21 D9B Three-State Digital Output, Bit 9 (MSB), Channel B
22 D8B Three-State Digital Output, Bit 8, Channel B
23 D7B Three-State Digital Output, Bit 7, Channel B
24 D6B Three-State Digital Output, Bit 6, Channel B
25 D5B Three-State Digital Output, Bit 5, Channel B
26 D4B Three-State Digital Output, Bit 4, Channel B
27 D3B Three-State Digital Output, Bit 3, Channel B
28 D2B Three-State Digital Output, Bit 2, Channel B
29 D1B Three-State Digital Output, Bit 1, Channel B
30 D0B Three-State Digital Output, Bit 0 (LSB), Channel B
31, 34 OGND Output Driver Ground
32, 33 OVDD Output Driver Supply Voltage. Bypass each supply pin to OGND with a 0.1µF capacitor.
The output driver supply accepts an input range of 1.7V to 3.6V.
35 D0A Three-State Digital Output, Bit 0 (LSB), Channel A
36 D1A Three-State Digital Output, Bit 1, Channel A
37 D2A Three-State Digital Output, Bit 2, Channel A
38 D3A Three-State Digital Output, Bit 3, Channel A
39 D4A Three-State Digital Output, Bit 4, Channel A
40 D5A Three-State Digital Output, Bit 5, Channel A
MAX1183
Detailed Description
The MAX1183 uses a nine-stage, fully differential,
pipelined architecture (Figure 1) that allows for high-
speed conversion while minimizing power consump-
tion. Samples taken at the inputs move progressively
through the pipeline stages every half-clock cycle.
Including the delay through the output latch, the total
clock-cycle latency is five clock cycles.
One-and-a-half bit (2-comparator) flash ADCs convert
the held-input voltages into a digital code. The digital-
to-analog converters (DACs) convert the digitized
results back into analog voltages, which are then sub-
tracted from the original held-input signals. The resulting
error signals are then multiplied by two, and the residues
are passed along to the next pipeline stages where the
process is repeated until the signals have been
processed by all nine stages. Digital error correction
compensates for ADC comparator offsets in each of
these pipeline stages and ensures no missing codes.
Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs
10 ______________________________________________________________________________________
T/H VOUT
x2
Σ
FLASH
ADC DAC
1.5 BITS
10
VINA
VIN
STAGE 1 STAGE 2
D9A–D0A
VINA = INPUT VOLTAGE BETWEEN INA+ AND INA- (DIFFERENTIAL OR SINGLE ENDED)
VINB = INPUT VOLTAGE BETWEEN INB+ AND INB- (DIFFERENTIAL OR SINGLE ENDED)
DIGITAL CORRECTION LOGIC
STAGE 8 STAGE 9
2-BIT FLASH
ADC
T/H
T/H VOUT
x2
Σ
FLASH
ADC DAC
1.5 BITS
10
VINB
VIN
STAGE 1 STAGE 2
D9B–D0B
DIGITAL CORRECTION LOGIC
STAGE 8 STAGE 9
2-BIT FLASH
ADC
T/H
Figure 1. Pipelined Architecture—Stage Blocks
Pin Description (continued)
PIN NAME FUNCTION
41 D6A Three-State Digital Output, Bit 6, Channel A
42 D7A Three-State Digital Output, Bit 7, Channel A
43 D8A Three-State Digital Output, Bit 8, Channel A
44 D9A Three-State Digital Output, Bit 9 (MSB), Channel A
45 REFOUT Internal Reference Voltage Output. May be connected to REFIN through a resistor or a resistor
divider.
46 REFIN Reference Input. VREFIN = 2 x (VREFP - VREFN). Bypass to GND with a >1nF capacitor.
47 REFP Positive Reference Input/Output. Conversion range is ± (VREFP - VREFN).
Bypass to GND with a > 0.1µF capacitor.
48 REFN Negative Reference Input/Output. Conversion range is ± (VREFP - VREFN).
Bypass to GND with a > 0.1µF capacitor.
— EP Exposed Pad. Connect to analog ground.
Input Track-and-Hold (T/H) Circuits
Figure 2 displays a simplified functional diagram of the
input track-and-hold (T/H) circuits in both track-and-hold
mode. In track mode, switches S1, S2a, S2b, S4a, S4b,
S5a, and S5b are closed. The fully differential circuits
sample the input signals onto the two capacitors (C2a
and C2b) through switches S4a and S4b. S2a and S2b
set the common mode for the amplifier input, and open
simultaneously with S1, sampling the input waveform.
Switches S4a and S4b are then opened before switch-
es S3a and S3b connect capacitors C1a and C1b to
the output of the amplifier and switch S4c is closed.
The resulting differential voltages are held on capaci-
tors C2a and C2b. The amplifiers are used to charge
capacitors C1a and C1b to the same values originally
held on C2a and C2b. These values are then presented
to the first-stage quantizers and isolate the pipelines
from the fast-changing inputs. The wide input bandwidth
T/H amplifiers allow the MAX1183 to track-and-sam-
ple/hold analog inputs of high frequencies (> Nyquist).
The ADC inputs (INA+, INB+, INA- and INB-) can be
driven either differentially or single-ended. Match the
impedance of INA+ and INA-, as well as INB+ and INB-
and set the common-mode voltage to midsupply
(VDD/2) for optimum performance.
Analog Inputs and Reference
Configurations
The full-scale range of the MAX1183 is determined by
the internally generated voltage difference between
REFP (VDD/2 + VREFIN/4) and REFN (VDD/2 -
VREFIN/4). The full-scale range for both on-chip ADCs is
adjustable through the REFIN pin, which is provided for
this purpose. REFOUT, REFP, COM (VDD/2), and REFN
are internally buffered low-impedance outputs.
The MAX1183 provides three modes of reference
operation:
• Internal reference mode
• Buffered external reference mode
• Unbuffered external reference mode
In internal reference mode, connect the internal refer-
ence output REFOUT to REFIN through a resistor (e.g.,
10kΩ) or resistor divider, if an application requires a
reduced full-scale range. For stability and noise filtering
purposes, bypass REFIN with a >10nF capacitor to
GND. In internal reference mode, REFOUT, COM, REFP,
and REFN become low-impedance outputs.
In buffered external reference mode, adjust the reference
voltage levels externally by applying a stable and accu-
rate voltage at REFIN. In this mode, COM, REFP, and
REFN become outputs. REFOUT may be left open or
connected to REFIN through a >10kΩresistor.
In unbuffered external reference mode, connect REFIN
to GND. This deactivates the on-chip reference buffers
for REFP, COM, and REFN. With their buffers shut
down, these nodes become high impedance and may
be driven through separate external reference sources.
Clock Input (CLK)
The MAX1183’s CLK input accepts CMOS-compatible
clock signals. Since the interstage conversion of the
device depends on the repeatability of the rising and
falling edges of the external clock, use a clock with low
jitter and fast rise and fall times (< 2ns). In particular,
sampling occurs on the rising edge of the clock signal,
requiring this edge to provide lowest possible jitter. Any
significant aperture jitter would limit the SNR perfor-
mance of the on-chip ADCs as follows:
MAX1183
Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs
______________________________________________________________________________________ 11
S3b
S3a
COM
S5b
S5a
INB+
INB-
S1
OUT
OUT
C2a
C2b
S4c
S4a
S4b
C1b
C1a
INTERNAL
BIAS
INTERNAL
BIAS
COM
HOLD HOLD CLK
INTERNAL
NONOVERLAPPING
CLOCK SIGNALS
TRACK TRACK
S2a
S2b
S3b
S3a
COM
S5b
S5a
INA+
INA-
S1
OUT
OUT
C2a
C2b
S4c
S4a
S4b
C1b
C1a
INTERNAL
BIAS
INTERNAL
BIAS
COM
S2a
S2b
MAX1183
Figure 2. MAX1183 T/H Amplifiers
SNR ft
IN AJ
log =× ×× ×
⎛
⎝
⎜
⎞
⎠
⎟
20 1
2π
MAX1183
where fIN represents the analog input frequency and
tAJ is the time of the aperture jitter.
Clock jitter is especially critical for undersampling
applications. The clock input should always be consid-
ered as an analog input and routed away from any ana-
log input or other digital signal lines.
The MAX1183 clock input operates with a voltage thresh-
old set to VDD/2. Clock inputs with a duty cycle other
than 50% must meet the specifications for high and low
periods as stated in the Electrical Characteristics.
System Timing Requirements
Figure 3 depicts the relationship between the clock
input, analog input, and data output. The MAX1183
samples at the rising edge of the input clock. Output
data for channels A and B is valid on the next rising
edge of the input clock. The output data has an internal
latency of five clock cycles. Figure 4 also determines
the relationship between the input clock parameters
and the valid output data on channels A and B.
Digital Output Data, Output Data Format
Selection (T/B), Output Enable (
OE
)
All digital outputs, D0A–D9A (Channel A) and D0B–D9B
(Channel B) are TTL/CMOS logic-compatible. There is a
five-clock-cycle latency between any particular sample
and its corresponding output data. The output coding
can be chosen to be either straight offset binary or
two’s complement (Table 1) controlled by a single pin
(T/B). Pull T/B low to select offset binary and high to
activate two’s complement output coding. The capaci-
tive load on the digital outputs D0A–D9A and D0B–D9B
should be kept as low as possible (<15pF) to avoid
large digital currents that could feed back into the ana-
log portion of the MAX1183, thereby degrading its
dynamic performance. Using buffers on the digital out-
puts of the ADCs can further isolate the digital outputs
from heavy capacitive loads. To further improve the
dynamic performance of the MAX1183, small-series
resistors (e.g., 100Ω) may be added to the digital out-
put paths close to the MAX1183.
Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs
12 ______________________________________________________________________________________
N - 6
N
N - 5
N + 1
N - 4
N + 2
N - 3
N + 3
N - 2
N + 4
N - 1
N + 5
N
N + 6
N + 1
5-CLOCK-CYCLE LATENCY
ANALOG INPUT
CLOCK INPUT
DATA OUTPUT
D9A–D0A
tDO tCH tCL
N - 6 N - 5 N - 4 N - 3 N - 2 N - 1 N N + 1
DATA OUTPUT
D9B–D0B
Figure 3. System Timing Diagram
Figure 4 displays the timing relationship between output
enable and data output valid, as well as power-
down/wake-up and data output valid.
Power-Down (PD) and Sleep
(SLEEP) Modes
The MAX1183 offers two power-save modes—sleep and
full power-down modes. In sleep mode (SLEEP = 1), only
the reference bias circuit is active (both ADCs are
disabled), and current consumption is reduced to 2.8mA.
To enter full power-down mode, pull PD high. With OE
simultaneously low, all outputs are latched at the last
value prior to the power down. Pulling OE high forces
the digital outputs into a high-impedance state.
Applications Information
Figure 5 depicts a typical application circuit containing
two single-ended to differential converters. The internal
reference provides a VDD/2 output voltage for level-
shifting purposes. The input is buffered and then split
to a voltage follower and inverter. One lowpass filter per
ADC suppresses some of the wideband noise associat-
ed with high-speed op amps follows the amplifiers. The
user may select the RISO and CIN values to optimize
the filter performance, to suit a particular application.
For the application in Figure 5, a RISO of 50Ωis placed
before the capacitive load to prevent ringing and
oscillation. The 22pF CIN capacitor acts as a small
bypassing capacitor.
Using Transformer Coupling
An RF transformer (Figure 6) provides an excellent solu-
tion to convert a single-ended source signal to a fully dif-
ferential signal, required by the MAX1183 for optimum
performance. Connecting the center tap of the trans-
former to COM provides a VDD/2 DC level shift to the
input. Although a 1:1 transformer is shown, a step-up
transformer may be selected to reduce the drive require-
ments. A reduced signal swing from the input driver, such
as an op amp, may also improve the overall distortion.
In general, the MAX1183 provides better SFDR and
THD with fully differential input signals than single-
ended drive, especially for very high input frequencies.
In differential input mode, even-order harmonics are
lower as both inputs (INA+, INA- and/or INB+, INB-) are
balanced, and each of the ADC inputs only requires
half the signal swing compared to single-ended mode.
Single-Ended AC-Coupled Input Signal
Figure 7 shows an AC-coupled, single-ended applica-
tion. Amplifiers like the MAX4108 provide high speed,
high bandwidth, low noise, and low distortion to main-
tain the integrity of the input signal.
Typical QAM Demodulation Application
The most frequently used modulation technique for dig-
ital communications applications is probably the quad-
rature amplitude modulation (QAM). Typically found in
spread-spectrum-based systems, a QAM signal repre-
sents a carrier frequency modulated in both amplitude
and phase. At the transmitter, modulating the base-
band signal with quadrature outputs, a local oscillator
followed by subsequent up-conversion can generate
the QAM signal. The result is an in-phase (I) and
a quadrature (Q) carrier component, where the Q
MAX1183
Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs
______________________________________________________________________________________ 13
OUTPUT
D9A–D0A
OE
tDISABLE
tENABLE
HIGH-ZHIGH-Z VALID DATA
OUTPUT
D9B–D0B
HIGH-ZHIGH-Z VALID DATA
Figure 4. Output Timing Diagram
DIFFERENTIAL INPUT
VOLTAGE* DIFFERENTIAL INPUT STRAIGHT OFFSET BINARY
T/B = 0
TWO'S COMPLEMENT
T/B = 1
VREF x 511/512 +FULL SCALE - 1LSB 11 1111 1111 01 1111 1111
VREF x 1/512 + 1LSB 10 0000 0001 00 0000 0001
0 Bipolar Zero 10 0000 0000 00 0000 0000
- VREF x 1/512 - 1LSB 01 1111 1111 11 1111 1111
-VREF x 512/512 -FULL SCALE +1LSB 00 0000 0001 10 0000 0001
-VREF x 512/512 -FULL SCALE 00 0000 0000 10 0000 0000
Table 1. MAX1183 Output Codes for Differential Inputs
*VREF = VREFP - VREFN
MAX1183
Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs
14 ______________________________________________________________________________________
INPUT
300Ω
-5V
+5V
0.1µF
0.1µF
0.1µF
-5V
600Ω
300Ω
300Ω
INA+
INA-
LOWPASS FILTER
COM
600Ω
+5V
-5V
0.1µF
600Ω
300Ω
600Ω
300Ω
0.1µF
0.1µF
0.1µF
+5V
0.1µF
300Ω
MAX4108
MAX1183
INB+
INB-
MAX4108
MAX4108
LOWPASS FILTER
INPUT
300Ω
-5V
+5V
0.1µF
0.1µF
0.1µF
CIN
22pF
-5V
600Ω
300Ω
300Ω
LOWPASS FILTER
600Ω
+5V
-5V
0.1µF
600Ω
300Ω
600Ω
300Ω
0.1µF
0.1µF
0.1µF
+5V
0.1µF
300Ω
MAX4108
MAX4108
MAX4108
300Ω
LOWPASS FILTER
RIS0
50ΩCIN
22pF
RIS0
50ΩCIN
22pF
RIS0
50ΩCIN
22pF
RIS0
50Ω
Figure 5. Typical Application for Single-Ended to Differential Conversion
component is 90 degree phase-shifted with respect to
the in-phase component. At the receiver, the QAM signal
is divided down into its I and Q components, essentially
representing the modulation process reversed. Figure 8
displays the demodulation process performed in the
analog domain, using the dual matched 3V, 10-bit ADC
(MAX1183), and the MAX2451 quadrature demodulator
to recover and digitize the I and Q baseband signals.
Before being digitized by the MAX1183, the mixed-down
signal components may be filtered by matched analog
filters, such as Nyquist or pulse-shaping filters, which
remove any unwanted images from the mixing process,
thereby enhancing the overall signal-to-noise (SNR) per-
formance and minimizing intersymbol interference.
Grounding, Bypassing, and
Board Layout
The MAX1183 requires high-speed board layout design
techniques. Locate all bypass capacitors as close to
the device as possible, preferably on the same side as
the ADC, using surface-mount devices for minimum
inductance. Bypass VDD, REFP, REFN, and COM with
two parallel 0.1µF ceramic capacitors and a 2.2µF
bipolar capacitor to GND. Follow the same rules to
bypass the digital supply (OVDD) to OGND. Multilayer
boards with separated ground and power planes pro-
duce the highest level of signal integrity. Consider the
use of a split ground plane arranged to match the
physical location of the analog ground (GND) and the
digital output driver ground (OGND) on the ADC’s
package. The two ground planes should be joined at a
single point such that the noisy digital ground currents
do not interfere with the analog ground plane. The ideal
location of this connection can be determined experi-
mentally at a point along the gap between the two
ground planes, which produces optimum results. Make
this connection with a low-value, surface-mount resistor
MAX1183
Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs
______________________________________________________________________________________ 15
MAX1183
T1
N.C.
VIN 6
1
5
2
43
22pF
22pF
0.1µF
0.1µF
2.2µF
25Ω
25Ω
MINICIRCUITS
TT1–6
T1
N.C.
VIN 6
1
5
2
4
3
22pF
22pF
0.1µF
0.1µF
2.2µF
25Ω
25Ω
MINICIRCUITS
TT1–6
INA-
INA+
INB-
INB+
COM
Figure 6. Transformer-Coupled Input Drive
MAX1183
0.1µF
1kΩ
1kΩ
100Ω
100Ω
CIN
22pF
CIN
22pF
INB+
INB-
COM
INA+
INA-
0.1µF
RISO
50Ω
RISO
50Ω
REFP
REFN
VIN
MAX4108
0.1µF
1kΩ
1kΩ
100Ω
100Ω
CIN
22pF
CIN
22pF
0.1µFRISO
50Ω
RISO
50Ω
REFP
REFN
VIN
MAX4108
Figure 7. Using an Op Amp for Single-Ended, AC-Coupled
Input Drive
MAX1183
(1Ωto 5Ω), a ferrite bead, or a direct short. Alternatively,
all ground pins could share the same ground plane, if the
ground plane is sufficiently isolated from any noisy, digital
systems ground plane (e.g. downstream output buffer or
DSP ground plane). Route high-speed digital signal
traces away from the sensitive analog traces of either
channel. Make sure to isolate the analog input lines to
each respective converter to minimize channel-to-chan-
nel crosstalk. Keep all signal lines short and free of 90
degree turns.
Static Parameter Definitions
Integral Nonlinearity (INL)
Integral nonlinearity is the deviation of the values on an
actual transfer function from a straight line. This straight
line can be either a best straight-line fit or a line drawn
between the endpoints of the transfer function, once
offset and gain errors have been nullified. The static lin-
earity parameters for the MAX1183 are measured using
the best straight-line fit method.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between an
actual step width and the ideal value of 1LSB. A DNL
error specification of less than 1LSB guarantees no
missing codes and a monotonic transfer function.
Dynamic Parameter Definitions
Aperture Jitter
Figure 9 depicts the aperture jitter (tAJ), which is the
sample-to-sample variation in the aperture delay.
Aperture Delay
Aperture delay (tAD) is the time defined between the
falling edge of the sampling clock and the instant when
an actual sample is taken (Figure 9).
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital sam-
ples, the theoretical maximum SNR is the ratio of the full-
scale analog input (RMS value) to the RMS quantization
error (residual error). The ideal, theoretical minimum ana-
log-to-digital noise is caused by quantization error only
and results directly from the ADC’s resolution (N-Bits):
SNRdB[max] = 6.02 ✕N + 1.76
In reality, there are other noise sources besides quanti-
zation noise (thermal noise, reference noise, clock jitter,
etc.). SNR is computed by taking the ratio of the RMS
signal to the RMS noise, which includes all spectral
components minus the fundamental, the first five har-
monics, and the DC offset.
Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs
16 ______________________________________________________________________________________
0°
90°
÷8
DOWNCONVERTER
MAX2451
INA+
MAX1183
INA-
INB+
INB-
DSP
POST-
PROCESSING
Figure 8. Typical QAM Application, Using the MAX1183
HOLD
ANALOG
INPUT
SAMPLED
DATA (T/H)
T/H
tAD
tAJ
TRACK TRACK
CLK
Figure 9. T/H Aperture Timing
Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS sig-
nal to all spectral components minus the fundamental
and the DC offset.
Total Harmonic Distortion (THD)
THD is typically the ratio of the RMS sum of the first four
harmonics of the input signal to the fundamental itself.
This is expressed as:
where V1is the fundamental amplitude, and V2through
V5are the amplitudes of the 2nd- through 5th-order
harmonics.
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio expressed in decibels of the RMS
amplitude of the fundamental (maximum signal compo-
nent) to the RMS value of the next largest spurious
component, excluding DC offset.
Intermodulation Distortion (IMD)
The two-tone IMD is the ratio expressed in decibels of
either input tone to the worst 3rd-order (or higher) inter-
modulation products. The individual input tone levels
are backed off by 6.5dB from full scale.
THD
VVVV
V
=×
+++
⎛
⎝⎞
⎠
⎛
⎝
⎜
⎜
⎜
⎜
⎞
⎠
⎟
⎟
⎟
⎟
20 10
22324252
1
log
MAX1183
Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs
______________________________________________________________________________________ 17
GND
REFERENCE
OUTPUT
DRIVERS
CONTROL
T/H
T/H PIPELINE
ADC DEC OUTPUT
DRIVERS
REFOUT
REFN COM REFP REFIN
INA+
INA-
CLK
INB+
INB-
VDD
DEC
PIPELINE
ADC
OGND
OVDD
D9A–D0A
OE
D9B–D0B
T/B
PD
SLEEP
MAX1183
10
10
10
10
Functional Diagram
PART RESOLUTION
(BITS)
SPEED
GRADE
(Msps)
OUTPUT
BUS
MAX1190 10 120 Full-Duplex
MAX1180 10 105 Full-Duplex
MAX1181 10 80 Full-Duplex
MAX1182 10 65 Full-Duplex
MAX1183 10 40 Full-Duplex
MAX1186 10 40 Half-Duplex
MAX1184 10 20 Full-Duplex
MAX1185 10 20 Half-Duplex
MAX1198 8 100 Full-Duplex
MAX1197 8 60 Full-Duplex
MAX1196 8 40 Half-Duplex
MAX1195 8 40 Full-Duplex
Table 2. Pin-Compatible Versions
MAX1183
Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2006 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.
48L,TQFP.EPS
G
12
21-0065
PACKAGE OUTLINE,
48L TQFP, 7x7x1.0mm EP OPTION
G22
21-0065
PACKAGE OUTLINE,
48L TQFP, 7x7x1.0mm EP OPTION
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
Revision History
Pages changed at Rev 1: Title change—all pages,
1-13, 15-18
