HD1-6402B/883 - Intersil Corporation

107

March 1997

HD-6402/883

CMOS U n iver sal Asynchronou s

Receiver Transmitter (UART)

Features

• This Circuit is Processed in Accordance to MIL-STD-

883 and is Fully Conformant Under the Provi sions of

Paragraph 1.2.1.

• 8.0MHz Operating Frequency (HD-6402/883B)

• 2.0MHz Operating Frequency (HD-6402/883R)

• Low Power CMOS Design

• Programma ble Word Length, Stop Bits and Parity

• Automatic Dat a Formatting and Status Generation

• Compatible with Industry Standard UARTs

• Single +5V Power Supply

• CMOS/TTL Compat ibl e Inputs

Description

The HD-6402/883 is a CMOS UART for interfacing comput-

ers or microprocessors to an asynchro nous serial data chan -

nel. The receiver converts serial start, data, parity and stop

bits. The transmitter converts parallel data into serial form

and automatically adds start, parity and stop bits. The data

word length can be 5, 6, 7 or 8 bits. Parity may be odd or

even. Parity checking and generation can be inhibited. The

stop bits may be one or two or one and one-half when trans-

mitting 5-bit code.

The HD-6402/883 can be used in a wide range of applica-

tions including modems, printers, peripherals and remote

data acquisition systems. Utilizing the Intersil advanced

scaled SAJI IV CMOS process permits operation clock fre-

quencies up to 8.0MHz (500K Baud). Power requirements,

by comparison, are reduced from 300mW to 10mW. Status

logic increases flexibility and simplifies the user interface.

Pinout

HD-64 02/8 83 (CERDIP)

TOP VIEW

Ordering Information

PACKAGE TEMPERATURE RANGE 2MHz = 125K BAUD 8MHz = 500K BAUD PKG. NO.

CERDIP -55oC to +125oC HD1-6402R/883 HD1-6402B/883 F40.6

VCC

GND

RRD

RBR8

RBR7

RBR6

RBR5

RBR4

RBR3

RBR2

RBR1

SFD

RRC

DRR

RRI

TRC

EPE

CLS1

CLS2

SBS

CRL

TBR8

TBR7

TBR6

TBR5

TBR4

TBR3

TBR2

TBR1

TRO

TRE

TBRL

TBRE

FN2953.1

CA UTION: These devices are sensitive to elect r ostati c discharge; follow proper IC Handling Pr ocedures.

1-888-INTERSIL or 321-724-7143 |Intersil (and design) is a trademark of Intersil Americas Inc.

108

Control Definition

CONTROL WORD CHARACTER FORMAT

CLS 2 CLS 1 PI EPE SBS START BIT DATA BITS PARITY BIT STOP BITS

0000015ODD1

0000115ODD1.5

0001015EVEN 1

0001115EVEN 1.5

001X015NONE1

001X115NONE1.5

0100016ODD1

0100116ODD2

0101016EVEN 1

0101116EVEN 2

011X016NONE1

011x116NONE2

1000017ODD1

1000117ODD2

1001017EVEN 1

1001117EVEN 2

101X017NONE1

101x117NONE2

1100018ODD1

1100118ODD2

1101018EVEN 1

1101118EVEN 2

111X018NONE1

111x118NONE2

HD-6402/883

109

Absolute Maximum Ratings Thermal Information

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+8.0V

Input, Output or I/O Voltage Applied. . . . . GND -0.5V to VCC +0.5V

Storage Temperature Range . . . . . . . . . . . . . . . . . -65oC to +150oC

Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC

Lead Temperature (Soldering 10s). . . . . . . . . . . . . . . . . . . . +300oC

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1

Typical Derating Factor . . . . . . . . . . . 1mA/MHz Increase in ICCOP

Thermal Resistance θJA θJC

CERDIP Package . . . . . . . . . . . . . . . . 50oC/W 12oC/W

Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1643 Gates

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation

of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Ope rat i ng Condit io ns

Operating Voltage Range. . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range . . . . . . . . . . . . . . . .-55oC to +125oC

TABLE 1. HD-6402/883 D.C. ELECTRICAL PERFORMANCE SPECIFICATIONS

Device Guaranteed and 100% Tested

D.C. PARAMETER SYMBOL CONDITIONS GROUP A

SUBGROUPS TEMPERATURE

LIMITS

UNITSMIN MAX

Logical ‘‘1’’ Input Vol tag e VIH VCC = 5.5V 1, 2, 3 - 55oC ≤ TA ≤ +125oC2.3 - V

Logical ‘‘0’’ Input Voltage VIL VC C = 4.5V 1, 2, 3 -55 oC ≤ TA ≤ +125oC- 0.8 V

Input Leakage Current IID VIN = GND or VCC,

VCC = 5. 5V 1, 2, 3 -55oC ≤ TA ≤ +125oC-1.0 1.0 µA

Logical ‘ ‘1’’ Out put Voltage VOH IO H = -2.5mA,

VCC = 4.5V (Note 1) 1, 2, 3 -55 oC ≤ TA ≤ +125oC3.0 - V

Logical ‘‘1’’ Out put Voltage VO H IO H = -100µA

VCC = 4.5V (Note 1) 1, 2, 3 -55 oC ≤ TA ≤ +125oCVCC

-0.4 -V

Logical ‘‘0’’ Outpu t Voltage VOL IO L = +2.5m A,

VCC = 4.5V (Note 1) 1, 2, 3 -55 oC ≤ TA ≤ +125oC- 0.4 V

Ou tput Le ak ag e C urr e nt I O VO = GND or VC C,

VCC = 5. 5V 1, 2, 3 -55oC ≤ TA ≤ +125oC-1.0 1.0 µA

Standby Supply Current ICCSB VIN = GND or VCC;

VCC = 5. 5V,

Output Open

1, 2, 3 -55 oC ≤ TA ≤ +125oC- 100µA

TABLE 2. HD-6402/883 A.C. ELECTRICAL PERFORMANCE SPECIFICATIONS

Device Guaranteed and 100% Tested

A.C.

PARAMETER SYMBOL (NOTE 1)

CONDITIONS GROUP A

SUBGROUPS TEMPERATURE

LIMITS

HD-6402/883R LIMITS

HD-6402/883B

UNITSMIN MAX MIN MAX

Clock Frequency (1) fCLOCK VCC = 4.5V

CL = 50pF 9, 10, 11 -55oC ≤ TA ≤ +125oC - 2.0 - 8.0 MHz

Pulse Widths,

CRL, DRR, TBRL (2) tPW 9, 10, 11 -5 5oC ≤ TA ≤ +125oC150 - 75 - ns

Pulse Width MR (3) tMR 9, 10, 11 -55oC ≤ TA ≤ +1 25oC 150 - 150 - ns

Inpu t Data Setup

Time (4) tSET 9, 10, 11 -5 5oC ≤ TA ≤ +125oC50 - 20 - ns

Input Data Hold

Time (5) tHOLD 9, 10, 11 -5 5oC ≤ TA ≤ +125oC60 - 20 - ns

Output Enable

Time (6) tEN 9, 10, 11 -5 5oC ≤ TA ≤ +125oC - 160 - 35 ns

NOTE:

1. Interchanging of force and sense conditions is permitted.

2. Tes te d w ith input lev e ls of VIH = 2.76V and V IL = 0.4 V. R is e an d fal l t im es are dr i ve n at 1n s/V.

HD-6402/883

110

TABLE 3. HD-6402/883 ELECTRICAL PERFORMANCE SPECIFICATIONS

A.C. PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE

LIMITS

UNITSMIN MAX

In p ut Capaci tanc e CIN f = 1 M hz

All Measurements are

Referenced to Device GND

A = +25oC-25.0pF

Output Capacit ance CO 1 TA = +25oC-25.0pF

Operating Supply Current ICCOP VCC = 5.5V,

Clock Freq. = 2MHz,

VIN = VCC or GND,

Output s Ope n

1-55

oC ≤ TA ≤ +125oC- 2.0 mA

NOTE:

1. The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are ch ar-

ac terized upon initial design an d after major process an d/or design changes.

TABLE 4. APPLICABLE SUBGROUPS

CONFORMANCE GROUPS METHOD SUBGROUPS

Initial Test 100%/5004 -

I nte r i m Tes t 100%/5 004 1, 7, 9

PDA 100% 1

Final Tes t 100% 2, 3, 8A, 8B , 10, 11

Group A - 1, 2, 3, 7, 8A, 8B, 9, 10, 11

Gr o u p C an d D S am pl es /500 5 1, 7, 9

HD-6402/883

111

Burn-In Circuits

HD-6402/883 CERDIP

NOTES:

1. VCC = 5.5V ± 0.5V

2. F0 = 100kHz ± 10%

3. R1 = 47kΩ, 1/4W ± 10%

4. C = 0.01µF minimum

5. One socket p er bo ard s hould not be loaded, but rather have pin 24 go the “C” of the 4011.

4011

QUAD

NAND

GATE

VCC

DIP

HD-6402/883

DETAIL

VCC

GND

CR1

R1 GND

VCC

GND

VCC

GND

VCC

GND

VCC

GND

VCC

GND

(NOTE 5)

NOTE: ONE PER BOARD

VCC

C (NOTE 5)

HD-6402/883

112

All Intersil U.S. pro ducts are manufactur ed, assembled and test ed utiliz ing I SO 9000 quali ty systems.

Intersil Corporati on’s quali ty ce rtificat ions can be viewed at www.intersi l. com/design /quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time wi thout

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties whi ch may result

from its use. No license i s granted by i m plication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For informat ion r egarding Intersi l Cor poration and its produc ts, see www.i ntersil.com

Die Charact eris tics

DIE DIMENSIONS:

126.4 m il s x 134.3 mils x 19 m ils

METALLIZATION:

Type: Si-A l

Thickness: 10kÅ - 12kÅ

GLASSIVATION:

Type: SiO2

Thickness: 7kÅ - 9kÅ

WORST CASE CURRENT DENSITY:

1.42 x 105 A/cm2

Metallization Mask Layout

HD-6402/883

RBR7

RBR6

RBR5

RBR4

RBR3

RBR2

RBR1

SFD

CRL

TBR8

TBR7

TBR6

TBR5

TBR4

TBR3

TBR2

TBR

RBR8 RRD GND NC VCC TRC EPE CLS1 CLS2 SBS

RRC DRR DR RRI MR TBRE TBRL TRE

HD-6402/883