DATA SH EET
Preliminary specification
Supersedes data of December 1993
File under Integrated Circuits, IC02
1996 Nov 07
INTEGRATED CIRCUITS
SAA5249
Integrated VIP and Teletext with
Background Memory Controller
(IVT1.1BMCX)
1996 Nov 07 2
Philips Semiconductors Preliminary specification
Integrated VIP and Teletext with
Background Memory Controller SAA5249
FEATURES
•Complete teletext decoder featuring a background
memory controller in a single 48-pin DIP package.
Capable of storing of up to 512 teletext pages in an
external DRAM, giving instant access to the teletext
data
•Automatic processing of extension packet 26 for widest
possible language decoding. All our standard language
options can be available, and the language option is
readable via I2C-bus.
•100% hardware compatible with the SAA5247 plug-in
replacement and with the possibility of extra market in
those countries with packet 26 transmissions.
Still pin-aligned to SAA5254 and SAA5244A.
•100% software compatible with the SAA5247, and
SAA5244A, except if the special OSD symbols were
used. Also 100% software compatible to SAA5254. In all
events there is a change to the ROM ID number.
•The device is pin-aligned with the other members of the
new Philips teletext decoder family, i.e. SAA5281 and
the SAA5254, making one hardware solution for the
whole range
•Low software overhead for the microprocessor
•RGB interface to standard colour decoder ICs, push-pull
output drive.
GENERAL DESCRIPTION
The Integrated VIP and Teletext (IVT1.1BMCX) is a
teletext decoder (contained within a single chip package)
for decoding 625-line based World System Teletext
transmissions. With its built-in background memory
controller the device can store incoming teletext packets in
the external 1M4 DRAM. With this large packet store
which can be rapidly scanned, we can achieve near
instantaneous access to all the pages transmitted by the
broadcaster.
This version of the decoder also contains some extra
hardware to process extension packet 26 automatically,
extending the markets to which the TV chassis can be
shipped and offering many more language options for the
set maker.
QUICK REFERENCE DATA
ORDERING INFORMATION
SYMBOL PARAMETER MIN. TYP. MAX. UNIT
VDD supply voltage 4.5 5.0 5.5 V
IDD supply current −90 120 mA
Vsyn sync amplitude 0.1 0.3 0.6 V
Vvid video amplitude 0.7 1.0 1.4 V
fXTAL crystal frequency −27 −MHz
Tamb operating ambient temperature −20 −+70 °C
TYPE
NUMBER PACKAGE
NAME DESCRIPTION VERSION
SAA5249P/E DIP48 plastic dual in-line package; 48 leads (600 mil) SOT240-1
SAA5249GP/E QFP64 plastic quad flat package; 64 leads (lead length 1.95 mm);
body 14 ×20 ×2.7 mm; high stand-off height SOT319-1
1996 Nov 07 3
Philips Semiconductors Preliminary specification
Integrated VIP and Teletext with
Background Memory Controller SAA5249
BLOCK DIAGRAM
Fig.1 Block diagram for SOT240-1 (DIP48) package.
handbook, full pagewidth
PAGE
MEMORY
I C - BUS
INTERFACE
2
DISPLAY
CLOCK
PHASE
LOCKED
LOOP
INPUT CLAMP
AND
SYNC
SEPARATOR
BACKGROUND
MEMORY
CONTROL
TELETEXT
ACQUISITION
AND
DECODING
TIMING
CHAIN
CRYSTAL
OSCILLATOR
DATA SLICER
AND
CLOCK
REGENERATOR
DRAM INTERFACE DISPLAY
MUX
SEL2
SEL1
VSS1
REF+
OSCOUT
OSCIN
GNDO BLACK IREF STTV/LFBPOL
SDA
SCL
R/G/BY BLANK RGBREFCAS0 RASR/W CAS1 ODD/EVEN
VCR/FFB
COR
SSn
V
DCVBS
VDD2
DD1
V
SAA5249
MLB304
CVBS
ANALOG
TO
DIGITAL
CONVERTER
A0 to A9 D0 to D3
31
30
911
10 13 15 14
7
8
4
5
6
46
45
3
12
16, 22
38
42
43
10
23 24 41 29 21 27 20 17 to 19 28
HAMMING
CHECKER
AND
PACKET 26
PROCESSING
ENGINE
1996 Nov 07 4
Philips Semiconductors Preliminary specification
Integrated VIP and Teletext with
Background Memory Controller SAA5249
PINNING
SYMBOL PIN DESCRIPTION
SOT240-1 SOT319-1(1)
n.c. 1 1 not connected
n.c. 2 2 not connected
VDD1 3 25 +5 V supply
OSCOUT 4 27 27 MHz crystal oscillator output
OSCIN 5 28 27 MHz crystal oscillator input
GNDO 6 29 0 V crystal oscillator ground
VSS1 7 12 0 V ground
REF+ 8 32 positive reference voltage; this pin should be connected to ground via a
100 nF capacitor
BLACK 9 35 video black level storage pin; this pin should be connected to ground via a
100 nF capacitor
CVBS 10 36 composite video input pin; a positive-going 1 V (p-p) input is required,
connected via a 100 nF capacitor
IREF 11 37 reference current input pin; connected to ground via a 27 kΩ resistor
VDD2 12 38 +5 V supply
POL 13 39 STTV/LFB/FFB polarity selection pin
STTV/LFB 14 40 sync to TV output pin/line flyback input pin; function controlled by an
internal register bit (scan sync mode)
VCR/FFB 15 42 PLL time constant switch/field input pin; function controlled by an internal
register bit (scan sync mode)
VSS2 16 30 0 V ground
REF−−31 negative reference voltage; this pin should be connected to REF+ via a
100 nF capacitor
R 17 49 dot rate character output of the RED colour information
G 18 50 dot rate character output of the GREEN colour information
B 19 51 dot rate character output of the BLUE colour information
RGBREF 20 52 input DC voltage to define the output high level on the RGB pins
BLANK 21 53 dot rate fast blanking output
VSS3 22 54, 55 0 V ground; internally connected for SOT319
CAS0 23 56 column address select to external DRAM for BMCX function
CAS1 24 57 column address select to external DRAM for BMCX function for second
DRAM where two 256 k ×4 devices are used
A4 25 58 address output to external DRAM for BMCX function
A3 26 59 address output to external DRAM for BMCX function
COR 27 60 programmable output to provide contrast reduction of the TV picture for
mixed text and picture displays or when viewing newsflash/subtitle pages;
open drain output
ODD/EVEN 28 61 25 Hz output synchronized with the CVBS input field sync pulses to
produce a non-interlaced display by adjustment of the vertical deflection
currents
1996 Nov 07 5
Philips Semiconductors Preliminary specification
Integrated VIP and Teletext with
Background Memory Controller SAA5249
Note
1. The remaining pins for SOT319 are not connected.
Y 29 62 dot rate character output of teletext foreground colour information; open
drain output
SCL 30 63 serial clock input for I2C-bus; it can still be driven HIGH during power-down
of the device
SDA 31 64 serial data port for the I2C-bus; open drain output. It can still be driven
HIGH during power-down of the device
A5 32 4 address output to external DRAM for BMCX function
A2 33 5 address output to external DRAM for BMCX function
A6 34 6 address output to external DRAM for BMCX function
A1 35 8 address output to external DRAM for BMCX function
A7 36 9 address output to external DRAM for BMCX function
A0 37 11 address output to external DRAM for BMCX function
VSS4 38 43 0 V ground
A8 39 13 address output to external DRAM for BMCX function
A9 40 14 address output to external DRAM for BMCX function
RAS 41 15 row address select to external DRAM
R/W 42 18 read/write for external DRAM
D2 43 19 data input/output for external DRAM
D0 44 20 data input/output for external DRAM
SEL2 45 21 RAM select input to choose external DRAM size
SEL1 46 22 RAM select input to choose external DRAM size
D3 47 23 data input/output for external DRAM
D1 48 24 data input/output for external DRAM
SYMBOL PIN DESCRIPTION
SOT240-1 SOT319-1(1)
1996 Nov 07 6
Philips Semiconductors Preliminary specification
Integrated VIP and Teletext with
Background Memory Controller SAA5249
Fig.2 Pin configuration; SOT240-1 (DIP48).
MLB305
1
2
3
4
5
6
7
8
9
10
11
12
13
40
39
38
37
36
35
34
33
32
31
30
29
28
27
14
15
16
17
18
19
20
22
23
24
26
25
21
42
41
43
44
45
46
47
48
VDD1
OSCOUT
OSCIN
GNDO
VSS1
BLACK
CVBS
IREF
VDD2
POL
STTV/LFB
R
G
B
RGBREF
BLANK
Y
SCL
SDA
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D3
D2
D1
D0
VSS4
SAA5249P
REF
VCR/FFB
COR
ODD/EVEN
RAS
SEL2
SEL1
R/W
CAS1
CAS0
VSS3
VSS2
n.c.
n.c.
1996 Nov 07 7
Philips Semiconductors Preliminary specification
Integrated VIP and Teletext with
Background Memory Controller SAA5249
Fig.3 Pin configuration; SOT319-1 (QFP64).
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
51
50
49
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
48
20
21
22
24
25
26
27
28
29
30
31
32
23
64
63
62
60
59
58
57
56
55
54
53
52
61
MLB306
D2
n.c.
n.c.
A9
A8
SS1
A7
A1
n.c.
A6
A2
A5
n.c.
SAA5249GP
n.c.
BLACK
IREF
CVBS
POL
STTV/LFB
VCR/FFB
n.c.
n.c.
VSS4
VDD2
n.c.
n.c.
SDA
SCL
Y
ODD/EVEN
COR
A3
CAS1
CAS0
RGBREF
BLAN
SS3
A4
VDD1
D1
D3
SEL1
SEL2
D0
n.c.
REF
REF
VSS2
OSCOUT
OSCIN
GNDO
n.c.
n.c.
A0
RAS
R/W
index
corner
V
B
G
R
V
SS3
V
1996 Nov 07 8
Philips Semiconductors Preliminary specification
Integrated VIP and Teletext with
Background Memory Controller SAA5249
LIMITING VALUES
In accordance with Absolute Maximum Rating System (IEC 134).
QUALITY AND RELIABILITY
This device will meet Philips Semiconductors General Quality Specification for Business group
“Consumer Integrated
Circuits SNW-FQ-611-Part E”
. The principal requirements are shown in Tables 1 to 4.
SYMBOL PARAMETER MIN. MAX. UNIT
VDD supply voltage (all supplies) −0.3 +6.5 V
VIinput voltage (any input) −0.3 VDD + 0.5 V
VOoutput voltage (any output) −0.3 VDD + 0.5 V
IOoutput current (each output) −±10 mA
IIOK DC input or output diode current −±20 mA
Tamb operating ambient temperature −20 +70 °C
1996 Nov 07 9
Philips Semiconductors Preliminary specification
Integrated VIP and Teletext with
Background Memory Controller SAA5249
Group A
Table 1 Acceptance tests per lot
Group B
Table 2 Processability tests (by package family)
Group C
Table 3 Reliability tests (by process family)
Table 4 Reliability tests (by device type)
Note to Tables 1 to 4
1. ppm = fraction of defective devices, in parts per million.
LTPD = Lot Tolerance Percent Defective.
FPM = fraction of devices failing at test condition, in Failures Per Million.
FITS = Failures In Time Standard.
TEST REQUIREMENTS(1)
Mechanical cumulative target: <100 ppm
Electrical cumulative target: <100 ppm
TEST REQUIREMENTS(1)
Solderability <7% LTPD
Mechanical <15% LTPD
Solder heat resistance <15% LTPD
TEST CONDITIONS REQUIREMENTS(1)
Operational life 168 hours at Tj= 150 °C <1500 FPM; equivalent to <100 FITS
at Tj=70°C
Humidity life temperature, humidity, bias
(1000 hours, 85 °C, 85% RH or
equivalent test)
<2000 FPM
Temperature cycling performance Tstg(min) to Tstg(max) <2000 FPM
TEST CONDITIONS REQUIREMENTS(1)
ESD and latch-up ESD Human body model
2000 V, 100 pF, 1.5 kΩ<15% LTPD
ESD Machine model
200 V, 100 pF, 1.5 kΩ<15% LTPD
latch-up 100 mA, 1.5 ×VDD
(absolute maximum) <15% LTPD
1996 Nov 07 10
Philips Semiconductors Preliminary specification
Integrated VIP and Teletext with
Background Memory Controller SAA5249
CHARACTERISTICS
VDD =5V±10%; Tamb =−20 to +70 °C; unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Supplies
VDD supply voltage 4.5 5.0 5.5 V
IDD(tot) total supply current −90 120 mA
Inputs
CVBS
Vsync sync amplitude 0.1 0.3 0.6 V
td(sync) delay from CVBS to TCS output
from STTV buffer (nominal video,
average of leading/trailing edge)
−150 0 +150 ns
∆td(sync) change in sync delay between all
black and all white video input at
nominal levels
0−25 ns
Vvid(p-p) video input amplitude
(peak-to-peak value) 0.7 1.0 1.4 V
display PLL catching range ±7−−%
Z
source source impedance −−250 Ω
Ciinput capacitance −−10 pF
IREF
Rgnd resistor to ground −27 −kΩ
POL
VIL LOW level input voltage −0.3 −+0.8 V
VIH HIGH level input voltage 2.0 −VDD + 0.5 V
ILI input leakage current Vi= 0 to VDD −10 −+10 µA
Ciinput capacitance −−10 pF
LFB
VIL LOW level input voltage −0.3 −+0.8 V
VIH HIGH level input voltage 2.0 −VDD + 0.5 V
ILI input leakage current Vi= 0 to VDD −10 −+10 µA
Iiinput current note 1 −1−+1 mA
td(LFB) delay between LFB front edge
and input video line sync −250 −ns
VCR/FFB
VIL LOW level input voltage −0.3 −+0.8 V
VIH HIGH level input voltage 2.0 −VDD + 0.5 V
ILI input leakage current Vi= 0 to VDD −10 −+10 µA
Iiinput current note 1 −1−+1 mA
1996 Nov 07 11
Philips Semiconductors Preliminary specification
Integrated VIP and Teletext with
Background Memory Controller SAA5249
RGBREF note 2
VIL LOW level input voltage −0.3 −VDD + 0.5 V
ILI input leakage current Vi= 0 to VDD −10 −+10 µA
IDC DC current −−10 mA
SEL1 AND SEL2
VIL LOW level input voltage −0.3 −+0.8 V
VIH HIGH level input voltage 2.0 −VDD + 0.5 V
ILI input leakage current Vi= 0 to VDD −10 −+10 µA
SCL
VIL LOW level input voltage −0.3 −+1.5 V
VIH HIGH level input voltage 3.0 −VDD + 0.5 V
ILI input leakage current Vi= 0 to VDD −10 −+10 µA
fSCL clock frequency 0 −100 kHz
trinput rise time 10% to 90% −−2µs
t
finput fall time 90% to 10% −−2µs
C
iinput capacitance −−10 pF
Inputs/outputs
CRYSTAL OSCILLATOR (OSCIN; OSCOUT)
fXTAL crystal frequency −27 −MHz
Gvsmall signal voltage gain 3.5 −−
G
mmutual conductance fi= 100 kHz 1.5 −−mA/V
Ciinput capacitance −−10 pF
CFB feedback capacitance −−5pF
BLACK
Cblk storage capacitor to ground −100 −nF
ILI input leakage current Vi= 0 to VDD −10 −+10 µA
SDA
VIL LOW level input voltage −0.3 −+1.5 V
VIH HIGH level input voltage 3.0 −VDD + 0.5 V
ILI input leakage current Vi= 0 to VDD −10 −+10 µA
Ciinput capacitance −−10 pF
trinput rise time 10% to 90% −−2µs
t
finput fall time 90% to 10% −−2µs
V
OL LOW level output voltage IOL = 3 mA 0 −0.5 V
tfoutput fall time 3 V to 1 V −−200 ns
CLload capacitance −−400 pF
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
1996 Nov 07 12
Philips Semiconductors Preliminary specification
Integrated VIP and Teletext with
Background Memory Controller SAA5249
D0 TO D3
VIL LOW level input voltage −0.3 −+0.8 V
VIH HIGH level input voltage 2.0 −VDD + 0.5 V
ILI input leakage current −10 −+10 µA
Ciinput capacitance −−10 pF
VOL LOW level output voltage IOL = +1.6 mA 0 −0.4 V
VOH HIGH level output voltage IOH =−0.2 mA 2.4 −VDD V
troutput rise time 0.6 to 2.2 V −−20 ns
tfoutput fall time 2.2 to 0.6 V −−20 ns
CLload capacitance −−50 pF
Outputs
STTV
Gstt gain of STTV relative to video
input 0.9 1.0 1.1
VTCS TCS amplitude 0.2 0.3 0.45 V
VDCs DC shift between TCS output and
nominal video output −−0.15 V
IOoutput drive current −−3.0 mA
CLload capacitance −−100 pF
A0 TO A9 ADDRESS OUTPUT TO MEMORY A0 TO A9
VOL LOW level output voltage IOL = +1.6 mA 0 −0.4 V
VOH HIGH level output voltage IOH =−0.2 mA 2.4 −VDD V
CLload capacitance −−50 pF
troutput rise time 0.6 to 2.2 V −−20 ns
tfoutput fall time 2.2 to 0.6 V −−20 ns
R/W, CASO AND CAS1
VOL LOW level output voltage IOL = +1.6 mA 0 −0.4 V
VOH HIGH level output voltage IOH =−0.2 mA 2.4 −VDD V
CLload capacitance −−50 pF
troutput rise time 0.6 to 2.2 V −−20 ns
tfoutput fall time 2.2 to 0.6 V −−20 ns
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
1996 Nov 07 13
Philips Semiconductors Preliminary specification
Integrated VIP and Teletext with
Background Memory Controller SAA5249
R, G AND B
VOL LOW level output voltage IOL = 2 mA 0 −0.2 V
VOH HIGH level output voltage IOH =−1.6 mA;
RGBREF ≤VDD −2V RGBREF
−0.25 RGBREF RGBREF
+0.25 V
|Zo|output impedance −−200 Ω
CLload capacitance −−50 pF
IDC DC current −−−3.3 mA
troutput rise time 10% to 90% −−20 ns
tfoutput fall time 90% to 10% −−20 ns
BLANK
VOL LOW level output voltage IOL = 1.6 mA 0 −0.4 V
VOH HIGH level output voltage IOH =−0.2 mA;
VDD = 4.5 V 1.1 −−V
V
OH HIGH level output voltage IOH = 0 mA;
VDD = 5.5 V −−2.8 V
VOH allowed voltage at pin with external pull-up −−V
DD V
CLload capacitance −−50 pF
troutput rise time 10% to 90% −−20 ns
tfoutput fall time 90% to 10% −−20 ns
ODD/EVEN
VOL LOW level output voltage IOL = +1.6 mA 0 −0.4 V
VOH HIGH level output voltage IOH =−0.2 mA 2.4 −VDD V
CLload capacitance −−120 pF
troutput rise time 0.6 to 2.2 V −−50 ns
tfoutput fall time 2.2 to 0.6 V −−50 ns
COR AND Y(OPEN-DRAIN)
VOH pull-up voltage at pin −−V
DD V
VOL output voltage LOW IOL = 5 mA 0 −1.0 V
CLload capacitance −−25 pF
tfoutput fall time load resistor of 1.2 kΩ
to VDD; measured
between VDD −0.5 V
and 1.5 V
−−50 ns
ILO output leakage current Vi= 0 to VDD −10 −+10 µA
tskew skew delay between display
outputs R, G, B, COR, Y and
BLANK
−−20 ns
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
1996 Nov 07 14
Philips Semiconductors Preliminary specification
Integrated VIP and Teletext with
Background Memory Controller SAA5249
Timing
DRAM INTERFACE
tRC read or write cycle time 344 380 415 ns
tRP RAS precharge time 125 140 155 ns
tRAS RAS pulse width 194 210 230 ns
tCAS CAS pulse width 113 133 153 ns
tASR row address set-up time 30 60 80 ns
tRAH row address hold time 50 60 92 ns
tASC column address set-up time 50 60 75 ns
tCAH column address hold time 50 60 70 ns
tRCD RAS to CAS delay time 130 148 160 ns
tRAD RAS to column address delay
time 60 74 105 ns
tRSH RAS hold time 15 60 70 ns
tCSH CAS hold time 260 286 300 ns
tCRP CAS to RAS precharge time 60 70 80 ns
tDZO CAS set-up time from data input 200 225 280 ns
tr, tfrise and fall times 10 15 20 ns
tWCS write set-up time 193 212 235 ns
tWCH write command hold time 116 137 150 ns
tDS data input set-up time 193 212 235 ns
tDH data input hold time 42 62 80 ns
tRAC access time from RAS 165 183 220 ns
tCAC access time from CAS 0 3540ns
t
AA access time from address 95 108 120 ns
tRCS read command set-up time 193 212 235 ns
tRCH read command hold time to CAS 0 1020ns
t
RRH read command hold time to RAS 55 65 100 ns
tRAL column address to RAS lead time 90 133 150 ns
tOFF1 output buffer turn-off time 20 30 40 ns
tCDD CAS to data input delay time 25 35 45 ns
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
1996 Nov 07 15
Philips Semiconductors Preliminary specification
Integrated VIP and Teletext with
Background Memory Controller SAA5249
Notes
1. This current is the maximum allowed into the inputs when line and field flyback signals are connected to these inputs.
Series current limiting resistors must be used to limit the input currents to ±1 mA.
2. RGBREF is the positive supply pin for the RGB output pins and it must be able to source the IOH current from the
R, G and B pins. The leakage specification on RGBREF only applies when there is no current load on the RGB pins.
I2C-BUS
tLOW clock LOW period 4 −−µs
t
HIGH clock HIGH period 4 −−µs
t
SU;DAT data set-up time 250 −−ns
tHD;DAT data hold time 170 −−ns
tSU;STO set-up time from clock HIGH to
STOP 4−−µs
t
BUF START set-up time following a
STOP 4−−µs
t
HD;STA START hold time 4 −−µs
t
SU;STA START set-up time following
clock LOW-to-HIGH transition 4−−µs
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
1996 Nov 07 16
Philips Semiconductors Preliminary specification
Integrated VIP and Teletext with
Background Memory Controller SAA5249
handbook, full pagewidth
0 4.66
0 2.33
0
32 34.33
27.33 32
64 µs
59.33
621
(308) 622
(309) 623
(310) 624
(311) 625
(312) 1 2 3456 7
308 309 310 311 312 1 2 3 4 5 6 7
309 310 311 312 313 314 (1) 315 (2) 316 (3) 317 (4) 318 (5) 319 (6) 320 (7)
LSP
(Line Sync Pulse)
EP
(Equalizing Pulse)
BP
(Broad Pulse)
TCS interlaced
TCS interlaced
TCS non-interlaced
MLA037 - 2
64 µs
64 µs
Fig.4 Composite sync waveforms.
1996 Nov 07 17
Philips Semiconductors Preliminary specification
Integrated VIP and Teletext with
Background Memory Controller SAA5249
Fig.5 Display output timing (a) line rate (b) field rate.
(1) Also BLANK in character and box blanking.
handbook, full pagewidth
0 4.66
0
0
LSP
MLA662 - 1
(TCS)
16.67
41
R, G, B, Y
(1)
R, G, B, Y
(1) display period
display period
lines 42 to 291 inclusive (and 355 to 604 inclusive interlaced)
291 312
line numbers
56.67 µs
40 µs64 µs
Fig.6 I2C-bus timing.
handbook, full pagewidth
MBC764
tBUF tf
tHIGH
tSU;DAT
tSU;STO
tHD;DAT
tSU;STA
tr
tLOW
tHD;STA
SDA
SCL
SDA
1996 Nov 07 18
Philips Semiconductors Preliminary specification
Integrated VIP and Teletext with
Background Memory Controller SAA5249
Fig.7 DRAM interface timing; read cycle.
MBA732
tRP
tRSH
tRAS
tRC
tRCD
tftCAS
tCSH
tCRP
tRAH
tASR tASC
ttCAH RCH
t
RAS
CAS
ADDRESS
WE
DATA OUTPUT
DATA INPUT
RAL
t
tRAD
tCAC
tAA RRH
t
OFF1
t
RAC
t
DZO
tt
CDD
RCS
ROW COLUMN
DATA VALID
high impedance
high impedance
1996 Nov 07 19
Philips Semiconductors Preliminary specification
Integrated VIP and Teletext with
Background Memory Controller SAA5249
Fig.8 DRAM interface timing; write cycle.
MBA731
tRP
tRSH
tRAS
tRC
tRCD
tftCAS
tCSH
tCRP
tRAH
tASR
ROW
tASC
WCS
ttCAH
WCH
t
tDS tDH
DATA VALID
high impedance
RAS
CAS
ADDRESS
WE
DATA OUTPUT
DATA INPUT
COLUMN
1996 Nov 07 20
Philips Semiconductors Preliminary specification
Integrated VIP and Teletext with
Background Memory Controller SAA5249
FIRST FIELD START (EVEN)
621
(308) 622
(309) 623
(310) 624
(311) 625
(312) 1 2 3456 7
309 310 311 312 313 314 (1) 315 (2) 316 (3) 317 (4) 318 (5) 319 (6) 320 (7)
SECOND FIELD START (ODD)
TCS interlaced
ODD/EVEN output
(normal sync mode)
ODD/EVEN output
(normal sync mode
when VCS to SCS
mode active)
ODD/EVEN output
(slave sync mode)
TCS interlaced
ODD/EVEN output
(normal sync mode)
ODD/EVEN output
(normal sync mode
when VCS to SCS
mode active)
ODD/EVEN output
(slave sync mode)
MBA073 - 4
2 µs
48 µs
31 µs
2 µs
16 µs
31 µs
Fig.9 ODD/EVEN timing.
1996 Nov 07 21
Philips Semiconductors Preliminary specification
Integrated VIP and Teletext with
Background Memory Controller SAA5249
APPLICATION INFORMATION
FOR +VE GOING
SYNC FIT LK1
D3
12
COR
27
L1
3.3 µH
C4
100 nF
+5 V
R2
1 kΩ
LK1
LINK
LK2
LINK
R3
1 kΩ
C9
100 nF
R9
27 kΩ
IC1
SAA5249
C10 100 nF
NOTE :
FOR - VE
GOING
SYNC FIT LK2
R G B BLANKING ODD/EVEN
C8 100 nF
C1
100 nF C2
33 µF
+5 V
KEY
KEY
KEY
GND
+5 V
n.c.
OE
IC2 IC3
-
256K x 4
256K x 4
-
-
256K x 4
DRAM (120 nS)
X3 1 23456
1
2
3
4
5
1
2
3
4
C13
100 nF
C14
100
nF
LK3
LINK LK4
LINK
R9
4.7 kΩR10
4.7 kΩ
D3
4
15
15
IC2
IC3
X2
X1
KEY
SCL SDA
GND
123
X4
+5 V
R5
4.7 kΩR6
4.7 kΩR7 220 Ω
R8 220 Ω
LINK
34
1M x 4 -
VCR
CVBS
STTV
+5 V
C3
100
nF
D
+5 V
R1
10 kΩ
IC2 and IC3 pin-outs are for
Dual In-Line Package (DIP)
VCC
VSS
DD2
V
VDD1
VSS1
V , V
SS3 SS4
VCC
VSS
OE
SS2
MLB307
R11
3.3 kΩ
C7
15 pF G1
27 MHz
C5 8.2 pF
C7 1 nF
C11
100 nF
C12
10 µF
C13 and C14
are optional
surface mounted
capacitors mounted
close to IC
5
1
3
7
6
10
20
19
18
17
16
14
13
12
8
9
2
D2
D1
D0
A8
A7
A6
A3
A1
A0
WE
RAS
CAS
A4
A2
A5
5
1
D3
4
D1
7
D0
6A8
20
D2
3
A7
19
A6
18
A0
11
A5
17
A1
12 A2
13 A3
14 A4
15
A9
10 WE
8RAS
9
CAS
2
D1
D0
A8
D2
A7
A6
A0
A5
A1
A2
A3
A4
A9
R/W
RAS
CAS0
47
48
44
39
43
36
34
37
32
35
33
26
25
40
42
41
23
24
46
45
CAS1
SEL1
SEL2
3
ODD/EVEN
B
G
R
BLANK
Y
VCR
POL
CVBS
V
RGBREF
BLACK
STTV
OSCOUT
OSCIN
REF +
IREF
GNDO
SCL
SDA
28
19
18
17
21
29
15
13
10
16
20
9
14
4
5
8
7
6
30
31
11
22, 38
Fig.10 Application diagram; 1 or 4 Mbit DRAM.
1996 Nov 07 22
Philips Semiconductors Preliminary specification
Integrated VIP and Teletext with
Background Memory Controller SAA5249
IVT1.1BMCX page memory organization
The organization of the page memory is illustrated by Fig.11. The IVT1.1BMCX provides an additional row as compared
with first generation decoders; this brings the display format up to 40 characters by 25 rows. Rows 0 to 23 form the
teletext page; Row 24 is the extra row available for software generated status messages and FLOF/FASTEXT prompt
information.
Fig.11 Basic page memory organization.
MBA274
7 characters
for status
8 characters
always rolling
(time)
fixed character
written by IVT hardware
alphanumerics white for normal
alphanumerics green when looking
for display page
71 824
24 characters from page header
rolling when display page looked for
5
to
20
0
1
2
3
4
ROW
21
22
23
24
25
MAIN PAGE DISPLAY AREA
PACKET X / 22
PACKET X / 23
PACKET X / 24 STORED HERE IF R0D7 = 1
10 14
10 bytes for
received
page information
14 bytes
free for use
by microcontroller
Fig.12 Organization of the extension memory.
MBA275 - 2
PACKET X / 24 if R0D7 = 0
PACKET X / 27 / 0
PACKETS 8 / 30 / 0 to 15
1
0
2
ROW
REMARK TO Fig.11
Row 0
Row 0 is for the page header. The first seven columns
(0 to 6) are free for status messages. The eighth is an
alphanumeric white or green control character, written
automatically by IVT1.1BMCX to give a green rolling
header when a page is being looked for. The last eight
characters are for rolling time.
Row 25
The first 10 bytes of row 25 contain control data relating to
the received page as shown in Table 5. The remaining
14-bytes are free for use by the microcomputer.
1996 Nov 07 23
Philips Semiconductors Preliminary specification
Integrated VIP and Teletext with
Background Memory Controller SAA5249
Table 5 Row 25 received control data format
Table 6 Page number and sub-code for Table 5
D0 PU0 PT0 MU0 MT0 HU0 HT0 C7 C11 MAG0 0
D1 PU1 PT1 MU1 MT1 HU1 HT1 C8 C12 MAG1 0
D2 PU2 PT2 MU2 MT2 HU2 C5 C9 C13 MAG2 0
D3 PU3 PT3 MU3 C4 HU3 C6 C10 C14 0 0
D4 HAM.ER HAM.ER HAM.ER HAM.ER HAM.ER HAM.ER HAM.ER HAM.ER FOUND 0
D5 0 0 0 0 0 0 0 0 0 PBLF
D60000000000
D70000000000
Column 0 1 2 3 4 5 6 7 8 9
Page number
MAG magazine
PU page units
PT page tens
PBLF page being looked for
FOUND LOW for page has been found
HAM.ER hamming error in corresponding byte
Page sub-code
MU minutes units
MT minutes tens
HU hours units
HT hours tens
C4 to C14 transmitted control bits
1996 Nov 07 24
Philips Semiconductors Preliminary specification
Integrated VIP and Teletext with
Background Memory Controller SAA5249
Register maps
IVT1.1BMCX mode registers R0 to R11 are shown in Table 7. R0 to R10 are write only; R11 is read/write.
Register map (R3), for page requests, is shown in detail in Table 9.
Table 7 Register map (notes 1 to 5)
REGISTER D7 D6 D5 D4 D3 D2 D1 D0
Adv. control 0 X24 POS FREE
RUN PLL AUTO
ODD/
EVEN
DISABLE
HDR
ROLL
DISPLAY
SRATUS
ROW
ONLY
DISABLE
ODD/
EVEN
−R11/R11B
SELECT
Mode 1 VCS TO
SCS 7 + P/
8-BIT ACQ
ON/OFF DISABLE
PKT 26 DEW/
FULL
FIELD
TCS
ON T1 T0
Page
request
address
2−− − − TB START
COLUMN
SC2
START
COLUMN
SC1
START
COLUMN
SC0
Page
request
data
3−− CLEAR
B.M. PRD4 PRD3 PRD2 PRD1 PRD0
−−−−−−−−
Display
control
(normal)
5 BKGND
OUT BKGND IN COR OUT COR IN TEXT OUT TEXT IN PON OUT PON IN
Display
control
(newsflash
/subtitle)
6 BKGND
OUT BKGND IN COR OUT COR IN TEXT OUT TEXT IN PON OUT PON IN
Display
mode 7 STATUS
BTM
TOP
CURSOR
ON CONCEA
L REVEAL
ON
TOP/BTM
HALF SINGLE
DOUBLE
HEIGHT
BOX ON
24 BOX ON
1-23 BOX ON 0
−−−−−−−−
Cursor row 9 −CLEAR
MEM. A0 R4 R3 R2 R1 R0
Cursor
column 10 −− C5 C4 C3 C2 C1 C0
Cursor data 11 D7 D6 D5 D4 D3 D2 D1 D0
Device
status 11B 625/525
SYNC ROM VER
R4 ROM
VER R3 ROM VER
R2 ROM VER
R1 ROM
VER R0 TEXT
SIGNAL
QUALITY
VCS
SIGNAL
QUALITY
1996 Nov 07 25
Philips Semiconductors Preliminary specification
Integrated VIP and Teletext with
Background Memory Controller SAA5249
Notes
1. The dash (−) indicates these bits are inactive and must be written to logic 0 for future compatibility.
2. All bits in registers R0 to R10 are cleared to logic 0 on power-up except bits D0 and D1 of Registers R1, R5 and R6
which are set to logic 1.
3. All memory is cleared to space (00100000) on power-up, except Row 0 Column 7 Chapter 0, which is alpha white
(00000111) as the acquisition circuit is enabled but the page is on hold.
4. TB must be set to logic 0 for normal operation.
5. The I2C-bus slave address is 0010001.
Table 8 Register description
R0 ADVANCED CONTROL - auto increments to register 1
R11/R11B SELECT selects reading of R11 or R11B
DISABLE ODD/EVEN forces ODD/EVEN output LOW when logic 1
DISPLAY STATUS ROW when SET = 1 and R1D6 = 1 open (8-bit mode) then all the text display is blanked
out apart from the status row, this allows the page memory to be used for
non-textural data, such as in the German TOP system
DISABLE HDR ROLL disables green rolling header and time
AUTO ODD/EVEN when set forces ODD/EVEN LOW if any TV picture displayed, if DISABLE
ODD/EVEN = 0
FREE RUN PLL will force the PLL to free run in all conditions
X24 POS automatic display of FASTEXT prompt row when logic 1
R1 MODE - auto increments to register 2
T0, T1 interlace/non-interlace 312/313 line control (see Table 10)
TCS ON text composite sync or direct sync select (see Table 10 for FFB mode selection)
DEW/FULL FIELD field-flyback or full-channel mode
DISABLE PKT 26 disable automatic processing of packet 26
ACQ ON/OFF acquisition circuits turned off when logic 1
7 + P/8-BIT 7-bits with parity checking or 8-bit mode
VCS TO SCS when logic 1 enables display of messages with 60 Hz input signal
R2 PAGE REQUEST ADDRESS - auto increments to register 3
COL SCO - SC2 point to start column for page request data (see Table 9)
TB must be logic 0 for normal operation
R3 PAGE REQUEST DATA - does not auto increment (see Table 9)
CLEAR B.M. when set to logic 1. Useful when transmission channel changes
R5 NORMAL DISPLAY CONTROL - auto increments to register 6
R6 NEWSFLASH/SUBTITLE DISPLAY CONTROL - auto increments to register 7; (note 1)
PON picture on
TEXT text on
COR contrast reduction on
BKGND background colour on
1996 Nov 07 26
Philips Semiconductors Preliminary specification
Integrated VIP and Teletext with
Background Memory Controller SAA5249
Note
1. These functions have IN and OUT referring to inside and outside the boxing function respectively.
R7 DISPLAY MODE - does not auto increment
BOX ON 0 boxing function allowed on Row 0
BOX ON 1-23 boxing function allowed on Rows 1 to 23
BOX ON 24 boxing function allowed on Row 24
DOUBLE HEIGHT to display double height text
BOTTOM HALF to select bottom half of page when DOUBLE HEIGHT = 1
REVEAL ON to reveal concealed text
CURSOR ON to display cursor
STATUS TOP row 25 displayed above or below the main text
R9 CURSOR ROW - auto increments to register 10
R0 to R4 active row for data written to or read from memory via the I2C-bus
A0 selects display memory page (when = 0) or extension packet memory (when = 1)
CLEAR MEM. when set to 1, clears the display memory; this bit is automatically reset
R10 CURSOR COLUMN - auto increments to register 11 or 11B
C0 to C5 active column for data written to or read from memory via the I2C-bus
R11 CURSOR DATA - does not auto increment
D0 to D7 data read from/written to memory via I2C-bus, at location pointed to by R9 and
R10. This location automatically increments each time R11 is accessed
R11B DEVICE STATUS - does not auto increment
VCS SIGNAL QUALITY indicates that the video signal quality is good and PLL is phase locked to input
video when = 1
TEXT SIGNAL QUALITY if a good teletext signal is being received when logic 1
ROM VER R0 to R4 indicated language/ROM variant. For Western European = 11000
625/525 SYNC if the input video is a 525 line signal when logic 1
1996 Nov 07 27
Philips Semiconductors Preliminary specification
Integrated VIP and Teletext with
Background Memory Controller SAA5249
Table 9 Register map for page requests (R3); notes 1 to 5
Notes
1. Abbreviations are as for Table 5 except for DO CARE bits.
2. When the DO CARE bit is set to logic 1 this means the corresponding digit is to be taken into account for page
requests. If the DO CARE bit is set to logic 0 the digit is ignored. This allows, for example, normal or timed page
selection.
3. If HOLD is set LOW, the page is held and not updated.
4. Columns auto-increment on successive I2C-bus transmission bytes.
5. X = don't care.
Table 10 Interlace/non-interlace 312/313 line control and ODD/EVEN field detection option; notes 1 and 2
Notes
1. Reverts to interlaced mode if a newsflash or subtitle is being displayed.
2. X = Don't care.
START COLUMN PRD4 PRD3 PRD2 PRD1 PRD0
0 DO CARE
magazine HOLD MAG2 MAG1 MAG0
1 DO CARE
page tens PT3 PT2 PT1 PT0
2 DO CARE
page units PU3 PU2 PU1 PU0
3 DO CARE
hours tens X X HT1 HT0
4 DO CARE
hours units HU3 HU2 HU1 HU0
5 DO CARE
minutes tens X MT2 MT1 MT0
6 DO CARE
minutes units MU3 MU2 MU1 MU0
TCS ON
FFB MODE T1 T0 RESULT
X 0 0 interlaced 312.5/312.5 lines
X 0 1 non-interlaced 312/313 lines (note 1)
X 1 0 non-interlaced 312/313 lines (note 1)
011
SCS (scan composite sync) mode: FFB leading edge in first broad
pulse of field
111
SCS (scan composite sync) mode: FFB leading edge in second
broad pulse of field
1996 Nov 07 28
Philips Semiconductors Preliminary specification
Integrated VIP and Teletext with
Background Memory Controller SAA5249
CLOCK SYSTEMS
Crystal oscillator
The crystal is a conventional 2-pin design operating at 27 MHz. It is capable of oscillating with both fundamental and third
overtone mode crystals. External components should be used to suppress the fundamental output of the third overtone
as illustrated in Fig.13.
Table 11 Crystal characteristics (see Fig.13)
SYMBOL PARAMETER MIN. TYP. MAX. UNIT
Crystal (27 MHz, 3rd overtone)
C1 series capacitance −1.7 −pF
C0 parallel capacitance −5.2 −pF
CLload capacitance −20 −pF
Rrresonance resistance −−50 Ω
R1 series resistance −20 −Ω
X
aageing −−±510
−6
/year
Xjadjustment tolerance −−±25 10−6
Xddrift −−±25 10−6
Fig.13 Crystal oscillator application diagram for SOT240-1; pins in parenthesis are for SOT319-1.
5 (28)
4 (27)
SAA5249
MLB308
6 (29)
3 (25)
8.2 pF CRYSTAL
OSCILLATOR
100 nF15 pF
1 nF 3.3 µH
3.3 kΩGNDO
OSCIN
OSCOUT
VDD1
27 MHz
3rd
overtone
1996 Nov 07 29
Philips Semiconductors Preliminary specification
Integrated VIP and Teletext with
Background Memory Controller SAA5249
CHARACTER SETS
The WST specification allows the selection of national character sets via the page header transmission bits, C12 to C14.
The basic 96 character sets differ only in 13 national option characters as indicated in the Tables 16, 17 and 18 with
reference to their table position in the basic character matrix illustrated in Table 15. The IVT1.1BMCX automatically
decodes transmission bits C12 to C14. Tables 12, 13 and 14 illustrate the character matrixes.
Character bytes are listed as transmitted from b1 to b7.
Fig.14 Character format.
handbook, full pagewidth
MLA663
alphanumerics and
graphics 'space'
character
0000010
alphanumerics
character
1011010
alphanumerics or
blast-through
alphanumerics
character
0001001
alphanumerics
character
1111111
contiguous
graphics character
1111111
separated
graphics character
1111111
separated
graphics character
0110111
contiguous
graphics character
0110111
background
colour display
colour
= =
1996 Nov 07 30
Philips Semiconductors Preliminary specification
Integrated VIP and Teletext with
Background Memory Controller SAA5249
Table 12 SAA5249P/E character data input decoding, West European languages; notes 1 to 9
For character version number (11000) see Register 11B.
handbook, full pagewidth
MBA429
normal
height
b4b3b2b1
b5
b6
b7
b8
0 1 22a3 3a4 5 66a77a8 912131415
column
r
o
w
B
I
T
S
0
0
0
0
0
0
0
1
0 or 1
01
0
0
01
1
0 or 1
01
1
0
01
1
0
10
0
0
10
1
1
00
0
1
00
1
1
10
0
1
10
1
1
11
0
1
11
1
0
1
1
0
0
1
1
1
141 1 1 0 SO hold
graphics
151 1 1 1 SI release
graphics
111 0 1 1 start box ESC
121 1 0 0 black
back -
ground
131 1 0 1 double
height
new
back -
ground
101 0 1 0 end box separated
graphics
91 0 0 1 steady contiguous
graphics
8
1 0 0 0 flash conceal
display
70 1 1 1 alpha -
numerics
white
graphics
white
60 1 1 0 alpha -
numerics
cyan graphics
cyan
5
0 1 0 1 alpha -
numerics
magenta
graphics
magenta
40 1 0 0 alpha -
numerics
blue graphics
blue
30 0 1 1 alpha -
numerics
yellow
graphics
yellow
2
0 0 1 0 alpha -
numerics
green
graphics
green
0
0 0 0 0 alpha -
numerics
black graphics
black
10 0 0 1 alpha -
numerics
red graphics
red
(2)
(2) (2)
(2)
(1)
(2) (2)
(1) (2)
(1)
1996 Nov 07 31
Philips Semiconductors Preliminary specification
Integrated VIP and Teletext with
Background Memory Controller SAA5249
Table 13 SAA5249P/H character data input decoding, West European languages; notes 1 to 9
For character version number (11001) see Register 11B.
handbook, full pagewidth
MLA961
normal
height
b4b3b2b1
b5
b6
b7
b8
0 1 22a3 3a4 5 66a77a8 912131415
column
r
o
w
B
I
T
S
0
0
0
0
0
0
0
1
0 or 1
01
0
0
01
0
0 or 1
01
1
0
01
1
0
10
0
0
10
1
1
00
0
1
00
1
1
10
0
1
10
1
1
11
0
1
11
1
0
1
1
0
0
1
1
1
141 1 1 0 SO hold
graphics
151 1 1 1 SI release
graphics
111 0 1 1 start box ESC
121 1 0 0 black
back -
ground
131 1 0 1 double
height
new
back -
ground
101 0 1 0 end box separated
graphics
91 0 0 1 steady contiguous
graphics
8
1 0 0 0 flash conceal
display
70 1 1 1 alpha -
numerics
white
graphics
white
60 1 1 0 alpha -
numerics
cyan graphics
cyan
5
0 1 0 1 alpha -
numerics
magenta
graphics
magenta
40 1 0 0 alpha -
numerics
blue graphics
blue
30 0 1 1 alpha -
numerics
yellow
graphics
yellow
2
0 0 1 0 alpha -
numerics
green
graphics
green
0
0 0 0 0 alpha -
numerics
black graphics
black
10 0 0 1 alpha -
numerics
red graphics
red
(2)
(2) (2)
(2)
(1)
(2) (2)
(1) (2)
(1)
1996 Nov 07 32
Philips Semiconductors Preliminary specification
Integrated VIP and Teletext with
Background Memory Controller SAA5249
Table 14 SAA5249P/T character data input decoding, West European and Turkish languages; notes 1 to 9
For character version number (11010) see Register 11B.
handbook, full pagewidth
MBA431
normal
height
b4b3b2b1
b5
b6
b7
b8
0 1 22a3 3a4 5 66a77a8 912131415
column
r
o
w
B
I
T
S
0
0
0
0
0
0
0
1
0 or 1
01
0
0
01
1
0 or 1
01
1
0
01
1
0
10
0
0
10
1
1
00
0
1
00
1
1
10
0
1
10
1
1
11
0
1
11
1
0
1
1
0
0
1
1
1
141 1 1 0 SO hold
graphics
151 1 1 1 SI release
graphics
111 0 1 1 start box ESC
121 1 0 0 black
back -
ground
131 1 0 1 double
height
new
back -
ground
101 0 1 0 end box separated
graphics
91 0 0 1 steady contiguous
graphics
8
1 0 0 0 flash conceal
display
70 1 1 1 alpha -
numerics
white
graphics
white
60 1 1 0 alpha -
numerics
cyan graphics
cyan
5
0 1 0 1 alpha -
numerics
magenta
graphics
magenta
40 1 0 0 alpha -
numerics
blue graphics
blue
30 0 1 1 alpha -
numerics
yellow
graphics
yellow
2
0 0 1 0 alpha -
numerics
green
graphics
green
0
0 0 0 0 alpha -
numerics
black graphics
black
10 0 0 1 alpha -
numerics
red graphics
red
(2)
(2) (2)
(2)
(1)
(2) (2)
(1) (2)
(1)
1996 Nov 07 33
Philips Semiconductors Preliminary specification
Integrated VIP and Teletext with
Background Memory Controller SAA5249
Table 15 SAA5249P/R character data input decoding, Baltic and Cyrillic languages; notes 1 to 9
For character version number (11101) see Register 11B.
h
andbook, full pagewidth
normal
height
b4b3b2b1
b5
b6
b7
b8
01 22a33a4 5 66a77a8 912131415
column
r
o
w
B
I
T
S
0
0
0
0
0
0
0
1
0 or 1
0
1
0
0
0
1
1
0 or 1
0
1
1
0
0
1
1
0
1
0
0
0
1
0
1
1
0
0
0
1
0
0
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
0
1
1
0
0
1
1
1
141 1 1 0 SO hold
graphics
151 1 1 1 SI release
graphics
111 0 1 1 start box TWIST
121 1 0 0 black
back -
ground
131 1 0 1 double
height
new
back -
ground
101 0 1 0 end box separated
graphics
91 0 0 1 steady contiguous
graphics
81 0 0 0 flash conceal
display
7
0 1 1 1 alpha -
numerics
white
graphics
white
60 1 1 0 alpha -
numerics
cyan graphics
cyan
5
0 1 0 1 alpha -
numerics
magenta
graphics
magenta
4
0 1 0 0 alpha -
numerics
blue graphics
blue
30 0 1 1 alpha -
numerics
yellow
graphics
yellow
20 0 1 0 alpha -
numerics
green
graphics
green
00 0 0 0 alpha -
numerics
black
graphics
black
1
0 0 0 1 alpha -
numerics
red
graphics
red
MBA648 - 1
(1)
(1)
(2)
(2)
(2)
(2) (2)
(2)
(2)
1996 Nov 07 34
Philips Semiconductors Preliminary specification
Integrated VIP and Teletext with
Background Memory Controller SAA5249
Notes to Tables 12, 13, 14 and 15
1. These control characters are reserved for compatibility with other data codes.
2. These control characters are presumed before each row begins.
3. Control characters shown in Columns 0 and 1 are normally displayed as spaces.
4. Characters may be referred to by column and row (for example 2/5 refers to %).
5. Black represents displayed colour. White represents background.
6. The SAA5249 national option characters are illustrated in Tables 16, 17,18 and 19.
7. Characters 8/6, 8/7, 9/5, 9/6 and 9/7 are special characters for combining with character 8/5
(E, H and T codes only).
8. National option characters will be displayed according to the setting of control bits C12 to C14. These will be mapped
into the basic code table into positions shown in Tables 16, 17, 18 and 19.
9. Columns 2a, 3a, 6a and 7a are displayed in graphics mode.
1996 Nov 07 35
Philips Semiconductors Preliminary specification
Integrated VIP and Teletext with
Background Memory Controller SAA5249
Table 16 SAA5249 basic character matrix; note 1
Note
1. Where: NC = national option character position.
f
ull pagewidth
MLA630
2/1
2/0 2/8 3/0 3/8 4/0 4/8 5/0 5/8 7/86/8 7/0
NC
6/0
NC
2/9 3/1 3/9 4/1 4/9 5/1 5/9 6/1 6/9 7/1 7/9
2/2 2/10 3/2 3/10 4/2 4/10 5/2 5/10 6/2 6/10 7/2 7/10
2/11 3/3 3/11 4/3 4/11 5/3 6/3 6/11 7/3
2/12 3/4 3/12 4/4 4/12 5/4 6/4 6/12 7/4
2/5 2/13 3/5 3/13 4/5 4/13 5/5 6/5 6/13 7/5
2/6 2/14 3/6 3/14 4/6 4/14 5/6 6/6 7/6
2/7 2/15 3/7 3/15 4/7 4/15 5/7 6/7 6/15 7/7 7/15
2/3
NC
5/11
NC
5/12
NC
5/13
NC
5/14
NC
5/15
NC
7/11
NC
7/12
NC
7/13
NC
7/14
NC
2/4
NC
1996 Nov 07 36
Philips Semiconductors Preliminary specification
Integrated VIP and Teletext with
Background Memory Controller SAA5249
Table 17 SAA5249P/E national option character set; note 1
Note
1. PHCB are the Page Header Control Bits. Other combinations default to English.
h
andbook, full pagewidth
MLB458
LANGUAGE C12 C13 C14
PHCB
000
001
010
011
100
FRENCH
ITALIAN
SWEDISH
GERMAN
ENGLISH
2 / 3 2 / 4 4 / 0 5 / 11 5 / 12 5 / 13 5 / 14 5 / 15 6 / 0 7 / 11 7 / 12 7 / 13 7 / 14
CHARACTER POSITION (COLUMN / ROW)
SPANISH 101
(1)
1996 Nov 07 37
Philips Semiconductors Preliminary specification
Integrated VIP and Teletext with
Background Memory Controller SAA5249
Table 18 SAA5249P/H national option character set; note 1
Note
1. PHCB are the Page Header Control Bits. Other combinations default to German. Only the above characters change
with the PHCB. All other characters in the basic set are shown in Table 15.
handbook, full pagewidth
MLA966
LANGUAGE C12 C13 C14
PHCB
(1)
000
001
010
101
110
111
RUMANIAN
CZECHOSLOVAKIA
SERBO-CROAT
SWEDISH
GERMAN
POLISH
2 / 3 2 / 4 4 / 0 5 / 11 5 / 12 5 / 13 5 / 14 5 / 15 6 / 0 7 / 11 7 / 12 7 / 13 7 / 14
CHARACTER POSITION (COLUMN / ROW)
1996 Nov 07 38
Philips Semiconductors Preliminary specification
Integrated VIP and Teletext with
Background Memory Controller SAA5249
Table 19 SAA5249P/R national option character set; note 1
Note
1. PHCB are the Page Header Control Bits. Other combinations default to Estonian.
h
andbook, full pagewidth
LANGUAGE C12 C13 C14
PHCB
(1)
010
011
100
RUSSIAN
LETTISH /
LITHUANIAN
ESTONIAN
2 / 3 2 / 4 4 / 0 5 / 11 5 / 12 5 / 13 5 / 14 5 / 15 6 / 0 7 / 11 7 / 12 7 / 13 7 / 14
CHARACTER POSITION (COLUMN / ROW)
MEA597
234567
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1996 Nov 07 39
Philips Semiconductors Preliminary specification
Integrated VIP and Teletext with
Background Memory Controller SAA5249
PACKAGE OUTLINES
UNIT A
max. 1 2 b1cD E e M
H
L
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC EIAJ
mm
inches
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
SOT240-1 92-11-17
95-01-25
A
min. A
max. bZ
max.
w
ME
e1
1.4
1.14 0.53
0.38 0.36
0.23 62.60
61.60 14.22
13.56 3.90
3.05 0.2542.54 15.24 15.88
15.24 18.46
15.24 2.14.9 0.36 4.06
0.055
0.045 0.021
0.015 0.014
0.009 2.46
2.42 0.56
0.53 0.15
0.12 0.010.10 0.60 0.63
0.60 0.73
0.60 0.083 0.19 0.014 0.16
MH
c
(e )
1
ME
A
L
seating plane
A1
wM
b1
e
D
A2
Z
48
1
25
24
b
E
pin 1 index
0 5 10 mm
scale
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
(1)
(1)(1)
DIP48: plastic dual in-line package; 48 leads (600 mil) SOT240-1
1996 Nov 07 40
Philips Semiconductors Preliminary specification
Integrated VIP and Teletext with
Background Memory Controller SAA5249
UNIT A1A2A3bpcE
(1) eH
E
LL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC EIAJ
mm 0.36
0.10 2.87
2.57 0.25 0.50
0.35 0.25
0.13 14.1
13.9 118.2
17.6 1.43
1.23 1.2
0.8 7
0
o
o
0.2 0.10.21.95
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
1.0
0.6
SOT319-1 92-11-17
95-02-04
D(1) (1)(1)
20.1
19.9
HD
24.2
23.6
E
Z
1.2
0.8
D
bp
e
θ
EA1
A
Lp
Q
detail X
L
(A )
3
B
19
y
c
D
H
bp
E
HA2
vMB
D
ZD
A
ZE
e
vMA
wM
1
64
52 51 33 32
20
X
wM
0 5 10 mm
scale
pin 1 index
64 leads (lead length 1.95 mm); body 14 x 20 x 2.7 mm; high stand-off height
QFP64: plastic quad flat package; SOT319-1
A
max.
3.3
1996 Nov 07 41
Philips Semiconductors Preliminary specification
Integrated VIP and Teletext with
Background Memory Controller SAA5249
SOLDERING
Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our
“IC Package Databook”
(order code 9398 652 90011).
DIP
SOLDERING BY DIPPING OR BY WAVE
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (Tstg max). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
REPAIRING SOLDERED JOINTS
Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.
QFP
REFLOW SOLDERING
Reflow soldering techniques are suitable for all QFP
packages.
The choice of heating method may be influenced by larger
plastic QFP packages (44 leads, or more). If infrared or
vapour phase heating is used and the large packages are
not absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our
“Quality
Reference Handbook”
(order code 9397 750 00192).
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary from
50 to 300 seconds depending on heating method. Typical
reflow temperatures range from 215 to 250 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheat for 45 minutes at 45 °C.
WAVE SOLDERING
Wave soldering is not recommended for QFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
If wave soldering cannot be avoided, the following
conditions must be observed:
•A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
•The footprint must be at an angle of 45° to the board
direction and must incorporate solder thieves
downstream and at the side corners.
Even with these conditions, do not consider wave
soldering the following packages: QFP52 (SOT379-1),
QFP100 (SOT317-1), QFP100 (SOT317-2),
QFP100 (SOT382-1) or QFP160 (SOT322-1).
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured. Maximum permissible solder
temperature is 260 °C, and maximum duration of package
immersion in solder is 10 seconds, if cooled to less than
150 °C within 6 seconds. Typical dwell time is 4 seconds
at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
REPAIRING SOLDERED JOINTS
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
1996 Nov 07 42
Philips Semiconductors Preliminary specification
Integrated VIP and Teletext with
Background Memory Controller SAA5249
DEFINITIONS
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
PURCHASE OF PHILIPS I2C COMPONENTS
Data sheet status
Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1996 Nov 07 43
Philips Semiconductors Preliminary specification
Integrated VIP and Teletext with
Background Memory Controller SAA5249
NOTES
Internet: http://www.semiconductors.philips.com
Philips Semiconductors – a worldwide company
© Philips Electronics N.V. 1996 SCA52
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
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Tel. +381 11 625 344, Fax.+381 11 635 777
For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
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Argentina: see South America
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Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,
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Hungary: see Austria
India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd.
Worli, MUMBAI 400 018, Tel. +91 22 4938 541, Fax. +91 22 4938 722
Indonesia: see Singapore
Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. +353 1 7640 000, Fax. +353 1 7640 200
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Printed in The Netherlands 537021/50/02/pp44 Date of release: 1996 Nov 07 Document order number: 9397 750 01014
