AVAILABLE
Functional Diagrams
Pin Configurations appear at end of data sheet.
Functional Diagrams continued at end of data sheet.
UCSP is a trademark of Maxim Integrated Products, Inc.
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
REV: 042208
DESCRIPTION
The DS18B20 digital thermometer provides 9-bit
to 12-bit Celsius temperature measurements and
has an alarm function with nonvolatile user-
programmable upper and lower trigger points.
The DS18B20 communicates over a 1-Wire bus
t hat by definition r equire s only one dat a line ( and
ground) for communication with a central
microprocessor. It has an operating temperature
range of -55°C to +125°C and is accurate to
±0.5°C over the range of -10°C to +85°C. In
add it io n, t he DS18B20 can derive power directly
fro m t he data line ( parasite power ”), eliminat ing
t he need fo r an exter nal power supply.
Each DS18B20 has a unique 64-bit serial code,
which allows multiple DS18B20s to function on
t he same 1-Wire bu s. T h u s , it is s imple to use one
microprocessor to control many DS18B20s
distributed over a large area. Applications that
can benefit from this feature include HVAC
environmental controls, temperature monitoring
systems inside buildings, equipment, or
machinery, and process monitoring and control
systems.
FEATURES
Unique 1-Wire® Interface Requires Only One
Port Pin for Communication
Each Device has a Unique 64-Bit Serial Code
S tor e d i n a n O n-Board ROM
Multidrop Capability Simplifies Distributed
Temperature-Se nsing App licat io ns
Requires No External Components
Can Be Powered from Data Line; Power Supply
Range is 3.0V to 5.5V
Measures Temperatures from -55°C to +125°C
(-67°F to +257°F)
±0.5°C Accuracy from -10°C to +85°C
Thermometer Resolution is User Selectable
from 9 to 12 Bits
Converts Temperature to 12-Bit D igita l Word in
750ms (Max)
User-Definable Nonvolatile (NV) Alarm
Settings
Alarm Search Command Identifies and
Addresses Devices Whose Temperature is
Outside Programmed Limits (Temperature
Alarm Condition)
Available in 8-Pin SO (150 mils), 8-Pin µSOP,
and 3-Pin TO-92 Packages
Software Compatible with the DS1822
Applications Include T hermostat ic Controls,
Industrial Systems, Consumer Products,
Thermometers, or Any Thermally Sensitive
System
PIN CONFIGURATIONS
DS18B20
Programmable Resolution
1-
Wire Digital Thermometer
TO-92
(DS18B20)
1
(BOTTOM VIEW)
2
3
18B20
1
GND
DQ
V
DD
2
3
SO (150 mil s)
(DS18B20Z)
N.C.
N.C.
N.C.
N.C.
GND
DQ
V
DD
N.C.
6
8
7
5
3
1
2
4
MAXIM
18B20
N.C.
V
DD
N.C.
N.C.
N.C.
GND
N.C.
DQ
6
8
7
5
3
1
2
4
18B20
µSOP
(DS18B20U)
1-Wire is a registered trademark of M axim Integr at ed P ro ducts , Inc .
DS18B20
2 of 22
ORDERING INFORMATION
PART
TEMP RANGE
PIN-PACKAGE
TOP MARK
DS18B20
-55
°
C to +125
°
C
3 TO-92
18B20
DS18B20+
-55°C to +125°C
3 TO-92
18B20
DS18B20/T&R
-55°C to +125°C
3 TO-92 (2000 Piece)
18B20
DS18B20+T&R
-55°C to +125°C
3 TO-92 (2000 Piece)
18B20
DS18B20-SL/T&R
-55
°
C to +125
°
C
3 TO-92 (2000 Piec e) *
18B20
DS18B20-SL+T&R
-55°C to +125°C
3 TO-92 (2000 Piec e) *
18B20
DS18B20U
-55°C to +125°C
8 µSOP
18B20
DS18B20U+
-55°C to +125°C
8 µSOP
18B20
DS18B20U/T&R
-55
°
C to +125
°
C
8
µ
SOP (3000 Piece)
18B20
DS18B20U+T&R
-55
°
C to +125
°
C
8
µ
SOP (3000 Piece)
18B20
DS18B20Z
-55
°
C to +125
°
C
8 SO
DS18B20
DS18B20Z+
-55°C to +125°C
8 SO
DS18B20
DS18B20Z/T&R
-55
°
C to +125
°
C
8 SO (2500 Piece)
DS18B20
DS18B20Z+T&R
-55°C to +125°C
8 SO (2500 Piece)
DS18B20
+Denotes a lead-free p ac k age . A “+ will appear on the top mark of lead-free packages.
T&R = Tape and reel.
*TO-92 packages in tape and r ee l c an b e or der ed w it h stra ig ht or f orme d lea ds. C hoos e “SL f or stra ig ht leads. Bu lk TO -9 2 orde rs are s tra ight
leads only.
PIN DESCRIPTION
PIN NAME FUNCTION
SO
µ
SOP TO-92
1, 2, 6,
7, 8 2, 3, 5,
6, 7 N.C. No Connect ion
3 8 3 VDD O p tio n al VDD. VDD must be gro unded fo r operatio n in
paras ite power mode.
4 1 2 DQ Data Inp ut/O utput. Ope n-drain 1-Wire inter face pin. Also
pro vides power to t he device w hen used in parasite power
mode (see the Powering the DS18B20 section.)
5 4 1 GND Ground
OVERVIEW
Figure 1 shows a block diagram of the DS18B20, and pin descriptions are given in the Pin Description
table. The 64 -bit RO M stor es t he device’s unique serial co d e. The scratchpad me mory conta ins t he 2 -byte
t emper at ure reg ist er t hat stor es t he d ig it al o ut put from the te mperat ur e sensor . In add itio n, t he scrat chpad
provides access to the 1-byte upper and lower alarm trigger registers (TH and TL) and the 1-byte
configuration reg ister . The configurat io n register allows t he user to set the resolut ion o f the temperature-
to-digital conversion to 9, 10, 11, or 12 bits. The TH, TL, and configuration registers are nonvolatile
(E E P ROM), so the y w ill retain data when the device is powered dow n.
The DS18B20 uses Maxim’s exclusive 1-Wire bus protocol that implements bus communication using
one co ntrol sig na l. The control line require s a weak pullup resistor since all devices are linked to the bus
via a 3-state or open-drain port (the DQ pin in the case of the DS18B20). In this bus system, the
micro p ro cesso r (the mast er dev ice) identifies and addr esses de vice s on the bus using each device’s uniqu e
64-bit code. Because each device has a unique code, the number o f devices that can be addressed on o ne
DS18B20
3 of 22
bus is virt ually u nlimited. The 1-Wire bus protocol, including detailed exp lanat ions of the command s and
“t ime slots,” is covered in the 1-Wire Bus Syst e m section.
Another feature of the DS18B20 is the ability to operate without an external power supply. Power is
instead supplied through the 1-Wire pullup resistor via the DQ pin when the bus is high. The high bus
signal also charges an internal capacitor (CPP), whic h then supplies po wer to the device w hen the bus is
low. This method of deriving power from the 1-Wire bus is referred to as “parasite power.” As an
alt e rna tive, the DS1 8B2 0 may als o be powere d by a n external suppl y on VDD.
Figure 1. DS18B20 Block Diagram
OPERATIONMEASURING TEMPERATURE
The core functionality of the DS18B20 is its direct-to-digital temperature sensor. The resolution of the
temperature sensor is user-configurable to 9, 10, 11, or 12 bits, corresponding to increments of 0.5°C,
0.25°C, 0. 125°C, and 0.0625°C, r espect ive ly. T he de fau lt resolution at po wer -up is 12-bit . T he DS18B20
powers up in a low-power idle state. To initiate a temperature measurement and A-to-D co nversio n, the
master must issue a Convert T [44h] command. Following the conversion, the resulting thermal data is
stored in the 2-byte temperature register in the scratchpad memory and the DS18B20 returns to its idle
state. If the DS18B20 is powered by an external supply, the master can issue “read time slots” (see the
1-Wire B us S yst em sect io n) after t he Convert T command and t he DS18B20 will respond by tr ans mitt ing
0 while the te mperature convers io n is in progress and 1 whe n t he co nvers io n is do ne. If the DS18B20 is
power ed with para s ite power, t his not ificatio n technique cannot be used since the bus must be pulled high
by a st r ong pu llup du r ing t he e nt ir e t emperat ure co nver sio n. T he bus requ irement s for p arasite po wer ar e
explain e d in detail in the Powering the DS18B20 section.
The DS18B20 output temperature data is calibrated in degrees Celsius; for Fahrenheit applications, a
lo o kup t able or co nversio n ro utine must be used. T he temp erat ur e dat a is st o red as a 16-b it sign-extended
two’s complement number in the temperature register (see Figure 2). The sign bits (S) indicate if the
temperature is positive or negative: for positive numbers S = 0 and for negative numbers S = 1. If the
DS18B20 is configured for 12-bit resolution, all bits in the temperature register will contain valid data.
For 11-bit resolution, bit 0 is undefined. For 10-bit resolution, bits 1 and 0 are undefined, and for 9-bit
resolution bits 2, 1, and 0 are undefined. Table 1 gives examples of digital output data and the
co rresponding temperature read ing for 1 2-bit r esolutio n c onversions.
V
PU
4.7k
POWER-
SUPPLY
SENSE
64-BIT ROM
AND
1-Wire PORT
DQ
VDD
INTERNAL V
DD
CPP
PARASITE POWER
CIRCUIT
MEMORY CONTROL
LOGIC
SCRATCHPAD
8-BIT CRC GENERATOR
TEM PERATURE SEN S OR
ALARM HIGH TRIGGER (T
H
)
REGISTER (EEPROM)
ALARM LOW TRIGGER (T
L
)
REGISTER (EEPROM)
CONFIGURATION REGISTER
(EEPROM)
GND
DS18B20
DS18B20
4 of 22
Figure 2. Temper atu re Register Form at
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
L S BYTE 23 22 21 20 2-1 2-2 2-3 2-4
BIT 15
BIT 14
BIT 13
BIT 12
BIT 11
BIT 10
BIT 9
BIT 8
MS BYTE S S S S S 26 25 24
S = SIGN
Table 1. Temperature/Data Relationship
TEMPERATURE (
°
C) DIGITAL OUTPUT
(BINARY) DIG ITAL OUTPUT
(HEX)
+125 0000 0111 1101 0000 07D0h
+85* 0000 0101 0101 0000 0550h
+25.0625 0000 0001 1001 0001 0191h
+10.125 0000 0000 1010 0010 00A2h
+0.5 0000 0000 0000 1000 0008h
0 0000 0000 0000 0000 0000h
-0.5 1111 1111 1111 1000 FFF8h
-10.125 1111 1111 0101 1110 FF5Eh
-25.0625 1111 1110 0110 1111 FE6Fh
-55 1111 1100 1001 0000 FC90h
*The power-on reset value of the temperature register is +85°C.
OPERATIONALARM SIGNALING
After the DS18B20 performs a temperature conversion, the temperature value is compared to the user-
defined twos complement alarm trigger values stored in the 1-byt e TH and TL registers (see Figure 3).
The s ig n bit ( S) ind ic ate s if the va lu e is po s itive o r negative: for positive number s S = 0 and for negat ive
numbers S = 1. The TH and TL registers are nonvolatile (EEPROM) so they will retain data when the
device is po wered do wn. T H and T L can be acces sed t hrough byt e s 2 and 3 of the scrat chpad as e xplained
in the Memory section.
Figure 3. TH and TL Register Format
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
S 26 25 24 23 22 21 20
Only bits 11 t hrough 4 o f t he t emperatur e register ar e used in t he TH a nd T L co mpar ison sinc e TH a nd TL
are 8-bit r egist ers. I f t he measured t e mp erat ure is lo wer than or eq ual to T L or higher t han or equa l t o TH,
an alarm condition exists and an alarm flag is set inside the DS18B20. This flag is updated after every
temperature measure me nt ; t here for e, if the alarm c onditio n go es away, the flag w ill be t u r ned o ff after the
next temperature conversi on.
DS18B20
5 of 22
The mast er dev ic e can check t he a larm flag status of all DS18B20 s on t he bus by issuing an Alarm Searc h
[ECh] co mmand. Any DS18B20s with a set alarm flag will respond to the command, so the master ca n
determine exactly which DS18B20s have experienced an alarm condition. If an alarm condition exists
and the TH or TL settings have changed, another temperature conversion should be done to validate the
alarm condition .
POWERING THE DS18B20
The DS18B20 can be powered by an external supp ly on the VDD pin, or it can oper ate in “paras ite power”
mode, which allows the DS18B20 to function without a local external supply. Parasite power is very
useful for applications that require remote temperature sensing or that are very space constrained.
Figure 1 shows the DS18B20’s parasite-power control circuitry, which “steals” power from the 1-Wire
bus via the DQ p in when t he bus is hig h. The stolen charge powers the DS18B20 while the bus is high,
and so me o f t he c har ge is stored o n t he par asit e po wer capacitor (CPP) to provide power whe n t he bus is
low. When t he DS18B20 is us ed in parasit e p ower mode, the VDD pin must be connect ed to ground.
In parasit e power mode, the 1-Wire bus a nd CPP c an pro vide sufficient current to t he DS18B20 for most
operations as long as the specified timing and voltage requirements are met (see the DC Electrical
Characteristics and AC Electrical Characteristics). However, when the DS18B20 is performing
t emper at ure convers ions o r copying data fro m the scrat chpad me mo r y to EEP ROM, the o perating cur rent
can be as high as 1.5mA. This current can cause an unacceptable voltage drop across the weak 1-Wire
pullup resistor and is mo re curr ent than can be sup plied by C PP. T o assure that t he DS18B20 has suf ficie nt
supply current, it is necessary to provide a strong pullup on the 1-Wire bus whenever temperature
conversions are taking place or data is being copied from the scratchpad to EEPROM. This can be
accomplished by using a MOSFET to pull the bus directly to the rail as shown in Figure 4. The 1-Wire
bus mu st be sw it c hed to the strong pullup w it hin 1 0µs (max) aft er a Convert T [44h] or Co py Scratchpa d
[48h] command is issued, and the bus must be he ld high by the pu llup for t he durat ion of the conversion
(tCONV) or data transfer (t WR = 10ms). No other activ ity ca n t ake place on t he 1-Wire bus while t he pullup
is enabled.
The DS18B20 can also be powered by the co nvent ional method o f connect ing an externa l power supp ly
to the VDD pin, as shown in Figure 5. The advantage of this method is that the MOSFET pullup is not
requir ed , and t he 1-Wire bus is free t o car r y other traffic during the temperat ur e convers io n t ime.
The use of parasite power is not recommended for temperatures above +100°C since the DS18B20 may
not be able to sustain communications due to the higher leakage currents that can exist at these
temperatures. For app licat io ns in whic h such t emperat ur es are likely, it is stro ngly recommended tha t t he
DS18B20 be powered by an ext ernal power supply.
In so me situat ions the bus master may not know whet her the DS18B20 s on the bus are parasite power ed
o r powered by e xte rna l su pp lies. The mast er need s t his info r mat io n t o det ermine if t he st ro ng bus p u llup
should be used during temper ature conversions. To get this info rmation, the mast er can issue a Sk ip RO M
[CCh] command followed by a Read Power Supply [B4h] command followed by a “read time slot”.
During the read time slot, parasite powered DS18B20s will pull the bus low, and externally powered
DS18B20s will let t he bus remain high. I f t he bus is pu lled lo w, t he master knows t hat it must supply t he
strong pullup on t he 1-Wire bus dur ing temper ature co nversions.
DS18B20
6 of 22
Figure 4. Supplying the Parasite-Powered DS18B20 During Temperature Conversions
Figure 5. Powering the DS18B20 with an External Supply
64-BIT LASERED ROM CODE
Each DS18 B20 conta ins a unique 64bit code (see Figure 6) stored in ROM. T he least s ig nificant 8 bit s
of the ROM code contain the DS18B20’s 1-Wire family code: 28h. The next 48 bits contain a unique
serial number. The most significant 8 bits contain a cyclic redundancy check (CRC) byte that is
calculated fro m t he first 56 bit s of the ROM code. A detailed explanat io n o f the CRC bits is provide d in
the CRC Generation sect io n. T he 64-bit RO M cod e and a ssoc iat ed ROM funct io n cont ro l lo gic a llo w t he
DS18B20 to o perate as a 1-Wir e d evice using t he protocol detailed in t he 1-Wire B us System section.
Figure 6. 64-Bit Lasered ROM Code
8-BIT CRC
48-BIT SERIAL NUMBER
8-BIT FAMI LY CODE (28h)
MSB
MSB
LSB
LSB
LSB
MSB
V
PU
V
PU
4.7k
1-Wire BUS
µ
P
DS18B20
GND
V
DD
DQ
TO OTHER
1-WIRE DEVICES
V
DD
(EXTER NAL SUPPL Y)
DS18B20
GND
V
DD
DQ
V
PU
4.7k
TO O T HER
1-WIRE DEVICES
1-Wi re BUS
µ
P
DS18B20
7 of 22
MEMORY
The DS18B20’s memory is organized as shown in Figure 7. The memory consists of an SRAM
scratchpad with nonvolatile EEPROM storage for the high and low alarm trigger registers (TH and TL)
and configuration register. Note that if the DS18B20 alarm function is not used, t he TH and TL registers
can serve as general-purpose memory. All memory commands are described in detail in the DS18B20
Function Commands section.
Byte 0 and byte 1 of the scratchpad contain the LSB and the MSB of the temperature register,
respectively. These bytes are read-only. Bytes 2 and 3 provide access to TH and TL registers. Byte 4
co nt ains t he co nfiguration reg ister d ata, which is explained in det ail in t he Configuration R egister section.
Bytes 5, 6 , and 7 are r eserved for interna l use by the dev ice and ca nno t be o verwritten.
Byte 8 of the scr atchpad is read-on ly a nd contain s the CRC code fo r byt es 0 t hro ugh 7 o f the scratchpad.
The DS18B20 generat es t his CRC using the method descr ibed in the CRC Generation section.
Dat a is writt en to b yt es 2, 3, and 4 of the scratchpad u s ing the Write Scratchpad [4Eh] co mmand; t he data
must be transmitted to the DS18B20 starting with the least significant bit of byte 2. To verify data
integrity, the scratchpad can be read (using the Read Scratchpad [BEh] command) after the data is
written. When reading the scratchpad, data is transferred over the 1-Wire bus starting with the least
significant bit of byte 0. To t ransfer t he TH, TL and configuration dat a from t he scrat chpad to EEPROM,
t he master must issue t he Cop y Scr atchpad [48h] command.
Data in the E EPROM reg ist ers is ret ained when the device is powered down; at power-up t he EEPROM
dat a is re lo ad ed int o t he corr espo nd ing scrat chpad locat ions. Dat a can also be reloaded from EEPROM to
the scratchpad at any time using the Recall E2 [B8h] command. The master can issue read time slots
following the R ec all E 2 command a nd the DS18B20 w ill ind icat e the status o f the rec all by transm itt ing 0
while the rec all is in pro gress and 1 when the r ecall is done.
Figure 7. DS18B20 Memory Map
SCRATCHPAD
(POWER-UP STATE)
Byte 0 Temper ature LSB (50h)
Byte 1 T emperat ur e MSB (05h) EEPROM
Byte 2 TH Reg ister o r User B yte 1* TH Reg ister o r User B yte 1
Byte 3 TL Reg ist er o r User Byt e 2 * TL Reg ist er o r User Byt e 2
Byte 4 Configurat ion Regist er * Co nfiguration Reg ist er
Byte 5 Reserved (FFh)
Byte 6 Reserved
Byte 7 Reserved (10h)
Byte 8 CRC*
*
Power-up state depends on value(s) stored in EEPROM.
(85°C)
DS18B20
8 of 22
CONFIGURATION REGISTER
Byte 4 o f the scrat chpad me mory co ntains the configurat io n reg ist er, whic h is or ganized as illustrated in
Figure 8. The user can set the conversion resolution of the DS18B20 using the R0 and R1 bits in this
reg ister as shown in Table 2. The pow er-up defau lt o f t hese bit s is R0 = 1 and R1 = 1 (12-b it re s olution ) .
Note that there is a direct tradeoff between resolution and conversion time. Bit 7 and bits 0 to 4 in the
co nfiguration reg ister are reserved for inter nal use by the devic e and ca nno t be o verwritten.
Figure 8. Configuration Register
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0 R1 R0 1 1 1 1 1
Table 2. Thermometer Resolution Configuration
R1 R0 RESOLUTION
(BITS) M AX CO NVERSION
TIME
0 0 9 93.75ms (tCONV/8)
0 1 10 187.5ms (tCONV/4)
1 0 11 375ms (tCONV/2)
1 1 12 750ms (tCONV)
CRC GENERATION
CRC byt es are pro vided as part of t he DS18B20’s 64-bit ROM co de and in the 9th byt e o f the scrat chpad
memo ry. The ROM code CRC is calcu lat ed fr om the first 5 6 b it s of t he ROM cod e and is co nt ained in t he
most significant byte of the ROM. The scratchpad CRC is calculated from the data stored in the
scrat chpad, and there fore it changes when t he data in t he scrat chpad changes. The CRCs pro vide t he bu s
master with a method of data validation when data is read from the DS18B20. To verify that data has
been read correctly, the bus master must re-calculate the CRC from the received data and then compare
t his value t o either t he ROM code CRC ( for ROM r eads) or to the scrat chpad C RC (for scr atchpad reads).
If the calculated CRC matches the read CRC, the data has been received error free. The comparison of
CRC values and the decision to continue with an operation are determined entirely by the bus master.
There is no circuitry inside the DS18B20 that prevents a command sequence from proceeding if the
DS18B20 CRC (ROM o r scratchpad) does not match the value g enerated by the bus master .
T he equivalent p olynomial func tion of the C R C ( R OM or s cratchpad) is:
CRC = X8 + X5 + X4 + 1
The bus master can re-ca lculat e t he CRC a nd co mpare it to the CRC values fr o m the DS18B20 using t he
po lyno mial generator shown in Figure 9. This circuit consists of a shift register and XOR gates, and the
shift register bits are init ialized to 0. Starting wit h the least significant bit of the ROM code or t he lea st
significant bit of byte 0 in the scratchpad, one bit at a time should shifted into the shift register. After
shifting in the 56th bit from the ROM or the most significant bit of byte 7 from the scratchpad, the
po lynomial generator will contain the re-calculated CRC. Next, the 8-bit ROM code or scratchpad CRC
fr om t he DS18B20 must be shifted into t he cir cuit . At this point, if the re-calculated CRC w as correct , t he
sh ift regis te r w ill c ontain all 0 s . Additional inform a tion abou t the Maxim 1-Wir e cyclic redundancy check
DS18B20
9 of 22
is available in Application Note 27: Understanding and Using Cyclic Redundancy Checks with Maxim
iButton Products.
Figure 9. CRC Generat or
1-WIRE BUS SYSTEM
The 1-Wire bus system uses a single bus master to control one or more slave devices. T he DS18B20 is
always a slave. When there is only one slave on the bus, the system is referred to as a “single-drop”
s ys tem; the system is multidr op” if t here ar e multiple slave s on t he bus.
All d ata and commands are t r ansmitted least sig n if ica nt bit first over the 1-Wire bus.
The following discussion of the 1-Wire bus system is broken down into three topics: hardware
co nfiguration, t r ansactio n sequence , and 1-Wire signaling (signal type s and timing).
HARDWARE CONFIGURATION
The 1-Wire bus has by definition only a single data line. Each device (master or slave) interfaces to the
data line via an open-drain or 3-state port. This allows each device to “release” the data line when the
device is not transmitt ing dat a so t he bu s is ava ilable for use by ano ther de vice. The 1-Wire port of the
DS1 8B2 0 (the DQ pin) is open dr ain with an internal circ uit e quivalent t o that show n in Figure 10.
The 1-Wire bus requires an external pullup resistor of approximately 5k; thus, the idle state for the
1-Wire bu s is hig h. I f for any reason a transaction need s to be suspended, the bus MUST be left in t he idle
state if the transaction is to resume. Infinite recovery time can occur between bits so long as the 1-Wire
bus is in the inact ive ( high) st ate during the reco very period. If the bus is held low for more t han 4 80µs,
all comp onents on the bus will be reset.
Figure 10. Hardware Configuration
(MSB)
(LSB)
XOR
XOR
XOR
INPUT
V
PU
4.7k
5μA
TYP
Rx
Tx
DS18B20 1-Wire PORT
100
MOSFET
TX
Rx
Rx = RECEIVE
Tx = TRA NSMIT
1-Wire BUS
DQ
PIN
DS18B20
10 of 22
TRANSACTION SEQUENCE
The t r ansaction sequence for access ing the DS18B20 is as follows:
S tep 1. Initialization
S tep 2. ROM Command (followed b y an y required data exchange)
S tep 3. DS18B20 Funct io n Co mma nd (fo llo wed by a ny required dat a exchange)
It is very i mpo r tant to fo llow t h is sequence every t i me t he DS18B20 is a cces sed, as the DS18B20 will no t
respond if any steps in the sequence are missing or out of order. Exceptions to this rule are the Search
ROM [F0h] and Alarm Search [ECh] commands. After issuing either of these ROM commands, the
mast er must ret urn to St ep 1 in the sequence.
INITIALIZATION
All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence
consists of a reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the
sla ve(s). T he presence pulse let s the bu s ma ster know t hat sla ve de vice s (such as the DS18 B20) ar e o n t he
bus a nd are read y t o o perate. Timing for t he re set and presence pu lses is det ailed in t he 1-Wire Signaling
section.
ROM COMMANDS
After the bus master has detected a presence pulse, it can issue a ROM command. These commands
operate on the unique 64-bit ROM codes o f each slave dev ice and a l lo w the ma ster to single out a specific
device if many are present on the 1-Wire bus. These co mmands also allow the master to determine how
many and what types of devices are present on the bus or if any device has experienced an alarm
condition. There are five ROM commands, and each command is 8 bits long. The master device must
issue an appropriate ROM command before issuing a DS18B20 function command. A flowchart for
op e ratio n of t he RO M comman ds is show n in Figure 11.
SEARCH ROM [F0h]
When a system is initially powered up, the master must identify the ROM codes of all slave devices on
the bus, which allows the master to determine the number of slaves and their device types. The master
learns t he ROM codes t hro u gh a pro cess o f elimination that r equ ires the ma ster to per for m a Search RO M
cycle ( i. e. , Sear ch ROM co mmand fo llo wed b y d at a exchange) as many t imes as neces sar y t o ide nt ify al l
of t he slave devices. If t here is only one slave on the bu s, t he simpler Read ROM co mmand (s ee below)
can be used in place of the Search ROM process. For a detailed explanation of the Search ROM
procedure, refer to the iButton® Book of Standards at www.maxim-ic.com/ibuttonbook. After every
Search ROM cyc le, the bu s mast er must return to St ep 1 (Initialization) in the t r ansaction sequence.
READ ROM [33h]
This co mma nd ca n o nly be used w hen t here is o ne s lave o n t he bu s. It allo w s t he bus ma st er to read t he
s lave ’s 64-bit ROM code without using the Searc h ROM procedure. I f t his co mma nd is u se d w he n t her e
is more than one slave present on the bus, a data collision will occur when all the slaves attempt to
respond at the same time.
MATCH ROM [55h]
The match ROM co mmand follo wed by a 64-bit ROM co de sequence a llo ws t he bus mast er to address a
specific slave device on a multidrop or single-drop bus. Only the slave that exactly matches the 64-bit
ROM code sequence will respond to the funct ion command issued by t he mast er; all other slaves on t he
bus will wa it fo r a reset pulse.
iButton is a registered trademark of M axim Int eg r at ed Prod uc t s , Inc .
DS18B20
11 of 22
SKIP ROM [CCh]
The master can use this command to address all devices on the bus simultaneously without sending out
any ROM code information. For example, the master can make all DS18B20s on the bus perform
simult aneous te mperature conversio ns by issuing a Skip ROM co mmand fo llo wed by a Convert T [44h]
command.
Note that the Read Scratchpad [BEh] command can follow the Skip ROM command only if there is a
single slave device on the bus. In this case, time is saved by allowing the master to read fro m the slave
without sending the device’s 64-bit ROM code. A Skip ROM command followed by a Read Scratchpad
co mmand will cause a data collision on the bus i f there is more than o ne s la ve s in c e mu ltip le d e vic e s w i l l
attempt to transmit data sim ul tan eously.
ALARM SEARCH [ECh]
The operation of this command is identical to the operation of the Search ROM command except that
only slaves wit h a set alarm flag will respond. This command allows the master device to determine if
any DS18B20s experienced an alarm condition during the most recent temperature conversion. After
every A lar m Searc h cycle ( i. e., Alar m Sear ch co mmand fo llo wed by d at a exchange), t he bus mast er must
return to Step 1 (Initialization) in the transaction sequence. See the OperationAlarm Signaling section
fo r an exp la nation of alar m flag op er ation.
DS18B20 FUNCTION COMMANDS
After the bus master has used a ROM command to address the DS18B20 with which it wishes to
co mmu nicat e, t he master can issue o ne o f the DS 18B20 fu nct io n commands. T hese co mmands a llo w t he
mast er to write to and read from the DS18B20’s sc r atchpad me mory, initiat e temperatur e conversions an d
determine the power supply mode. The DS18B20 function commands, which are described below, are
su mma r iz ed in Table 3 and il lus trate d by the flo wchart in Figure 12.
CONVERT T [44h]
This co mmand init iates a single temperat ure co nversion. Followin g t he co nvers io n, t he resu lt ing the r ma l
dat a is sto red in the 2-byt e t e mper at ure reg ist er in t he scrat chpad me mo r y and t he DS18 B20 ret urns to it s
low-power idle state. If the device is being used in parasite power mode, within 10µs (max) after this
command is issued the master must enable a strong pullup on the 1-Wire bus for the duration of the
co nvers io n ( t CONV) as described in t he Powering the DS18B20 section. If the DS18B20 is powered by an
exte r na l s up p l y, t he master can issue r ead t ime s lot s after the C o nve r t T c o mma nd a nd t he DS 1 8B 20 w ill
respo nd by transmitt ing a 0 while the temperat ure co nversio n is in pro gress and a 1 w hen t he co nve rsio n
is done. In paras it e power mo de this not ificatio n t echnique c annot be used since the bus is pulled high by
the stro ng pullup during t he convers ion.
WRITE SCRATCHPAD [4Eh]
This comma nd a llow s the mast er to wr ite 3 bytes o f data to t he DS18 B20’s scr atchpad. T he first d ata byt e
is written into the TH register (byte 2 of the scratchpad), the second byte is written into the TL register
(byte 3), and the third byte is written into the configuration register (byte 4). Data must be transmitted
least significant bit first. All three bytes MUST be written before the master issues a reset, or the data
may be corrupted.
READ SCRATCHPAD [ BEh]
This co mmand a llo ws the ma ster to read the content s o f t he scratchpad. The data transfer starts with the
least significant bit of byte 0 and continues through the scratchpad until the 9th byte (byte 8 CRC) is
read. The master may issue a reset t o terminate reading at any t ime if only part of the scrat chpad d at a is
needed.
DS18B20
12 of 22
COPY SCRATCHPAD [48h]
This co mmand cop ie s the co nt ents o f t he scr at chp ad TH, TL and configur at io n registers (byt e s 2, 3 and 4)
to EEPROM. If the device is being used in para s ite power mode, within 10µs (max) after this command is
issued the master must enable a strong pullup on the 1-Wire bus for at least 10ms as described in the
Powering the DS18B20 section.
RECALL E2 [B8h]
This command recalls the alarm trigger values (TH and TL) and configuration data from EEPROM and
places the data in bytes 2, 3, and 4, respect ive ly, in the scrat chpad me mo ry. The ma ster device can issue
read t ime slot s follo wing the Recall E2 co mmand and the DS18B20 will ind icat e the statu s of the recall by
transmit ting 0 while the recall is in progress and 1 when the re ca ll is done. The re call operat ion happens
auto mat ica lly at power-up, so valid dat a is available in the scratchpad as soo n as po wer is app lied to t he
device.
READ POWER SUPPL Y [B4h]
The master device issues t his comma nd followed by a read time slot to determine if any DS18B20s on the
bus are using parasite power. During the read time slot, parasite powered DS18B20s will pull the bus
low, and externally powered DS18B20s will let the bus remain high. See the Powering the DS18B20
section for usage information for t his co mmand.
Table 3. DS18B20 Function Command Set
COMMAND DESCRIPTION PROTOCOL
1-Wire BU S
ACTIVITYAFTER
COMMAND IS ISS UED
NOTES
TEMPERATURE CONVERSION COM MANDS
Convert T
Initi ates temperature
conversion. 44h
DS18B20 transmit s
co nversion status to master
(not app licable for par asite-
power ed DS18B20s).
1
MEMORY COMM ANDS
Read
Scratchpad
Reads t he ent ire scrat chpad
includ ing the CRC byte.
BEh
DS18B20 transmit s up to 9
dat a b ytes to master .
2
Write
Scratchpad
Writ es data int o scratchpad
bytes 2, 3, and 4 (TH, TL,
and configuratio n
registers).
4Eh
Master t r ansmits 3 data bytes
to DS18B20. 3
Copy
Scratchpad
Copies T
H
, T
L
, and
co nfiguration reg ister dat a
from the scrat chpad to
EEPROM.
48h
None
1
Recal l E
2
Recal ls T
H
, T
L
, a nd
co nfiguration reg ister dat a
from EEPROM to the
scratchpad.
B8h
DS18B20 transmit s reca ll
sta tus to master.
Read Power
Supply
S ig nals DS18B20 po wer
supply mo d e to the ma ster. B4h
DS18B20 transmit s suppl y
sta tus to master.
Note 1:
For par a sit e-powered DS18B20s, th e ma ster must enable a strong pullup on the 1-Wire bus during temperat ure
conversi ons a nd c opi es from t he s cratch pa d to EEPRO M. N o other bus activity may take place during this time.
Note 2:
The master can interrupt the transmission of data at any time by issuing a reset.
Note 3:
All three bytes must be written before a reset is issued.
DS18B20
13 of 22
Figure 11. ROM Commands Flowchart
CCh
SKIP ROM
COMMAND
MASTER TX
RESET PULSE
DS18B20 T
X
PRESENCE
PULSE
MASTER T
X
ROM
COMMAND
33h
READ ROM
COMMAND
55h
MATCH ROM
COMMAND
F0h
SEARCH ROM
COMMAND
ECh
ALARM SEARCH
COMMAND
MASTER TX
BIT 0
DS18B20 T
X
BIT 0
DS18B20 TX BIT 0
MASTER TX BIT 0
BIT 0
MATCH?
MASTER T
X
BIT 1
BIT 1
MATCH?
BIT 63
MATCH?
MASTER TX
BIT 63
N
Y
Y
Y
Y
Y
N N
N
N
N
N
N
Y
Y
Y
DS18B20 T
X
BIT 1
DS18B20 T
X
BIT 1
MASTER TX BIT 1
DS18B20 TX BIT 6 3
DS18B20 T
X
BIT 63
MASTER TX BIT 63
BIT 0
MATCH?
BIT 1
MATCH?
BIT 63
MATCH?
N
N
N
Y
Y
Y
DS18B20 T
X
FAMILY CODE
1 B YTE
DS18B20 TX
SERIAL NUMBER
6 BYTES
DS18B20 TX
CRC BYTE
DS18B20 TX BIT 0
DS18B20 TX BIT 0
MASTER TX BIT 0
N
Y
DEVICE(S)
WITH ALARM
FLAG SET?
Initialization
Sequence
MASTER T
X
FUNCTION
COMMAND
(FIGURE 12)
DS18B20
14 of 22
Figure 12. DS18B20 Function Command s Flowchart
MASTER TX
FUNCTION
COMMAND
Y
N
44h
CONVERT
TEMPERATURE
?
PARASITE
POWER
?
N
Y
DS18B20 BEGINS
CONVERSION
DEVICE
CONVERTING
TEMPERATURE
?
N
Y
MASTER
RX “0s”
MASTER
RX “1s”
MASTER ENABLES
STRONG PULLUP ON DQ
DS18B 20 CONVERTS
TEMPERATURE
MASTER DISABLES
STRONG PULLUP
Y
N
48h
COPY
SCRATCHPAD
?
PARASITE
POWER
?
N
Y
MASTER ENABLES
STRONG PULL-
UP ON DQ
DATA COPIED FROM
SCRATCHPAD TO EEPROM
MASTER DISABLES
STRONG PULLUP
MASTER
RX “0s”
COPY IN
PROGRESS
?
Y
MASTER
R
X
“1s
N
RETURN TO INITIALIZA TION
SEQUENCE (FIGURE 11) FOR
NEXT TRANSACTION
B4h
READ
POWER SUPPLY
?
Y
N
PARASITE
POWERED
?
N
MASTER
RX “1s”
MASTER
RX “0s”
Y
MASTER TX TH BYTE
TO SCRATCHPAD
Y
N
4Eh
WRITE
SCRATCHPAD
?
MASTER TX TL BYTE
TO SCRATCHPAD
MASTER T
X
CONFIG. BYTE
TO SCRATCHPAD
Y
N
Y
BEh
READ
SCRATCHPAD
?
HAVE 8 BYTES
BEEN READ
?
N
MASTER
TX RESET
?
MASTER R
X
DATA BYTE
FROM SCRATCHPAD
N
Y
MASTER RX SCRATCHPAD
CRC BYTE
MASTER
RX “1s”
Y
N
B8h
RECALL E2
?
MASTER BEGINS DATA
RECALL FROM E2 PROM
DEVICE
BUSY RECALLING
DATA
?
N
Y
MASTER
RX “0s”
DS18B20
15 of 22
1-WIRE SIGNALING
The DS18B20 u ses a strict 1-Wire communication protocol to ensure data integrit y. Several signal types
are defined by this protocol: reset pulse, presence pulse, write 0, write 1, read 0, and read 1. The bus
maste r initiate s all these sig nals, with the except ion of the prese nce pulse.
INITIAL IZATION PROCEDURERESET AND PRESENCE PULSES
All communic ation with t he DS18 B20 begins with an init ia lizat io n sequenc e that co nsists of a reset pulse
fro m t he mast er fo llowed by a prese nce pu lse from the D S18B2 0. Th is is illu st rat ed in Figure 13. Whe n
the DS18B20 sends the presence pulse in response to the reset, it is indicating to the master that it is on
t he bus and read y to oper at e.
Dur ing t he init ializ at io n sequ e nce t he bus mast er tr ansmit s (T X) t he reset pu lse by pull ing t he 1-Wir e bu s
low for a minimum of 480µs. The bus master then releases the bus and goes into receive mode (RX).
When the bus is released, the 5k pullu p res ist or pu lls t he 1-Wir e bus high. When the DS18B20 detects
this r ising edge, it wait s 15µs to 60µs and t hen transmit s a presence pulse by pulling the 1-Wire bu s low
for 60µs to 240µs.
Figure 13. In itialization Tim ing
REA D/WRITE TIME SLOTS
The bus master writes data to the DS18B20 during write time slots and reads data from the DS18B20
during read t ime slot s. One bit of dat a is t r ansmitted over t he 1-Wire bus p er time slo t.
WRITE TIME SLOTS
There are two types of write time slots: “Write 1” time slots and “Write 0” time slots. The bus master
uses a Wr ite 1 time slot to write a logic 1 to the DS18B20 and a Wr ite 0 time slot to write a logic 0 to the
DS18B20. All write time s lo ts must be a mini mum of 60µs in duration with a minimum of a 1µs recovery
t ime bet wee n in dividual w r it e s lo t s. Bo th types o f write t ime slot s are init iated by the master pulling t he
1-Wire bu s low ( se e Figure 14).
To generat e a Writ e 1 time slo t , a ft er pulling the 1-Wire bus lo w, t he bu s mast er must re leas e t he 1-Wire
bus within 15µs. When t he bus is released, t he 5k pullup resistor will pull the bus high. To generate a
Writ e 0 time slo t, aft er pulling the 1-Wire bus lo w, t he bu s master must co ntinue to hold the bus low for
the duration of the time slot (at least 60µs).
LINE TYPE LEGEND
Bus master pulling low
DS 18B20 pulling low
Resi stor pu l lup
VPU
GND
1-WIRE BUS
480µs minimum
480µs minimum
DS18B20 T
X
presence pulse
60-240
µ
s
MASTER T
X
RESET PULSE
MASTER R
X
DS18B20
waits 15-60
µ
s
DS18B20
16 of 22
The DS18B20 samples the 1-Wire bus during a window that lasts from 15µs to 60µs after the master
initiates t he write time slot. I f t he bus is high dur ing the sampling window, a 1 is wr it ten t o t he DS18B20.
If t he line is low, a 0 is writ ten to the DS18B20.
Figure 14. Read/Wr ite Time Slot Timin g Diagram
REA D TIME SLOTS
The DS18B20 can o nly tr ansmit d at a to the mast er when t he mast er issues read t ime s lo t s. T he refo r e , t he
master must generate read time slots immediately after issuing a Read Scratchpad [BEh] or Read Power
Supp ly [B4h] co mmand, so that the DS18B20 can pro vide t he request ed data. In add it io n, t he mast er ca n
generat e read t ime slot s a ft er issuing Co nvert T [44h] o r Reca ll E2 [ B8h] co mmands to find out the status
o f the op er ation as exp lained in the DS18B20 Function Commands section.
All read time slots must be a minimum of 60µs in duration with a minimum of a 1µs recovery time
between slots. A read time slot is initiated by the master device pulling the 1-Wire bus low for a
min imum of 1µs a nd t he n re le as ing the bus (see Figure 14). After t he master init iates the read t ime slo t,
t he DS18B20 will begin trans mit ting a 1 or 0 on bus. The DS18B20 t r ansmits a 1 by leaving the bus high
and t ransmits a 0 by pu lling the bus lo w. When transmit ting a 0, t he DS18B20 will re lease the bu s by the
end of the time slot, and the bus will be pulled back to its high idle state by the pullup resister. Output
45
µ
s
15µs
V
PU
GND
1-WIRE B US
60µs < T
X
0” < 120µs
1
µ
s < TREC <
DS18B20 Samples
MIN TYP MAX
15
µ
s
30µs
> 1
µ
s
MASTER WRITE “0” SLOT
MASTER WRITE “1” SLOT
V
PU
GND
1-WIRE B US
15
µ
s
MASTER READ “0” SLOT
MASTER READ “1” SLOT
Master samples
Master samples
START
OF SLOT
START
OF SLOT
> 1
µ
s
1
µ
s < TREC <
15
µ
s
15
µ
s
30
µ
s
15µs
DS18B20 Samples
MIN TYP MAX
LINE TYPE LEGEND
Bus master pulling low DS18B20 pull ing low
Resi stor pu l lup
> 1
µ
s
DS18B20
17 of 22
data from t he DS18B20 is valid for 15µs a ft er t he fal ling edge t hat init iat ed t he read t ime s lo t . Therefo re,
t he master must r elease t he bus and the n samp le t he bus st ate wit hin 15µs fro m the start of the slot.
Figure 15 illustrates that the sum of TINIT, TRC, and TSAMPLE mu st be less than 15µs for a read time slot.
Figure 16 shows that system timing margin is maximized by keeping TINIT and TRC as short as possible
and by lo cating the master sample time dur ing read time slots tow ar ds the end of the 15µs perio d.
Figure 15. Detailed Master Read 1 Timin g
Figure 16. Recommended Master Read 1 Timing
RELATED APPLIC ATION NOTES
The following application notes can be applied to the DS18B20 and are available on our website at
www.maxim-ic.com.
Application Note 27: Understanding and Using Cyclic Redundancy Checks with Maxim iButton Products
Application Note 122: Using Dallas' 1-Wire ICs i n 1-Cell Li-Ion Battery Packs with L ow-Side N-Channel
Safety FETs Master
Application Note 126: 1-Wire Communication Through Soft ware
Application Note 162: Interfacing the DS18x20/DS1822 1-Wire Temperature Sensor in a Microcontroller
Environment
Application Note 208: Curve Fitting the E rror of a Bandgap-Based Digital Temperature Sensor
Application Note 2420: 1-Wire Communication with a Microchip PICmicro Microcontroller
Application Note 3754: Single-Wire Serial Bus Carries Isolated Power and Data
Sample 1-Wire subroutines that can be used in conjunction with Application Note 74: Reading and
Writing iButtons via Serial Interf aces can be downlo ad ed from the Maxim we b s ite.
V
PU
GND
1-WIRE B US
15µs
VIH of Master
T
RC
T
INT
> 1µs
Master samples
LINE TYPE LEGEND
Bus master p