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Product Specification 1

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General Description

The Virtex®-6 family provides the newest, most advanced features in the FPGA market. Virtex-6 FPGAs are the programmable silicon

foundation for Targeted Design Platforms that deliver integrated software and hardware components to enable designers to focus on

innovation as soon as their development cycle begins. Using the third-generation ASMBL™ (Advanced Silicon Modular Block) column-

based architecture, the Virtex-6 family contains multiple distinct sub-families. This overview covers the devices in the LXT, SXT, and HXT

sub-families. Each sub-family contains a different ratio of features to most efficiently address the needs of a wide variety of advanced logic

designs. In addition to the high-performance logic fabric, Virtex-6 FPGAs contain many built-in system-level blocks. These features allow

logic designers to build the highest levels of performance and functionality into their FPGA-based systems. Built on a 40 nm state-of-the-

art copper process technology, Virtex-6 FPGAs are a programmable alternative to custom ASIC technology. Virtex-6 FPGAs offer the best

solution for addressing the needs of high-performance logic designers, high-performance DSP designers, and high-performance

embedded systems designers with unprecedented logic, DSP, connectivity, and soft microprocessor capabilities.

Summary of Virtex-6 FPGA Features

• Three sub-families:

• Virtex-6 LXT FPGAs: High-performance logic with

advanced serial connectivity

• Virtex-6 SXT FPGAs: Highest signal processing

capability with advanced serial connectivity

• Virtex-6 HXT FPGAs: Highest bandwidth serial

connectivity

• Compatibility across sub-families

• LXT and SXT devices are footprint compatible in

the same package

• Advanced, high-performance FPGA Logic

• Real 6-input look-up table (LUT) technology

• Dual LUT5 (5-input LUT) option

• LUT/dual flip-flop pair for applications requiring rich

• Improved routing efficiency

• 64-bit (or two 32-bit) distributed LUT RAM option

per 6-input LUT

• SRL32/dual SRL16 with registered outputs option

• Powerful mixed-mode clock managers (MMCM)

• MMCM blocks provide zero-delay buffering,

frequency synthesis, clock-phase shifting, input-

jitter filtering, and phase-matched clock division

•36-Kb block RAM/FIFOs

• Dual-port RAM blocks

• Programmable

-Dual-port widths up to 36 bits

-Simple dual-port widths up to 72 bits

• Enhanced programmable FIFO logic

• Built-in optional error-correction circuitry

• Optionally use each block as two independent

18 Kb blocks

• High-performance parallel SelectIO™ technology

• 1.2 to 2.5V I/O operation

• Source-synchronous interfacing using

ChipSync™ technology

• Digitally controlled impedance (DCI) active

termination

• Flexible fine-grained I/O banking

• High-speed memory interface support with

integrated write-leveling capability

• Advanced DSP48E1 slices

• 25 x 18, two's complement multiplier/accumulator

• Optional pipelining

• New optional pre-adder to assist filtering

applications

• Optional bitwise logic functionality

• Dedicated cascade connections

• Flexible configuration options

• SPI and Parallel Flash interface

• Multi-bitstream support with dedicated fallback

reconfiguration logic

• Automatic bus width detection

• System Monitor capability on all devices

• On-chip/off-chip thermal and supply voltage

monitoring

• JTAG access to all monitored quantities

• Integrated interface blocks for PCI Express® designs

• Compliant to the PCI Express Base Specification

2.0

• Gen1 (2.5 Gb/s) and Gen2 (5 Gb/s) support with

GTX transceivers

• Endpoint and Root Port capable

• x1, x2, x4, or x8 lane support per block

• GTX transceivers: up to 6.6 Gb/s

• Data rates below 480 Mb/s supported by

oversampling in FPGA logic.

• GTH transceivers: 2.488 Gb/s to beyond 11 Gb/s

• Integrated 10/100/1000 Mb/s Ethernet MAC block

• Supports 1000BASE-X PCS/PMA and SGMII

using GTX transceivers

• Supports MII, GMII, and RGMII using SelectIO

technology resources

• 2500Mb/s support available

• 40 nm copper CMOS process technology

• 1.0V core voltage (-1, -2, -3 speed grades only)

• Lower-power 0.9V core voltage option (-1L speed

grade only)

• High signal-integrity flip-chip packaging available in

standard or Pb-free package options

Virtex-6 Family Overview

DS150 (v2.4) January 19, 2012 Product Specification

Virtex-6 Family Overview

DS150 (v2.4) January 19, 2012 www.xilinx.com

Product Specification 2

Virtex-6 FPGA Feature Summary

Table 1: Virtex-6 FPGA Feature Summary by Device

Device Logic

Cells

Configurable Logic

Blocks (CLBs)

DSP48E1

Slices(2)

Block RAM Blocks

MMCMs(4) Interface

Blocks for

PCI Express

Ethernet

MACs(5)

Maximum

Transceivers Total

I/O

Banks(6)

Max

User

I/O(7)

Slices(1) Max

Distributed

RAM (Kb) 18 Kb(3) 36 Kb Max

(Kb) GTX GTH

XC6VLX75T 74,496 11,640 1,045 288 312 156 5,616 6 1 4 12 0 9 360

XC6VLX130T 128,000 20,000 1,740 480 528 264 9,504 10 2 4 20 0 15 600

XC6VLX195T 199,680 31,200 3,040 640 688 344 12,384 10 2 4 20 0 15 600

XC6VLX240T 241,152 37,680 3,650 768 832 416 14,976 12 2 4 24 0 18 720

XC6VLX365T 364,032 56,880 4,130 576 832 416 14,976 12 2 4 24 0 18 720

XC6VLX550T 549,888 85,920 6,200 864 1,264 632 22,752 18 2 4 36 0 30 1200

XC6VLX760 758,784 118,560 8,280 864 1,440 720 25,920 18 0 0 0 0 30 1200

XC6VSX315T 314,880 49,200 5,090 1,344 1,408 704 25,344 12 2 4 24 0 18 720

XC6VSX475T 476,160 74,400 7,640 2,016 2,128 1,064 38,304 18 2 4 36 0 21 840

XC6VHX250T 251,904 39,360 3,040 576 1,008 504 18,144 12 4 4 48 0 8 320

XC6VHX255T 253,440 39,600 3,050 576 1,032 516 18,576 12 2 2 24 24 12 480

XC6VHX380T 382,464 59,760 4,570 864 1,536 768 27,648 18 4 4 48 24 18 720

XC6VHX565T 566,784 88,560 6,370 864 1,824 912 32,832 18 4 4 48 24 18 720

Notes:

1. Each Virtex-6 FPGA slice contains four LUTs and eight flip-flops, only some slices can use their LUTs as distributed RAM or SRLs.

2. Each DSP48E1 slice contains a 25 x 18 multiplier, an adder, and an accumulator.

3. Block RAMs are fundamentally 36 Kbits in size. Each block can also be used as two independent 18 Kb blocks.

4. Each CMT contains two mixed-mode clock managers (MMCM).

5. This table lists individual Ethernet MACs per device.

6. Does not include configuration Bank 0.

7. This number does not include GTX or GTH transceivers.

Virtex-6 Family Overview

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Product Specification 3

Virtex-6 FPGA Device-Package Combinations and Maximum I/Os

Virtex-6 LXT and SXT FPGA package combinations with the maximum available I/Os per package are shown in Ta b l e 2 .

Virtex-6 HXT FPGA package combinations with the maximum available I/Os per package are shown in Ta b l e 3 .

Table 2: Virtex-6 LXT and SXT FPGA Device-Package Combinations and Maximum Available I/Os

Package FF484

FFG484

FF784

FFG784

FF1156

FFG1156

FF1759

FFG1759

FF1760

FFG1760

Size (mm) 23 x 23 29 x 29 35 x 35 42.5 x 42.5 42.5 x 42.5

Device GTXs I/O GTXs I/O GTXs I/O GTXs I/O GTXs I/O

XC6VLX75T 8 240 12 360

XC6VLX130T 8 240 12 400 20 600

XC6VLX195T 12 400 20 600

XC6VLX240T 12 400 20 600 24 720

XC6VLX365T 20 600 24 720

XC6VLX550T 36 840 0 1200

XC6VLX760 0 1200

XC6VSX315T 20 600 24 720

XC6VSX475T 20 600 36 840

Notes:

1. Flip-chip packages are also available in Pb-Free versions (FFG).

Table 3: Virtex-6 HXT FPGA Device-Package Combinations and Maximum Available I/Os

Package FF1154

FFG1154

FF1155

FFG1155

FF1923

FFG1923

FF1924

FFG1924

Size(mm) 35x35 35x35 45x45 45x45

Device GTXs GTHs I/O GTXs GTHs I/O GTXs GTHs I/O GTXs GTHs I/O

XC6VHX250T 48 0 320

XC6VHX255T 24 12 440 24 24 480

XC6VHX380T 48 0 320 24 12 440 40 24 720 48 24 640

XC6VHX565T 40 24 720 48 24 640

Notes:

1. Flip-chip packages are also available in Pb-Free versions (FFG).

Virtex-6 Family Overview

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Product Specification 4

Configuration

Virtex-6 FPGAs store their customized configuration in SRAM-type internal latches. The number of configuration bits is

between 26 Mb and 177 Mb, depending on device size but independent of the specific user-design implementation, unless

compression mode is used. The configuration storage is volatile and must be reloaded whenever the FPGA is powered up.

This storage can also be reloaded at any time by pulling the PROGRAM_B pin Low. Several methods and data formats for

loading configuration are available, determined by the three mode pins.

Bit-serial configurations can be either master serial mode where the FPGA generates the configuration clock (CCLK) signal,

or slave serial mode where the external configuration data source also clocks the FPGA. For byte- and word-wide

configurations, master SelectMAP mode generates the CCLK signal while slave SelectMAP mode receives the CCLK signal

for the 8-, 16-, or 32-bit-wide transfer. Alternatively, serial-peripheral interface (SPI) and byte-peripheral interface (BPI)

modes are used with industry-standard flash memories and are clocked by the CCLK output of the FPGA. JTAG mode uses

boundary-scan protocols to load bit-serial configuration data.

The bitstream configuration information is generated by the ISE® software using a program called BitGen. The configuration

process typically executes the following sequence:

• Detects power-up (power-on reset) or PROGRAM_B when Low.

• Clears the whole configuration memory.

• Samples the mode pins to determine the configuration mode: master or slave, bit-serial or parallel, or bus width.

• Loads the configuration data starting with the bus-width detection pattern followed by a synchronization word, checks

for the proper device code, and ends with a cyclic redundancy check (CRC) of the complete bitstream.

• Start-up executes a user-defined sequence of events: releasing the internal reset (or preset) of flip-flops, optionally

waiting for the phase-locked loops (PLLs) to lock and/or the DCI to match, activating the output drivers, and transitions

the DONE pin High.

Dynamic Reconfiguration Port

The dynamic reconfiguration port (DRP) gives the system designer easy access to configuration bits and status registers for

three block types: 32 locations for each clock tile, 128 locations for the System Monitor, and 128 locations for each serial

GTX or GTH transceiver.

The DRP behaves like memory-mapped registers, and can access and modify block-specific configuration bits as well as

status and control registers.

Encryption, Readback, and Partial Reconfiguration

As a special option, the bitstream can be AES-encrypted to prevent unauthorized copying of the design. The Virtex-6 FPGA

performs the decryption using the internally stored 256-bit key that can use battery backup or alternative non-volatile

storage.

Most configuration data can be read back without affecting the system’s operation. Typically, configuration is an all-or-

nothing operation, but the Virtex-6 FPGA also supports partial reconfiguration. When applicable in certain designs, partial

reconfiguration can greatly improve the versatility of the FPGA. It is even possible to reconfigure a portion of the FPGA while

the rest of the logic remains active i.e., active partial reconfiguration.

CLBs, Slices, and LUTs

The look-up tables (LUTs) in Virtex-6 FPGAs can be configured as either one 6-input LUT (64-bit ROMs) with one output, or

as two 5-input LUTs (32-bit ROMs) with separate outputs but common addresses or logic inputs. Each LUT output can

optionally be registered in a flip-flop. Four such LUTs and their eight flip-flops as well as multiplexers and arithmetic carry

logic form a slice, and two slices form a configurable logic block (CLB). Four flip-flops per slice (one per LUT) can optionally

be configured as latches. In that case, the remaining four flip-flops in that slice must remain unused.

Between 25–50% of all slices can also use their LUTs as distributed 64-bit RAM or as 32-bit shift registers (SRL32) or as two

SRL16s. Modern synthesis tools take advantage of these highly efficient logic, arithmetic, and memory features. Expert

designers can also instantiate them.

Virtex-6 Family Overview

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Product Specification 5

Clock Management

Each Virtex-6 FPGA has up to nine clock management tiles (CMTs), each consisting of two mixed-mode clock managers

(MMCMs), which are PLL based.

Phase-Locked Loop

The MMCM can serve as a frequency synthesizer for a wider range of frequencies and as a jitter filter for incoming clocks.

The heart of the MMCM is a voltage-controlled oscillator (VCO) with a frequency from 600 MHz up to 1600 MHz, spanning

more than one octave. There are three sets of programmable frequency dividers (D, M, and O).

The pre-divider D (programmable by configuration) reduces the input frequency and feeds one input of the traditional PLL

phase/frequency comparator. The feedback divider (programmable by configuration) acts as a multiplier because it divides

the VCO output frequency before feeding the other input of the phase comparator. D and M must be chosen appropriately

to keep the VCO within its specified frequency range.

The VCO has eight equally-spaced output phases (0°, 45°, 90°, 135°, 180°, 225°, 270°, and 315°). Each can be selected to

drive one of the seven output dividers, O0 to O6 (each programmable by configuration to divide by any integer from 1 to 128).

MMCM Programmable Features

The MMCM has three input-jitter filter options: low bandwidth, high bandwidth, or optimized mode. Low-bandwidth mode has

the best jitter attenuation but not the smallest phase offset. High-bandwidth mode has the best phase offset, but not the best

jitter attenuation. Optimized mode allows the tools to find the best setting.

The MMCM can have a fractional counter in either the feedback path (acting as a multiplier) or in one output path. Fractional

counters allow non-integer increments of 1/8 and can thus increase frequency synthesis capabilities by a factor of 8.

The MMCM can also provide fixed or dynamic phase shift in small increments that depend on the VCO frequency. At

600 MHz the phase-shift timing increment is 30 ps; at 1600 MHz, it is 11.5 ps.

Clock Distribution

Each Virtex-6 FPGA provides five different types of clock lines (BUFG, BUFR, BUFIO, BUFH, and the high-performance

clock) to address the different clocking requirements of high fanout, short propagation delay, and extremely low skew.

Global Clock Lines

In each Virtex-6 FPGA, 32 global-clock lines have the highest fanout and can reach every flip-flop clock, clock enable,

set/reset, as well as many logic inputs. There are 12 global clock lines within any region. Global clock lines can be driven by

global clock buffers, which can also perform glitchless clock multiplexing and the clock enable function. Global clocks are

often driven from the CMT, which can completely eliminate the basic clock distribution delay.

Regional Clocks

Regional clocks can drive all clock destinations in their region as well as the region above and below. A region is defined as

any area that is 40 I/O and 40 CLB high and half the chip wide. Virtex-6 FPGAs have between 6 and 18 regions. There are

6 regional clock tracks in every region. Each regional clock buffer can be driven from either of four clock-capable input pins,

and its frequency can optionally be divided by any integer from 1 to 8.

I/O Clocks

I/O clocks are especially fast and serve only I/O logic and serializer/deserializer (SerDes) circuits, as described in the I/O

Logic section. Virtex-6 devices have a high-performance direct connection from the MMCM to the I/O directly for low-jitter,

high-performance interfaces.

Virtex-6 Family Overview

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Product Specification 6

Block RAM

Every Virtex-6 FPGA has between 156 and 1064 dual-port block RAMs, each storing 36 Kbits. Each block RAM has two

completely independent ports that share nothing but the stored data.

Synchronous Operation

Each memory access, read and write, is controlled by the clock. All inputs, data, address, clock enables, and write enables

are registered. Nothing happens without a clock. The input address is always clocked, retaining data until the next operation.

An optional output data pipeline register allows higher clock rates at the cost of an extra cycle of latency.

During a write operation, the data output can reflect either the previously stored data, the newly written data, or remain

unchanged.

Programmable Data Width

• Each port can be configured as 32K × 1, 16K × 2, 8K × 4, 4K × 9 (or 8), 2K × 18 (or 16), 1K × 36 (or 32), or 512 x 72

(or 64). The two ports can have different aspect ratios, without any constraints.

• Each block RAM can be divided into two completely independent 18 Kb block RAMs that can each be configured to any

aspect ratio from 16K x 1 to 512 x 36. Everything described previously for the full 36 Kb block RAM also applies to each

of the smaller 18 Kb block RAMs.

• In 18 Kb block RAMs, only simple dual-port mode can provide data width of >36 bits. In this mode, one port is

dedicated to read and the other port is dedicated to write operation. In SDP mode one side (read or write) can be

variable while the other is fixed to 32/36 or 64/72. There is no read output during write. The dual-port 36 Kb RAM both

sides can be of variable width.

• Two adjacent 36 Kb block RAMs can be configured as one cascaded 64K × 1 dual-port RAM without any additional

logic.

Error Detection and Correction

Each 64 bit-wide block RAM can generate, store, and utilize eight additional Hamming-code bits, and perform single-bit error

correction and double-bit error detection (ECC) during the read process. The ECC logic can also be used when writing to,

or reading from external 64/72-wide memories. This works in simple dual-port mode and does not support read-during-write.

FIFO Controller

The built-in FIFO controller for single-clock (synchronous) or dual-clock (asynchronous or multirate) operation increments

the internal addresses and provides four handshaking flags: full, empty, almost full, and almost empty. The almost full and

almost empty flags are freely programmable. Similar to the block RAM, the FIFO width and depth are programmable, but the

write and read ports always have identical width. First-word fall-through mode presents the first-written word on the data

output even before the first read operation. After the first word has been read, there is no difference between this mode and

the standard mode.

Digital Signal Processing—DSP48E1 Slice

DSP applications use many binary multipliers and accumulators, best implemented in dedicated DSP slices. All Virtex-6

FPGAs have many dedicated, full-custom, low-power DSP slices combining high speed with small size, while retaining

system design flexibility.

Each DSP48E1 slice fundamentally consists of a dedicated 25 × 18 bit two's complement multiplier and a 48-bit

accumulator, both capable of operating at 600 MHz. The multiplier can be dynamically bypassed, and two 48-bit inputs can

feed a single-instruction-multiple-data (SIMD) arithmetic unit (dual 24-bit add/subtract/accumulate or quad 12-bit

add/subtract/accumulate), or a logic unit that can generate any one of 10 different logic functions of the two operands.

The DSP48E1 includes an additional pre-adder, typically used in symmetrical filters. This new pre-adder improves

performance in densely packed designs and reduces the logic slice count by up to 50%.

The DSP48E1 slice provides extensive pipelining and extension capabilities that enhance speed and efficiency of many

applications, even beyond digital signal processing, such as wide dynamic bus shifters, memory address generators, wide

bus multiplexers, and memory-mapped I/O register files. The accumulator can also be used as a synchronous up/down

counter. The multiplier can perform logic functions (AND, OR) and barrel shifting.

Virtex-6 Family Overview

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Product Specification 7

Input/Output

The number of I/O pins varies from 240 to 1200 depending on device and package size. Each I/O pin is configurable and can

comply with a large number of standards, using up to 2.5V. The Virtex-6 FPGA SelectIO Resources User Guide describes

the I/O compatibilities of the various I/O options. With the exception of supply pins and a few dedicated configuration pins,

all other package pins have the same I/O capabilities, constrained only by certain banking rules.

All I/O pins are organized in banks, with 40 pins per bank. Each bank has one common VCCO output supply-voltage pin,

which also powers certain input buffers. Some single-ended input buffers require an externally applied reference voltage

(VREF). There are two VREF pins per bank (except configuration bank 0). A single bank can have only one VREF voltage

value.

I/O Electrical Characteristics

Single-ended outputs use a conventional CMOS push/pull output structure driving High towards VCCO or Low towards

ground, and can be put into high-Z state. The system designer can specify the slew rate and the output strength. The input

is always active but is usually ignored while the output is active. Each pin can optionally have a weak pull-up or a weak pull-

down resistor.

Any signal pin pair can be configured as differential input pair or output pair. Differential input pin pairs can optionally be

terminated with a 100Ω internal resistor. All Virtex-6 devices support differential standards beyond LVDS: HT, RSDS, BLVDS,

differential SSTL, and differential HSTL.

Digitally Controlled Impedance

Digitally controlled impedance (DCI) can control the output drive impedance (series termination) or can provide parallel

termination of input signals to VCCO, or split (Thevenin) termination to VCCO/2. DCI uses two pins per bank as reference pins,

but one such pair can also control multiple banks. VRN must be resistively pulled to VCCO, while VRP must be resistively

connected to ground. The resistor must be either 1× or 2× the characteristic trace impedance, typically close to 50Ω.

I/O Logic

Input and Output Delay

This section describes the available logic resources connected to the I/O interfaces. All inputs and outputs can be configured

as either combinatorial or registered. Double data rate (DDR) is supported by all inputs and outputs. Any input or output can

be individually delayed by up to 32 increments of ~78 ps each. This is implemented as IODELAY. The number of delay steps

can be set by configuration and can also be incremented or decremented while in use.

For using either IODELAY, the system designer must instantiate the IODELAY control block and clock it with a frequency

close to 200 MHz. Each 32-tap total IODELAY is controlled by that frequency, thus unaffected by temperature, supply

voltage, and processing variations.

ISERDES and OSERDES

Many applications combine high-speed bit-serial I/O with slower parallel operation inside the device. This requires a

serializer and deserializer (SerDes) inside the I/O structure. Each input has access to its own deserializer (serial-to-parallel

converter) with programmable parallel width of 2, 3, 4, 5, 6, 7, 8, or 10 bits. Each output has access to its own serializer

(parallel-to-serial converter) with programmable parallel width of up to 8 bits wide for single data rate (SDR), or up to 10 bits

wide for double data rate (DDR).

System Monitor

Every Virtex-6 FPGA contains a System Monitor circuit providing thermal and power supply status information. Sensor

outputs are digitized by a 10-bit 200kSPS analog-to-digital converter (ADC). This fully tested and specified ADC can also be

used to digitize up to 17 external analog input channels. The System Monitor ADC utilizes an on-chip reference circuit

thereby eliminating the need for any external active components. On-chip temperature and power supplies are monitored

with a measurement accuracy of ±4°C and ±1% respectively.

By default the System Monitor continuously digitizes the output of all on-chip sensors. The most recent measurement results

together with maximum and minimum readings are stored in dedicated registers for access at any time through the DRP or

JTAG interfaces. User defined alarm thresholds can automatically indicate over temperature events and unacceptable power

supply variation. A specified limit (for example: 125°C) can be used to initiate an automatic power down.

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Product Specification 8

The System Monitor does not require explicit instantiation in a design. Once the appropriate power supply connections are

made, measurement data can be accessed at any time, even pre-configuration or during power down, through the JTAG test

access port (TAP).

Low-Power Gigabit Transceivers

Ultra-fast serial data transmission between ICs, over the backplane, or over longer distances is becoming increasingly

popular and important. It requires specialized dedicated on-chip circuitry and differential I/O capable of coping with the

signal integrity issues at these high data rates.

All but one Virtex-6 device has between 8 to 72 gigabit transceiver circuits. Each GTX transceiver is a combined transmitter

and receiver capable of operating at a data rate between 480 Mb/s and 6.6 Gb/s. Lower data rates can be achieved using

FPGA logic-based oversampling. Each GTH transceiver is a combined transmitter and receiver capable of operating at a

rate between 2.488 Gb/s and 11.18 Gb/s. The GTX transmitter and receiver are independent circuits that use separate

PLLs to multiply the reference frequency input by certain programmable numbers between 4 and 25, to become the bit-serial

data clock. The GTH transceiver is a purpose-built design for 10 Gb/s rates and shares a single high-performance PLL

between four transmitter and receiver circuits. Each GTX and GTH transceiver has a large number of user-definable features

and parameters. All of these can be defined during device configuration, and many can also be modified during operation.

Transmitter

The GTX transmitter is fundamentally a parallel-to-serial converter with a conversion ratio of 8, 10, 16, 20, 32, or 40. The

GTH transmitter offers bit widths of 16, 20, 32, 40, 64, or 80 to allow additional timing margin for high-performance designs.

These transmitter outputs drive the PC board with a single-channel differential current-mode logic (CML) output signal.

TXOUTCLK is the appropriately divided serial data clock and can be used directly to register the parallel data coming from

the internal logic. The incoming parallel data is fed through a small FIFO and can optionally be modified with the 8B/10B,

64B/66B, or the 64B/67B (GTX only) algorithm to guarantee a sufficient number of transitions. The bit-serial output signal

drives two package pins with complementary CML signals. This output signal pair has programmable signal swing as well as

programmable pre-emphasis to compensate for PC board losses and other interconnect characteristics.

Receiver

The receiver is fundamentally a serial-to-parallel converter, changing the incoming bit serial differential signal into a parallel

stream of words, each 8, 10, 16, 20, 32, or 40 bits wide. The GTH transceiver offers 16, 20, 32, 40, 64, and 80 bit widths to

allow greater timing margin. The receiver takes the incoming differential data stream, feeds it through a programmable

equalizer (to compensate for PC board and other interconnect characteristics), and uses the FREF input to initiate clock

recognition. There is no need for a separate clock line. The data pattern uses non-return-to-zero (NRZ) encoding and

optionally guarantees sufficient data transitions by using the selected encoding scheme. Parallel data is then transferred into

the FPGA logic using the RXUSRCLK clock. The serial-to-parallel conversion ratio for GTX transceivers can be 8, 10, 16, 20,

32, or 40. The serial-to-parallel conversion ratio for GTH transceivers can be 16, 20, 32, 40, 64, or 80 for GTH.

Out-of-Band Signaling

The GTX transceivers provide Out-of-Band (OOB) signaling, often used to send low-speed signals from the transmitter to

the receiver, while high-speed serial data transmission is not active, typically when the link is in a power-down state or has

not been initialized. This benefits PCI Express and SATA/SAS applications.

Integrated Interface Blocks for PCI Express Designs

The PCI Express standard is a packet-based, point-to-point serial interface standard. The differential signal transmission

uses an embedded clock, which eliminates the clock-to-data skew problems of traditional wide parallel buses.

The PCI Express Base Specification Revision 2.0 is backwards compatible with Revision 1.1 and defines a configurable raw

data rate of 2.5 Gb/s, or 5.0 Gb/s per lane in each direction. To scale bandwidth, the specification allows multiple lanes to be

joined to form a larger link between PCI Express devices.

All Virtex-6 devices (except the XC6VLX760) include at least one integrated interface block for PCI Express technology that

can be configured as an Endpoint or Root Port, compliant to the PCI Express Base Specification Revision 2.0. The Root Port

can be used to build the basis for a compatible Root Complex, to allow custom FPGA-FPGA communication via the PCI

Express protocol, and to attach ASSP Endpoint devices such as Fibre Channel HBAs to the FPGA.

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Product Specification 9

This block is highly configurable to system design requirements and can operate 1, 2, 4, or 8 lanes at the 2.5 Gb/s data rate

and the 5.0 Gb/s data rate. For high-performance applications, advanced buffering techniques of the block offer a flexible

maximum payload size of up to 1024 bytes. The integrated block interfaces to the GTX transceivers for serial connectivity,

and to block RAMs for data buffering. Combined, these elements implement the Physical Layer, Data Link Layer, and

Transaction Layer of the PCI Express protocol.

Xilinx provides a light-weight, configurable, easy-to-use LogiCORE™ wrapper that ties the various building blocks (the

integrated block for PCI Express, the GTX transceivers, block RAM, and clocking resources) into an Endpoint or Root Port

solution. The system designer has control over many configurable parameters: lane width, maximum payload size, FPGA

logic interface speeds, reference clock frequency, and base address register decoding and filtering.

More information and documentation on solutions for PCI Express designs can be found at:

http://www.xilinx.com/technology/protocols/pciexpress.htm

10/100/1000 Mb/s Ethernet Controller (2,500 Mb/s Supported)

An integrated Tri-mode Ethernet MAC (TEMAC) block is easily connected to the FPGA logic, the GTX transceivers, and the

SelectIO resources. This TEMAC block saves logic resources and design effort. All of the Virtex-6 devices (except the

XC6VLX760) have four TEMAC blocks, implementing the link layer of the OSI protocol stack. The CORE Generator™

software GUI helps to configure flexible interfaces to GTX transceiver or SelectIO technology, to the FPGA logic, and to a

microprocessor (when required). The TEMAC is designed to the IEEE Std 802.3-2005 specification. 2,500 Mb/s support is

also available.

Virtex-6 FPGA Ordering Information

Ta ble 4 shows the speed and temperature grades available in the different Virtex-6 devices. Some devices might not be

available in every speed and temperature grade.

The Virtex-6 FPGA ordering information shown in Figure 1 applies to all packages including Pb-Free.

Table 4: Virtex-6 FPGAs Speed Grade and Temperature Ranges

Device Family

Speed Grade and Temperature Range

Commercial (C)

0°C to +85°C

Extended (E)

0°C to +100°C

Industrial (I)

-40°C to +100°C

Virtex-6 LXT -3, -2, -1, -1L -2 -2, -1, -1L

Virtex-6 SXT -3, -2, -1, -1L -2 -2, -1, -1L

Virtex-6 HXT -3, -2, -1 -2 -2, -1

X-Ref Target - Figure 1

Figure 1: Virtex-6 FPGA Ordering Information

Example: XC6VLX240T-1FFG1156C

Device Type Temperature Range:

Number of Pins(3)

Package Type

Speed Grade

(-1, -L1(1), -2, -3(2))

Pb-Free

DS150_01_103111

Note:

1) -L1 is the ordering code for the lower power -1L speed grade.

-L1 is not available in the Virtex-6 HXT devices. See

the Virtex-6 FPGA data sheet for more information.

2) -3 speed grades are not available in all devices.

3) Some package names do not exactly match the number

of pins present on that package. Please see UG365: Virtex-6 FPGA Packaging and Pinout Specifications for package details.

I = Industrial (Tj = –40°C to +100°C)

E = Extended (Tj = 0°C to +100°C)

C = Commercial (Tj = 0°C to +85°C)

Virtex-6 Family Overview

DS150 (v2.4) January 19, 2012 www.xilinx.com

Product Specification 10

Revision History

The following table shows the revision history for this document:

Notice of Disclaimer

The information disclosed to you hereunder (the "Materials") is provided solely for the selection and use of Xilinx products. To the

maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL

WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF

MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable

(whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature

related to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect,

special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a

result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the

possibility of the same. Xilinx assumes no obligation to correct any errors contained in the Materials, or to advise you of any corrections

or update. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products

are subject to the terms and conditions of the Limited Warranties which can be viewed at http://www.xilinx.com/warranty.htm; IP cores

may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended

to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in

Critical Applications: http://www.xilinx.com/warranty.htm#critapps.

Date Version Description of Revisions

02/02/09 1.0 Initial Xilinx release.

05/05/09 1.1 Added the FF1156 package for both the XC6VSX315T and XC6VSX475T devices in Table2, page3.

Updated the PCI Express design discussion on page 9 to remove the LogiCORE wrapper (<100 LUT)

description and clarify 8 lanes at the 5.0 Gb/s data rate. Clerical edits to Global Clock Lines and

10/100/1000 Mb/s Ethernet Controller (2,500 Mb/s Supported) sections. Overall clarifications made in

text.

06/24/09 1.2 Added ordering information and FPGA documentation sections.

09/16/09 2.0 Added Virtex-6 HXT family information. Updated number to 26 Mb in Configuration section.

11/06/09 2.1 Clarified distributed RAM features on page 1. Updated CLB slice number for the XC6VHX565T in

Ta b le 1 . Updated compliance to the PCI Express Base Specification Revision 2.0. Updated Integrated

Interface Blocks for PCI Express Designs section with link to documentation.

01/28/10 2.2 In Ta b l e 1 , there are two Ethernet MACs in the XC6VHX255T. Under Clock Management, page 5,

revised the VCO frequency minimum to 600 MHz which also revised the phase-shift timing increment.

Updated GTX transceivers operating data rate range to 6.6 Gb/s. Changed GTX PLL input reference

clock frequency divider.

03/24/11 2.3 Changed document classification to Preliminary Product Specification from Advance Product

Specification. Updated Figure 1.

01/19/12 2.4 Changed document classification to Product Specification from Preliminary Product Specification.

Updated Configuration, CLBs, Slices, and LUTs, Low-Power Gigabit Transceivers, and Virtex-6 FPGA

Ordering Information (including Figure 1).

Virtex-6 Family Overview

DS150 (v2.4) January 19, 2012 www.xilinx.com

Product Specification 11

Virtex-6 FPGA Documentation

Complete and up-to-date documentation of the Virtex-6 family of FPGAs is available on the Xilinx website. In addition to the

most recent Virtex-6 Family Overview, the following files are also available for download:

Virtex-6 FPGA Data Sheet: DC and Switching

Characteristics (DS152)

This data sheet contains the DC and Switching

Characteristic specifications for the Virtex-6 family.

Virtex-6 FPGA Packaging and Pinout Specifications

(UG365)

These specifications includes the tables for device/package

combinations and maximum I/Os, pin definitions, pinout

tables, pinout diagrams, mechanical drawings, and thermal

specifications.

Virtex-6 FPGA Configuration Guide (UG360)

This all-encompassing configuration guide includes

chapters on configuration interfaces (serial and parallel),

multi-bitstream management, bitstream encryption,

boundary-scan and JTAG configuration, and reconfiguration

techniques.

Virtex-6 FPGA SelectIO Resources User Guide (UG361)

This guide describes the SelectIO™ resources available in

all the Virtex-6 devices.

Virtex-6 FPGA Clocking Resources User Guide (UG362)

This guide describes the clocking resources available in all

the Virtex-6 devices, including the MMCM and clock buffers.

Virtex-6 FPGA Memory Resources User Guide (UG363)

This guide describes the Virtex-6 device block RAM and

FIFO capabilities.

Virtex-6 FPGA CLB User Guide (UG364)

This guide describes the capabilities of the configurable

logic blocks (CLB) available in all Virtex-6 devices.

Virtex-6 FPGA GTX Transceivers User Guide (UG366)

This guide describes the GTX transceivers available in all

the Virtex-6 FPGAs except the XC6VLX760.

Virtex-6 FPGA GTH Transceivers User Guide (UG371)

This guide describes the GTH transceivers available in all

Virtex-6 HXT FPGAs except the XC6VHX250T and the

XC6VHX380T in the FF1154 package.

Virtex-6 FPGA DSP48E1 Slice User Guide (UG369)

This guide describes the architecture of the DSP48E1 slice

in Virtex-6 FPGAs and provides configuration examples.

Virtex-6 FPGA Tri-Mode Ethernet MAC User Guide

(UG368)

This guide describes the dedicated tri-mode Ethernet

media access controller (TEMAC) available in all the

Virtex-6 FPGAs except the XC6VLX760.

Virtex-6 FPGA System Monitor User Guide (UG370)

This guide describes the System Monitor functionality.

Virtex-6 FPGA PCB Design Guide (UG373)

This guide provides information on PCB design for Virtex-6

devices, with a focus on strategies for making design

decisions at the PCB and interface level.