LPC11A13FHI33/201, - NXP Semiconductors

1. General description

The LPC11Axx are an ARM Cortex-M0 based, low-cost 32-bit MCU family, designed for

8/16-bit microcontroller applications, offering performance, low power, simple instruction

set and memory addressing together with reduced code size compared to existing 8/16 -bit

architectures.

The LPC11Axx operate at CPU frequencies of up to 50 MHz.

Analog/mixed-signal subsystems can be configured by software from interconnected

digital and analog peripherals.

The digital peripherals on the LPC11Axx include up to 32 kB of flash memory, up to 4 kB

of EEPROM data memory, up to 8 kB of SRAM data memory, a Fast-mode Plus I2C-bus

interface, a RS-485/EIA-485 USART, two SSP controllers, four general purpose

counter/timers, and up to 42 general purpose I/O pins.

Analog peripherals include a 10-bit ADC, a 10-bit DAC, an analog comparator, a

temperature sensor, an internal voltage reference, and UnderVoltage LockOut (UVLO)

protection.

2. Features and benefits

System:

ARM Cortex-M0 processor, running at frequencies of up to 50 MHz.

ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC).

Serial Wire Debug (SWD)

JTAG boundary scan.

System tick timer.

Memory:

Up to 32 kB on-chip flash program memory.

Up to 4 kB on-chip EEPROM data memory; byte erasable and byte programmable.

Up to 8 kB SRAM data memory.

16 kB boot ROM.

In-System Programming (ISP) for flash and In-Application Programming (IAP) for

flash and EEPROM via on-chip bootloader software.

Includes ROM-based 32-bit integer division and I2C-bus driver routines.

Digital peripherals:

Up to 42 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down

resistors, repeater mode, and open-drain mode.

LPC11Axx

32-bit ARM Cortex-M0 microcontroller; up to 32 kB flash, 8 kB

SRAM, 4 kB EEPROM; configurable analog/mixed-signal

Rev. 4 — 30 October 2012 Product data sheet

Product data sheet Rev. 4 — 30 October 2012 2 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

Up to 16 pins are configurable with a digital input glitch filter for removing glitches

with widths of 10 ns or less and two pins are configurable for 50 ns glitch filters.

GPIO pins can be used as edge and level sensitive interrupt sources.

High-current source output driver (20 mA) on one pin (PIO0_21).

High-current sink driver (20 mA) on true open-drain pins (PIO0_2 and PIO0_3).

Four general pu rp os e co un te r/ tim er s wi th a total of up to 16 captu re inpu ts and 14

match outpu ts.

Programmable Windowed WatchDog Timer (WWDT) with a dedicated, internal

low-power WatchDog Oscillator (WDOsc).

Analog peripherals:

10-bit ADC with input multiplexing among 8 pins.

10-bit DAC with flexible conversion triggering.

Highly flexible analog comparator with a programmable voltage reference.

Integrated temperature sensor.

Internal voltage refere n ce.

UnderVoltage Lockout (UVLO) protection against power-supply droop below 2.4 V.

Serial interfaces:

USART with fractional baud rate generation, internal FIFO, support for

RS-485/9-bit mode and synchronous mode.

Two SSP controllers with FIFO and multi-protocol capabilities. Support data rates

of up to 25 Mbit/s.

I2C-bus interface suppor tin g the full I2C-bu s specifica tion and Fast-mode Plus with

a data rate of 1 Mbit/s with multiple ad d re ss reco gn itio n an d m on ito r mo de .

Clock generation :

Crystal Oscillator (SysOsc) with an operating range of 1 MHz to 25 MHz.

12 MHz internal RC Oscillator (IRC) trimmed to 1% accuracy that can optionally be

used as a system clock.

Internal low-power, Low-Frequency Oscillator (LFOsc) with programmable

frequency outp ut .

Clock input for external system clock (25 MHz typical).

PLL allows CPU operation up to the maximum CPU rate with the IRC, the external

clock, or the SysOsc as clock sources.

Clock output function with divider that can reflect the SysOsc, the IRC, the main

clock, or the LFOsc.

Power control:

Supports one reduced powe r m od e: The ARM Slee p mod e .

Power profiles residing in boot ROM allowing to optimize performance and

minimize power consumption for any given application through one simple fun ction

call.

Processor wake-up from reduced power mode using any interrupt.

Power-On Reset (POR).

Brown-Out Detect (BOD) with two programmable thresholds for interrupt and one

hardware controlled reset trip point.

POR and BOD are always enabled for rapid UVLO protection against power supply

voltage droop below 2.4 V.

Unique device serial number for identification.

Product data sheet Rev. 4 — 30 October 2012 3 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

Single 3.3 V power supply (2.6 V to 3.6 V).

Temperature range 40 C to +85 C.

Availa ble as LQFP48 package , HVQFN33 (7  7) and HVQFN33 (5  5) packages, and

in a very small WLCSP20 package.

3. Applications

4. Ordering information

Power management Gaming equipment

Industrial control Motion control

Remote monitoring Medical instrumentation

Point-of-sale Fire and security

Test and measurement equipment Sensors

Network appliances and services Precision instrumentation

Factory auto ma tio n HVAC and building control

Table 1. Ordering information

Type number Package

Name Description Version

LPC11A02UK WLCSP20 wafer level chip-size package; 20 bumps; 2.5  2.5  0.6 mm -

LPC11A04UK WLCSP20 wafer level chip-size package; 20 bumps; 2.5  2.5  0.6 mm -

LPC1 1A11FHN33/001 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33

terminals; body 7  7  0.85 mm n/a

LPC1 1A12FHN33/101 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33

terminals; body 7  7  0.85 mm n/a

LPC1 1A13FHI33/201 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33

terminals; body 5  5  0.85 mm n/a

LPC1 1A14FHN33/301 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33

terminals; body 7  7  0.85 mm n/a

LPC11A12FBD48/101 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7  7 

1.4 mm SOT313-2

LPC11A14FBD48/301 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7  7 

1.4 mm SOT313-2

Product data sheet Rev. 4 — 30 October 2012 4 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

4.1 Ordering options

Table 2. Ordering options

Type number Flash SRAM EEPROM

10-bit ADC channels

10-bit DAC

Temperature sensor

Analog comparator

USART

SSP/SPI

I2C

GPIO

Package

LPC11A02UK 16 kB 4 kB 2 kB 8 1 1 1 1 1 1 18 WLCSP20

LPC11A04UK 32 kB 8 kB 4 kB 8 1 1 1 1 1 1 18 WLCSP20

LPC11A11FHN33/001 8 kB 2 kB 512 B 8 1 1 1 1 2 1 28 HVQFN33

LPC11A12FHN33/101 16 kB 4 kB 1 kB 8 1 1 1 1 2 1 28 HVQFN33

LPC11A12FBD48/101 16 kB 4 kB 1 kB 8 1 1 1 1 2 1 42 LQFP48

LPC11A13FHI33/201 24 kB 6 kB 2 kB 8 1 1 1 1 2 1 28 HVQFN33

LPC11A14FHN33/301 32 kB 8 kB 4 kB 8 1 1 1 1 2 1 28 HVQFN33

LPC11A14FBD48/301 32 kB 8 kB 4 kB 8 1 1 1 1 2 1 42 LQFP48

Product data sheet Rev. 4 — 30 October 2012 5 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

5. Block diagram

(1) Open-drain pins.

(2) Standard I/O pins.

(3) Not available on WLCSP packages.

(4) Modem control pins not available on WLCSP packages.

Fig 1. LPC11Axx block diagram

SRAM

2/4/6/8 kB

ARM

CORTEX-M0

TEST/DEBUG

INTERFACE

FLASH

8/16/24/32 kB

EEPROM

512 B/

1/4 kB

HIGH-SPEED

GPIO

AHB TO APB

BRIDGE

CLOCK

GENERATION,

POWER CONTROL,

SYSTEM

FUNCTIONS

RESET

clocks, internal voltage reference,

and controls

SWD

LPC11Axx

002aaf428

slave

slave slave

ROM

16 kB

slave

AHB-LITE BUS

GPIO ports

CLKOUT

CLKIN

IRC, LFOSC, WDOSC

SysOsc(3)

POR

BOD

ANALOG COMPARATOR

10-bit ADC

USART(4)

32-bit COUNTER/TIMER 0

CT32B0_MAT[3:0]

AD[7:0]

AOUT

CT32B0_CAP[2:0]

RXD

TXD

RTS, DTR

SCLK

PMU

SYSTEM CONTROL

32-bit COUNTER/TIMER 1

CT32B1_MAT[3:0]

CT32B1_CAP[2:0]

CTS, DCD, DSR, RI ATRG[1:0]

ACMP_I[5:1]

ACMP_O

VDDCMP

16-bit COUNTER/TIMER 1

WINDOWED WATCHDOG

TIMER

CT16B1_MAT[3:0]

16-bit COUNTER/TIMER 0

CT16B0_MAT[3:0]

CT16B0_CAP[2:0]

CT16B1_CAP[2:0]

10-bit DAC

system bus

TEMPERATURE SENSOR

SSP0 SCK0, SSEL0,

MISO0, MOSI0

SSP1(3) SCK1, SSEL1,

MISO1, MOSI1

I2C-BUS

IOCONFIG

SCL, SDA(2)

SCL, SDA(1)

SCL, SDA(2)

XTALIN XTALOUT

Product data sheet Rev. 4 — 30 October 2012 6 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

6. Pinning information

6.1 Pinning

Fig 2. Pin configuration LQFP48 package

LPC11A12FBD48/101

LPC11A14FBD48/301

PIO0_26 PIO1_1

PIO0_28 TRST/PIO0_9

RESET/PIO0_0 TDO/PIO0_8

PIO0_1 TMS/PIO0_7

SS(IO)

TDI/PIO0_6

XTALIN PIO1_0

XTALOUT PIO0_14

DD(IO)

TCK/SWCLK/PIO0_5

PIO0_24 PIO0_4

PIO0_18 PIO0_22

PIO1_6 PIO1_8

PIO1_9 PIO1_7

PIO0_29 PIO1_3

PIO0_19 PIO0_13

PIO0_2 PIO0_12

PIO0_3 PIO0_23

PIO0_25 V

DD(3V3)

PIO0_16 PIO0_27

PIO1_4 V

PIO1_5 PIO0_15

PIO0_17 PIO0_30

PIO0_20 PIO0_11

PIO0_21

PIO0_31

SWDIO/PIO0_10

PIO1_2

002aaf499

Product data sheet Rev. 4 — 30 October 2012 7 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

6.2 Pin description

All functional pins on the LPC11Axx are mapped to GPIO port 0 and port 1 (see Table 4).

The port pins are multiplexed to accommodate more than one function (see Table 3).

The pin function is controlled by the pin’s IOCON register (see the LPC11Axx user

manual). The standard I/O pad configuration is illustrated in Figure 31 and a detailed pin

description is give n in Table 4.

Parts: LPC11A11FHN33/001, LPC11A12FHN33/101, LPC11A13FHI33/201,

LPC11A14FHN33/301

Fig 3. Pin configuration HVQFN 33 package

Parts: LPC11A02UK, LPC11A04UK

Fig 4. Pin configuration WLCSP20 package

002aaf500

Transparent top view

PIO0_22

PIO0_24

PIO0_18

PIO0_4

VDD(IO) TCK/SWCLK/PIO0_5

XTALOUT PIO0_14

XTALIN TDI/PIO0_6

PIO0_1 TMS/PIO0_7

RESET/PIO0_0 TDO/PIO0_8

PIO0_26 TRST/PIO0_9

PIO0_19

PIO0_2

PIO0_3

PIO0_25

PIO0_16

PIO0_17

PIO0_20

PIO0_21

PIO0_13

PIO0_12

PIO0_23

VDD(3V3)

PIO0_27

PIO0_15

PIO0_11

SWDIO/PIO0_10

817

718

619

520

421

322

223

124

terminal 1

index area

33 VSS

002aaf175

1234

Product data sheet Rev. 4 — 30 October 2012 8 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

Table 3. Pin multiplexing

Function Type LQFP48 HVQFN33 WCSP20

Port Glitch filter Pin Pin Ball

System clocks, reset, and wake-up

CLKIN I PIO0_1 no 4 3 B2

PIO0_12 no 46 31 E1

PIO0_19 no 14 9 -

PIO0_24 no 9 7 -

CLKOUT O PIO0_1 no 4 3 B2

PIO0_19 no 14 9 -

XTALIN I

(analog) --64-

XTALOUT O

(analog) --75-

RESET I PIO0_0 20 ns[1] 32C1

Serial Wire Debug (SWD) an d JTAG

TRST I PIO0_9 10 ns[2] 35 24 D4

TCK I PIO0_5 10 ns[2] 29 19 B3

TDI I PIO0_6 10 ns[2] 32 21 C3

TDO O PIO0_8 no 34 23 C2

TMS I PIO0_7 10 ns[2] 33 22 C4

SWCLK I PIO0_2 50 ns[2] 15 10 A1

PIO0_5 10 ns[2] 29 19 B3

SWDIO I/O PIO0_3 50 ns[2] 16 11 B1

PIO0_10 10 ns[2] 38 25 D3

Analog peripherals (ADC, DAC, comp arator)

ACMP_I1 I

(analog) PIO0_27 no 43 28 -

ACMP_I2 I

(analog) PIO0_13 no 47 32 D1

ACMP_I3 I

(analog) PIO0_16 no 18 13 A2

ACMP_I4 I

(analog) PIO0_17 no 21 14 A3

ACMP_I5 I

(analog) PIO0_22 no 27 17 -

ACMP_O O

(digital) PIO0_2 no 15 10 A1

PIO0_3 no 16 11 B1

PIO0_12 no 46 31 E1

PIO0_21 no 23 16 -

PIO0_23 no 45 30 -

AD0 I

(analog) PIO0_6 no 32 21 C3

AD1 I

(analog) PIO0_7 no 33 22 C4

Product data sheet Rev. 4 — 30 October 2012 9 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

AD2 I

(analog) PIO0_8 no 34 23 C2

AD3 I

(analog) PIO0_9 no 35 24 D4

AD4 I

(analog) PIO0_10 no 38 25 D3

AD5 I

(analog) PIO0_11no3926D2

AD6 I

(analog) PIO0_14 no 30 20 B4

AD7 I

(analog) PIO0_15 no 41 27 E4

AOUT O

(analog) PIO0_4 no 28 18 A4

ATRG0 I PIO0_16 10 ns[2] 18 13 A2

ATRG1 I PIO0_17 10 ns[2] 21 14 A3

VDDCMP I

(analog) PIO0_14 no 30 20 -

PIO0_5 no - - B3

I2C-bus interface

SCL I/O PIO0_2 50 ns[2] 15 10 A1

PIO0_12 no 46 31 E1

PIO0_16 10 ns[2] 18 13 A2

PIO0_24 no 9 7 -

SDA I/O PIO0_3 50 ns[2] 16 11 B1

PIO0_13 10 ns[2] 47 32 D1

PIO0_15 10 ns[2] 41 27 E4

PIO0_25 no 17 12 -

SSP0 controller

MISO0 I/O PIO0_6 10 ns[2] 32 21 C3

PIO0_22 10 ns[2] 27 17 -

PIO1_2 no 37 - -

MOSI0 I/O PIO0_4 10 ns[2] 28 18 A4

PIO0_19 no 14 9 -

PIO1_3 no 48 - -

PIO1_7 no 25 - -

SCK0 I/O PIO0_5 10 ns[2] 29 19 B3

PIO0_20 no 22 15 -

PIO1_0 no 31 - -

SSEL0 I/O PIO0_1 no 4 3 B2

PIO0_18 no 10 8 -

PIO1_1 no 36 - -

Table 3. Pin multiplexing

Function Type LQFP48 HVQFN33 WCSP20

Port Glitch filter Pin Pin Ball

Product data sheet Rev. 4 — 30 October 2012 10 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

SSP1 controller

MISO1 I/O PIO0_14 10 ns[2] 30 20 -

PIO0_26 no 1 1 -

PIO1_8 no 26 - -

MOSI1 I/O PIO0_27 10 ns[2] 43 28 -

PIO0_31 no 24 - -

PIO0_30 no 40 - -

PIO1_6 no 11 - -

SCK1 I/O PIO0_8 10 ns[2] 34 23 -

PIO1_5 no 20 - -

PIO0_29 no 13 - -

SSEL1 I/O PIO0_25 no 17 12 -

PIO1_4 no 19 - -

PIO0_28 no 2 - -

USART

RXD I PIO0_1 no 4 3 B2

PIO0_12 no 46 31 E1

PIO1_4 no 19 - -

PIO1_8 no 26 - -

TXD O PIO0_13 no 47 32 D1

PIO0_15 no 41 27 E4

PIO0_26 no 1 1 -

PIO1_5 no 20 - -

SCLK I/O PIO0_11 10 ns[2] 39 26 D2

PIO0_21 no 23 16 -

PIO0_23 no 45 30 -

CTS I PIO0_9 10 ns[2] 35 24 D4

PIO0_21 no 23 16 -

PIO1_7 no 25 - -

RTS O PIO0_10 no 38 25 D3

PIO0_23 no 45 30 -

PIO1_6 no 11 - -

DCD IPIO1_9no 12 - -

PIO1_0 no 31 - -

DSR I PIO0_29 no 13 - -

PIO1_2 no 37 - -

DTR O PIO0_28 no 2 - -

PIO1_1 no 36 - -

Table 3. Pin multiplexing

Function Type LQFP48 HVQFN33 WCSP20

Port Glitch filter Pin Pin Ball

Product data sheet Rev. 4 — 30 October 2012 11 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

RI I PIO0_30 no 40 - -

PIO0_31 no 24 - -

PIO1_3 no 48 - -

16-bit counter/timer CT1 6B0

CT16B0_CAP0 I PIO0_2 50 ns[2] 15 10 A1

PIO0_18 no 10 8 -

PIO0_30 no 40 - -

CT16B0_CAP1 I PIO0_16 10 ns[2] 18 13 A2

PIO1_4 no 19 - -

CT16B0_CAP2 I PIO0_17 10 ns[2] 21 14 A3

PIO1_5 no 20 - -

CT16B0_MAT0 O PIO0_7 no 33 22 C4

PIO0_17 no 21 14 A3

PIO1_6 no 11 - -

CT16B0_MAT1 O PIO0_4 no 28 18 A4

PIO0_9 no 35 24 D4

PIO1_0 no 31 - -

CT16B0_MAT2 O PIO0_5 no 29 19 B3

PIO0_10 no 38 25 D3

PIO1_7 no 25 - -

16-bit counter/timer CT1 6B1

CT16B1_CAP0 I PIO0_3 50 ns[2] 16 11 B1

PIO0_24 no 9 7 -

PIO1_3 no 48 - -

CT16B1_CAP1 I PIO0_18 no 10 8 -

PIO0_26 no 1 1 -

PIO0_31 no 24 - -

CT16B1_CAP2 I PIO0_27 10 ns[2] 43 28 -

PIO1_7 no 25 - -

CT16B1_MAT0 O PIO0_19 no 14 9 -

PIO0_25 no 17 12 -

PIO1_1 no 36 - -

CT16B1_MAT1 O PIO0_14 no 30 20 B4

PIO1_2 no 37 - -

PIO1_8 no 26 - -

CT16B1_MAT2 O PIO0_20 no 22 15 -

PIO1_2 no 37 - -

PIO1_9 no 12 - -

Table 3. Pin multiplexing

Function Type LQFP48 HVQFN33 WCSP20

Port Glitch filter Pin Pin Ball

Product data sheet Rev. 4 — 30 October 2012 12 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

32-bit counter/timer CT3 2B0

CT32B0_CAP0 I PIO0_11 10 ns[2] 39 26 D2

PIO0_23 no 45 30 -

PIO0_28 no 2 - -

CT32B0_CAP1 I PIO0_14 10 ns[2] 30 20 B4

PIO0_29 no 13 - -

CT32B0_CAP2 I PIO0_15 10 ns[2] 41 27 E4

PIO0_26 no 1 1 -

CT32B0_MAT0 O PIO0_12 no 46 31 E1

PIO0_30 no 40 - -

CT32B0_MAT1 O PIO0_13 no 47 32 D1

PIO1_4 no 19 - -

CT32B0_MAT2 O PIO0_1 no 4 3 B2

PIO1_5 no 20 - -

CT32B0_MAT3 O PIO0_6 no 32 21 C3

PIO1_6 no 11 - -

32-bit counter/timer CT3 2B1

CT32B1_CAP0 I PIO0_7 10 ns[2] 33 22 C4

PIO0_20 no 22 15 -

PIO1_4 no 19 - -

CT32B1_CAP1 I PIO0_21 no 23 16 -

PIO1_5 no 20 - -

CT32B1_CAP2 I PIO0_22 10 ns[2] 27 17 -

PIO1_6 no 11 - -

CT32B1_MAT0 O PIO0_8 no 34 23 C2

PIO0_31 no 24 - -

PIO1_8 no 26 - -

CT32B1_MAT1 O PIO0_9 no 35 24 D4

PIO0_27 no 43 28 -

PIO1_7 no 25 - -

CT32B1_MAT2 O PIO0_10 no 38 25 D3

PIO0_22 no 27 17 -

PIO1_9 no 12 - -

CT32B1_MAT3 O PIO0_11 no 39 26 D2

PIO1_1 no 36 - -

PIO1_0 no 31 - -

Supply and ground pin s

VDD(IO) Supply - - 8 6 E2

Table 3. Pin multiplexing

Function Type LQFP48 HVQFN33 WCSP20

Port Glitch filter Pin Pin Ball

Product data sheet Rev. 4 — 30 October 2012 13 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

[1] Always on.

[2] Programmable on/off. By default, the glitch filter is disabled.

Table 4 shows all pins in order of their port number. The default function after reset is

listed first. All port pins PIO0_0 to PIO1_9 have internal pull-up resistors enabled after

reset with the exception of the true open-drain pins PIO0_2 and PIO0_3.

Pull-up/pull-down configuration, repeater, and open-drain modes can be programmed

through the IOCON registers for each of the port pins.

VDD(3V3) Supply - - 44 29 E2

VSS Ground - - 42 33 E3

VSS(IO) Ground - - 5 33 E3

Table 3. Pin multiplexing

Function Type LQFP48 HVQFN33 WCSP20

Port Glitch filter Pin Pin Ball

Table 4. LPC11Axx pin description table

Symbol Pin/Ball Type Reset

state

[1]

Description

LQFP48

HVQFN33

WLCSP20

RESET/PIO0_0 3 2 C1 [2] II; PURESET — External reset input with fixed 20 ns glitch filter: A

LOW on this pin resets the device, causing I/O ports and

peripherals to take on their default states and processor

execution to begin at address 0.

I/O - PIO0_0 — General purpose digital input/output pin.

PIO0_1/RXD/CLKOUT/

CT32B0_MAT2/SSEL0/

CLKIN

43B2

[3] I/O I; PU PIO0_1 — General purpose digital input/output pin. A LOW

level on this pin during reset starts the ISP command handler.

I- RXD — Receiver data input for USART.

O- CLKOUT — Clock ou tput.

O- CT32B0_MAT2 — Match output 2 for 32-bit timer 0.

I/O - SSEL0 — Slave Select for SSP0.

I- CLKIN — External clock input.

PIO0_2/SCL/ACMP_O/

TCK/SWCLK/

CT16B0_CAP0

15 10 A1 [4][5] I/O I; IA PIO0_2 — General purpose digital input/output pin.

High-current sink (20 mA) or standard-current sink (4 mA)

programmable; true open-drain for all pin functions. Input

glitch filter (50 ns) capable.

I/O - SCL — I2C-bus clock (true open-drain) input/output. Input

glitch filter (50 ns) capable.

O- ACMP_O — Analog comparator output.

I- TCK/SWCLK — Serial Wire Debug Clock (secondary for

LQFP and HVQFN packages). Input glitch filter (50 ns)

capable. For the WLCSP20 package only, this pin is

configured to the SWCLK function by the boot loader after

reset.

I- CT16B0_CAP0 — Capture input 0 for 16-bit timer 0. Input

glitch filter (50 ns) capable.

Product data sheet Rev. 4 — 30 October 2012 14 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

PIO0_3/SDA/ACMP_O/

SWDIO/CT16B1_CAP0 16 11 B1 [4][6] I/O I; IA PIO0_3 — General purpose digital input/output pin.

High-current sink (20 mA) or standard-current sink (4 mA)

programmable; true open-drain for all pin functions. Input

glitch filter (50 ns) capable.

I/O - SDA — I2C-bus data (true open-drain) input/output. Input

glitch filter (50 ns) capable.

O- ACMP_O — Analog comparator output.

I/O - SWDIO — Serial Wire Debug I/O (secondary for LQFP and

HVQFN packages). Input glitch filter (50 ns) capable. For the

WLCSP20 package only, this pin is configured to the SWDIO

function by the boot loader after reset.

I- CT16B1_CAP0 — Capture input 0 for 16-bit timer 1. Input

glitch filter (50 ns) capable.

PIO0_4/R/AOUT/

CT16B0_MAT1/MOSI0 28 18 A4 [7] I/O I; PU PIO0_4 — General purpose digital input/output pin. Input

glitch filter (10 ns) capable.

-- R — Reserved.

O- AOUT — D/A converter output.

O- CT16B0_MAT1 — Match output 1 for 16-bit timer 0.

I/O - MOSI0 — Master Out Slave In for SSP0. Input glitch filter

(10 ns) capable.

TCK/SWCLK/PIO0_5/

R/CT16B0_MAT2/

SCK0

29 19 - [9] II; PUTCK/SWCLK — Test clock TCK for JTAG interface and

primary (default) Serial Wire Debug Clock. Input glitch filter (10

ns) capable.

I/O - PIO0_5 — General purpose digital input/output pin. Input

glitch filter (10 ns) capable.

-- R — Reserved.

O- CT16B0_MAT2 — Match output 2 for 16-bit timer 0.

I/O - SCK0 — Serial clock for SSP0. Input glitch filter (10 ns)

capable.

TCK/SWCLK/PIO0_5/

VDDCMP/

CT16B0_MAT2/

SCK0

--B3

[7][8] II; PUTCK/SWCLK — Test clock TCK for JTAG interface and

secondary Serial Wire Debug ClocK. Use PIO0_2 for the

default TCK/SWCLK function. Input glitch filter (10 ns)

capable.

I/O - PIO0_5 — General purpose digital input/output pin. Input

glitch filter (10 ns) capable.

I- VDDCMP — Analog comparator alternate reference voltage.

O- CT16B0_MAT2 — Match output 2 for 16-bit timer 0.

I/O - SCK0 — Serial clock for SSP0. Input glitch filter (10 ns)

capable.

Table 4. LPC11Axx pin description table

Symbol Pin/Ball Type Reset

state

[1]

Description

LQFP48

HVQFN33

WLCSP20

Product data sheet Rev. 4 — 30 October 2012 15 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

TDI/PIO0_6/AD0/

CT32B0_MAT3/MISO0 32 21 C3 [9] II; PUTDI — Test Data In for JTAG interface. Input glitch filter (10 ns)

capable.

I/O - PIO0_6 — General purpose digital input/output pin. Input

glitch filter (10 ns) capable.

I- AD0 — A/D converter input 0.

O- CT32B0_MAT3 — Match output 3 for 32-bit timer 0.

I/O - MISO0 — Master In Slave Out for SSP0. Input glitch filter

(10 ns) capable.

TMS/PIO0_7/AD1/

CT32B1_CAP0/

CT16B0_MAT0

33 22 C4 [9] II; PUTMS — Test Mode Select for JTAG interface. Input glitch filter

(10 ns) capable.

I/O - PIO0_7 — General purpose digital input/output pin. Input

glitch filter (10 ns) capable.

I- AD1 — A/D converter input 1.

I- CT32B1_CAP0 — Capture input 0 for 32-bit timer 1. Input

glitch filter (10 ns) capable.

O- CT16B0_MAT0 — Match output 2 for 16-bit timer 0.

TDO/PIO0_8/AD2/

CT32B1_MAT0/SCK1 34 23 C2 [9] OI; PUTDO — Test Data Out for JTAG interface.

I/O - PIO0_8 — General purpose digital input/output pin. Input

glitch filter (10 ns) capable.

I- AD2 — A/D converter input 2.

O- CT32B1_MAT0 — Match output 0 for 32-bit timer 1.

I/O - SCK1 — Serial clock for SSP1. Input glitch filter (10 ns)

capable.

TRST/PIO0_9/AD3/

CT32B1_MAT1/

CT16B0_MAT1/CTS

35 24 D4 [9] II; PUTRST — Test Reset for JTAG interface. Input glitch filter

(10 ns) capable.

I/O - PIO0_9 — General purpose digital input/output pin. Input

glitch filter (10 ns) capable.

I- AD3 — A/D converter, input 3.

O- CT32B1_MAT1 — Match output 1 for 32-bit timer 1.

O- CT16B0_MAT1 — Match output 1 for 16-bit timer 0.

I- CTS — Clear To Send input for USART. Input glitch filter

(10 ns) capable.

Table 4. LPC11Axx pin description table

Symbol Pin/Ball Type Reset

state

[1]

Description

LQFP48

HVQFN33

WLCSP20

Product data sheet Rev. 4 — 30 October 2012 16 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

SWDIO/PIO0_10/AD4/

CT32B1_MAT2/

CT16B0_MAT2/RTS

38 25 D3 [9] I/O I; PU SWDIO — Primary (default) Serial Wire Debug I/O for the

LQFP48 and HVQFN33 packages. For the WLCSP20

packa ge , use PIO0_3. Input gli tch fi lt er (1 0 ns) capable .

I/O - PIO0_10 — General purpo se digital input/output pin. Input

glitch filter (10 ns) capable.

I- AD4 — A/D converter, input 4.

O- CT32B1_MAT2 — Match output 2 for 32-bit timer 1.

O- CT16B0_MAT2 — Match output 2 for 16-bit timer 0.

O- RTS — Request To Send output for USART.

PIO0_11/SCLK/

AD5/CT32B1_MAT3/

CT32B0_CAP0

39 26 D2 [9] I/O I; PU PIO0_11 — General purpose digital input/output pin. Input

glitch filter (10 ns) capable.

I/O - SCLK — Serial clock for USART. Input glitch filter (10 ns)

capable.

I- AD5 — A/D converter, input 5.

O- CT32B1_MAT3 — Match output 3 for 32-bit timer 1.

I- CT32B0_CAP0 — Capture input 0 for 32-bit timer 0. Input

glitch filter (10 ns) capable.

PIO0_12/RXD/

ACMP_O/

CT32B0_MAT0/SCL/

CLKIN

46 31 E1 [3] I/O I; PU PIO0_12 — General purpose digital input/output pin.

I- RXD — Receiver data input for USART. This pin is used for

ISP communication.

O- ACMP_O — Analog comparator output.

O- CT32B0_MAT0 — Match output 0 for 32-bit timer 0.

I/O - SCL — I2C-bus clock input/output. This is not an I 2C-bus

open-drain pin[10].

I- CLKIN — External clock input.

PIO0_13/TXD/

ACMP_I2/

CT32B0_MAT1/SDA

47 32 D1 [9] I/O I; PU PIO0_13 — General purpo se digital input/output pin. Input

glitch filter (10 ns) capable.

O- TXD — Tra nsmitter data output for USART. This pin is used

for ISP communication.

I- ACMP_I2 — Analog comparator input 2.

O- CT32B0_MAT1 — Match output 1 for 32-bit timer 0.

I/O - SDA — I2C-bus data input/output. This is not an I2C-bus

open-drain pin[10]. Input glitch filter (10 ns) capable.

Table 4. LPC11Axx pin description table

Symbol Pin/Ball Type Reset

state

[1]

Description

LQFP48

HVQFN33

WLCSP20

Product data sheet Rev. 4 — 30 October 2012 17 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

PIO0_14/MISO1/AD6/

CT32B0_CAP1/

CT16B1_MAT1/

VDDCMP

30 20 - [7] I/O I; PU PIO0_14 — General purpose digital input/output pin. Input

glitch filter (10 ns) capable.

I/O - MISO1 — Master In Slave Out for SSP1. Input glitch filter

(10 ns) capable.

I- AD6 — A/D converter, input 6.

I- CT32B0_CAP1 — Capture input 1 for 32-bit timer 0. Input

glitch filter (10 ns) capable.

O- CT16B1_MAT1 — Match output 1 for 16-bit timer 1.

I- VDDCMP — Analog comparator alternate reference voltage.

PIO0_14/MISO1/AD6/

CT32B0_CAP1/

CT16B1_MAT1

--B4

[9] I/O I; PU PIO0_14 — General purpo se digital input/output pin. Input

glitch filter (10 ns) capable.

I/O - MISO1 — Master In Slave Out for SSP1. Input glitch filter

(10 ns) capable.

I- AD6 — A/D converter, input 6.

I- CT32B0_CAP1 — Capture input 1 for 32-bit timer 0. Input

glitch filter (10 ns) capable.

O- CT16B1_MAT1 — Match output 1 for 16-bit timer 1.

PIO0_15/TXD/AD7/

CT32B0_CAP2/SDA 41 27 E4 [9] I/O I; PU PIO0_15 — General purpose digital input/output pin. Input

glitch filter (10 ns) capable.

O- TXD — Transmitter data output for USART.

I- AD7 — A/D converter, input 7.

I- CT32B0_CAP2 — Capture input 2 for 32-bit timer 0. Input

glitch filter (10 ns) capable.

I/O - SDA — I2C-bus data input/output. This is not an I2C-bus

open-drain pin[10]. Input glitch filter (10 ns) capable.

PIO0_16/

ATRG0/ACMP_I3/

CT16B0_CAP1/SCL

18 13 A2 [9] I/O I; PU PIO0_16 — General purpose digital input/output pin. Input

glitch filter (10 ns) capable.

I- ATRG0 — Conversion trigger 0 for ADC or DAC. Input gl itch

filter (10 ns) capable.

I- ACMP_I3 — Analog comparator input 3.

I- CT16B0_CAP1 — Capture input 1 for 16-bit timer 0. Input

glitch filter (10 ns) capable.

I/O - SCL — I2C-bus clock input/output. This is not an I 2C-bus

open-drain pin[10]. Input glitch filter (10 ns) capable.

Table 4. LPC11Axx pin description table

Symbol Pin/Ball Type Reset

state

[1]

Description

LQFP48

HVQFN33

WLCSP20

Product data sheet Rev. 4 — 30 October 2012 18 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

PIO0_17/

ATRG1/ACMP_I4/

CT16B0_CAP2/

CT16B0_MAT0

21 14 A3 [9] I/O I; PU PIO0_17 — General purpose digital input/output pin. Input

glitch filter (10 ns) capable.

I- ATRG1 — Conversion trigger 1 for ADC or DAC. Input gl itch

filter (10 ns) capable.

I- ACMP_I4 — Analog comparator input 4.

I- CT16B0_CAP2 — Capture input 2 for 16-bit timer 0. Input

glitch filter (10 ns) capable.

O- CT16B0_MAT0 — Match output 0 for 16-bit timer 0.

PIO0_18/R/SSEL0/

CT16B0_CAP0/

CT16B1_CAP1

10 8 - [3] I/O I; PU PIO0_18 — General purpose digital input/output pin.

-- R — Reserved.

I/O - SSEL0 — Slave Select for SSP0.

I- CT16B0_CAP0 — Capture input 0 for 16-bit timer 0.

I- CT16B1_CAP1 — Capture input 1 for 16-bit timer 1.

PIO0_19/CLKIN/

CLKOUT/

MOSI0/CT16B1_MAT0

14 9 - [3] I/O I; PU PIO0_19 — General purpose digital input/output pin.

I- CLKIN — External clock input.

O- CLKOUT — Clock ou tput.

I/O - MOSI0 — Master Out Slave In for SSP0.

O- CT16B1_MAT0 — Match output 0 for 16-bit timer 1.

PIO0_20/R/SCK0/

CT32B1_CAP0/

CT16B1_MAT2

22 15 - [3] I/O I; PU PIO0_20 — General purpose digital input/output pin.

-- R — Reserved.

I/O - SCK0 — Serial clock for SSP0.

I- CT32B1_CAP0 — Capture input 0 for 32-bit timer 1.

O- CT16B1_MAT2 — Match output 2 for 16-bit timer 1.

PIO0_21/CTS/

ACMP_O/

CT32B1_CAP1/SCLK

23 16 - [3] I/O I; PU PIO0_21 — General purpose digital input/output pin. If

configured as output, this pin is a high-current source output

driver (20 mA).

I- CTS — Clear To Send input for USART.

O- ACMP_O — Analog comparator output.

I- CT32B1_CAP1 — Capture input 1 for 32-bit timer 1.

I/O - SCLK — Serial clock for USART.

PIO0_22/MISO0/

ACMP_I5/

CT32B1_MAT2/

CT32B1_CAP2

27 17 - [9] I/O I; PU PIO0_22 — General purpose digital input/output pin. Input

glitch filter (10 ns) capable.

I/O - MISO0 — Master In Slave Out for SSP0. Input glitch filter

(10 ns) capable.

I- ACMP_I5 — Analog comparator input 5.

O- CT32B1_MAT2 — Match output 2 for 32-bit timer 1.

I- CT32B1_CAP2 — Capture input 2 for 32-bit timer 1. Input

glitch filter (10 ns) capable.

Table 4. LPC11Axx pin description table

Symbol Pin/Ball Type Reset

state

[1]

Description

LQFP48

HVQFN33

WLCSP20

Product data sheet Rev. 4 — 30 October 2012 19 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

PIO0_23/RTS/

ACMP_O/

CT32B0_CAP0/SCLK

45 30 - [3] I/O I; PU PIO0_23 — General purpose digital input/output pin.

O- RTS — Request To Send output for USART.

O- ACMP_O — Analog comparator output.

I- CT32B0_CAP0 — Capture input 0 for 32-bit timer 0.

I/O - SCLK — Serial clock for USART.

PIO0_24/SCL/CLKIN/

CT16B1_CAP0 97- [3] I/O I; PU PIO0_24 — General purpose digital input/output pin.

I/O - SCL — I2C-bus clock input/output. This is not an I 2C-bus

open-drain pin[10].

I- CLKIN — External clock input.

I- CT16B1_CAP0 — Capture input 0 for 16-bit timer 1.

PIO0_25/SDA/SSEL1/

CT16B1_MAT0 17 12 - [3] I/O I; PU PIO0_25 — General purpose digital input/output pin.

I/O - SDA — I2C-bus data input/output. This is not an I2C-bus

open-drain pin[10].

I/O - SSEL1 — Slave Select for SSP1.

O- CT16B1_MAT0 — Match output 0 for 16-bit timer 1.

PIO0_26/TXD/MISO1/

CT16B1_CAP1/

CT32B0_CAP2

11- [3] I/O I; PU PIO0_26 — General purpo se digital input/output pin.

O- TXD — Transmitter data output for USART.

I/O - MISO1 — Master In Slave Out for SSP1.

I- CT16B1_CAP1 — Capture input 1 for 16-bit timer 1.

I- CT32B0_CAP2 — Capture input 2 for 32-bit timer 0.

PIO0_27/MOSI1/

ACMP_I1/

CT32B1_MAT1/

CT16B1_CAP2

43 28 - [9] I/O I; PU PIO0_27 — General purpose digital input/output pin. Input

glitch filter (10 ns) capable.

I/O - MOSI1 — Master Out Slave In for SSP1. Input glitch filter

(10 ns) capable.

I- ACMP_I1 — Analog comparator input 1.

O- CT32B1_MAT1 — Match output 1 for 32-bit timer 1.

I- CT16B1_CAP2 — Capture input 2 for 16-bit timer 1. Input

glitch filter (10 ns) capable.

PIO0_28/DTR/SSEL1/

CT32B0_CAP0 2- - [3] I/O I; PU PIO0_28 — General purpose digital input/output pin.

O- DTR — Data Terminal Ready output for USART.

I/O - SSEL1 — Slave Select for SSP1.

I- CT32B0_CAP0 — Capture input 0 for 32-bit timer 0.

PIO0_29/DSR/SCK1/

CT32B0_CAP1 13 - - [3] I/O I; PU PIO0_29 — General purpo se digital input/output pin.

I- DSR — Data Set Ready input for USART.

I/O - SCK1 — Serial clock for SSP1.

I- CT32B0_CAP1 — Capture input 1 for 32-bit timer 0.

Table 4. LPC11Axx pin description table

Symbol Pin/Ball Type Reset

state

[1]

Description

LQFP48

HVQFN33

WLCSP20

Product data sheet Rev. 4 — 30 October 2012 20 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

PIO0_30/RI/MOSI1/

CT32B0_MAT0/

CT16B0_CAP0

40 - - [3] I/O I; PU PIO0_3 0 — General purpose digital input/output pin.

I- RI — Ring Indicator input for USART.

I/O - MOSI1 — Master Out Slave In for SSP1.

O- CT32B0_MAT0 — Match output 0 for 32-bit timer 0.

I- CT16B0_CAP0 — Capture input 0 for 16-bit timer 0.

PIO0_31/RI/MOSI1/

CT32B1_MAT0/

CT16B1_CAP1

24 - - [3] I/O I; PU PIO0_3 1 — General purpose digital input/output pin.

I- RI — Ring Indicator input for USART.

I/O - MOSI1 — Master Out Slave In for SSP1.

O- CT32B1_MAT0 — Match output 0 for 32-bit timer 1.

I- CT16B1_CAP1 — Capture input 1 for 16-bit timer 1.

PIO1_0/DCD/SCK0/

CT32B1_MAT3/

CT16B0_MAT1

31 - - [3] I/O I; PU PIO1_0 — General purpose digital input/output pin.

I- DCD — Data Carrier Detect input for USART.

I/O - SCK0 — Serial clock for SSP0.

O- CT32B1_MAT3 — Match output 3 for 32-bit timer 1.

O- CT16B0_MAT1 — Match output 1 for 16-bit timer 0.

PIO1_1/DTR/SSEL0/

CT32B1_MAT3/

CT16B1_MAT0

36 - - [3] I/O I; PU PIO1_1 — General purpose digital input/output pin.

O- DTR — Data Terminal Ready output for USART.

I/O - SSEL0 — Slave Select for SSP0.

O- CT32B1_MAT3 — Match output 3 for 32-bit timer 1.

O- CT16B1_MAT0 — Match output 0 for 16-bit timer 1.

PIO1_2/DSR/MISO0/

CT16B1_MAT2/

CT16B1_MAT1

37 - - [3] I/O I; PU PIO1_2 — General purpose digital input/output pin.

I- DSR — Data Set Ready input for USART.

I/O - MISO0 — Master In Slave Out for SSP0.

O- CT16B1_MAT2 — Match output 2 for 16-bit timer 1.

O- CT16B1_MAT1 — Match output 1 for 16-bit timer 1.

PIO1_3/RI/MOSI0/

CT16B1_CAP0 48 - - [3] I/O I; PU PIO1_3 — General purpose digital input/output pin.

I- RI — Ring Indicator input for USART.

I/O - MOSI0 — Master Out Slave In for SSP0.

I- CT16B1_CAP0 — Capture input 0 for 16-bit timer 1.

PIO1_4/RXD/SSEL1/

CT32B0_MAT1/

CT32B1_CAP0/

CT16B0_CAP1

19 - - [3] I/O I; PU PIO1_4 — General purpose digital input/output pin.

I- RXD — Receiver data input for USART.

I/O - SSEL1 — Slave Select for SSP1.

O- CT32B0_MAT1 — Match output 1 for 32-bit timer 0.

I- CT32B1_CAP0 — Capture input 0 for 32-bit timer 1.

I- CT16B0_CAP1 — Capture input 1 for 16-bit timer 0.

Table 4. LPC11Axx pin description table

Symbol Pin/Ball Type Reset

state

[1]

Description

LQFP48

HVQFN33

WLCSP20

Product data sheet Rev. 4 — 30 October 2012 21 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

PIO1_5/TXD/SCK1/

CT32B0_MAT2/

CT32B1_CAP1/

CT16B0_CAP2

20 - - [3] I/O I; PU PIO1_5 — General purpose digital input/output pin.

O- TXD — Transmitter data output for USART.

I/O - SCK1 — Serial clock for SSP1.

O- CT32B0_MAT2 — Match output 2 for 32-bit timer 0.

I- CT32B1_CAP1 — Capture input 1 for 32-bit timer 1.

I- CT16B0_CAP2 — Capture input 2 for 16-bit timer 0.

PIO1_6/RTS/MOSI1/

CT32B0_MAT3/

CT32B1_CAP2/

CT16B0_MAT0

11 - - [3] I/O I; PU PIO1_6 — General purpose digital input/output pin.

O- RTS — Request To Send output for USART.

I/O - MOSI1 — Master Out Slave In for SSP1.

O- CT32B0_MAT3 — Match output 3 for 32-bit timer 0.

I- CT32B1_CAP2 — Capture input 2 for 32-bit timer 1.

O- CT16B0_MAT0 — Match output 0 for 16-bit timer 0.

PIO1_7/CTS/MOSI0/

CT32B1_MAT1/

CT16B0_MAT2/

CT16B1_CAP2

25 - - [3] I/O I; PU PIO1_7 — General purpose digital input/output pin.

I- CTS — Clear To Send input for USART.

I/O - MOSI0 — Master Out Slave In for SSP0.

O- CT32B1_MAT1 — Match output 1 for 32-bit timer 1.

O- CT16B0_MAT2 — Match output 2 for 16-bit timer 0.

I- CT16B1_CAP2 — Capture input 2 for 16-bit timer 1.

PIO1_8/RXD / MISO1/

CT32B1_MAT0/

CT16B1_MAT1

26 - - [3] I/O I; PU PIO1_8 — General purpose digital input/output pin.

I- RXD — Receiver data input for USART.

I/O - MISO1 — Master In Slave Out for SSP1.

O- CT32B1_MAT0 — Match output 0 for 32-bit timer 1.

O- CT16B1_MAT1 — Match output 1 for 16-bit timer 1.

PIO1_9/DCD/R/

CT32B1_MAT2 /

CT16B1_MAT2

12 - - [3] I/O I; PU PIO1_9 — General purpose digital input/output pin.

I- DCD — Data Carrier Detect input for USART.

-- R — Reserved.

O- CT32B1_MAT2 — Match output 2 for 32-bit timer 1.

O- CT16B1_MAT2 — Match output 2 for 16-bit timer 1.

XTALIN 6 4 - [11] - - Input to the oscillator circuit and internal clock generator

circuits. Input voltage must not exceed 1.8 V.

XTALOUT 7 5 - [11] - - Output from the oscillator amplifier.

VDD(IO) 86E2

[12]

[13] - - 3.3 V input/output supply voltage.

Table 4. LPC11Axx pin description table

Symbol Pin/Ball Type Reset

state

[1]

Description

LQFP48

HVQFN33

WLCSP20

Product data sheet Rev. 4 — 30 October 2012 22 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

[1] Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up resistor (weak PMOS device) enabled; IA = inactive, no

pull-up/down enabled.

[2] See Figure 32 for the reset configuration.

[3] 5 V tolerant pin providing standard digital I/O functions with configurable modes and configurable hysteresis (Figure 31).

[4] I2C-bus pins compliant with the I2C-bus specification for I2C standard mode, I2C Fast-mode, and I2C Fast-mode Plus.

[5] For the SWD function, a pull-up resistor is recommended for the SWCLK pin (WLCSP20 parts only).

[6] For the SWD function, a pull-up resistor is recommended for the SWDIO pin (WLCSP20 parts only).

[7] Not a 5 V tolerant pin due to special analog functionality. Pin provides standard digital I/O functions with configurable modes,

configurable hysteresis, and analog I/O. When configured as an analog I/O, the digital section of the pin is disabled (Figure 31).

[8] If this pin is configured for its VDDCMP function, it cannot be used for SWCLK when the part is on the board. The bypass filter of the

power supply filters out the SWCLK clock input signal.

[9] 5 V tolerant pin providing standard digital I/O functions with configurable modes, configurable hysteresis, and analog I/O. When

configured as an analog I/O, digital section of the pin is disabled, and the pin is not 5 V tolerant (Figure 31).

[10] I2C-bus pins are standard digital I/O pins and have limited performance and electrical characteristics compared to the full I2C-bus

specification. Pins can be configured with an on-chip pull-up resistor (pMOS device) and with open-drain mode. In this mode, typical bit

rates of up to 100 kbit/s with 20 pF load are supported if the internal pull-ups are enabled. Higher bit rates can be achieved with an

external resistor.

[11] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded

(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating. See Section 12.3 if an external clock is

connected to the XTALIN pin.

[12] If separate supplies are used for VDD(3V3) and V DD(IO), ensure that the power supply pins are filtered for noise with respect to their

corresponding grounds VSS and VSS(IO) (LQFP48 package). Using separate filtered supplies reduces the noise to the analog blocks (see

also Section 12.1).

[13] If separate supplies are used for VDD(3V3) and VDD(IO), ensure that the voltage dif ference between both supplies is smaller than or equal

to 0.5 V.

[14] Thermal pad (HVQFN33 pin package). Connect to ground.

VSS(IO) 533E3

[14] - - Ground.

VDD(3V3) 44 29 E2 [12]

[13] - - 3.3 V supply voltage to the analog blocks, internal regulator,

and internal clock generator circuits. Also used as the ADC

reference voltage.

VSS 42 33 E3 [14] - - Ground.

Table 4. LPC11Axx pin description table

Symbol Pin/Ball Type Reset

state

[1]

Description

LQFP48

HVQFN33

WLCSP20

Product data sheet Rev. 4 — 30 October 2012 23 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

7. Functional description

7.1 ARM Cortex-M0 processor

The ARM Cortex-M0 is a general purpose, 32-bit microprocessor, which offers high

performance and very low power consumption.

7.2 On-chip flash program memory

The LPC11Axx contain up to 32 kB of on-chip flash program memory.

7.3 On-chip EEPROM data memory

The LPC11Axx contain up to 4 kB of on-chip EEPROM data memory.

Remark: The top 64 bytes of the 4 kB EEPROM memory are reserved and cannot be

written to. The entire EEPROM is writable for smaller EEPROM sizes.

7.4 On-chip SRAM

The LPC11Axx contain a total of 8 kB, 4 kB, or 2 kB on-chip static RAM dat a memory.

7.5 On-chip ROM

The on-chip ROM contains the boot loader and the following Applicatio n Prog ra m min g

Interfaces (API):

•In-System Programming (ISP) and In-Application Programming (IAP) support for flash

programming

•Power profiles for configuring power consumption and PLL settings

•32-bit integer division routines

•I2C-bus driver routines

7.6 Memory map

The LPC11Axx incorporates several distinct memory regions, shown in the following

figures. Figure 5 shows the overall map of the entire address space from the user

program viewpoint following reset. The interrupt vector area supports address remapping.

The AHB peripheral are a is 2 M B in size, and is divided to allow for up to 128 peripherals.

The APB peripheral area is 512 kB in size and is divided to allow for up to 32 peripherals.

Each peripheral of either type is allocated 16 kB of space. This allows simplifying the

address decoding for each peripheral.

Product data sheet Rev. 4 — 30 October 2012 24 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

7.7 Nested Vectored Interrupt Controller (NVIC)

The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M0. The

tight coupling to the CPU allows for low interrupt latency and efficient processing of late

arriving interrupts.

7.7.1 Features

•Controls system exceptions and peripheral interrupts.

•In the LPC11Axx, the NVIC support s 32 vectored interrup ts includ ing up to 8 inputs to

the start logic from the individual GPIO pins.

Fig 5. LPC11Axx memory map

APB peripherals

0x4000 4000

0x4000 8000

0x4000 C000

0x4001 0000

0x4001 8000

0x4002 0000

0x4002 8000

0x4003 8000

0x4003 C000

0x4004 0000

0x4004 4000

0x4004 8000

0x4004 C000

0x4005 8000

0x4005 C000

0x4008 0000

0x4002 4000

0x4001 C000

0x4001 4000

0x4000 0000

WWDT

32-bit counter/timer 0

32-bit counter/timer 1

ADC

USART

C-bus

11 - 13 reserved

DAC

SSP0

SSP1

reserved

GPIO interrupts

reserved

25 - 31 reserved

0x4002 C000

analog comparator

reserved

0x0000 0000

0 GB

0.5 GB

4 GB

1 GB

0x1000 1800

0x1000 1000

0x1000 0800

0x1FFF 0000

0x1FFF 4000

0x2000 0000

0x4000 0000

0x4008 0000

0x5000 0000

0x5004 0000

0xFFFF FFFF

reserved

APB peripherals

GPIO

0x1000 0000

2 kB SRAM (LPC11Ax/001)

4 kB SRAM (LPC11Ax/101, LPC11A02))

6 kB SRAM (LPC11A1x/201)

0x1000 2000

8 kB SRAM (LPC11A1x/301, LPC11A04)

LPC11Axx

16 kB boot ROM

0x0000 0000

0x0000 00C0

active interrupt vectors

002aaf429

reserved

16-bit counter/timer 1

16-bit counter/timer 0

IOCONFIG

system control

0x4005 0000

0x4005 4000

GPIO GROUP0 INT

GPIO GROUP1 INT

flash/EEPROM controller

0x0000 2000

8 kB on-chip flash (LPC11A11)

0x0000 4000

0x0000 6000

16 kB on-chip flash (LPC11A12, LPC11A02)

0x0000 8000

32 kB on-chip flash (LPC11A14, LPC11A04)

24 kB on-chip flash (LPC11A13)

0xE000 0000

0xE010 0000

private peripheral bus

Product data sheet Rev. 4 — 30 October 2012 25 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

•Four programmable interrupt priority levels with hardware priority level masking.

•Software interrupt generation.

7.7.2 Interrupt sources

Each peripheral devi ce has one interrupt line con nected to the NVIC but may have several

interrupt flags. Individual interrupt flags may also represent more than one interrupt

source.

Up to eight GPIO pins, regardless of the selected function, can be programmed to

generate an interrupt on a level, or rising edge or falling edge, or both. The interrupt

generating GPIOs can be selected from the GPIO pins with a configurable input glitch

filter.

7.8 IOCON block

The IOCON block allows selected pins of the microcontroller to have more than one

function. Configuration registers control the multiplexers to allow connection between the

pin and the on-chip peripherals.

Peripherals should be conn ected to the appro priate pins prior to being activated and pr ior

to any related interrup t(s) being enabled. Activity of any enabled peripheral function that is

not mapped to a related pin should be considered undefined.

Up to 16 pins can be configured with a digital input glitch filter for removing voltage

glitches with widths of 10 ns or less (see Table 3 and Table 4), two pins (PIO0_2 and

PIO0_3) can be configured with a 50 ns digital input glitch filter.

7.9 Fast general purpose parallel I/O

Device pins that are not connected to a specific peripheral function are controlled by the

GPIO registers. Pins may be dynamica lly configured as input s or output s. Multiple output s

can be set or cleared in on e wr ite op e ratio n.

LPC11Axx use accelerate d GPIO func tio ns :

•GPIO registers are a dedicated AHB peripheral so that the fastest possible I/O timing

can be achieved .

•An entire port value can be written in one instruction.

Additionally, any GPIO pin (total of up to 42 pins) providing a digital function can be

programmed to generate an interrupt on a level, a rising or falling edge, or both.

7.9.1 Features

•Bit level port registers allow a single instruction to set and clear any number of bits in

one write operation.

•Direction control of individual bits.

•All I/O default to inputs with internal pull-up resistors enabled after reset - except for

the I2C-bus true ope n-drain pins PIO0_2 and PIO0_3.

•Pull-up/pull-down configuration, re peater, and open-drain modes can be programmed

through the IOCON block for each GPIO pin (see Figure 31 and Figure 32 for

functional diagrams).

Product data sheet Rev. 4 — 30 October 2012 26 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

•Control of the digital output slew rate allowing to switch more output s simultaneously

without degrading the power/ground distribution of the device.

7.10 USART

The LPC11Axx contains one USART.

Support for RS-4 85 /9 -b it mo d e allo ws bo th software addr ess detection and auto m at ic

address detection using 9-bit mode.

The USART includes a fractional baud rate generator. Standard baud rates such as

115200 Bd can be achieved with any crystal frequency above 2 MHz.

7.10.1 Features

•Maximum USART data bit rate of 3.125 MBit/s.

•16-byte Receive an d Transmit FIFOs.

•Register locations conform to 16C550 industry standard.

•Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.

•Built-in fractional baud rate generator covering wide range of baud rates without a

need for external crystals of particular values.

•FIFO control mechanism that enables software flow control implementation.

•Support for RS-4 85 /9 -b it mo d e.

•Supports a full modem contr ol ha nd sha k e int er fac e .

•Support for synchronous mode.

7.11 SSP serial I/O controller

The LPC11Axx contain two SSP controllers.

The SSP controller is capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can

interact with multiple masters and slaves on the bus. Only a sing le mas ter an d a sing le

slave can communicate on the bus during a given data transfer. The SSP supports full

duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the

slave and from the slave to the master. In practice, often only one of these data flows

carries meaningful data.

7.11.1 Features

•Maximum SSP speed of 25 Mbit/s (master) or 4.17 Mbit/s (slave) (in SPI mode)

•Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National

Semiconductor Microwire buses

•Synchronous serial communication

•Master or slave operation

•8-frame FIFOs for both transmit and receive

•4-bit to 16-bit frame

7.12 I2C-bus serial I/O controller

The LPC11Axx contains one I2C-bus controller.

Product data sheet Rev. 4 — 30 October 2012 27 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

The I2C-bus is bidirectional for inter-IC control using only two wires: a serial clock line

(SCL) and a serial data line (SDA). Each device is recognized by a unique address and

can operate as either a r eceiver-o nly device ( e.g., an LCD driver) or a tra nsmitter with the

capability to both receive and send information (such as memory). Transmitters and/or

receivers can oper ate in eithe r master or sl ave mo de, dependin g on wheth er the chip has

to initiate a data transfer or is only addressed. The I2C is a multi-master bus an d ca n be

controlled by more than one bus master connected to it.

Remark: On the WLCSP package, the boot loa d er configu re s th e op en - dr ain pins

(PIO0_2 and PIO 0_3 ) for the Serial Wire Debu g (SWD) function.

7.12.1 Features

•The I2C-interface is a standard I2C-bus compliant interface with open-drain pins

(PIO0_2 and PIO0_3). The I2C-bus interface also supports Fast-mode Plus with bit

rates up to 1 Mbit/s. For the I2C-bus specification, see UM10204.

•The true open-drain pins PIO0_2 and PIO0_3 can be configured with a 50 ns digital

input glitch filter.

•If the true open-dr ain pins are used for other purposes, a limite d-performance I2C-bus

interface can be configured from a choice of six GPIO pins configured in open-drain

mode and with a pull-up resistor. In this mode, typical bit rates of up to 100 kbit/s with

20 pF load are supported if the internal pull-ups are enabled. Higher bit rates can be

achieved with an external resistor.

•Fail-safe operation: When the power to an I2C-bus device is switched off, the SDA

and SCL pins connected to the I2C-bus are floating and do not disturb th e bu s.

•Easy to configure as master, slave, or master/slave.

•ROM-based I2C-bus driver routines to easily create applications.

•Programmable clocks allow versatile rate control.

•Bidirectional data transfer between masters and slaves.

•Multi-master bus (no central master).

•Arbitration between simultaneously transmitting masters without corruption of serial

data on the bus.

•Serial clock synchronization allows devices with different bit rates to communicate via

one serial bus.

•Serial clock synchronization can be used as a handshake mech anism to suspend and

resume serial transfer.

•The I2C-bus can be used for test and diagnostic purpose s.

•The I2C-bus controller support s multiple ad dress recognition and a bus monitor mode.

7.13 Configurable analog/mixed-signal subsystems

Multiple analog/mixed-signal subsystems can be configured by software from

interconnected digital and analog peripherals. See Figure 6.

Product data sheet Rev. 4 — 30 October 2012 28 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

7.14 10-bit ADC

The LPC11Axx contains one ADC. It is a si ngle 10-bit successive approximation ADC with

eight channels.

Fig 6. Configurable analog/mixed signal subsystem

aaa-003042

10-bit ADC

10-bit

DAC AOUT

ACMP_O

TRIG

32-bit TIMER

INTERRUPT

CONTROLLER

VOLTAGE

DIVIDER REF

SIGNAL LEGEND:

CONFIGURABLE ANALOG/MIXED-SIGNAL SUBSYSTEM

AD[7:0]

ATRG[1:0]

VDD(3V3)

VDDCMP

ACMP_I[5:1]

analog

ANALOG

COMPARATOR

ARM

CORTEX-M0

digital

0.9 V VOLTAGE

REFERENCE

TEMPERATURE

SENSOR

TRIG

MATCAP

16-bit TIMER

EDGE DETECT

MATCAP

Product data sheet Rev. 4 — 30 October 2012 29 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

7.14.1 Features

•10-bit successive approximation ADC.

•Input multiplexing among 8 pins.

•Power-down mode.

•Measurement range 0 V to VDD(3V3).

•10-bit conver sio n time  2.44 s (up to 400 kSamples/s).

•Burst conversion mode for single or multiple inputs.

•Optional conversion on transition of input pins ATRG0 or ATRG1, timer match signal,

or comparator output. (Input signals must be held for a minimum of three system clock

periods). Also see Section 12.2.

•Individual result registers for each ADC channel to reduce interrupt overhead.

7.15 Internal voltage reference

The internal volt age reference is an accurate 0.9 V and is the output of a low voltage band

gap circuit. A typical value at Tamb = 25 C is 0.903 V and varie s typically only 3 mV over

the 0 C to 85 C temperature range (see Table 21 and Figure 27). The internal voltage

reference can be used in the following applications:

Fig 7. ADC block diagram

INPUT

MUX

10-bit ADC

aaa-003043

comparator

AD7

IOCONFIG

AD5

AD6

AD0

ADC control

INTERNAL

VOLTAGE REFERENCE

TEMPERATURE

SENSOR to

comparator

IOCONFIG

SENSOR

ADC

Product data sheet Rev. 4 — 30 October 2012 30 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

•When the supply voltage VDD(3V3) is known accurately, the internal voltage reference

can be used to reduce the offset error EO of the ADC code output. The ADC error

correction then increases the accuracy of temperature sensor voltage output

measurements.

•When the ADC is accurately calibrated, the internal voltage reference can be used to

measure the power supply voltage. This requires calibration by recording the ADC

code of the internal voltage reference at different power supply levels yielding a

diff eren t ADC code value for ea ch supply volt age level. In a par ticul ar application, th e

internal voltage reference can be measured and the actual power supply voltage can

be determined fr om the stored calibration valu es. The calibration values can be stored

in the EEPROM for easy access.

After power-up and after switching the input channels of the ADC or the comparator, the

internal voltage reference must be allowed to settle to its stable value befo re it can be

used as an ADC reference voltage input. Settling times are given in Table 21.

For an accurate measurement of the internal voltage reference by the ADC, the ADC must

be configured in single-chan nel burst mode. The last value of a nin e-conversion (or mo re)

burst provides an accurate result.

7.16 Temperature sensor

The temperature sensor transducer uses an intrinsic pn-junction diode reference and

outputs a CTAT voltage (Complement To Absolute Temperature). The output voltage

varies inversely with device temperature with an absolute acc urac y of bette r than 3 C

over the full temperature range (40 C to +85 C). The temperature sensor is only

approximately linear with a slight curvature. The output voltage is measured over different

ranges of temperature s and fit with linear- least-squa re lines. Se e Table 23 and Figure 28.

For a volt age to temp erature conv ersion, the te mperature for a given vo ltag e is calculated

using the parameters of th e line ar -lea st- sq ua re line (s ee Table 23).

After power-up and after switching the input channels of the ADC or the comparator, the

temperature sensor output must be allowed to settle to its stable value before it can be

used as an accurate ADC input. Settling times are given in Table 22.

For an accurate measurement of the temperature sensor by the ADC, the ADC must be

configured in single-channel burst mode. The last value of a nine-conversion (or more)

burst provides an accurate result.

7.17 10-bit DAC

The DAC allows generation of a variable, rail-to-rail analog output.

Product data sheet Rev. 4 — 30 October 2012 31 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

7.17.1 Features

•10-bit DAC.

•Resistor string architecture.

•Buffered output.

•Power-down mode.

•Conversion speed controlled via a programmable bias current.

•Optional output update modes:

–write operation s to the DAC re gis te r.

–a transition of pins ATRG0 or ATRG1. Input signals mu st be held fo r a mini mum of

three system clock periods.

–a timer match signal.

–a comparator output signal held for a minimum of two system clock periods.

•Holds output value during Sleep mode if the DAC is not powered down.

7.18 Analog comparator

The analog comp arator with select able hysteresis can compa re volt age levels o n external

pins and internal voltages. See Table 24.

After po wer- up and after switching the input channels of the comparator, the output of the

voltage ladder must be allowed to settle to its stable value before it can be used as a

comparator reference input. Settling times are given in Table 25.

Fig 8. DAC block diagram

10 10

DAC

INPUT

D/A

CONVERTER

CONTROL

AND DATA

APB REGISTERS

analog comparator output

ATRG1

ATRG0

CT16B1_MAT1

CT16B1_MAT0

CT32B1_MAT1

CT32B1_MAT0

AOUT

aaa-003044

Product data sheet Rev. 4 — 30 October 2012 32 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

7.18.1 Features

•Selectable 0 mV, 10 mV ( 5 mV), and 20 mV ( 10 mV), 40 mV ( 20 mV) input

hysteresis.

•Five selectable external voltages; fully configurable on either positive or negative

input channel.

•Internal volt age reference fr om band gap and temperature sensor selectab le on either

positive or negative input channel.

•32-stage voltage ladder with the internal reference voltage selectable on either the

positive or the negative input channel. See Table 24 to Table 26.

•Voltage ladder source voltage is selectable from an external pin or the main 3.3 V

supply voltage rail.

•Voltage ladder can be separately powered down for applications only requirin g the

comparator function.

•Interrupt output is connected to NVIC.

•Comparator level output is connected to output pin ACMP_O.

•Comparator output is internally connected to the ADC and DAC and can be used to

trigger a conversion.

•The comparator output is also connected internally to capture channel 3 on each of

the 32-bit and 16- bit co un te r/ tim er s.

Fig 9. Comparator bloc k dia g ram

ACMPI[5:1]

VDDCMP

internal

voltage

reference

edge detect

sync

comparator

level

to ADC and DAC

comparator

edge

COMPARATOR ANALOG BLOCK COMPARATOR DIGITAL BLOCK

aaa-003045

temperature

sensor

Product data sheet Rev. 4 — 30 October 2012 33 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

7.19 General purpose external event counter/timers

The LPC11Axx includes two 32-bit counter/timers and two 16-bit counter/timers. The

counter/timer is designed to count cycles of the system derived clock. It can optionally

generate interrupts or perform other actions at specified timer values, based on four

match registers. Each counter/timer also includes four capture inputs to trap the timer

value when an input signal transitions, optionally generating an interrupt.

7.19.1 Features

•A 32-bit/16-bit timer/counter with a programmable 32-bit/16-bit prescaler.

•Counter or timer op er a tion .

•Four capture channels pe r timer, that can take a snapshot of the timer value when an

input signal tran sitio n s. A capt ur e ev en t ma y also gene ra te an int erru pt . U p to thre e

capture channels are pinned out. One channel is internally connected to the

comparator output ACMP_O.

•Four match registers per timer tha t allow:

–Continuous operation with optional interrupt generation on match.

–Stop timer on match with optional interr upt generation.

–Reset timer on match with optional interrupt generation.

•Up to four external outputs corresponding to match registers, with the following

capabilities:

–Set LOW on match.

–Set HIGH on match.

–Toggle on match.

–Do nothing on match.

7.20 System tick timer

The ARM Cortex-M0 includes a system tick timer (SYSTICK) that is intended to generate

a dedicated SYSTICK exc ep tion at a fixed time interval (typically 10 ms).

7.21 Wi ndowed WatchDog Timer (WWDT)

The purpose of the watchdog is to reset the controller if sof tware fails to periodically

service it within a programmable time window.

7.21.1 Features

•Internally resets chip if not periodically reloaded during the programmable time-out

period.

•Optional windowed operation requires reload to occur between a minimum and

maximum time period, both programmable.

•Optional warning interrupt can be generated at a progr ammable time prior to

watchdog time-out.

•Enabled by soft ware but requires a har dware reset or a watchdog reset/interrupt to be

disabled.

•Incorrect feed sequence causes reset or interrupt if enabled.

Product data sheet Rev. 4 — 30 October 2012 34 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

•Flag to indicate watchdog reset.

•Programmable 24-bit timer with internal prescaler.

•Selectable time period from (Tcy(WDCLK) 256 4) to (Tcy(WDCLK) 224 4) in

multiples of Tcy(WDCLK) 4.

•The W atchdog Clock (WDCLK) source can be selected from the internal RC oscillator

(IRC), or the dedicated watchdog oscillator (WDOsc). This gives a wide range of

potential timing choices of watchdog operation under different power conditions.

7.22 Clocking and power control

7.22.1 Crystal and internal oscillators

The LPC11Axx include four independent oscillators.

1. The crystal oscillator (SysOsc) operating at frequencies between 1 MHz and 25 MHz.

2. The internal RC Oscillator (IRC) with a fixed frequency of 12 MHz, trimmed to 1%

accuracy.

3. The internal low-power, Low-Frequency Oscillator (LFOsc) with a prog rammable

nominal frequency between 9.4 kHz and 2.3 MHz with 40% accuracy.

4. The dedicated Watchdog Oscillator (WDOsc) with a programmable nominal

frequency betwe e n 9. 4 kH z an d 2.3 MH z wi th 40 % acc ur ac y.

Each oscillator , except the WDOsc, can be used for more than one purpose as required in

a particular application.

Following reset, the LPC11Axx will operate from the IRC until switched by software. This

allows systems to operate without an y external crystal and the bootloader code to ope rate

at a known frequency.

See Figure 10 for an overview of the LPC11Axx clock generation.

Product data sheet Rev. 4 — 30 October 2012 35 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

7.22.1.1 Internal RC Oscillator (IRC)

The IRC may be used as the clock source for the WWDT, and/or as the clock that drives

the PLL and subsequently the CPU. The nominal IRC frequency is 12 MHz. The IRC is

trimmed to 1 % accuracy over the entire voltage and temperature range.

The IRC can be used as a clock source for the CPU with or without using the PLL. The

IRC frequency can be boosted to a higher frequency, up to the maximum CPU operating

frequency, by the system PLL .

Upon power-up or any chip reset, the LPC11Axx use the IRC as the clock source.

Software may later switch to one of the other available clock sources.

7.22.1.2 Crystal Oscillator (SysOsc)

The crystal oscillator can be used as the clock source for the CPU, with or without using

the PLL.

The SysOsc operates at freque ncies of 1 MHz to 25 MHz. This frequen cy can be boosted

to a higher frequency, up to the maximum CPU operating frequency, by the system PLL.

Fig 10. LPC11Axx clock generation block diagram

SYSTEM PLL

IRC

SysOsc

WDOsc

IRC

LFOsc

MAINCLKSEL

(main clock select)

SYSPLLCLKSEL

(system PLL clock select)

SYSTEM CLOCK

DIVIDER

system

SYSCLKCTRL[1:18]

memories

and peripherals

SSP0 PERIPHERAL

CLOCK DIVIDER SSP0

SSP1 PERIPHERAL

CLOCK DIVIDER SSP1

USART PERIPHERAL

CLOCK DIVIDER USART

WWDT CLOCK

DIVIDER WWDT

WDCLKSEL

LFOsc

IRC

SysOsc CLKOUT PIN CLOCK

DIVIDER CLKOUT pin

CLKOUTUEN

(CLKOUT update enable)

002aaf430

main clock

system clock

IRC

CLKIN

Product data sheet Rev. 4 — 30 October 2012 36 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

7.22.1.3 Internal Low-Frequency Oscillator (LFOsc) and Watchdog Oscillator (WDOsc)

The LFOsc and the WDOsc are identical internal oscillators. The nominal frequency is

programmable between 9.4 kHz and 2.3 MHz. The frequency spread over silicon process

variations is 40%.

The WDOsc is a dedicated oscillator for the windowed WWDT.

The LFOsc can be used as a clock source that directly drives the CPU or the CLKOUT

pin.

7.22.2 Clock input

A 3.3 V external clock source (25 MHz typical) can be supplied on the selected CLKIN pin

or a 1.8 V external clock source can be supplied on the XTALIN pin (see Section 12.3).

7.22.3 System PLL

The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input

frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO).

The multiplier can be an integer value from 1 to 32. The CCO operates in the range of

156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within

its frequency range while the PLL is providing the desired output frequency. The output

divider may be set to divide by 2, 4, 8, or 16 to produce th e ou tp ut clock . Since the

minimum output divider value is 2, it is insured that the PLL output has a 50 % duty cycle.

The PLL is turned off and bypassed following a chip reset and may be enabled by

software. The program must conf igure and activate the PLL, wait for the PLL to lock, and

then connect to the PLL as a clock source. The PLL settling time is 100 s.

7.22.4 Clock output

The LPC11Axx features a clock output functio n that routes the IRC, the SysOsc, the

LFOsc, or the main clock to an output pin.

7.22.5 Wake-up process

The LPC11Axx begin operation at power-up by using the IRC as the clock source. This

allows chip operation to resume quickly. If the SysOsc, the external clock source, or the

PLL is needed by the application, sof tware will need to enable these features and wait for

them to stabilize before they are used as a clock source.

7.22.6 Power control

The LPC11Axx supports the ARM Cortex-M0 Sleep mode. The CPU clock rate may also

be controlled as needed by changing clock sources, reconfiguring PLL values, and/or

altering the CPU clock divider value. This allows a trade-off of power versus processing

speed based on application requirements. In addition, a register is provided for shutting

down the clocks to individual on-chip periphe rals, allowing fine tuning of power

consumption by eliminating all dynamic power use in any pe ripherals that are not required

for the application. Selecte d peri pherals have their own clock divider which provides even

better power control.

7.22.6.1 Sleep mode

When Sleep mode is entered, the clock to the core is stoppe d. Resumption from the Sleep

mode does not need any special sequence but re-enabling the clock to the ARM core.

Product data sheet Rev. 4 — 30 October 2012 37 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

In Sleep mode, execution of instructions is suspended until either a reset or interrupt

occurs. Peripheral functions continue operation during Sleep mode and may generate

interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic

power used by the processor itself, memory systems and related controllers, and internal

buses.

7.22.6.2 Power profiles

The power consumption in Active and Sleep modes can be optimized for the application

through simple calls to the power profile. The power configuration routine configures the

LPC11Axx for one of the following power modes:

•Default mode corresponding to power configuration after reset.

•CPU performance mode corresponding to optimized processing capability.

•Efficie ncy mode corresponding to optimi zed balance of current consumption and CPU

performance.

•Low-current mode corresponding to lowest power consumption.

In addition, the power profile includes routines to select the optimal PLL settings for a

given system clock and PLL input clock.

7.23 System control

7.23.1 UnderVoltage LockOut (UVLO) protection

The BOD and POR circuits remain enab le d at all tim es to provid e UVL O pr ot ection from

an unexpected power supply droop below a typical threshold level of 2.4 V (see also the

LPC11A xx us er manu al ). UVLO protection means that the LPC11Axx is held in reset

whenever the supply voltage falls below 2.4 V.

See also Section 10.1 “Power supply fluctuations”, Section 12.7 “UVLO protection and

reset timer circuit”, and Section 12.8 “Guidelines for selecting a power supply filter for

UVLO protectio n ”.

7.23.2 Reset

Reset has several sources on the LPC11Axx: the RESET pin, the Wa tchdog reset,

power-on reset (POR), the ARM SYSRESETREQ software request, and the Brown-Out

Detection (BOD) circuit. After the BOD and th e POR resets are released, the internal reset

timer counts for 100 μs until the internal reset is removed.

Assertion of chip reset by any source (after the operating voltage attains a usable level)

starts the IRC and initializes the flash memory controller.

When the internal Reset is removed, the processor begins executing at address 0, which

is initially the Reset vector mapped from the boot block. At that point, all of the processor

and peripheral registers have been initialized to predetermined values.

Writing to a specia l function re gister allows the sof tware to reset the following peripherals:

the I2C-bus interface, the USART, both SSP controllers, the four counter/timers, the

comparator, the ADC, and th e DAC.

The RESET pin is a Schmitt trigger input pin and uses a special pad. See Figure 32.

Product data sheet Rev. 4 — 30 October 2012 38 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

7.23.3 Brown-out detection

The LPC11Axx include two programmable levels for monitoring the voltage on the

VDD(3V3) pin. If this voltage falls below the selected level, the BOD asserts an interrupt

signal to the NVIC. This signal can be enabled for interrupt in the Interrupt Enable

the signal by reading a dedicated status register. In addition, the BOD circuit support s one

hardware controlled voltage level for triggering a chip reset.

7.23.4 Code security (Code Read Protection - CRP)

This feature of the LPC11Axx allows user to enable different levels of security in the

system so that access to the on-chip flash and use of the Serial Wire Debugger (SWD)

and In-System-Programming (ISP) can be restricted. When needed, CRP is invoked by

programming a specific pattern into a dedicated flash location. IAP commands are not

affected by the CRP.

In addition, ISP entry via the PIO0_1 pin can be disabled without enabling CRP. For

details see the LPC11Axx user manual.

There are three levels of Code Read Protection:

1. CRP1 disables access to the chip via the SWD and allows partial flash update

(excluding flash sector 0) using a limited set of the ISP commands. This mode is

useful when CRP is required and flash field updates are needed but all sectors can

not be erased.

2. CRP2 disables access to the chip via the SWD and only allows full flash erase and

update using a reduced set of the ISP commands.

3. Running an application with level CRP3 selected fully disables any access to the chip

via the SWD pins and the ISP. This mode effectively disables ISP override using

PIO0_1 pin, too. It is up to the user’s application to provide (if needed) flash update

mechanism using IAP calls or call reinvoke ISP command to enable flash update via

the USART.

In addition to the three CRP levels, sampling of pin PIO0_1 for valid user code can be

disabled. For details see the LPC11Axx user manual.

7.23.5 APB interface

The APB peripherals are located on one APB bus.

7.23.6 AHBLite

The AHBLite connects the CPU bus of the ARM Cortex-M0 to the flash memory, the main

static RAM, and the Boot ROM.

CAUTION

If level three Code Read Protection (CRP3) is selected, no future factory testing can be

performed on the device.

Product data sheet Rev. 4 — 30 October 2012 39 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

7.23.7 External interrupt inputs

All GPIO pins can be level or edge sensitive interrupt inputs.

7.24 Emulation and debugging

Debug functions are integrated into the ARM Cortex-M0. JTAG and Serial Wire Debug

(SWD) with four breakpoints and two watchpoints are supported.

The RESET pin selects between the JTAG boundary scan (RESET = LOW) and the ARM

SWD debug (RESET = HIGH). The ARM SWD debug port is disabled while the

LPC11Axx is in reset.

To perform boundary scan testing, follow these steps:

1. Erase any user code residing in flash.

2. Power up the part with the RESET pin pulled HIGH externally.

3. Wait for at least 250 s.

4. Pull the RESET pin LOW externally.

5. Perform boundary scan operations.

6. Once the boundary scan operations are completed, assert the TRST pin to enable the

SWD debug mode and release the RESET pin (pull HIGH).

Remark: The JTAG interface cannot be used for debug purposes.

On the WLCSP package, the TCK signal is shared with the VDDCMP input on pin

PIO0_5. To perform a boundary scan on a bla nk device, ma ke sure th at the PIO0_5 pi n is

not filtered on the board. The bypass filter usually added to the comparator voltage

reference input (VDDCMP) filters out the SWCLK/TCK input signal.

For SWD debug, an alte rnative TCK/SWCLK clock pin is available on pin PIO0_2. This is

the default function after booting for the WLCSP package.

Product data sheet Rev. 4 — 30 October 2012 40 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

8. Limiting values

[1] The following applies to the limiting values:

a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive

static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated

maximum.

b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless

otherwise noted.

[2] Maximum/minimum voltage above the maximum operating voltage (see Table 6) and below ground that can be applied for a short time

(< 10 ms) to a device without leading to irrecoverable failure. Failure includes the loss of reliability and shorter lifetime of the device.

[3] Applies to all 5 V tolerant I/O pins except true open-drain pins PIO0_2 and PIO0_3 and except the 3 V tolerant pins PIO0_4 and

PIO0_14 (LQFP and HVQFN packages) or PIO0_5 (WLCSP package).

Table 5. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).[1]

Symbol Parameter Conditions Min Max Unit

VDD(3V3) supply voltage (3.3 V) [2] 0.5 4.6 V

VDD(IO) input/output supply voltage [2] 0.5 4.6 V

VIinput voltage 5 V tol erant I/O

pins; only valid

when the VDD(IO)

supply voltage is

present

[3][4] 0.5 +5.5 V

on pins PIO0_2

and PIO0_3 [5] 0.5 +5.5 V

3 V tolerant I/O

pins without

over-voltage

protection

[6] 0.5 +3.6 V

VIA analog input voltage [7][8]

[9] 0.5 V 4.6 V

Vi(xtal) crystal input voltage [2] 0.5 +2.5 V

IDD supply current per supply pin - 100 mA

ISS ground current per ground pin - 100 mA

Ilatch I/O latch-up current (0.5VDD(IO)) < VI <

(1.5VDD(IO));

Tj < 125 C

- 100 mA

Tstg storage temperature [10] 65 +150 C

Tj(max) maximum junction temperature - 150 C

Ptot(pack) total power dissipation (per package) based on package

heat transfer, not

device power

consumption

-1.5W

Vesd electrostatic discharge voltage human body

model; all pins [11] 6.5 +6.5 kV

Vtrig trigger voltage for LVTSCR based

ESD pin protection;

1 ns to 10 ns rise

time

[12] 8.2 - V

10 ns rise time 8.5 - V

Product data sheet Rev. 4 — 30 October 2012 41 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

[4] Including the voltage on outputs in 3-state mode.

[5] VDD(IO) present or not present. Compliant with the I2C-bus standard. 5.5 V can be applied to this pin when VDD(IO) is powered down.

[6] Applies to 3 V tolerant pins PIO0_4 and PIO0_14 (LQFP and HVQFN packages) or PIO0_5 (WLCSP package).

[7] An ADC input voltage above 3.6 V can be applied for a short time without leading to immediate, unrecoverable failure. Accumulated

exposure to elevated voltages at 4.6 V must be less than 106 s total over the lifetime of the device. Applying an elevated voltage to the

ADC inputs for a long time affects the reliability of the device and reduces its lifetime.

[8] If the comparator is configured with the common mode input VIC = VDD, the other comparator input can be up to 0.2 V above or below

VDD without affecting the hysteresis range of the comparator function.

[9] It is recommended to connect an overvoltage protection diode between the analog input pin and the voltage supply pin.

[10] Dependent on package type.

[11] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor.

[12] Not characterized.

Product data sheet Rev. 4 — 30 October 2012 42 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

9. Static characteristics

Table 6. Static characteristics

Tamb =





C to +85



C, unless otherwise specified.

Symbol Parameter Conditions Min Typ[1] Max Unit

VDD(3V3) supply voltage (3.3 V) 2.6 3.3 3.6 V

VDD(IO) input/output supply

voltage 2.6 3.3 3.6 V

IDD supply current Active mode; code

while(1){}

executed from flash;

VDD(3V3) = VDD(IO) = 3.3 V;

low-current mode (see

Section 7.22.6.2)

system clock = 12 MHz;

all peripherals disabled [2][4][5] -3-mA

system clock = 48 MHz;

all peripherals disabled [2][6][5] -8-mA

Sleep mode;

system clock = 12 MHz;

VDD(3V3) = VDD(IO) = 3.3 V;

low-current mode (see

Section 7.22.6.2)

all peripherals disabled;

12 MHz [2][4][5] -2-mA

all peripherals disabled;

48 MHz [2][4][5] -5-mA

Standard port pins, RESET

IIL LOW-level input current VI= 0 V; on-chip pull-up

resistor disabled - 0.5 1000 nA

IIH HIGH-level input

current VI=V

DD(IO); on-chip

pull-down resistor

disabled

- 0.5 1000 nA

IOZ OFF-state output

current VO=0V; V

O=V

DD(IO);

on-chip pull-up/down

resistors disabled

- 0.5 1000 nA

VIinput voltage pin configured to provide

a digital function

5 V tolerant pins

[7][8] 0- 5.0V

3 V tolerant pins:

PIO0_4 and PIO0_14

(LQFP and HVQFN

packages) or PIO0_5

(HVQFN package)

[7][8] VDD(IO)

VOoutput voltage output active 0 - VDD(IO) V

VIH HIGH-level input

voltage 0.7VDD(IO) --V

VIL LOW-level input volta ge - - 0.3VDD(IO) V

Vhys hysteresis voltage 3.0 V  VDD(IO) 3.6 V 0.4 - - V

Product data sheet Rev. 4 — 30 October 2012 43 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

VOH HIGH-level output

voltage 2.6 V  VDD(IO) 3.6 V;

IOH =4 mA 0.85VDD(IO) --V

VOL LOW-level output

voltage 2.6 V  VDD(IO) 3.6 V;

IOL =4 mA --0.15V

DD(IO) V

IOH HIGH-level output

current VOH =V

DD(IO) 0.4 V;

2.6 V  VDD(IO) 3.6 V

4--mA

IOL LOW-level output

current VOL =0.4V

2.6 V  VDD(IO) 3.6 V 4--mA

IOHS HIGH-level short-circuit

output current VOH =0V [9] --45 mA

IOLS LOW-level short-circuit

output current VOL =V

DD(IO) [9] --50mA

Ipd pull-down current VI=5V [10] 10 50 150 A

Ipu pull-up current VI=0V;

2.6 V  VDD(IO) 3.6 V

15 50 85 A

VDD(IO) <V

I<5V 000A

High-drive output pin (PIO0_21)

IIL LOW-level input current VI= 0 V; on-chip pull-up

resistor disabled - 0.5 10 nA

IIH HIGH-level input

current VI=V

DD(IO); on-chip

pull-down resistor

disabled

- 0.5 10 nA

IOZ OFF-state output

current VO=0V; V

O=V

DD(IO);

on-chip pull-up/down

resistors disabled

- 0.5 10 nA

VIinput voltage pin configured to provide

a digital function [7][8] 0- 5.0V

VOoutput voltage output active 0 - VDD(IO) V

VIH HIGH-level input

voltage 0.7VDD(IO) --V

VIL LOW-level input volta ge - - 0.3VDD(IO) V

Vhys hysteresis voltage 0.4 - - V

VOH HIGH-level output

voltage 2.6 V  VDD(IO) 3.6 V;

IOH =20 mA VDD(IO) 

0.4 --V

2.6 V  VDD(IO)  2.5 V;

IOH =12 mA VDD(IO) 

0.4 --V

VOL LOW-level output

voltage 2.6 V  VDD(IO) 3.6 V;

IOL =4 mA --0.4V

IOH HIGH-level output

current VOH =V

DD(IO) 0.4 V;

2.6 V  VDD(IO) 3.6 V 20--mA

IOL LOW-level output

current VOL =0.4V

2.6 V  VDD(IO) 3.6 V 4--mA

Table 6. Static characteristics …continued

Tamb =





C to +85



C, unless otherwise specified.

Symbol Parameter Conditions Min Typ[1] Max Unit

Product data sheet Rev. 4 — 30 October 2012 44 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages.

[2] Tamb =25C.

[3] IDD measurements were performed with all pins configured as GPIO outputs driven LOW and pull-up resistors disabled.

[4] IRC enabled; SysOsc disabled; system PLL disabled.

[5] All digital peripherals disabled in the SYSCLKCTRL register except ROM, RAM, and flash. Peripheral clocks to USART and SSP0/1

disabled in system configuration block. Analog peripherals disabled in the PDRUNCFG register except flash memory.

[6] IRC disabled; SysOsc enabled; system PLL enabled.

[7] Including voltage on outputs in 3-state mode.

[8] All supply voltages must be present.

[9] Allowed as long as the current limit does not exceed the maximum current allowed by the device.

[10] Does not apply to 3 V tolerant pins PIO0_4 and PIO0_14 (LQFP and H VQFN packages) or PIO0_5 (HVQFN package).

[11] To VSS.

IOHS HIGH-level short-circuit

output current VOH =0V [9] --160 mA

IOLS LOW-level short-circuit

output current VOL =V

DD(IO) [9] --50mA

Ipd pull-down current VI=5V 10 50 150 A

Ipu pull-up current VI=0V

2.6 V  VDD(IO) 3.6 V

15 50 85 A

VDD(IO) <V

I<5V 000A

I2C-bus pins (PIO0_2 and PIO0_3)

VIH HIGH-level input

voltage 0.7VDD(IO) --V

VIL LOW-level input volta ge - - 0.3VDD(IO) V

Vhys hysteresis voltage - 0.05VDD(IO) -V

IOL LOW-level output

current VOL =0.4V; I

2C-bus pins

configured as standard

mode pins

2.6 V  VDD(IO) 3.6 V

4--mA

IOL LOW-level output

current VOL =0.4V; I

2C-bus pins

configured as high-current

sink pins

2.6 V  VDD(IO) 3.6 V

20--mA

ILI input leakage current VI=V

DD(IO) [11] -24A

VI=5V - 10 22 A

Oscillator pins

Vi(xtal) crystal input voltage 0.5 1.8 1.95 V

Vo(xtal) crystal output voltage 0.5 1.8 1.95 V

Table 6. Static characteristics …continued

Tamb =





C to +85



C, unless otherwise specified.

Symbol Parameter Conditions Min Typ[1] Max Unit

Product data sheet Rev. 4 — 30 October 2012 45 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

9.1 Power consumption

Power measurements in Active and Sleep modes were performed under the following

conditions (see LPC11Axx user manual):

•Configure all pins as GPIO with pull-up resistor disabled in the IOCON block.

•Configure GPIO pins as outputs using the GPIOnDIR registers.

•Write 0 to all GPIO DIR registers to drive the outputs LOW.

Conditions: VDD(3V3) = 3.3 V; active mode entered executing code

while(1){}

from flash; all

peripherals disabled in the SYSAHBCLKCTRL register; all peripheral clocks disabled; all analog

peripherals disabled in the PDRUNCFG register; low-current mode (see Section 7.22.6.2).

(1) SysOsc and system PLL disabled; IRC enabled.

(2) SysOsc and system PLL enabled; IRC disabled.

Fig 11. Active mode: Typical supply current IDD vers us temperature for different system

clock frequencies (all p eripherals disabled)

002aah184

-40 -15 10 35 60 85

1.6

3.2

4.8

6.4

temperature (°C)

IDD

(mA)

12 MHz(1)

24 MHz(2)

36 MHz(2)

48 MHz(2)

Product data sheet Rev. 4 — 30 October 2012 46 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

Conditions: Tamb = 25 °C; active mode entered executing code

while(1){}

from flash; all peripherals

disabled in the SYSAHBCLKCTRL register; all peripheral clocks disabled; all analog peripherals

disabled in the PDRUNCFG register; low-current mode (see Section 7.22.6.2).

(1) SysOsc and system PLL disabled; IRC enabled.

(2) SysOsc and system PLL enabled; IRC disabled.

Fig 12. Active mo de: Typical supply curr ent IDD versus core voltage VDD(3V3) for different

system clock frequencies (all peripherals disabled)

Conditions: VDD(3V3) = 3.3 V; sleep mode entered from flash; all peripherals disabled in the

SYSAHBCLKCTRL register and PDRUNCFG register; all peripheral clocks disabled; BOD

disabled; low-current mode (see Section 7.22.6.2).

(1) SysOsc and system PLL disabled; IRC enabled.

(2) SysOsc and system PLL enabled; IRC disabled.

Fig 13. Sleep mode: Typical supply current IDDversu s temperature for different system

clock frequencies (all p eripherals disabled)

002aah185

2.7 3 3.3 3.6

1.6

3.2

4.8

6.4

VDD(3V3) (V)

IDD

(mA)

12 MHz(1)

24 MHz(2)

36 MHz(2)

48 MHz(2)

002aah186

-40 -15 10 35 60 85

1.6

3.2

4.8

6.4

temperature (°C)

IDD

(mA)

12 MHz(1)

24 MHz(2)

36 MHz(2)

48 MHz(2)

Product data sheet Rev. 4 — 30 October 2012 47 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

9.2 Peripheral power consumption

The supply current p er peripheral is measured as the differ ence in supply current between

the peripheral block enabled and the peripheral block disabled in the SYSAHBCLKCFG

and PDRUNCFG (for analog blocks) registers. All other blocks are disabled in both

registers and no code is executed. Measured on a typical sample at Tamb =25 C.

[1] IRC on; PLL off.

9.3 Electrical pin characteristics

Tabl e 7. Pow er consumption for individual analog and digital blocks

Peripheral Typica l supply

current in mA

12 MHz[1] A verage A/MHz

Analog periph era ls

BOD 0.05 -

BOD, comparator 0.14 -

BOD, comparator, ADC, DAC, temperature sensor 0.40 -

DAC 0.26 -

ADC 0.01 -

Temperature sensor, ADC 0.01 -

Digital peripherals

USART 0.15 12

I2C 0.02 2

16-bit counter/timer 0/1 0.02 2

32-bit counter/timer 0/1 0.02 2

WWDT 0.02 2

Conditions: VDD(IO) = 3.3 V; on pin PIO0_21.

Fig 14. High-current source output driver: Typical HIGH-level output voltage VOH versus

HIGH-level output current IOH

IOH (mA)

0 60402010 5030

002aae990

2.8

2.4

3.2

3.6

VOH

(V)

T = 85 °C

25 °C

−40 °C

Product data sheet Rev. 4 — 30 October 2012 48 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

Conditions: VDD(IO) = 3.3 V; on pins PIO0_2 and PIO0_3.

Fig 15. High-current sink pins: Typical LOW-level output current IOL versus LOW-level

output voltage VOL

Conditions: VDD(IO) = 3.3 V; standard port pins and PIO0_21.

Fig 16. Typical LOW-level output current IOL versus LOW-level output voltage VOL

VOL (V)

0 0.60.40.2

002aaf019

IOL

(mA)

T = 85 °C

25 °C

−40 °C

VOL (V)

0 0.60.40.2

002aae991

IOL

(mA)

T = 85 °C

25 °C

−40 °C

Product data sheet Rev. 4 — 30 October 2012 49 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

Conditions: VDD(IO) = 3.3 V; standard port pins.

Fig 17. Typical HIGH-level output voltage VOH versus HIGH-level output source current

IOH

Conditions: VDD(IO) = 3.3 V; standard port pins.

Fig 18. Typical pull-up current Ipu versus input voltage VI

IOH (mA)

0 24168

002aae992

2.8

2.4

3.2

3.6

VOH

(V)

T = 85 °C

25 °C

−40 °C

VI (V)

0 54231

002aae988

−30

−50

−10

Ipu

(μA)

−70

T = 85 °C

25 °C

−40 °C

Product data sheet Rev. 4 — 30 October 2012 50 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

Conditions: VDD(IO) = 3.3 V; standard port pins.

Fig 19. Typical pull-down current Ipd versus input voltage VI

VI (V)

0 54231

002aae989

Ipd

(μA)

T = 85 °C

25 °C

−40 °C

Product data sheet Rev. 4 — 30 October 2012 51 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

10. Dynamic characteristics

10.1 Power supply fluctuations

If the input voltage (VDD(3V3)) to the internal regulator fluctuates, the LPC11Axx is held in

reset during a brown-out condition as long as the UVLO circuit is operating. The settling

times of the BOD and POR circuits, which constitute the UVLO, determine the minimum

time the supply level must remain in the shallow or deep brown-out condition to ensure

that the internal reset is asserted properly.

See also Section 7.23.1, Section 12.7, and Section 12.8.

10.2 Flash/EEPROM memory

Table 8. UVLO circuits settling characteristics

Symbol Parameter Conditions Min Typ Max Unit

tssettling time power droop:

from active level to shallow

brown-out level

(0.9 V  VDD(3V3)  2.4 V)

5--s

from active level to deep brown-out

level (0 < VDD(3V3) < 0.9 V) 12 - - s

Fig 20. UVLO timing

External

power supply

BOD trip point

(typical)

POR trip point

(typical)

internal reset

time

brown-out

shallow

brown-out

deep

supply

voltage

DD(3V3)

2.4 V

0.9 V

0 V

cold

start-up

> 5 μs

> 12 μs

002aah326

Table 9. Flash characteristics

Tamb =





C to +85



C. Based on JEDEC NVM qualification. Failure rate < 10 ppm for parts as

specified below.

Symbol Parameter Conditions Min Typ Max Unit

Nendu endurance [2][1] 10000 100000 - cycles

Product data sheet Rev. 4 — 30 October 2012 52 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

[1] Number of program/erase cycles.

[2] Min and max values are valid for Tamb =40 C to +85 C only.

[3] Programming times are given for writing 256 bytes to the flash. Tamb < +85 C. Data must be written to the

flash in blocks of 256 bytes. Flash programming is accomplished via IAP calls (see LPC11Axx user

manual). Execution time of IAP calls depends on the system clock and is typically between 1.5 and 2 ms

per 256 bytes.

[1] Min and max values are valid for Tamb =40 C to +85 C only.

[2] Tamb < +85 C.

10.3 External clock for oscillator in slave mode

Remark: The input voltage on the XTALIN pin must be  1.95 V (see Table 6). For

connecting the oscillator to the XTALIN/XTALOUT pins also see Section 12.3.

[1] Parameters are valid over operating temperature range unless otherwise specified.

[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply

voltages.

tret retention time powered [2] 10 20 - years

unpowered [2] 20 40 - years

ter erase time sector or multiple

consecutive

sectors

[2] 95 100 105 ms

tprog programming

time [2][3] 0.95 1 1.05 ms

Table 10. EEPROM characteristics

Tamb =





Cto+125



C; VDD(3V3) = 2.7 V to 3.6 V. Based on JEDEC NVM qualification. Failure

rate < 10 ppm for parts as specified below.

Symbol Parameter Conditions Min Typ Max Unit

Nendu endurance [1] 100000 1000000 - cycles

tret retention time powered [1] 100 200 - years

unpowered [1] 150 300 - years

tprog programming

time 64 bytes [2] -1.1-ms

Table 9. Flash characteristics

Tamb =





C to +85



C. Based on JEDEC NVM qualification. Failure rate < 10 ppm for parts as

specified below.

Symbol Parameter Conditions Min Typ Max Unit

Table 11. Dynamic characteristic: external clock (XTALIN or CLKIN pin)

Tamb =





C to +85



C; VDD(3V3) over specified rang e s.[1]

Symbol Parameter Conditions Min Typ[2] Max Unit

fosc oscillator frequency 1 - 25 MHz

Tcy(clk) clock cycle time 40 - 1000 ns

tCHCX clock HIGH time Tcy(clk) 0.4--ns

tCLCX clock LOW time Tcy(clk) 0.4--ns

tCLCH clock rise time - - 5 ns

tCHCL clock fall time - - 5 ns

Product data sheet Rev. 4 — 30 October 2012 53 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

10.4 Internal oscillators

[1] Parameters are valid over operating temperature range unless otherwise specified.

[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply

voltages.

[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply

voltages.

Fig 21. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV)

tCHCL tCLCX tCHCX

Tcy(clk)

tCLCH

002aaa907

Table 12. Dyn amic characteristic: IRC

Tamb =





C to +85



C; 2.7 V



VDD(3V3)



3.6 V.[1]

Symbol Parameter Conditions Min Typ[2] Max Unit

fosc(RC) internal RC oscillator frequency - 11.88 12 12.12 MHz

Conditions: Frequency values are typical values. 12 MHz  1% accuracy is guaranteed for

2.7 V  VDD(3V3)  3.6 V and Tamb =40 C to +85 C. Variations between parts may cause the

IRC to fall outside the 12 MHz  1% accuracy specification for voltages below 2.7 V.

Fig 22. Internal IRC frequency vs. temperature

Table 13. Dynamic characteristics: WDOsc and LFOsc

Symbol Parameter Conditions Min Typ[1] Max Unit

fosc internal oscillator

frequency DIVSEL = 0x1F, FREQSEL = 0x1

in the WDTOSCCTRL register; [2][3] -9.4 - kHz

DIVSEL = 0x00, FREQSEL = 0xF

in the WDTOSCCTRL register [2][3] - 2300 - kHz

002aah011

11.95

12.05

12.15

(MHz)

11.85

temperature (°C)

-40 853510 60-15

VDD = 3.6 V

3.3 V

3.0 V

2.7 V

Product data sheet Rev. 4 — 30 October 2012 54 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

[2] The typical frequency spread over processing and temperature (Tamb =40 C to +85 C) is  40%.

[3] See the LPC11Axx user manual.

10.5 I/O pins

[1] Applies to standard port pins and RESET pin. Simulated results.

[2] SSO indicates maximum number of simultaneously switching digital output pins. The pins are optimized for

half of the maximum SSO.

[3] Set SLEW bit in the IOCON register to 1.

[4] Set SLEW bit in the IOCON register to 0.

10.6 I2C-bus

Remark: All I2C modes (Standard-mode, Fast-mode, Fast-mode Plus) can be configured

for the true open-drain pins PIO0_2 and PIO0_3. If the limited-performance I2C-bus pins

are used (I2C-bus functions on standard I/O pins), only Standard-mode with internal

pull-up enabled or Fast-mode with external pull-up resistor are supported.

Table 14. Dynamic characteristic: di gital I/O pins[1]

Tamb =





C to +85



C; 3.0 V



VDD(IO)



3.6 V; load capacitor = 30 pF.

Symbol Parameter Conditions Min Typ Max Unit

trrise time pin

configured as

output

SSO = 1 [2][3] 2.5 - 5.0 ns

SSO = 6 [2][3] 2.5 - 4.5 ns

SSO = 16 [2][4] 3.0 - 5.0 ns

tffall time pin

configured as

output

SSO = 1

[2][3]

2.0 - 4.5 ns

SSO = 6 [2][3] 2.0 - 4.5 ns

SSO = 16 [2][4] 2.5 - 5.0 ns

Table 15. Dyn amic characteristic: I2C-bus pins[1]

Tamb =





C to +85



C.[2]

Symbol Parameter Conditions Min Max Unit

fSCL SCL clock

frequency Standard-mode 0 100 kHz

Fast-mode 0 400 kHz

Fast-mode Plus 0 1 MHz

tffall time [4][5][6][7] of both SDA and

SCL signals

Standard-mode

- 300 ns

Fast-mode 20 + 0.1  Cb300 ns

Fast-mode Plus - 120 ns

tLOW LOW period of

the SCL clock Standard-mode 4.7 - s

Fast-mode 1.3 - s

Fast-mode Plus 0.5 - s

Product data sheet Rev. 4 — 30 October 2012 55 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

[1] See the I2C-bus specification UM10204 for details.

[2] Parameters are valid over operating temperature range unless otherwise specified.

[3] tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission

and the acknowledge.

[4] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the

VIH(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL.

[5] Cb = total capacitance of one bus line in pF.

[6] The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA

output stage tf is specified at 250 ns. This allows series protection resistors to be connected in between the

SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf.

[7] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors

are used, designers should allow for this when considering bus timing.

[8] The maximum tHD;DAT could be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than

the maximum of tVD;DAT or tVD;ACK by a transition time (see UM10204). This ma ximum must only be met if

the device does not stretch the LOW period (tLOW) of the SCL signal. If the clock stretches the SCL, the

data must be valid by the set-up time before it releases the clock.

[9] tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in

transmission and the acknowledge.

[10] A Fast-mode I2C-bus device can be used in a S tandard-mode I2C-bus system but the requirement tSU;DAT =

250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period

of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next

data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus

specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time.

tHIGH HIGH period of

the SCL clock Standard-mode 4.0 - s

Fast-mode 0.6 - s

Fast-mode Plus 0.26 - s

tHD;DAT data hold time [3][4][8] Standard-mode 0 - s

Fast-mode 0 - s

Fast-mode Plus 0 - s

tSU;DAT data set-up

time

[9][10] Standard-mode 250 - ns

Fast-mode 100 - ns

Fast-mode Plus 50 - ns

Table 15. Dyn amic characteristic: I2C-bus pins[1]

Tamb =





C to +85



C.[2]

Symbol Parameter Conditions Min Max Unit

Product data sheet Rev. 4 — 30 October 2012 56 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

10.7 SSP interfaces

[1] Tcy(clk) = (SSPCLKDIV  (1 + SCR)  CPSDVSR) / fmain. The clock cycle time derived from the SPI bit rate Tcy(clk) is a function of the

main clock frequency fmain, the SPI peripheral clock divider (SSPCLKDIV), the SPI SCR parameter (specified in the SSP0CR0 register),

and the SPI CPSDVSR parameter (specified in the SPI clock prescale register).

[2] Tamb = 40 C to 85 C.

[3] Tcy(clk) = 12  Tcy(PCLK).

[4] Tamb = 25 C; for normal voltage supply range: VDD(io) = vdd(3v3) = 3.3 V.

Fig 23. I2C-bus pins clock timing

002aaf425

70 %

30 %

SDA

70 %

30 %

70 %

30 %

70 %

30 %

HD;DAT

SCL

1 / f

SCL

70 %

30 % 70 %

30 %

VD;DAT

HIGH

LOW

SU;DAT

Table 16. Dynamic characteristics of SSP pins in SPI mode

2.6 V <= VDD(3V3) = VDD(IO) <= 3.6 V.

Symbol Parameter Conditions Min Typ Max Unit

SPI master (in SPI mode)

Tcy(clk) clock cycle time full-duplex mode [1] 50 - - ns

when only transmitting [1][1] 40 ns

tDS data set-up time in SPI mode [1][2] 15 - - ns

tDH data hold time in SPI mode [1][2] 0-- ns

tv(Q) data output valid time in SPI mode [1][2] --10 ns

th(Q) data output hold time in SPI mode [1][2] 0-- ns

SPI slave (in SPI mode)

Tcy(PCLK) PCLK cycle time 20 - - ns

tDS data set-up time in SPI mode [3][4] 0-- ns

tDH data hold time in SPI mode [3][4] 3  Tcy(PCLK) + 4 - - n s

tv(Q) data output valid time in SPI mode [3][4] --3  Tcy(PCLK) + 11 ns

th(Q) data output hold time in SPI mode [3][4] --2  Tcy(PCLK) + 5 ns

Product data sheet Rev. 4 — 30 October 2012 57 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

Pin names SCK, MISO, and MOSI refer to pins for both SSP peripherals, SSP0 and SSP1.

Fig 24. SSP master timing in SPI mode

SCK (CPOL = 0)

MOSI

MISO

Tcy(clk) tclk(H) tclk(L)

tDS tDH

tv(Q)

D ATA V ALID D ATA V ALID

th(Q)

SCK (CPOL = 1)

D ATA V ALID D ATA V ALID

MOSI

MISO

tDS tDH

D ATA V ALID D ATA V ALID

th(Q)

D ATA V ALID D ATA V ALID

tv(Q)

CPHA = 1

CPHA = 0

002aae829

Product data sheet Rev. 4 — 30 October 2012 58 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

11. Characteristics of analog peripherals

[1] Interrupt levels are selected by writing the level value to the BOD control register BODCT RL, see

LPC11Axx user manual.

Pin names SCK, MISO, and MOSI refer to pins for both SSP peripherals, SSP0 and SSP1.

Fig 25. SSP slave timing in SPI mode

SCK (CPOL = 0)

MOSI

MISO

cy(clk)

clk(H)

clk(L)

v(Q)

D ATA V ALID D ATA V ALID

h(Q)

SCK (CPOL = 1)

D ATA V ALID D ATA V ALID

MOSI

MISO

v(Q)

D ATA V ALID D ATA V ALID

h(Q)

D ATA V ALID D ATA V ALID

CPHA = 1

CPHA = 0

002aae830

Table 17. BOD static characteristics[1]

Tamb =25



Symbol Parameter Conditions Min Typ Max Unit

Vth threshold voltage interrupt level 2

assertion - 2.52 - V

de-assertion - 2.66 - V

interrupt level 3

assertion - 2.80 - V

de-assertion - 2.90 - V

Product data sheet Rev. 4 — 30 October 2012 59 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

[1] The ADC is monotonic, there are no missing codes.

[2] The differential linearity error (ED) is the difference between the actual step width and the ideal step width.

See Figure 26.

[3] The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and

the ideal transfer curve after appropriate adjustment of gain and offset errors. See Figure 26.

[4] The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the

straight line which fits the ideal curve. See Figure 26.

[5] The full-scale error voltage or gain error (EG) is the difference between the straight line fitting the actual

transfer curve after removing offset error, and the straight line which fits the ideal transfer curve. See

Figure 26.

[6] The absolute error (ET) is the maximum difference between the center of the steps of the actual transfer

curve of the non-calibrated ADC and the ideal transfer curve. See Figure 26.

[7] Tamb = 25 C; maximum sampling frequency fs = 400 kSamples/s and analog input capacitance Cia = 1pF.

[8] Input resistance Ri depends on the sampling frequency fs: Ri = 1 / (fs  Cia).

Table 18. ADC static characteristics

Tamb =





C to +85



C unless otherwise specified; ADC frequency 4.5 MHz, VDD(3V3) = 2.7 V to

3.6 V; VSS = 0 V.

Symbol Parameter Conditions Min Typ Max Unit

VIA analog input voltage 0 - VDD(3V3) V

Cia analog input capacitance - - 4 pF

EDdifferential linearity error [1][2] -- 1LSB

EL(adj) integral non-linearity [3] -- 1.5 LSB

EOoffset error [4] -- 20 mV

Verr(FS) full-scale error voltage [5] -- 20 mV

ETabsolute error [6] -- 4LSB

Riinput resistance [7][8] --2.5 M

Product data sheet Rev. 4 — 30 October 2012 60 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

[1] Measured on typical samples.

Table 19. DAC static and dynamic characteristics

VDD(3V3) = 2.7 V to 3.6 V; Tamb =





C to +85



C unless otherwise specified

Symbol Parameter Conditions Min Typ Max Unit

EDdifferential

linearity error --1LSB

EL(adj) integral

non-linearity --1.5 LSB

EOoffset error - - 20 mV

EGgain error - - 2 0 mV

CLload capacitance - - 200 pF

RLload resistance 1 - - k

ROoutput resistance [1] -< 40 

fc(DAC) DAC conversion

frequency -0.41MHz

tssettling time - - 1 s

VOoutput voltage Output voltage range with

less than 1 LSB deviation;

with minimum RL

connected to ground or

power supply

0.3 - VDD(3V3)

 0.3 V

with minimum RL

connected to ground or

power supply

0.175 - VDD(3V3)

 0.175 V

Table 20. DAC sampling frequency range and power consumption

Bias bit Maximum current DAC sampling frequency range

0700 A 0 MHz to 1 MHz

1350 A 0 MHz to 400 kHz

Product data sheet Rev. 4 — 30 October 2012 61 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

(1) Example of an actual transfer curve.

(2) The ideal transfer curve.

(3) Differential linearity error (ED).

(4) Integral non-linearity (EL(adj)).

(5) Center of a step of the actual transfer curve.

Fig 26. ADC characteristics

002aah327

1023

1022

1021

1020

1019

(2)

(1)

10241018 1019 1020 1021 1022 1023

7123456

1018

(5)

(4)

(3)

1 LSB

(ideal)

code

out

VDD(3V3) - VSS

1024

offset

error

gain

error

offset error

VIA (LSBideal)

1 LSB =

Product data sheet Rev. 4 — 30 October 2012 62 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

[1] Characterized through simulation.

[2] Characterized on a typical silicon sample.

[3] Typical values are derived from nominal simulation (VDD(3V3) = 3.3 V; Tamb = 27 C; nominal process

models). Maximum values are derived from worst case simulation (VDD(3V3) = 2.6 V; Tamb = 85 C; slow

process models).

[4] Settling time applies to switching between comparator and ADC channels.

Table 21. Internal voltage reference static and dynamic characteristics

Symbol Parameter Conditions Min Typ Max Unit

VOoutput voltage Tamb = 40 C to +85 C[1] 0.855 0.900 0.945 V

Tamb = 70 C to 85 C[2] -0.906- V

Tamb = 50 C[2] -0.905- V

Tamb = 25 C[3] 0.893 0.903 0.913 V

Tamb = 0 C[2] -0.902- V

Tamb = 20 C[2] -0.899- V

Tamb = 40 C[2] -0.896- V

ts(pu) power-up

settling time to 99% of VO[3] - 155 195 s

ts(sw) switching

settling time to 99% of VO[3]

[4] -5075s

VDD(3V3) = 3.3 V

Fig 27. Typical internal volt age reference output voltage

002aag063

temperature (°C)

-40 853510 60-15

895

905

900

910

(mV)

890

Product data sheet Rev. 4 — 30 October 2012 63 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

[1] Absolute temperature accuracy.

[2] Typical values are derived from nominal simulation (VDD(3V3) = 3.3 V; Tamb = 27 C; nominal process

models). Maximum values are derived from worst case simulation (VDD(3V3) = 2.6 V; Tamb = 85 C; slow

process models).

[3] Settling time applies to switching between comparator and ADC channels.

Table 22. Temperature sensor static and dynamic characteristics

VDD(3V3) = 2.6 V to 3.6 V

Symbol Parameter Conditions Min Typ Max Unit

DTsen sensor

temperature

accuracy

Tamb = 40 C to +85 C[1] -- 3C

ELlinearity error Tamb = 40 C to +85 C-- 1.1 C

ts(pu) power-up

settling time to 99% of temperature

sensor output value [2] -8185s

ts(sw) switching

settling time to 99% of temperature

sensor output value [2][3] -1.52 s

Table 23. Temperature sensor Linear-Least-Sq uare (LLS) fit parameters

VDD(3V3) = 2.6 V to 3.6 V

Fit parameter Range Min Typ Max Unit

LLS slope Tamb = 0 C to 85 C-2.36 - mV/C

Tamb = 40 C to +85 C- 2.36 - mV/C

LLS intercept Tamb = 0 C to 85 C - 577 - mV

Tamb = 40 C to +85C - 576 - mV

VDD(3V3) = 3.3 V; measured on a typical silicon sample.

Fig 28. Typical LLS fit of the temperature sensor output voltage

temperature (°C)

-40 853510 60-15

002aag064

400

600

800

(mV)

200

y = -2.366x + 578.34

R2 = 0.9995

Product data sheet Rev. 4 — 30 October 2012 64 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

[1] CL = 10 pF; results from measurements on silicon samples over process corners and over the full temperature range Tamb = -40 C to

+85 C.

[2] Input hysteresis is relative to the reference input channel and is software programmable.

Table 24. Comparator characteristics

VDD(3V3)= 3.0 V and Tamb = 25



C unless noted otherwise.

Symbol Parameter Conditions Min Typ Max Unit

Static characteristics

IDD supply current - 55 - A

VIC common-mode input voltage 0 - VDD(3V3) V

DVOoutput voltage variation 0 - VDD(3V3) V

Voffset offset voltage VIC = 0.1 V - 4 to +4.2 - mV

VIC = 1.5 V - 2-mV

VIC = 2.8 V - 2.5 mV

Dynamic characteristics

tstartup start-up time nominal process - 4 - s

tPD propagation delay HIGH to LOW; VDD(3V3) = 3.0 V;

VIC = 0.1 V; 50 mV overdrive input [1] -129 140 ns

VIC = 0.1 V; rail-to-rail input [1] - 210 250 ns

VIC = 1.5 V; 50 mV overdrive input [1] -112 130ns

VIC = 1.5 V; rail-to-rail input [1] - 127 160 ns

VIC = 2.9 V; 50 mV overdrive input [1] - 151 170 ns

VIC = 2.9 V; rail-to-rail input [1] -57 70 ns

tPD propagation delay LOW to HIGH; VDD(3V3) = 3.0 V;

VIC = 0.1 V; 50 mV overdrive input [1] -232 240 ns

VIC = 0.1 V; rail-to-rail input [1] -58 60 ns

VIC = 1.5 V; 50 mV overdrive input [1] - 210 230 ns

VIC = 1.5 V; rail-to-rail input [1] - 178 200 ns

VIC = 2.9 V; 50 mV overdrive input [1] - 166 190 ns

VIC = 2.9 V; rail-to-rail input [1] - 333 550 ns

Vhys hysteresis voltage positive hysteresis; VDD(3V3) = 3.0 V;

VIC = 1.5 V [2] - 5, 10, 20 - mV

Vhys hysteresis voltage negative hysteresis; VDD(3V3) = 3.0 V;

VIC = 1.5 V [2] - 5, 10, 20 - mV

Rlad ladder resistance - - 1.034 - M

Product data sheet Rev. 4 — 30 October 2012 65 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

[1] Maximum values are derived from worst case simulation (VDD(3V3) = 2.6 V; Tamb = 85 C; slow process

models).

[2] Settling time applies to switching between comparator and ADC channels.

[1] Measured over a polyresistor matrix lot with a 2 kHz input signal and overdrive < 100 V.

[2] All peripherals except comparator, temperature sensor, and IRC turned off.

Table 25. Comparator voltage ladder dyn amic characteristics

Symbol Parameter Conditions Min Typ Max Unit

ts(pu) power-up settling

time to 99% of voltage

ladder output

value

[1] -- 30 s

ts(sw) switching settling

time to 99% of voltage

ladder output

value

[1]

[2] -- 15 s

Table 26. Comparator voltage ladder reference static characteristics

VDD(3V3) = 3.3 V; Tamb = -40



C to + 85



Symbol Parameter Conditions Min Typ Max[1] Unit

EV(O) output voltage error Internal VDD(3V3) supply

decimal code = 00 [2] -00 %

decimal code = 08 - 0 0.4 %

decimal code = 16 - 0.2 0.2 %

decimal code = 24 - 0.2 0.2 %

decimal code = 30 - 0.1 0.1 %

decimal code = 31 - 0.1 0.1 %

EV(O) output voltage error External VDDCMP

supply

decimal code = 00 - 0 0 %

decimal code = 08 - 0.1 0.5 %

decimal code = 16 - 0.2 0.4 %

decimal code = 24 - 0.2 0.3 %

decimal code = 30 - 0.2 0.2 %

decimal code = 31 - 0.1 0.1 %

Product data sheet Rev. 4 — 30 October 2012 66 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

12. Application information

12.1 ADC usage notes

The following guidelines show how to increase the performance of the ADC in a noisy

environment beyond the ADC specifications listed in Table 18:

•The ADC input trace must be short and as close as possible to the LPC11Axx chip.

•The ADC input traces must be shielded from fast switching digital signals and noisy

power supply line s .

•Because the ADC and the digital co re share the same power sup ply, the power supply

line must be adequately filtered.

•To improve the ADC performance in a very noisy environment, put the device in Sleep

mode during the ADC conversion.

12.2 Use of ADC input trigger signals

For applications that use trigger signals to st art conversions and require a precise sa mple

frequency, ensure that the period of the trigger signal is an integral multiple of the period

of the ADC clock.

12.3 XTAL input

The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a

clock in slave mode, it is recommende d that the inpu t be coupled throug h a cap acitor with

Ci = 100 pF. To limit the input voltage to the specified range, choose an additio nal

capacitor to ground Cg which attenuate s the input volt age by a facto r Ci/(Ci + Cg). In slave

mode, a minimum of 200 mV(RMS) is needed.

In slave mode the input clock signal should be coup led by means of a cap acitor of 100 pF

(Figure 29), with an amplitude between 200 mV (RMS) and 1000 mV (RMS). This

corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V.

The XTALOUT pin in this configuration can be left unconnected.

External components and models used in oscillation mode are shown in Figure 30 and in

Table 27 and Table 28. Since the feedback resistance is integrated on ch ip, only a crystal

and the capacitances CX1 and CX2 need to be connected externally in case of

fundamental mode oscillation (the fundamental frequency is represented by L, CL and

Fig 29. Slave mode operation of the on-chip oscillator

LPC1xxx

XTALIN

100 pF Cg

002aae788

Product data sheet Rev. 4 — 30 October 2012 67 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

RS). Capacitance CP in Figure 30 represent s the p arallel p ackage cap acitance and sho uld

not be larger than 7 pF. Parameters FOSC, CL, RS and CP are supplied by the crystal

manufacturer (see Table 27).

Fig 30. Oscillator mod es and models: oscillation mode of operation and external crystal

model used for CX1/CX2 evaluation

Table 27. Recommended values for CX1/CX2 in oscillation mode (crystal and external

components parameters) low frequency mode

Fundamental oscillation

frequency FOSC

Crystal load

capacitance CL

Maximum crystal

series resistance RS

External load

capacitors CX1, CX2

1 MHz - 5 MHz 10 pF < 300 18 pF, 18 pF

20 pF < 300 39 pF, 39 pF

30 pF < 300 57 pF, 57 pF

5 MHz - 10 MHz 10 pF < 300 18 pF, 18 pF

20 pF < 200 39 pF, 39 pF

30 pF < 100 57 pF, 57 pF

10 MHz - 15 MHz 10 pF < 160 18 pF, 18 pF

20 pF < 60 39 pF, 39 pF

15 MHz - 20 MHz 10 pF < 80 18 pF, 18 pF

Table 28. Recommended values for CX1/CX2 in oscillation mode (crystal and external

components parameters) hi gh frequency mode

Fundamental oscillation

frequency FOSC

Crystal load

capacitance CL

Maximum crystal

series resistance RS

External load

capacitors CX1, CX2

15 MHz - 20 MHz 10 pF < 180 18 pF, 18 pF

20 pF < 100 39 pF, 39 pF

20 MHz - 25 MHz 10 pF < 160 18 pF, 18 pF

20 pF < 80 39 pF, 39 pF

002aaf424

LPC1xxx

XTALIN XTALOUT

CX2

CX1

XTAL

=CLCP

Product data sheet Rev. 4 — 30 October 2012 68 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

12.4 XTAL Printed Circuit Board (PCB) layout guidelines

The crystal should be connected on the PCB as close as possible to the oscillator input

and output pins of the chip. Take care that the load capacito rs Cx1,Cx2, and Cx3 in case of

third overtone crystal usage have a common ground plane. The external components

must also be connected to the ground plain. Loops must be made as small as possible in

order to keep the no ise couple d in via th e PCB as sm all as po ss ible . A lso parasitic s

should stay as small as possible. Values of Cx1 and Cx2 should be chosen smaller

accordingly to the increase in parasitics of the PCB layout.

12.5 Standard I/O pad configuration

Figure 31 shows the possible pin modes for standard I/O pins with analog input function:

•Digital output driver with configurable open-drain output

•Digital input: Weak pull-up resistor (PMOS device) enabled/disabled

•Digital input: Weak pull-down resistor (NMOS device) enabled/disabled

•Digital input: Repeater mode enabled/disabled

•Digital input: Input glitch filter selectable on 17 pins.

•Analog input

Fig 31. Standard I/O pad configuration

ESD

strong

pull-up

strong

pull-down

weak

pull-up

weak

pull-down

open-drain enable

output enable

repeater mode

enable

pull-up enable

pull-down enable

select data

inverter

data output

data input

select glitch

filter

analog input

select analog input

002aaf695

pin configured

as digital output

driver

pin configured

as digital input

pin configured

as analog input

10 ns RC

GLITCH FILTER

Product data sheet Rev. 4 — 30 October 2012 69 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

12.6 Reset pad configuration

12.7 UVLO protection and reset timer circuit

12.8 Guidelines for selecting a power supply filter for UVLO protection

For the UVLO circuits to hold the part in reset during shallow and deep brown-out

conditions, you must filter the power supply line to allow for the BOD and POR circuits to

settle when short voltage drops occur (see Section 10.1 “Power supply fluctuations”).

Select the capacitance of the decoupling/bypass capacitor according to the following

guidelines:

C >> IDD  ts/VDD(3V3) with

•VDD(3V3)  100 mV for th e voltage drop below th e BOD or POR trip poin ts.

•IDD  3 mA with the IRC running and PLL/SysOsc off (see Figure 12).

Fig 32. Reset pad configuration

VSS

reset

002aaf274

VDD

Rpu ESD

ESD

20 ns RC

GLITCH FILTER PIN

Fig 33. Functional diagram of the UVLO protec tio n an d re s et timer circuit

002aah324

INTERNAL

REGULATOR

VINT

1.8 V

VEXT

VINT

analog reset

VREF

POR

VEXT

3.3 V

UVLO

BOD

POR

OR OR internal reset

100 μs RESET

TIMER

Product data sheet Rev. 4 — 30 October 2012 70 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

•ts = 5 s for shallow brown-out (see Table 8).

•ts = 12 s for deep brown-out (see Table 8).

With these parameters, the decoupling/bypass capacitor to add to the supply line is:

•C 0.15 F for shallow brown-out

•C >> 0.36 F for deep brown-out

Product data sheet Rev. 4 — 30 October 2012 71 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

13. Package outline

Fig 34. Package outline LQFP48

UNIT A

max. A1A2A3bpcE

(1) eH

ELL

pZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 1.6 0.20

0.05 1.45

1.35 0.25 0.27

0.17 0.18

0.12 7.1

6.9 0.5 9.15

8.85 0.95

0.55 7

0.12 0.10.21

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

0.75

0.45

SOT313-2 MS-026136E05 00-01-19

03-02-25

D(1) (1)(1)

7.1

6.9

9.15

8.85

0.95

0.55

vMB

vMA

36 25

detail X

(A )

0 2.5 5 mm

scale

pin 1 index

LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2

Product data sheet Rev. 4 — 30 October 2012 72 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

Fig 35. Package outline HVQFN33 (7x7)

References

Outline

version European

projection Issue date

IEC JEDEC JEITA

- - -

hvqfn33_po

09-03-17

09-03-23

Unit

mm max

nom

min

1.00

0.85

0.80

0.05

0.02

0.00 0.2 7.1

7.0

6.9

4.85

4.70

4.55

7.1

7.0

6.9 0.65 4.55 0.75

0.60

0.45 0.1

A(1)

Dimensions

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

HVQFN33: plastic thermal enhanced very thin quad flat package; no leads;

33 terminals; body 7 x 7 x 0.85 mm

A1b

0.35

0.28

0.23

(1) DhE(1) Eh

4.85

4.70

4.55

1e2

4.55

0.1

0.05

0.08

0 2.5 5 mm

scale

terminal 1

index area

detail X

AC B

vCw

terminal 1

index area Dh

L9 16

Product data sheet Rev. 4 — 30 October 2012 73 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

Fig 36. Package outline HVQFN33 (5x5)

References

Outline

version

European

projection Issue date

IEC JEDEC JEITA

MO-220

hvqfn33f_po

11-10-11

11-10-17

Unit(1)

max

nom

min

0.85

0.05

0.00

0.2

5.1

4.9

3.75

3.45

5.1

4.9

3.75

3.45

0.5 3.5

Dimensions (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

HVQFN33: plastic thermal enhanced very thin quad flat package; no leads;

32 terminals; body 5 x 5 x 0.85 mm

0.30

0.18

D(1)

A(1) DhE(1) Ehee

1e2L

3.5

0.1 0.1

0.05

0.5

0.3

0.05

0 2.5 5 mm

scale

1/2 e

AC B

terminal 1

index area

detail X

y1C

916

32 25

terminal 1

index area

1/2 e

Product data sheet Rev. 4 — 30 October 2012 74 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

Fig 37. Package outline (WLCSP20)

References

Outline

version

European

projection Issue date

IEC JEDEC JEITA

LPC11AxxUK

wlcsp20_lpc11axxuk_po

12-03-26

Unit

max

nom

min

0.65 0.27 0.35 2.60 2.60

2.0 0.15 0.05

Dimensions (mm are the original dimensions)

WLCSP20: wafer level chip-size package; 20 bumps; 2.5 x 2.5 x 0.6 mm LPC11AxxUK

A1A2

0.38

bDEe ye1

1.5

e2v

0.05

0.60 0.24 0.32 2.55 2.55 0.50.36

0.55 0.21 0.29 2.50 2.500.34

0 0.5 1 mm

scale

detail X

ball A1

index area

ball A1

index area

1234

AC B

Ø v

CØ w

Product data sheet Rev. 4 — 30 October 2012 75 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

14. Soldering

Fig 38. Re flo w soldering of the LQFP48 package

SOT313-2

DIMENSIONS in mm

occupied area

Footprint information for reflow soldering of LQFP48 package

AyBy

D2 (8×)D1

(0.125)

Ax Ay Bx By D1 D2 Gx Gy Hx Hy

10.350

0.560 10.350 7.350 7.350

0.500 0.280

1.500 0.500 7.500 7.500 10.650 10.650 sot313-2_fr

solder land

Generic footprint pattern

Refer to the package outline drawing for actual layout

Product data sheet Rev. 4 — 30 October 2012 76 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

Fig 39. Reflow so ldering of the HVQFN33(7x7) package

Footprint information for reflow soldering of HVQFN33 package

001aao134

occupied area

solder land

solder resist

solder land plus solder paste

solder paste deposit

Dimensions in mm

Remark:

Stencil thickness: 0.125 mm

e = 0.65

evia = 4.25

OwDtot = 5.10 OA

PID = 7.25 PA+OA

OID = 8.20 OA

0.20 SR

chamfer (4×)

0.45 DM

evia = 1.05

W = 0.30 CU

evia = 4.25

evia = 2.40

LbE = 5.80 CU

LbD = 5.80 CU

PIE = 7.25 PA+OA

LaE = 7.95 CU

LaD = 7.95 CU

OIE = 8.20 OA

OwEtot = 5.10 OA

EHS = 4.85 CU

DHS = 4.85 CU

4.55 SR

B-side

(A-side fully covered)

number of vias: 20

Solder resist

covered via

0.30 PH

0.60 SR cover

0.60 CU

SEhtot = 2.70 SP

SDhtot = 2.70 SP

GapE = 0.70 SP

SPE = 1.00 SP

0.45 DM

SPD = 1.00 SP

GapD = 0.70 SP

Product data sheet Rev. 4 — 30 October 2012 77 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

Fig 40. Reflow so ldering of the HVQFN33(5x5) package

Footprint information for reflow soldering of HVQFN33 package

occupied area

solder paste

solder land

Dimensions in mm

0.5

002aag766

Issue date 11-11-15

11-11-20

Ax Ay Bx C D

5.95 5.95 4.25 0.85

4.25 0.27

5.25

6.2

SLx SLy nSPx nSPy

3.75 3.75 3 3

0.30

0.60

detail X

SLy

SLx

nSPy

nSPx

see detail X

GyHy By

Product data sheet Rev. 4 — 30 October 2012 78 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

15. Abbreviations

Table 29. Abbreviations

Acronym Description

ADC Analog-to-Di gital Converter

AHB Adva nced High-performance Bus

AMBA Advanced Microcontroller Bus Architecture

APB Advanced Peripheral Bus

BOD Brown-Out Detection

GPIO General Purpose Input/Outp ut

I2C Inter Integrated Circuit

JEDEC Joint Electron Devices Engineering Council

LVTSCR Low-Voltage Triggered Silicon-Controlled Rectifier

NVM Non-Volatile Memory

PLL Phase-Locked Loop

SPI Serial Periph eral Interface

SSI Serial Synchronous Interface

TTL Transistor-Transistor Logic

USART Universal Synchronous/Asynchronous Receiver/Transmitter

UVLO Under-Voltage LockOut

Product data sheet Rev. 4 — 30 October 2012 79 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

16. Revision history

Table 30. Revision history

Document ID Release date Data sh ee t status Cha nge notice Supersedes

LPC11AXX v.4 20121030 Product data sheet - LPC11AXX v.3

•Parameter tPD corrected in Table 25.

•Editorial updates.

•Maximum and minimum values for VDD and VDD(IO) updated in Table 5 “Limiting

values”.

•Limiting values for parameter VI added for open-drain pins PIO0_2 and PIO0_3 in

Table 5 “Limiting values”.

•Table 26 “Comparator voltage ladder reference static characteristics” updated.

•Parameters ts(pu) and ts(sw) added to Table 21 “Internal voltage reference static and

dynamic characteristics”.

•Parameters VIA and Vtrig and Vi(xtal) added to Table 5.

LPC11AXX v.3 20120907 Product data sheet - LPC11AXX v.2.1

•Section 10.1 abbreviated for clarity.

•UVLO description including description of cold start-up behavior moved to the

LPC11Axx user manual.

•Table “Slew rate for the internal regulator power-up from ground” removed. This

specification is included in the cold start-up description in the LPC11Axx user manual.

•Details regarding boundary scan added to Section 7.24 “Emulation and debugging”.

•Figure 33 “Functional diagram of the UVLO protection and reset timer circuit” updated

to include the reset timer circuit.

•Section 12.8 “Guidelines for selecting a power supply filter for UVLO protection”

added.

•Section 7.23.2 updated to include internal reset timer.

•Parameter tPD corrected in Table 24.

•Parameter EV(O) corrected in Table 26.

LPC11AXX v.2.1 20120704 Product data sheet - LPC11AXX v.2

•Data sheet status changed to Product.

•Changed Table note [2] in Table 24.

•Changed Table note [1] in Table 8.

•Added Table note [1] in Table 9.

•Moved DTsen and EL values from typ to max in Table 22.

•Corrected Vesd in Table 5.

•Added Table note [5] and Table note [6] to Table 4.

Product data sheet Rev. 4 — 30 October 2012 80 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

LPC11AXX v.2 20120625 Preliminary data sheet - LPC11AXX v.1

•Data sheet status changed to Preliminary.

•Parameter fclk removed from Table 11.

•ter removed in Table 11.

•Writable EEPROM size specified in Section 7.3.

•Section 10.3 “UVLO reset behavior” added.

•Power consumption data updated for active mode and sleep mode (see Figure 11 to

Figure 13).

•Power consumption data for active and sleep modes with all peripheral s enabled

removed in Table 6 and Section 9.1.

•Parameters ts(pu) and ts(sw) removed from Section 7.15.

•Parameter tPD updated in Table 25.

•SSP dynamic characteristics added in Table 17.

•WDOsc and LFOsc max and min frequency values updated throughout the data sheet.

•Section 12.7 “UVLO protection circuit” added.

•Typical values fo r parameters ED, EL(adj), EO, EG, and CL in Table 20 “DAC static and

dynamic characteristics” changed to maximum values.

•Parameter VO corrected for condition Tamb = 40 C to +85 C in Table 22.

LPC11AXX v.1 20120322 Objective data sheet - -

Table 30. Revision history …continued

Document ID Release date Data sh ee t status Cha nge notice Supersedes

Product data sheet Rev. 4 — 30 October 2012 81 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

17. Legal information

17.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

17.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liab ility for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall pre vail.

Product specificat io n — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to off er functions and qualities beyond those described in the

Product data sheet.

17.3 Disclaimers

Limited warr a nty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Se miconductors takes no

responsibility for the content in this document if provided by an inf ormation

source outside of NXP Semiconductors.

In no event shall NXP Semiconductors be liable for any indirect , incidental,

punitive, special or consequ ential damages (including - wit hout limitatio n - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconduct ors’ aggregate and cumulati ve liability toward s

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all informa tion supplied prior

to the publication hereof .

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors pro duct can reasonably be expected

to result in perso nal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconducto rs products in such equipment or

applications and ther efore such inclu sion and/or use is at the cu stomer’s own

risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty tha t such application s will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and ope ration of their applications

and products using NXP Semiconductors product s, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suit able and fit for the custome r’s applications and

products planned, as well as fo r the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

NXP Semiconductors does not accept any liabili ty related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessa ry

testing for th e customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanent ly and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individua l agreement. In case an individual

agreement is concluded only the ter ms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly object s to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing i n this document may be interpreted or

construed as an of fer t o sell product s that is open for accept ance or t he grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the objective specification for product development .

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.

Product [short] dat a sheet Production This document contains the product specification.

Product data sheet Rev. 4 — 30 October 2012 82 of 84

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It i s neit her qua lified nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automot ive specifications and standard s, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from custome r design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specif ications.

17.4 Trademarks

Notice: All referenced b rands, produc t names, service names and trademarks

are the property of their respect i ve ow ners.

I2C-bus — logo is a trademark of NXP B.V.

18. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Product data sheet Rev. 4 — 30 October 2012 83 of 84

continued >>

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

19. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

4 Ordering information. . . . . . . . . . . . . . . . . . . . . 3

4.1 Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 4

5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5

6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 6

6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7

7 Functional description . . . . . . . . . . . . . . . . . . 23

7.1 ARM Cortex-M0 processor. . . . . . . . . . . . . . . 23

7.2 On-chip flash program memory . . . . . . . . . . . 23

7.3 On-chip EEPROM data memory. . . . . . . . . . . 23

7.4 On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 23

7.5 On-chip ROM . . . . . . . . . . . . . . . . . . . . . . . . . 23

7.6 Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 23

7.7 Nested Vectored Interrupt Controller (NVIC) . 24

7.7.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7.7.2 Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 25

7.8 IOCON block . . . . . . . . . . . . . . . . . . . . . . . . . 25

7.9 Fast general purpose parallel I/O . . . . . . . . . . 25

7.9.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7.10 USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

7.10.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

7.11 SSP serial I/O controller . . . . . . . . . . . . . . . . . 26

7.11.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

7.12 I2C-bus serial I/O controller . . . . . . . . . . . . . . 26

7.12.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.13 Configurable analog/mixed-signal

subsystems. . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.14 10-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

7.14.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7.15 Internal voltage reference. . . . . . . . . . . . . . . . 29

7.16 Temperature sensor . . . . . . . . . . . . . . . . . . . . 30

7.17 10-bit DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.17.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

7.18 Analog comparator . . . . . . . . . . . . . . . . . . . . . 31

7.18.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7.19 General purpose external even t

counter/timers. . . . . . . . . . . . . . . . . . . . . . . . . 33

7.19.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.20 System tick timer . . . . . . . . . . . . . . . . . . . . . . 33

7.21 Windowed WatchDog Timer (WWDT) . . . . . . 33

7.21.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.22 Clocking and power control . . . . . . . . . . . . . . 34

7.22.1 Crystal and internal oscillators . . . . . . . . . . . . 34

7.22.1.1 Internal RC Oscillator (IRC) . . . . . . . . . . . . . . 35

7.22.1.2 Crystal Oscillator (SysOsc) . . . . . . . . . . . . . . 35

7.22.1.3 Internal Low-Frequency Oscillator (LFOsc)

and Watchdog Oscillato r (WDOsc) . . . . . . . . 36

7.22.2 Clock input. . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.22.3 System PLL . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.22.4 Clock output. . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.22.5 Wake-up process. . . . . . . . . . . . . . . . . . . . . . 36

7.22.6 Power control. . . . . . . . . . . . . . . . . . . . . . . . . 36

7.22.6.1 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.22.6.2 Power profiles . . . . . . . . . . . . . . . . . . . . . . . . 37

7.23 System control. . . . . . . . . . . . . . . . . . . . . . . . 37

7.23.1 UnderVoltage LockOut (UVLO) protection. . . 37

7.23.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7.23.3 Brown-out detection. . . . . . . . . . . . . . . . . . . . 38

7.23.4 Code security (Code Read Protection - CRP) 38

7.23.5 APB interface. . . . . . . . . . . . . . . . . . . . . . . . . 38

7.23.6 AHBLite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

7.23.7 External interrupt inputs. . . . . . . . . . . . . . . . . 39

7.24 Emulation and debugging . . . . . . . . . . . . . . . 39

8 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 40

9 Static characteristics . . . . . . . . . . . . . . . . . . . 42

9.1 Power consumption . . . . . . . . . . . . . . . . . . . 45

9.2 Peripheral power consumption . . . . . . . . . . . 47

9.3 Electrical pin characteristics. . . . . . . . . . . . . . 47

10 Dynamic characteristics. . . . . . . . . . . . . . . . . 51

10.1 Power supply fluctuations . . . . . . . . . . . . . . . 51

10.2 Flash/EEPROM memory . . . . . . . . . . . . . . . . 51

10.3 Externa l clock for oscillator in slave mode. . . 52

10.4 Internal oscilla tors . . . . . . . . . . . . . . . . . . . . . 53

10.5 I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

10.6 I2C-bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

10.7 SSP interfaces . . . . . . . . . . . . . . . . . . . . . . . . 56

11 Characteristics of analog peripherals. . . . . . 58

12 Application information . . . . . . . . . . . . . . . . . 66

12.1 ADC usage notes. . . . . . . . . . . . . . . . . . . . . . 66

12.2 Use of ADC input trigger signals . . . . . . . . . . 66

12.3 XTAL input . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

12.4 XTAL Printed Circuit Board (PCB) layout

guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

12.5 Standard I/O pad configuration . . . . . . . . . . . 68

12.6 Reset pad configuration. . . . . . . . . . . . . . . . . 69

12.7 UVL O protection and reset timer circuit. . . . . 69

12.8 Guidelines for selecti ng a power supply filter

for UVLO protection. . . . . . . . . . . . . . . . . . . . 69

13 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 71

14 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

NXP Semiconductors LPC11Axx

32-bit ARM Cortex-M0 microcontroller

For more information, please visit: http://www.nxp.co m

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 30 October 2012

Document id en tifier: LPC11 A XX

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

15 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 78

16 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 79

17 Legal information. . . . . . . . . . . . . . . . . . . . . . . 81

17.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 81

17.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

17.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 81

17.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 82

18 Contact information. . . . . . . . . . . . . . . . . . . . . 82

19 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Mouser Electronics

Authorized Distributor

Click to View Pricing, Inventory, Delivery & Lifecycle Information:

NXP:

LPC11A12FBD48/101, LPC11A12FHN33/101, LPC11A14FBD48/301, LPC11A13FHI33/201, LPC11A11FHN33/001,

LPC11A14FHN33/301,