ams Datasheet Page 1
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AS5043
Programmable 360° Magnetic Angle
Encoder with Absolute SSI and Analog
Outputs
The AS5043 is a contactless magnetic angle encoder for
accurate measurement up to 360°.
It is a system-on-chip, combining integrated Hall elements,
analog front end and digital signal processing in a single device.
The AS5043 provides a digital 10-bit as well as a programmable
analog output that is directly proportional to the angle of a
magnet, rotating over the chip.
The analog output can be configured in many ways, including
user programmable angular range, adjustable output voltage
range, voltage or current output, etc...
An internal voltage regulator allows operation of the AS5043
from 3.3V or 5.0V supplies.
Ordering Information and Content Guide appear at end of
datasheet.
Key Benefits & Features
The benefits and features of AS5043, Programmable 360°
Magnetic Angle Encoder with Absolute SSI and Analog Outputs
are listed below:
Figure 1:
Added Value of Using AS5043
Benefits Features
•Highest reliability and durability •Contactless high resolution rotational position
encoding over a full turn of 360 degrees
•Simple programming •Simple user-programmable zero position
•Multiple interfaces •Serial communication interface (SSI)
•Programmable 10-bit analog output
•Ideal for robotic and motor applications •Input mode for optimizing noise vs. speed
•Failure diagnostics •Failure detection mode for magnet placement
monitoring and loss of power supply
•Easy setup •Serial read-out of multiple interconnected AS5043
devices using Daisy Chain mode
•Small form factor •SSOP 16 (5.3mm x 6.2mm)
•Robust environmental tolerance •Wide temperature range: -40°C to 125°C
General Description
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AS5043 − General Description
Applications
AS5043, Programmable 360° Magnetic Angle Encoder with
Absolute SSI and Analog Outputs is ideal for applications with
an angular travel range from a few degrees up to a full turn of
360°, such as:
•Industrial applications:
• Contactless rotary position sensing
• Robotics
•Valve controls
•Automotive applications:
• Throttle position sensors
•Gas/brake pedal position sensing
• Headlight position control
•Front panel rotary switches
•Replacement of potentiometers
Figure 2:
Typical Arrangement of AS5043 and Magnet
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AS5043 − General Description
Block Diagram
The functional blocks of this device are shown below:
Figure 3:
AS5043 Block Diagram
DSP
Hall Array
&
Frontend
Amplifier OTP
Register
Programming
Parameters
Absolute
Interface
(SSI)
Sin
Cos
MagRNGn
Mode
DO
CLK
FB
Vout
Prog_DI
CSn
10bit
DAC +
-
10
DACout
DACref
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AS5043 − Pin Assignment
Figure 4:
AS5043 Pin Configuration SSOP16
Package = SSOP16 (16 lead Shrink Small Outline Package)
Figure 5:
Pin Description SSOP16
Pin Symbol Type Description
1 MagRngn DO_OD
Magnet Field Magnitude RaNGe warning; active low, indicates
that the magnetic field strength is outside of the recommended
limits.
2 Mode DI_PD, ST
Mode input. Select between low noise (low, connect to VSS) and
high speed (high, connect to VDD5V) mode at power up. Internal
pull-down resistor.
3 CSn DI_PU, ST
Chip Select, active low; Schmitt-Trigger input, internal pull-up
resistor (~50kΩ)
4 CLK DI,ST Clock Input of Synchronous Serial Interface; Schmitt-Trigger input
5 NC - Must be left unconnected
6 DO DO_T Data Output of Synchronous Serial Interface
7 VSS S Negative Supply Voltage (GND)
8 Prog_DI DI_PD
OTP Programming Input and Data Input for Daisy Chain mode.
Internal pull-down resistor (~74kΩ).
Should be connected to VSS if programming is not used
9 DACref AI DAC Reference voltage input for external reference
10 DACout AO DAC output (unbuffered, Ri ~8kΩ)
11 FB AI Feedback, OPAMP inverting input
Pin Assignment
MagRngn
Prog_DI
VSS
DO
NC
CLK
CSn
VDD5V
DACref
DACout
FB
Vout
NC
NC
1
4
3
2
13
12
11
10
9
8
7
6
5
16
15
14
Mode VDD3V3
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AS5043 − Pin Assignment
Abbreviations for Pin Types in Figure 5:
Pin Description
Pins 7, 15 and 16 are supply pins, pins 5, 13 and 14 are for
internal use and must be left open.
Pin 1 is the magnetic field strength indicator, MagRNGn. It is
an open-drain output that is pulled to VSS when the magnetic
field is out of the recommended range (45mT to 75mT). The chip
will still continue to operate, but with reduced performance,
when the magnetic field is out of range. When this pin is low,
the analog output at pins #10 and #12 will be 0V to indicate the
out-of-range condition.
Pin 2 MODE allows switching between filtered (slow) and
unfiltered (fast mode). This pin must be tied to VSS or VDD5V,
and must not be switched after power up.
Pin 3 Chip Select (CSn; active low) selects a device for serial
data transmission over the SSI interface. A “logic high” at CSn
forces output DO to digital tri-state.
Pin 4 CLK is the clock input for serial data transmission over the
SSI interface.
12 Vout AO OPAMP output
13 NC - Must be left unconnected
14 NC - Must be left unconnected
15 VDD3V3 S
3V-Regulator Output for internal core, regulated from
VDD5V.Connect to VDD5V for 3V supply voltage. Do not load
externally.
16 VDD5V S Positive Supply Voltage, 3.0 to 5.5 V
DO_OD : Digital output open drain
DI_PD : Digital input pull-down
DI_PU : Digital input pull-up
S : Supply pin
DO_T : Digital output /tri-state
ST : Schmitt-Trigger input
AI : Analog input
AO : Analog output
D1 : Digital input
Pin Symbol Type Description
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AS5043 − Pin Assignment
Pin 6 DO (Data Out) is the serial data output during data
transmission over the SSI interface.
Pin 8 PROG_DI is used to program the different operation
modes, as well as the zero-position in the OTP register.
This pin is also used as a digital input to shift serial data through
the device in Daisy Chain Mode.
Pin 9 DACref is the external voltage reference input for the
Digital-to-Analog Converter (DAC). If selected, the analog
output voltage on pin 12 (Vout) will be ratiometric to the voltage
on this pin.
Pin10 DACout is the unbuffered output of the DAC. This pin
may be used to connect an external OPAMP, etc. to the DAC.
Pin 11 FB (Feedback) is the inverting input of the OPAMP buffer
stage.
Access to this pin allows various OPAMP configurations.
Pin 12 Vout is the analog output pin. The analog output is a DC
voltage, ratiometric to VDD5V (3.0 – 5.5V) or an external voltage
source and proportional to the angle.
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AS5043 − Absolute Maximum Ratings
Stresses beyond those listed in Absolute Maximum Ratings
may cause permanent damage to the device. These are stress
ratings only. Functional operation of the device at these or any
other conditions beyond those indicated in Operating
Conditions is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
Figure 6:
Absolute Maximum Ratings
Symbol Parameter Min Max Units Note
VDD5V DC supply voltage at pin
VDD5V
-0.3 7 V Pin VDD5V
VDD3V3 5 V Pin VDD3V3
Vin Input pin voltage
-0.3 VDD5V +0.3
V
Pins MagRngn, Mode, CSn, CLK,
DO, DACout, FB, Vout
-0.3 5 Pin DACref
-0.3 7.5 Pin PROG_DI
Iscr Input current
(latchup immunity) -100 100 mA JEDEC 78
ESD Electrostatic discharge ±2 kV MIL 883 E method 3015
Tstrg Storage temperature -55 125 ºC Min – 67°F; Max 257°F
TBody Body temperature 260 ºC
t=20s to 40s, IPC/JEDEC
J-Std-020C
Lead finish 100% Sn “matte tin”
RHNC Relative humidity
(non condensing) 5 85 %
MSL Moisture sensitivity level 3 Maximum floor life time of 168h
Absolute Maximum Ratings
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AS5043 − Electrical Characteristics
Operating Conditions
Figure 7:
Operating Conditions
DC Characteristics for Digital Inputs and
Outputs
CMOS Schmitt-Trigger Inputs: CLK, CSn (Internal
Pull-Up), Mode (Internal Pull-Down)
(operating conditions: Tamb = -40°C to 125°C, VDD5V = 3.0V to
3.6V (3V operation) VDD5V = 4.5V to 5.5V (5V operation) unless
otherwise noted)
Figure 8:
CMOS Schmitt-Trigger Inputs: CLK, CSn (CSn = Internal Pull-Up), Mode (Internal Pull-Down)
Symbol Parameter Min Typ Max Unit Note
Tamb Ambient temperature -40 125 °C -40°F to 257°F
Isupp Supply current 16 21 mA
VDD5V
VDD3V3
Supply voltage at pin VDD5V
Voltage regulator output
voltage at pin VDD3V3
4.5
3.0
5.0
3.3
5.5
3.6
V
V
5V operation
VDD5V
VDD3V3
Supply voltage at pin VDD5V
Supply voltage at pin VDD3V3
3.0
3.0
3.3
3.3
3.6
3.6
V
V
3.3V operation (pins VDD5V
and VDD3V3 connected)
Symbol Parameter Min Max Unit Note
VIH High level input voltage 0.7 * VDD5V V Normal operation
VIL Low level input voltage 0.3 * VDD5V V
VIon-VIoff Schmitt Trigger hysteresis 1 V
ILEAK
IiL
IiH
Input leakage current
Pull-up low level input current
Pull-down high level input
current
-1 1
μA
Pin CLK,
VDD5V = 5.0V
-30
30
-100
100
Pin CSn,
VDD5V= 5.0V
Pin Mode,
VDD5V= 5.0V
Electrical Characteristics
ams Datasheet Page 9
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AS5043 − Electrical Characteristics
CMOS Input: Program Input (Prog)
(operating conditions: Tamb = -40°C to 125°C, VDD5V = 3.0V to
3.6V (3V operation) VDD5V = 4.5V to 5.5V (5V operation) unless
otherwise noted)
Figure 9:
CMOS Input: Program Input (Prog)
CMOS Output Open Drain: MagRngn
(operating conditions: Tamb = -40°C to 125°C, VDD5V = 3.0V to
3.6V (3V operation) VDD5V = 4.5V to 5.5V (5V operation) unless
otherwise noted).
Figure 10:
CMOS Output Open Drain: MagRngn
Symbol Parameter Min Max Unit Note
VIH High level input voltage 0.7 * VDD5V 5 V
VPROG High level input voltage See Programming
Conditions V During
programming
VIL Low level input voltage 0.3 * VDD5V V
IiL Pull-down high level input
current 100 μA VDD5V: 5.5V
Symbol Parameter Min Max Unit Note
VOL Low level output voltage VSS+0.4 V
IO Output current 4
2 mA VDD5V: 4.5V
VDD5V: 3V
IOZ Open drain leakage current 1 μA
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AS5043 − Electrical Characteristics
Tristate CMOS Output: DO
(operating conditions: Tamb = -40°C to 125°C, VDD5V = 3.0V to
3.6V (3V operation) VDD5V = 4.5V to 5.5V (5V operation) unless
otherwise noted).
Figure 11:
Tristate CMOS Output: DO
Digital-to-Analog Converter
Figure 12:
Digital-to-Analog Converter
Symbol Parameter Min Max Unit Note
VOH High level output voltage VDD5V-0.5 V
VOL Low level output voltage VSS+0.4 V
IO Output current 4
2 mA VDD5V: 4.5V
VDD5V: 3V
IOZ Tri-state leakage current 1 μA
Symbol Parameter Min Typ Max Unit Note OTP Setting
Resolution 10 bit
VOUTM1 Output range 0 Vref V 0% …100% Vref
(default)
ClampMdEn = 0
(default)
VOUTM2 0.10
*Vref
0.90
*Vref V 10% …90% Vref ClampMdEn = 1
ROut,DAC Output
resistance 8 kΩUnbuffered Pin
DACout (#10)
Vref
DAC
reference
voltage (DAC
full scale
range)
0.2 VDD3V3
- 0.2 V
DAC reference =
external: Pin:
DACref (#9)
RefExt EN = 1
VDD5V /
2 V DAC reference =
internal RefExtEn = 0 (default)
INLDAC Integral
non-linearity ±1.5 LSB
Non-Linearity of
DAC and OPAMP;
-40°C to 125°C,
for all analog
modes: 1LSB =
Vref / 1024
DNLDAC Differential
non-linearity ±0.5 LSB
Hyst
Analog
output
hysteresis
1 LSB All analog modes
2 LSB
At 360°-0°
transition, 360°
mode only
OR1,OR0 = 00 (default)
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AS5043 − Electrical Characteristics
OPAMP Output Stage
Figure 13:
OPAMP Output Stage
Symbol Parameter Min Typ Max Unit Note
VDD5V Power Supply
Range 3.0 5.5 V
CL Parallel Load
Capacitance 100 pF
RL Parallel Load
Resistance 4.7 kΩ3.3V operation
A0 Open Loop Gain 92 130 144 dB
VosOP Offset Voltage RTI -5 5 mV 3 sigma
VoutL Output Range Low 0.05 *
VDD5V V
Linear range of analog
output
VoutH Output Range High 0.95 *
VDD5V V
Isink Current capability
sink 4.8 50 mA
Permanent short circuit
current: Vout to VDD5V
Isource Current capability
source 4.6 66 mA
Permanent short circuit
current: Vout to VSS
Vnoise Output noise 160 220 490 μVrms
Over full temperature
range;
BW= 1Hz …10MHz,
Gain = 2x
Gain OPAMP gain
(non-inverting)
2 Internal; OTP: FB_int EN = 1
1 4
External OTP: FB_int EN = 0
(default) With external
resistors, pins Vout [#12]
and FB [#11]:
see Figure 33
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AS5043 − Electrical Characteristics
Magnetic Input Specification
(operating conditions: Tamb = -40°C to 125°C, VDD5V = 3.0V to
3.6V (3V operation) VDD5V = 4.5V to 5.5V (5V operation) unless
otherwise noted).
Two-pole cylindrical diametrically magnetized source:
Figure 14:
Magnetic Input Specification
Symbol Parameter Min Typ Max Unit Note
dmag Diameter 4 6 mm
Recommended magnet: Ø 6mm x
2.5mm for cylindrical magnets
tmag Thickness 2.5 mm
Bpk Magnetic input
field amplitude 45 75 mT
Required vertical component of the
magnetic field strength on the die’s
surface, measured along a concentric
circle with a radius of 1.1mm
Boff Magnetic offset ± 10 mT Constant magnetic stray field
Field non-linearity 5 % Including offset gradient
fmag_abs
Input frequency
(rotational speed
of magnet)
10 Hz
Absolute mode: 600 rpm @ readout of
1024 positions (see Figure 48)
fmag_inc 166 Hz
Incremental mode: no missing pulses
at rotational speeds of up to 10,000
rpm (see Figure 48)
Disp Displacement
radius 0.25 mm
Max. offset between defined device
center and magnet axis
Recommended
magnet material
and temperature
drift
-0.12
%/K
NdFeB (Neodymium Iron Boron)
-0.035 SmCo (Samarium Cobalt)
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AS5043 − Electrical Characteristics
Electrical System Specifications
(operating conditions: Tamb = -40°C to 125°C, VDD5V = 3.0V to
3.6V (3V operation) VDD5V = 4.5V to 5.5V (5V operation) unless
otherwise noted).
Figure 15:
Electrical System Specifications
Symbol Parameter Min Typ Max Unit Note
RES Resolution (1) 10 bit 0.352 deg
INLopt Integral non-linearity
(optimum)(1) ± 0.5 deg
Maximum error with respect to
the best line fit. Verified at
optimum magnet placement,
Tamb =25 °C.
INLtemp
Integral non-linearity
(optimum) (1) ± 0.9 deg
Maximum error with respect to
the best line fit. Verified at
optimum magnet placement,
Tamb = -40°C to 125°C
INL Integral non-linearity (1) ± 1.4 deg
Best line fit = (Errmax – Errmin) /
2 Over displacement tolerance
with 6mm diameter magnet,
Tamb = -40°C to 125°C
DNL Differential non-linearity (1) ± 0.176 deg 10bit, no missing codes
TN Transition noise (1)
0.06
deg
RMS
1 sigma, fast mode
(pin MODE = 1)
0.03 1 sigma, slow mode (pin
MODE=0 or open)
Von
Power-ON reset threshold
ON voltage; 300mV typ.
hysteresis
1.37 2.2 2.9 V
DC supply voltage 3.3V
(VDD3V3)
Voff
Power-ON reset threshold
OFF voltage; 300mV typ.
hysteresis
1.08 1.9 2.6 V DC supply voltage 3.3V
(VDD3V3)
tPwrUp
Power-up time,
Until offset compensation
finished, OCF = 1, Angular
Data valid
20
ms
Fast mode (pin MODE=1)
80 Slow mode (pin MODE=0 or
open)
tdelay
System propagation delay
absolute output : delay of
ADC and DSP
96
μs
Fast mode (pin MODE=1)
384 Slow mode (pin MODE=0 or
open)
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AS5043 − Electrical Characteristics
Note(s) and/or Footnote(s):
1. Digital interface
Figure 16:
Integral and Differential Non-Linearity Example (exaggerated curve)
Integral Non-Linearity (INL) is the maximum deviation between
actual position and indicated position.
Differential Non-Linearity (DNL) is the maximum deviation of
the step length from one position to the next.
Transition Noise (TN) is the repeatability of an indicated
position.
fS, mode 0 Internal sampling rate for
absolute output
2.48 2.61 2.74
kHz
Tamb = 25°C, slow mode (pin
MODE = 0 or open)
2.35 2.61 2.87 Tamb = -40°C to 125°C, slow
mode (pin MODE = 0 or open)
fS, mode 1 Internal sampling rate for
absolute output
9.90 10.4
2 10.94
kHz
Tamb = 25°C, fast mode (pin
MODE = 1)
9.38 10.4
2 11.46 Tamb = -40°C to 125°C, fast
mode (pin MODE = 1)
CLK Read-out frequency >0 1 MHz
Max. clock frequency to read
out serial data
Symbol Parameter Min Typ Max Unit Note
q 360 q
0q
0
512
1023
D
D
10bit code
0
1
2
0.35°
INL
Ideal curve
Actual curve
TN
512
1023
DNL+1LSB
[degrees]
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AS5043 − Electrical Characteristics
Timing Characteristics
Synchronous Serial Interface (SSI)
(operating conditions: Tamb = -40°C to 125°C, VDD5V = 3.0V to
3.6V (3V operation) VDD5V = 4.5V to 5.5V (5V operation) unless
otherwise noted).
Figure 17:
Synchronous Serial Interface (SSI)
Symbol Parameter Min Typ Max Unit Note
t DO active Data output activated
(logic high) 100 ns
Time between falling edge of CSn
and data output activated
tCLK FE First data shifted to
output register 500 ns
Time between falling edge of CSn
and first falling edge of CLK
T CLK / 2 Start of data output 500 ns Rising edge of CLK shifts out one bit
at a time
t DO valid Data output valid 413 ns Time between rising edge of CLK
and data output valid
t DO tristate Data output tristate 100 ns After the last bit DO changes back to
“tristate”
t CSn Pulse width of CSn 500 ns CSn = high; To initiate read-out of
next angular position
fCLK Read-out frequency >0 1 MHz Clock frequency to read out serial
data
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AS5043 − Electrical Characteristics
Programming Conditions
(operating conditions: Tamb = -40°C to 125°C, VDD5V = 3.0V to
3.6V (3V operation) VDD5V = 4.5V to 5.5V (5V operation) unless
otherwise noted).
Figure 18:
Programming Conditions
Symbol Parameter Min Typ Max Unit Note
t Prog enable Programming enable
time 2 μs Time between rising edge at
Prog pin and rising edge of CSn
t Data in Write data start 2 μs
t Data in valid Write data valid 250 ns Write data at the rising edge of
CLKPROG
t Load PROG Load programming
data 3 μs
t PrgR
Rise time of VPROG
before CLKPROG 0 μs
t PrgH Hold time of VPROG
after CLKPROG 0 5 μs
CLK PROG Write data –
programming CLKPROG 250 kHz
t PROG CLK pulse width 1.8 2 2.2 μs During programming; 16 clock
cycles
t PROG finished Hold time of VPROG
after programming 2 μs Programmed data is available
after next power-on
V PROG Programming voltage 7.3 7.4 7.5 V Must be switched OFF after
zapping
V ProgOff Programming voltage
OFF level 0 1 V
Line must be discharged to this
level
I PROG Programming current 130 mA During programming
CLKAread Analog read CLK 100 kHz Analog readback mode
Vprogrammed Programmed Zener
voltage (log.1) 100 mV
VRef-VPROG during analog
readback mode (see Analog
Readback Mode)
Vunprogrammed Unprogrammed Zener
voltage (log. 0) 1 V
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AS5043 − Functional Description
The AS5043 is manufactured in a CMOS standard process and
uses a spinning current Hall technology for sensing the
magnetic field distribution across the surface of the chip.
The integrated Hall elements are placed in a circle around the
center of the device and deliver a voltage representation of the
magnetic field perpendicular to the surface of the IC.
Through Sigma-Delta Analog / Digital Conversion and Digital
Signal-Processing (DSP) algorithms, the AS5043 provides
accurate high-resolution absolute angular position
information. For this purpose a Coordinate Rotation Digital
Computer (CORDIC) calculates the angle and the magnitude of
the Hall array signals.
The DSP is also used indicate movements of the magnet
towards or away from the chip and to indicate, when the
magnetic field is outside of the recommended range
(status bits = MagInc, MagDec; hardware pin = MagRngn).
A small low cost diametrically magnetized (two-pole) standard
magnet, centered over the chip, is used as the input device.
The AS5043 senses the orientation of the magnetic field and
calculates a 10-bit binary code. This code can be accessed via a
Synchronous Serial Interface (SSI). In addition, the absolute
angular representation is converted to an analog signal,
ratiometric to the supply voltage.
The analog output can be configured in many ways, such as
360°/180°/90° or 45° angular range, external or internal DAC
reference voltage, 0-100%*VDD or 10-90% *VDD analog output
range, external or internal amplifier gain setting.
The various output modes as well as a user programmable zero
position can be programmed in an OTP register. As long as no
programming voltage is applied to pin PROG, the new setting
may be overwritten at any time and will be reset to default when
power is cycled. To make the setting permanent, the OTP
register must be programmed by applying a programming
voltage.
The AS5043 is tolerant to magnet misalignment and unwanted
external magnetic fields due to differential measurement
technique and Hall sensor conditioning circuitry.
It is also tolerant to airgap and temperature variations due to
Sin-/Cos- signal evaluation.
Functional Description
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AS5043 − 3.3V / 5V Operation
The AS5043 operates either at 3.3V ±10% or at 5V ±10%. This is
made possible by an internal 3.3V Low-Dropout (LDO) Voltage
regulator. The core supply voltage is always taken from the LDO
output, as the internal blocks are always operating at 3.3V.
For 3.3V operation, the LDO must be bypassed by connecting
VDD3V3 with VDD5V (see Figure 19).
For 5V operation, the 5V supply is connected to pin VDD5V,
while VDD3V3 (LDO output) must be buffered by a 1 to10μF
capacitor, which should be placed close to the supply pin.
The VDD3V3 output is intended for internal use only. It should
not be loaded with an external load.
The voltage levels of the digital interface I/O’s correspond to
the voltage at pin VDD5V, as the I/O buffers are supplied from
this pin (see Figure 19).
Figure 19:
Connections for 5V / 3.3V Supply Voltages
A buffer capacitor of 100nF is recommended in both cases close
to pin VDD5V. Note that pin VDD3V3 must always be buffered
by a capacitor. It must not be left floating, as this may cause an
instable internal 3.3V supply voltage which may lead to larger
than normal jitter of the measured angle.
3.3V / 5V Operation
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The serial data transmission timing is outlined in Figure 21: if
CSn changes to logic low, Data Out (DO) will change from high
impedance (tri-state) to logic high and the read-out sequence
will be initiated. After a minimum time tCLK FE, data is latched
into the output shift register with the first falling edge of CLK.
Each subsequent rising CLK edge shifts out one bit of data.The
serial word contains 16 bits, the first 10 bits are the angular
information D[9:0], the subsequent 6 bits contain system
information, about the validity of data such as OCF, COF, LIN,
Parity and Magnetic Field status (increase / decrease /
out of range).
A subsequent measurement is initiated by a logic “high” pulse
at CSn with a minimum duration of tCSn. Data transmission
may be terminated at any time by pulling CSn = high.
Serial Data Contents
D9:D0 absolute angular position data (MSB is clocked out first).
OCF (Offset Compensation Finished), logic high indicates that
the Offset Compensation Algorithm has finished and data is
valid.
COF (CORDIC Overflow), logic high indicates an out of range
error in the CORDIC part. When this bit is set, the data at D9:D0
is invalid. The absolute output maintains the last valid angular
value. This alarm may be resolved by bringing the magnet
within the X-Y-Z tolerance limits.
LIN (Linearity Alarm), logic high indicates that the input field
generates a critical output linearity. When this bit is set, the data
at D9:D0 may still be used, but may contain invalid data. This
warning may be resolved by bringing the magnet within the
X-Y-Z tolerance limits.
Data D9:D0 is valid, when the status bits have the following
configurations:
Figure 20:
Status Bit Outputs
OCF COF LIN Mag INC Mag DEC Parity
10 0
00
Even checksum of bits 1:1501
10
10-Bit Absolute Synchronous
Serial Interface (SSI)
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AS5043 − 10-Bit Absolute Synchronous Serial Interface (SSI)
MagInc, (Magnitude Increase) becomes HIGH, when the
magnet is pushed towards the IC, thus the magnetic field
strength is increasing.
MagDec, (Magnitude Decrease) becomes HIGH, when the
magnet is pulled away from the IC, thus the magnetic field
strength is decreasing.
Both signals HIGH indicate a magnetic field that is out of the
allowed range (see Figure 22).
Note(s): Pin 1 (MagRngn) is a combination of MagInc and
MagDec. It is active low via an open drain output and requires
an external pull-up resistor. If the magnetic field is in range, this
output is turned OFF. (logic “high”).
Even Parity bit for transmission error detection of bits 1 …15
(D9 …D0, OCF, COF, LIN, MagInc, MagDec)
The absolute angular output is always set to a resolution of 10
bit / 360°. Placing the magnet above the chip, angular values
increase in clockwise direction by default.
Figure 21:
Synchronous Serial Interface with Absolute Angular Position Data
Even
PAR
CSn
CLK
DO D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
18 16
COF LINOCF Mag
INC
Mag
DEC
t DO active tDO Tristate
1
D9
t CLK FE
t DO valid
t CLK FE
t CSn
T CLK / 2
Angular Position Data Status Bits
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AS5043 − 10-Bit Absolute Synchronous Serial Interface (SSI)
Z-Axis Range Indication (Push Button Feature,
Red/Yellow/Green Indicator)
The AS5043 provides several options of detecting movement
and distance of the magnet in the vertical (Z-) direction. Signal
indicators MagINC, MagDEC and LIN are available as status bits
in the serial data stream, while MagRngn is an open-drain
output that indicates an out-of range status (On in YELLOW or
RED range). Additionally, the analog output provides a safety
feature in the form that it will be turned OFF when the magnetic
field is too strong or too weak (RED range). The serial data is
always available, the red/yellow/green status is indicated by the
status bits as shown below:
Figure 22:
Magnetic Field Strength Indicators
SSI Status Bits Hardware Pins
Description
Mag
INC Mag
DEC LIN Mag
Rngn Analog
Output
0 0 0 OFF Enabled
No distance change
Magnetic Input Field OK (GREEN range,
~45mT … 75mT)
0 1 0 OFF Enabled
Distance increase, GREEN range; Pull-function. This
state is dynamic and only active while the magnet is
moving away from the chip.
1 0 0 OFF Enabled
Distance decrease, GREEN range; Push- function. This
state is dynamic and only active while the magnet is
moving towards the chip.
1 1 0 ON Enabled
YELLOW Range: Magnetic field is ~ 25mT …45mT or
~75mT …135mT. The AS5043 may still be operated in
this range, but with slightly reduced accuracy.
1 1 1 ON Disabled
RED Range: Magnetic field is ~<25mT or >~135mT. The
analog output will be turned OFF in this range by
default. It can be enabled permanently by OTP
programming (see Diagnostic Output Mode).
It is still possible to use the absolute serial interface in
the red range, but not recommended.
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AS5043 − Mode Input Pin
The absolute angular position is sampled at a rate of 10.4kHz
(t=96μs) in fast mode and at a rate of 2.6kHz (t=384μs) in slow
mode.
These modes are selected by pin MODE (#2) during the power
up of the AS5043. This pin activates or deactivates an internal
filter, which is used to reduce the digital jitter and consequently
the analog output noise.
Activating the filter by pulling Mode = LOW reduces the
transition noise to <0.03° rms. At the same time, the sampling
rate is reduced to 2.6kHz and the signal propagation delay is
increased to 384μs. This mode is recommended for high
precision, low speed and ≤360° applications.
Deactivating the filter by setting Mode = HIGH increases the
sampling rate to 10.4kHz and reduces the signal propagation
delay to 96μs. The transition noise will increase to <0.06° rms.
This mode is recommended for higher speed and
full scale= 360° applications.
Switching the MODE pin affects the following parameters:
Figure 23:
Mode Pin Settings
The M ODE pin should be set at power-up. A change of the mode
during operation is not allowed.
Parameter Slow Mode
(Pin MODE = 0) Fast Mode
(Pin MODE = 1)
Sampling rate 2.61 kHz (383μs) 10.42 kHz (95.9μs)
Transition noise (1 sigma) ≤ 0.03° rms ≤ 0.06° rms
Propagation delay 384μs 96μs
Startup time 20ms 80ms
Mode Input Pin
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AS5043 − Daisy Chain Mode
The Daisy Chain mode allows connection of several AS5043’s
in series, while still keeping just one digital input for data
transfer (see “Data IN” in Figure 24 below). This mode is
accomplished by connecting the data output (DO; pin 9) to the
data input (Prog; pin 8) of the subsequent device. An RC filter
must be implemented between each PROG pin of device n and
DO pin of device n+1, to prevent the encoders to enter the
alignment mode, in case of ESD discharge, long cables, or not
conform signal levels or shape. Using the values R=100R and
C=1nF allow a max. CLK frequency of 1MHz on the whole chain.
The serial data of all connected devices is read from the DO pin
of the first device in the chain. The length of the serial bit stream
increases with every connected device, it is
n * (16+1) bits:
e.g. 34 bit for two devices, 51 bit for three devices, etc…
The last data bit of the first device (Parity) is followed by a
dummy bit and the first data bit of the second device (D9), etc…
(see Figure 25).
Figure 24:
Daisy Chain Hardware Configuration
Figure 25:
Daisy Chain Data Transfer Timing Diagram
Daisy Chain Mode
CSn
PROG
DI
CLK
CSn
DO
CLK
CSn
DO
CLK
PROG
CSn
DO
CLK
PROG
100R 100R
1nF 1nF
GND GND GND
MCU AS5043 AS5043 AS5043
Even
PAR
CSn
C LK
D O
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
18 16
COF LINOCF Mag
INC
Mag
DEC
1
tC L K F E
Angu lar P o sition D a ta S tatus Bits
TCL K /2
tD O a c tiv e tDO v a lid
D2
D9 D8 D7
1st D e vic e 2n d Device
3
Angu lar P osition D ata
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AS5043 − Analog Output
The analog output Vout provides an analog voltage that is
proportional to the angle of the rotating magnet and
ratiometric to the supply voltage VDD5V (max.5.5V). It can
source or sink currents up to ±1mA in normal operation (up to
66mA short circuit current).
The analog output block consists of a digital angular range
selector, a 10-bit Digital-to-Analog converter and an OPAMP
buffer stage (see Figure 33).
The digital range selector allows a preselection of the angular
range for 360°,180°,90° or 45° (see Figure 38). Fine-tuning of the
angular range can be accomplished by adjusting the gain of the
OPAMP buffer stage.
The reference voltage for the Digital-to-Analog converter (DAC)
can be taken internally from VDD5V / 2. In this mode, the output
voltage is ratiometric to the supply voltage.
Alternatively, an external DAC reference can be applied at pin
DACref (#9). In this mode, the analog output is ratiometric to
the external reference voltage.
An ON-chip diagnostic feature turns the analog output OFF in
case of an error (broken supply or magnetic field out of range;
see Figure 22).
The DAC output can be accessed directly at pin #10 DACout.
The addition of an OPAMP to the DAC output allows a variety
of user configurable options, such as variable output voltage
ranges and variable output voltage versus angle response. By
adding an external transistor, the analog voltage output can be
buffered to allow output currents up to hundred milliamperes
or more.
Furthermore, the OPAMP can be configured as constant current
source.
As an OTP option, the DAC can be configured to 2 different
output ranges:
a) 0 to 100% VDACref. The reference point may be either taken
from VDD5V/2 or from the external DACref input. The
0%… 100% range allows easy replacement of potentiometers.
Due to the nature of rail-to-rail outputs, the linearity will
degrade at output voltages that are close to the supply rails.
b) 10%… 90% VDACref. This range allows better linearity, as the
OPAMP is not driven to the rails. Furthermore, this mode allows
failure detection, when the analog output voltage is outside of
the normal operating range of 10%… 90%VDD, as in the case
of broken supply or when the magnetic field is out of range and
the analog output is turned OFF.
Analog Output
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AS5043 − Analog Output
Analog Output Voltage Modes
The Analog output voltage modes are programmable by OTP.
Depending on the application, the analog output can be
selected as rail-to-rail output or as clamped output with
10%-90% VDD5V.
The output is ratiometric to the supply voltage (VDD5V), which
can range from 3.0V to 5.5V. If the DAC reference is switched to
an external reference (pin DACref ), the output is ratiometric to
the external reference.
Full Scale Mode
This output mode provides a ratiometric DAC output of (0% to
100%)x Vref1, amplified by the OPAMP stage (default =internal
2x gain, see Figure 33)
Figure 26:
Analog Output, Full Scale Mode (shown for 360°mode)
Note(s):
•In real case the output does not reach 100% Vref, because
of saturation effects of the OPAMP output driver
transistors. Figure 26 describes a linear output voltage
from rail to rail (0V to VDD) over 360°.
•See Figure 38 for further angular range programming
options.
Vref
0° 90° 180° 270° 360°
0V
analog
output
voltage
angle
100%
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AS5043 − Analog Output
Diagnostic Output Mode
Figure 27:
Diagnostic Output Mode
In Diagnostic Output Mode (see Figure 27) the analog output
of the internal DAC ranges from 10% - 90% Vref1. In an error case,
either when the supply is interrupted or when the magnetic
field is in the “red” range, (see Figure 22) the output is switched
to 0V and thus indicates the error condition.
It is possible to enable the analog output permanently (it will
not be switched OFF even if the magnetic field is out of range).
To enable this feature an OTP bit in the factory setting must be
set. The corresponding bit is FS6. See application note
AS5040-20 (Extended features of OTP programming) for further
details. The application note is available for download at the
ams website.
1. Vref = internal: ½ * VDD5V (pin #16) or external: VDACref (pin#9), depending on Ref_extEN bit in OTP (0=int., 1=ext.)
Vref
0° 90° 180
°
270° 360°
0%
analog
output
voltage
angle
100%
90%
10%
normal
operating
area
In an error case, the output
voltage is in the grey area
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AS5043 − Analog Output
The analog and digital outputs will have the following
conditions:
Figure 28:
The Analog and Digital Outputs
Note(s) and/or Footnote(s):
1. Vref = internal: ½ * VDD5V (pin #16) or external: VDACref (pin#9), depending on Ref_extEN bit in OTP (0=int., 1=ext.).
2. VDD = positive supply voltage at receiving side (3.0 – 5.5V).
Status DAC Output Voltage SSI Digital Output
Normal operation 10% - 90% Vref (1) #0 - #1023 (0°-360°), MagRngn = 1
Magnetic field out of range < 10% Vref (1),
DAC output is switched to 0V
#0 - #1023 (0°-360°)
Out of range is signaled in status bits:
MagInc=MagDec=LIN=1, MagRngn= 0
Broken positive power supply
(VOUT pull down resistor at
receiving side)
< 10% VDD (2)
With pull down resistor at DO (receiving
side), all bits read by the SSI will be “0”-s,
indicating a non-valid output
Broken power supply ground
(VOUT pull down resistor at
receiving side)
< 10% VD (2)
Broken positive power supply
(VOUT pull up resistor at
receiving side)
> 90% VDD(2)
Broken power supply ground
(VOUT pull up resistor at
receiving side)
> 90% VDD(2)
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AS5043 − Programming the AS5043
After power-on, programming the AS5043 is enabled with the
rising edge of CSn and Prog = logic high. 16 bit configuration
data must be serially shifted into the OTP register via the
Prog-pin. The first “CCW” bit is followed by the zero position
data (MSB first) and the Analog Output Mode setting as shown
in Figure 38. Data must be valid at the rising edge of CLK (see
Figure 29). Following this sequence, the voltage at pin Prog
must be raised to the programming voltage VPROG (see
Figure 29). 16 CLK pulses (tPROG) must be applied to program
the fuses. To exit the programming mode, the chip must be reset
by a power-on-reset. The programmed data is available after
the next power-up.
Note(s): During the programming process, the transitions in
the programming current may cause high voltage spikes
generated by the inductance of the connection cable. To avoid
these spikes and possible damage to the IC, the connection
wires, especially the signals PROG and VSS must be kept as short
as possible. The maximum wire length between the VPROG
switching transistor and pin PROG (see Figure 31) should not
exceed 50mm (2 inches).
To suppress eventual voltage spikes, a 10nF ceramic capacitor
sho uld be co nne cted close to pin s PROG and VSS. Thi s capacitor
is only required for programming, it is not required for normal
operation. The clock timing tclk must be selected at a proper
rate to ensure that the signal PROG is stable at the rising edge
of CLK (see Figure 29). Additionally, the programming supply
voltage should be buffered with a 10μF capacitor mounted
close to the switching transistor. This capacitor aids in providing
peak currents during programming. The specified
programming voltage at pin PROG is 7.3 –7.5V (see
Programming Conditions). To compensate for the voltage drop
across the VPROG switching transistor, the applied programming
voltage may be set slightly higher (7.5 - 8.0V, see Figure 31).
OTP Register Contents:
CCW Counter Clockwise Bit
•ccw=0 – angular value increases in
clockwise direction
•ccw=1 – angular value increases in
counterclockwise direction
Z [9:0] Programmable Zero / Index Position
FB_intEN OPAMP gain setting: 0=external, 1=internal
RefExtEN DAC reference: 0=internal, 1=external
ClampMd EN Analog output span: 0=0-100%,
1=10-90%*VDD
Output Range
(OR0, OR1)
[1:0]
Analog Output Range Selection
00 = 360°; 01 = 180°; 10 = 90°; 11 = 45°
Programming the AS5043
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AS5043 − Programming the AS5043
Figure 29:
Programming Access – OTP Write Cycle
Figure 30:
Complete OTP Programming Sequence
CCW Z9 Z8 Z7 Z6 Z5 Z4 Z3 Z2 Z1 Z0 FB_int
EN
RefExt
EN
Clamp
Md En
Output
Range1
Analog Modes
Zero Position
tDatain valid
tProg enable
CSn
Prog Output
Range0
1168
CLKPROG
tDatain
tclk
see text
Data
CSn
Prog
CLKPROG
7.5V
VDD
tLoad PROG tPROG finished
Write Data Power OffProgramming Mode
tPROG
tPrgH
VProgOff
tPrgR
0V
116
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AS5043 − Programming the AS5043
Figure 31:
OTP Programming Hardware Connection of AS5043 (shown with AS5043 demoboard)
Zero Position Programming
The AS5043 allows easy assembly of the system, as the actual
angle of the magnet does not need to be considered. By OTP
programming, any position can be assigned as the new
permanent zero position with an accuracy of 0.35° (all modes).
Using the same procedure, the AS5043 can be calibrated to
assign a given output voltage to a given angle. With this
approach, all offset errors (DAC + OPAMP) are also compensated
for the calibrated position.
Essentially, for a given mechanical position, the angular
measurement system is electrically rotated (by changing the
Zero Position value in the OTP register), until the output
matches the desired mechanical position.
The example in Figure 32 below shows a configuration for 5V
supply voltage and 10%-90% output voltage range. It adjusted
by Zero Position Programming to provide an analog output
voltage of 2.0 Volts at an angle of 180°. The slope of the curve
may be further adjusted by changing the gain of the OPAMP
output stage and by selecting the desired angular range
(360°/180°/90°/45°).
USB
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AS5043 − Programming the AS5043
Figure 32:
Zero Position Programming (shown for 360° mode)
Analog Mode Programming
The analog output can be configured in many ways: It consists
of three major building blocks,
•A digital range preselector,
•A 10-bit Digital-to-Analog-Converter (DAC),
•An OP-AMP buffer stage.
In the default configuration (all OTP bits = 0), the analog
output is set for 360° operation, internal DAC reference
(VDD5V/2), external OPAMP gain, 0-100% ratiometric to VDD5V.
Shown below is a typical example for a 0°-360° range, 0-5V
output. The complete application requires only one external
component, a buffer capacitor at VDD3V3 and has only 3
connections VDD, VSS and Vout (connectors 1-3).
Note(s): The default setting for the OPAMP feedback path
is:FB_intEn=0=external. The external resistors Rf and Rg must be
installed. In the programmed state (FB_intEn=1=internal), these
resistors do not need to be installed as the feedback path is internal
(Rf_int and Rg_int).
VDD5V
0° 90° 180° 270° 360°
analog
output
voltage
Mechanical
angle
5V
2V
the output can be electrically rotated to
match a given output voltage to any
mechanical position
0V
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AS5043 − Programming the AS5043
Figure 33:
Analog Output Block Diagram
AS
5043
Range
Selecto
r
OR
1
OR
0
ClampMdEN
0 360
°
0
0 180
°
1
1 90°
0
1 45°
1
10
bit
digital
REF
_
extEN
0=int
DACref
VDD
5
V
+
-
0
-
100% VDD5V
/
2
LDO
3
.
3V VDD
3V3
9
16
15
DACout 10
VOUT 12
R
f
_
int
30k
Rg
_
int
30k
10
bit
analog
FB 11
FB
_
int
EN
1=
int
Gain =
2
x
(
int
)
C
L
<100pF
+
360
°angle0
Vou
VDD
DAC
1=ext
0
=ext
0=
0-
100
% * Vre
f
(
de
f
.)
1=
10-9
0% *
Vref
VDD
5
V
/
2
Vre
f
V
DD
VSS
1
-10µF
7
PROGDO
CLK
CSn
for OTP
prog r a mmin g an d
alignment mode
only . Leav e open
or connect to VSS
if not used
Digital serial
interface
,
10
bit
/
360
°
.
Leave open i f not
used
.CSn and CL
K
may also be tied to
VSS if not used
3
4
6
8
MagRng Mode
Magnetic field range alarm
.
A
ctive
lo
. Leave open or connect to
VSS if not used
Mode pin
.
Default = open
(
low noise
)
OP-
A
mp feedbac k pin
.
Leave open if not used
.
DAC output pin
.
Leave open if not used
External DA C r ef ere nce pi n.
Leave open or connect to
VSS if not used
NC
13
Test pins.
Leave open
NC
5
NC
14
2
1Connect pi ns 15 and
16 fo r VDD=
3.
0
-
3
.6
V
.
Do NOT connect for
VDD =
4.
5
-5.5
V
!
fro
DSP
1
2
3
RLmin
=
4k
7
V
out
V
SS
R
f
Rg
ams Datasheet Page 33
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AS5043 − Programming the AS5043
Angular Range Selector
The Angular Range selector allows a digital pre-selection of the
angular range. The AS5043 can be configured for a full scale
angular range of 45°, 90°, 180° or 360°. In addition, the Output
voltage versus angle response can be fine-tuned by setting the
gain of the OP-AMP with external resistors and the maximum
output voltage can be set in the DAC.
The combination of these options allows to configure the
operation range of the AS5043 for all angles up to 360° and
output voltages up to 5.5V.
The response curve for the analog output is linear for the
selected range (45°/90°/180°/360°). In addition, the slope is
mirrored at 180° for 45°- and 90°- modes and has a step response
at 270° for the 180°-mode. This allows the AS5043 to be used in
a variety of applications. In these three modes, the output
remains at Vout,max and Vout,min to avoid a sudden output
change when the mechanical angle is rotated beyond the
selected analog range. In 360°-mode, a jitter between Vout,max
and Vout,min at the 360° point is also prevented due to a
hysteresis.
Figure 34:
360° Angular Range (default)
0
0°
256
90° 180° 270°
360°
0
angle*)
gg()
1023
512 768 1024
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AS5043 − Programming the AS5043
Figure 37:
45° Angular Range
Figure 38:
Digital Range Selector Programming Option
Note(s) and/or Footnote(s):
1. The resolution on the digital SSI interface is always 10bit (0.35°/step) over 360°, independent on analog mode.
Output
Range1 Output
Range0 Mode Note
00
See Figure 34 (1)
Default mode,
Analog resolution= 10bit (1024 steps) over 360°
Analog step size: 1LSB = 0.35°
01See Figure 35 Analog resolution= 10bit (1024 steps) over 180°
Analog step size: 1LSB = 0.175°
10See Figure 36 Analog resolution= 10bit (1024 steps) over 90°
Analog step size: 1LSB = 0.088°
11See Figure 37 Analog resolution= 9 bit (512 steps) over 45°
Analog step size: 1LSB = 0.088°
0
0° 90° 180°
225° 360°
0
angle
511
256 512
640 1024
128
45°
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AS5043 − Programming the AS5043
Repeated OTP Programming
Although a single AS5043 OTP register bit can be programmed
only once (from 0 to 1), it is possible to program other,
unprogrammed bits in subsequent programming cycles.
However, a bit that has already been programmed should not
be programmed twice. Therefore it is recommended that bits
that are already programmed are set to “0” during a
programming cycle.
Non-Permanent Programming
It is also possible to re-configure the AS5043 in a
non-permanent way by overwriting the OTP register.
This procedure is essentially a “Write Data” sequence (see
Figure 29) without a subsequent OTP programming cycle.
The “Write Data” sequence may be applied at any time during
normal operation. This configuration remains set while the
power supply voltage is above the power-on reset level (see
Electrical System Specifications).
See Application Note AN5000-20 for further information.
Digital-to-Analog Converter (DAC)
The DAC has a resolution of 10bit (1024 steps) and can be
configured for the following options.
Internal or External Reference
The default DAC reference is the voltage at pin #16 (VDD5V)
divided by 2 (see Figure 32). Using this reference, a system that
has an output voltage ratiometric to the supply voltage can be
built.
Optionally, an external reference source, applied at pin#9
(DACref) can be used. This programming option is useful for
applications requiring a precise output voltage that is
independent of supply fluctuations, for current sink outputs or
for applications with a dynamic reference, e.g. attenuation of
audio signals.
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AS5043 − Programming the AS5043
0-100% or 10-90% Full Scale Range
The reference voltage for the DAC is buffered internally. The
recommended range for the external reference voltage is 0.2V
to (VDD3V3 -0.2)V.
The DAC output voltage will be switched to 0V, when the
magnetic field is out of range, when the MagInc and MagDec
indicators are both =1 and the MagRngn-pin (#1) will go low.
The default full scale output voltage range is 0-100%*VDD5V.
Due to limitations in the output stage of an OP-Amp buffer, it
cannot drive the output voltage from 0-100% rail-to-rail.
Without load, the minimum output voltage at 0° will be a few
millivolts higher than 0V and the maximum output voltage will
be slightly lower than VDD5V. With increasing load, the voltage
drops will increase accordingly.
As a programming option, an output range of 10-90%*VDD5V
can be selected. In this mode, there is no saturation at the upper
and lower output voltage limits like in the 0-100% mode and it
allows failure detection as the output voltage will be outside
the 10-90% limits, when the magnetic field is in the “red” range
(Vout=0V, see Figure 22) or when the supply to the chip is
interrupted (Vout=0V or VDD5V).
The unbuffered output of the DAC is accessible at pin #10
(DACout). This output must not be loaded.
OP-AMP Stage
The DAC output is buffered by a non-inverting Op-Amp stage.
The amplifier is supplied by VDD5V (pin #16) and can hence
provide output voltages up to 5V.
By allowing access to the inverting input of the Op-Amp and
with the addition of a few discrete components it can be
configured in many ways, like high current buffer, current sink
output, adjustable angle range, etc...
Per default, the gain of the Op -Amp must be set by two external
resistors (see Figure 22). Optionally, the fixed internal gain
setting (2x) may be programmed by OTP, eliminating the need
for external resistors.
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AS5043 − Programming the AS5043
Output Noise
The noise level at the analog output depends on two states of
the digital angular output:
•The digital angular output value is stable.
In this case, the output noise is the figure given as Vnoise
in OPAMP Output Stage. Note that the noise level is given
for the default gain of 2x For other gains, it must be scaled
accordingly.
•The digital output is at the edge of a step.
In this case, the digital output may jitter between two
adjacent values. The rate of jitter is specified as transition
noise (parameter TN in Electrical System Specifications).
The resulting output noise is calculated by:
where:
Vnoise, Vout = noise level at pin Vout in Vrms
TN = transition noise (in °rms; see Electrical System
Specifications)
VDD5V = Supply voltage VDD5V in V
Vnoise, OPAMP = noise level of OPAMP (OPAMP Output Stage) in
Vrms
Application Examples
See Application Note AN5043-10 for AS5043 Application
Examples.
(EQ1)
Vnoise Vout,TN VDD5V•360
----------------------------------- V noise OPAMP,
+=
ams Datasheet Page 39
[v1-83] 2017-Jul-18 Document Feedback
AS5043 − Analog Readback Mode
Non-volatile programming (OTP) uses on-chip Zener diodes,
which become permanently low resistive when subjected to a
specified reverse current.
The quality of the programming process depends on the
amount of current that is applied during the programming
process (up to 130mA). This current must be provided by an
external voltage source. If this voltage source cannot provide
adequate power, the Zener diodes may not be programmed
properly.
In order to verify the quality of the programmed bits, an analog
level can be read for each Zener diode, giving an indication
whether this particular bit was properly programmed or not.
To put the AS5043 in Analog Readback Mode, a digital sequence
must be applied to pins CSn, PROG and CLK as shown in
Figure 39. The digital level for this pin depends on the supply
configuration (3.3V / 5V Operation).
The second rising edge on CSn (OutpEN) changes pin PROG to
a digital output and the log. high signal at pin PROG must be
removed to avoid collision of outputs (grey area in Figure 39).
The following falling slope of CSn changes pin PROG to an
analog output, providing a reference voltage Vref, that must be
saved as a reference for the calculation of the subsequent
programmed and unprogrammed OTP bits.
Following this step, each rising slope of CLK outputs one bit of
data in the reverse order as during programming. (see
Figure 39: Output Range OR0 and -1, ClampMdEn, RefExtEn,
FB_IntEn, Z0 …Z9, ccw)
During analog readback, the capacitor at pin PROG (see
Figure 31) should be removed to allow a fast readout rate.
The measured analog voltage for each bit must be subtracted
from the previously measured Vref, and the resulting value
gives an indication on the quality of the programmed bit: a
reading of <100mV indicates a properly programmed bit and a
reading of >1V indicates a properly unprogrammed bit.
A reading between 100mV and 1V indicates a faulty bit, which
may result in an undefined digital value, when the OTP is read
at power-up.
Following the 16th clock (after reading bit “ccw”), the chip must
be reset by disconnecting the power supply.
Figure 39:
Analog OTP Register Read
Analog Readback Mode
In te r n al
test bit
digital Vun
p
ro
g
rammed
V
p
ro
g
rammed
CSn
CLK 1 16
PROG
ProgEN
OR1OR0
Analog Readback Data at PROG OutpEN
tLoadProg CLK
A
read
Prog changes to Output
Vref
Power-on-
Reset;
cycle supply
RefExt
EN
Clamp
MdEN Z6 Z5 Z8 Z7 ccw Z9
Page 40 ams Datasheet
Document Feedback [v1-83] 2017-Jul-18
AS5043 − Alignment Mode
The alignment mode simplifies centering the magnet over the
chip to gain maximum accuracy and XY-alignment tolerance.
This electrical centering method allows a wider XY-alignment
tolerance (0.485mm radius) than mechanical
centering(0.25mm radius) as it eliminates the placement
tolerance of the die within the IC package (±0.235mm).
Alignment mode can be enabled with the falling edge of CSn
while Prog = logic high (Figure 40). The Data bits D9-D0 of the
SSI change to a 10-bit displacement amplitude output. A high
value indicates large X or Y displacement, but also higher
absolute magnetic field strength. The magnet is properly
aligned, when the difference between highest and lowest value
over one full turn is at a minimum.
Under normal conditions, a properly aligned magnet will result
in a reading of less than 32 over a full turn.
Stronger magnets or short gaps between magnet and IC may
show values larger than 32. These magnets are still properly
aligned as long as the difference between highest and lowest
value over one full turn is at a minimum.
The MagINC and MagDEC indicators will be = 1 when the
alignment mode reading is < 32. At the same time, hardware
pin MagRngn (#1) will be pulled to VSS.
The Alignment mode can be reset to normal operation mode
by a power-on-reset (cycle power supply) or by a falling edge
of CSn with PROG =low (see Figure 40).
Figure 40:
Enabling the Alignment Mode
Figure 41:
Exiting Alignment Mode
Alignment Mode
AlignMode enabl
e
PROG
CSn
Read-out
via SSI
2μs
min.
2μs
min.
exit AlignMode
PROG
CSn
Read-out
via SSI
ams Datasheet Page 41
[v1-83] 2017-Jul-18 Document Feedback
AS5043 − Choosing the Proper Magnet
Typically the magnet should be 6mm in diameter and ≥2.5mm
in height. Magnetic materials such as rare earth AlNiCo, SmCo5
or NdFeB are recommended.
The magnet’s field strength perpendicular to the die surface
should be verified using a gauss-meter. The magnetic field Bv
at a given distance, along a concentric circle with a radius of
1.1mm (R1), should be in the range of ±45mT to ±75mT. (see
Figure 42).
Figure 42:
Typical Magnet and Magnetic Field Distribution
Choosing the Proper Magnet
N
S
Magnet axis
Vertical field
component
(45…75mT)
0
360
360
Bv
Vertical field
component
R1 concentric circle;
radius 1.1mm
R1
Magnet axis
typ. 6mm diameter
SN
Page 42 ams Datasheet
Document Feedback [v1-83] 2017-Jul-18
AS5043 − Choosing the Proper Magnet
Physical Placement of the Magnet
The best linearity can be achieved by placing the center of the
magnet exactly over the defined center of the IC package as
shown in Figure 43.
Figure 43:
Defined IC Center and Magnet Displacement Radius
1
Defined
center
2.433 mm
2.433 mm
3.9 mm 3.9 mm
A
rea of recommended maximum
magnet misalignment
Rd
ams Datasheet Page 43
[v1-83] 2017-Jul-18 Document Feedback
AS5043 − Choosing the Proper Magnet
Magnet Placement
The magnet’s center axis should be aligned within a
displacement radius Rd of 0.25mm from the defined center of
the IC with reference to the edge of pin #1 (see Figure 43). This
radius includes the placement tolerance of the chip within the
SSOP-16 package (± 0.235mm).
The displacement radius Rd is 0.485mm with reference to the
center of the chip (see Alignment Mode).
The vertical distance should be chosen such that the magnetic
field on the die surface is within the specified limits (see
Figure 42). The typical distance “z” between the magnet and
the package surface is 0.5mm to 1.8mm with the recommended
magnet (6mm x 3mm). Larger gaps are possible, as long as the
required magnetic field strength stays within the defined limits.
A magnetic field outside the specified range may still produce
usable results, but the out-of-range condition will be indicated
by MagINCn (pin 1), which will be pulled low. At this condition,
the angular data is still available over the digital serial interface
(SSI), but the analog output will be turned OFF.
Figure 44:
Vertical Placement of the Magnet
1.282mm ± 0.15mm
0.576mm ± 0.1mm
z
SN
Package surfaceDie surface
Page 44 ams Datasheet
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AS5043 − Simulation Modelling
Figure 45:
Arrangement of Hall Sensor Array on Chip (principle)
With reference to Figure 45, a diametrically magnetized
permanent magnet is placed above or below the surface of the
AS5043. The chip uses an array of Hall sensors to sample the
vertical vector of a magnetic field distributed across the device
package surface. The area of magnetic sensitivity is a circular
locus of 1.1mm radius with respect to the center of the die. The
Hall sensors in the area of magnetic sensitivity are grouped and
configured such that orthogonally related components of the
magnetic fields are sampled differentially.
The differential signal Y1-Y2 will give a sine vector of the
magnetic field. The differential signal X1-X2 will give an
orthogonally related cosine vector of the magnetic field.
The angular displacement (θ) of the magnetic source with
reference to the Hall sensor array may then be modelled by:
The ±0.5° angular error assumes a magnet optimally aligned
over the center of the die and is a result of gain mismatch errors
of the AS5043. Placement tolerances of the die within the
package are ±0.235mm in X and Y direction, using a reference
point of the edge of pin #1 (Figure 45).
Simulation Modelling
(EQ2)
Θarc Y1 Y2–()
X1 X2–()
--------------------------0.5°±
tan=
ams Datasheet Page 45
[v1-83] 2017-Jul-18 Document Feedback
AS5043 − Simulation Modelling
In order to neglect the influence of external disturbing
magnetic fields, a robust differential sampling and ratiometric
calculation algorithm has been implemented. The differential
sampling of the sine and cosine vectors removes any common
mode error due to DC components introduced by the magnetic
source itself or external disturbing magnetic fields. A
ratiometric division of the sine and cosine vectors removes the
need for an accurate absolute magnitude of the magnetic field
and thus accurate Z-axis alignment of the magnetic source.
The recommended differential input range of the magnetic
field strength (B(X1-X2),B(Y1-Y2)) is ±75mT at the surface of the
die. In addition to this range, an additional offset of ±5mT,
caused by unwanted external stray fields is allowed.
The chip will continue to operate, but with degraded output
linearity, if the signal field strength is outside the recommended
range. Too strong magnetic fields will introduce errors due to
saturation effects in the internal preamplifiers. Too weak
magnetic fields will introduce errors due to noise becoming
more dominant.
Page 46 ams Datasheet
Document Feedback [v1-83] 2017-Jul-18
AS5043 − Failure Diagnostics
The AS5043 also offers several diagnostic and failure detection
features:
Magnetic Field Strength Diagnosis
By Software: the MagINC and MagDEC status bits will both be
high when the magnetic field is out of range.
By Hardware: Pin #1 (MagRngn) is a logical NAND-ed
combination of the MagInc and MagDec status bits. It is an
opendrain output and will be turned ON (= low with external
pull-up resistor) when the magnetic field is out of range.
By Hardware: Pin #12 (Vout) is the analog output of the DAC
and OP-Amp. The analog output will be 0V, when the magnetic
field is out of range (all analog modes).
Power Supply Failure Detection
By Software: If the power supply to the AS5043 is interrupted,
the digital data read by the SSI will be all “0”s. Data is only valid,
when bit OCF is high, hence a data stream with all “0”s is invalid.
To ensure adequate low levels in the failure case, a pull-down
resistor (~10kΩ) should be added between pin DO and VSS at
the receiving side.
By Hardware: The MagRngn pin is an open drain output and
requires an external pull-up resistor. In normal operation, this
pin is high ohmic and the output is high. In a failure case, either
when the magnetic field is out of range or the power supply is
missing, this output will become low. To ensure an adequate
low level in case of a broken power supply to the AS5043, the
pull-up resistor (~10kΩ) must be connected to the positive
supply at pin 16 (VDD5V).
Failure Diagnostics
ams Datasheet Page 47
[v1-83] 2017-Jul-18 Document Feedback
AS5043 − Angular Output Tolerances
Accuracy of Digital Outputs
Accuracy is defined as the error between measured angle and
actual angle. It is influenced by several factors:
•The non-linearity of the analog-digital converters,
•Internal gain and mismatch errors,
•Non-linearity due to misalignment of the magnet
As a sum of all these errors, the accuracy with centered
magnet = (Errmax – Errmin)/2 is specified as better than ±0.5
degrees @ 25°C (see Figure 47).
Misalignment of the magnet further reduces the accuracy.
Figure 46 shows an example of a 3D-graph displaying
nonlinearity over XY-misalignment. The center of the square
XY-area corresponds to a centered magnet (see dot in the center
of the graph). The X- and Y- axis extends to a misalignment of
±1mm in both directions. The total misalignment area of the
graph covers a square of 2mm x 2 mm (79mil x 79mil) with a
step size of 100μm.
For each misalignment step, the measurement as shown in
Figure 47 is repeated and the accuracy (Errmax – Errmin)/2 (e.g.
0.25° in Figure 47) is entered as the Z-axis in the 3D-graph.
Angular Output Tolerances
Page 48 ams Datasheet
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AS5043 − Angular Output Tolerances
Accuracy of Analog Output
The analog output has the same accuracy as the digital output
with the addition of the nonlinearities of the DAC and the
OPAMP (±1LSB; see Figure 38 and 0).
Figure 46:
Example of Linearity Error Over XY Misalignment
The maximum non-linearity error on this example is better than
±1 degree (inner circle) over a misalignment radius of ~0.7mm.
For volume production, the placement tolerance of the IC
within the package (±0.235mm) must also be taken into
account.
The total nonlinearity error over process tolerances,
temperature and a misalignment circle radius of 0.25mm is
specified better than ±1.4 degrees.
The magnet used for this measurement was a cylindrical NdFeB
(Bomatec® BMN-35H) magnet with 6mm diameter and 2.5mm
in height.
ams Datasheet Page 49
[v1-83] 2017-Jul-18 Document Feedback
AS5043 − Angular Output Tolerances
Figure 47:
Example of Linearity Error Over 360º
Transition Noise
Transition noise is defined as the jitter in the transition between
two steps.
Due to the nature of the measurement principle (Hall sensors
+ Preamplifier + ADC), there is always a certain degree of noise
involved.
This transition noise voltage results in an angular transition
noise at the outputs. It is specified as 0.06 degrees rms
(1 sigma)2 in fast mode (pin MODE = high) and 0.03 degrees rms
(1 sigma)2 in slow mode (pin MODE = low or open). These values
are the repeatability of an indicated angle at a given mechanical
position.
The transition noise has different implications on the type of
output that is used:
•Absolute Output; SSI Interface:
The transition noise of the absolute output can be reduced
by the user by applying an averaging of readings. An
averaging of 4 readings will reduce the transition noise by
6dB or 50%, e.g. from 0.03°rms to 0.015°rms (1 sigma)2 in
slow mode.
•Analog Output:
Ideally, the analog output should have a jitter that is less
than one digit. In 360° mode, both fast or slow mode may
be selected for adequate low jitter. In 180°, 90° or 45°
mode, where the step sizes are smaller, slow mode should
be selected to reduce the output jitter.
2. Statistically, 1 sigma represents 68.27% of readings, 3 sigma represents 99.73% of readings.
Linearity error with centered magnet [degrees]
1 55 109 163 217 271 325 379 433 487 541 595 649 703 757 811 865 919 973
transition noise
Errmax
Errmin
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
Page 50 ams Datasheet
Document Feedback [v1-83] 2017-Jul-18
AS5043 − Angular Output Tolerances
High Speed Operation
Sampling Rate
The AS5043 samples the angular value at a rate of 10.42k
samples per second (ksps) in fast mode and 2.61ksps in slow
mode.
Consequently, a new reading is performed each 96μs. (fast
mode) or 384μs (slow mode).
At a stationary position of the magnet, this sampling rate
creates no additional error.
Absolute Mode
With the given sampling rates, the number of samples (n) per
turn for a magnet rotating at high speed can be calculated by
for fast mode
for slow mode
In practice, there is no upper speed limit. The only restriction is
that there will be fewer samples per revolution as the speed
increases.
Regardless of the rotational speed, the absolute angular value
is always sampled at the highest resolution.
Figure 48:
Speed Performance
Fast Mode
(Pin Mode = 1) Slow Mode
(Pin Mode = 0 or Open)
610rpm = 1024 samples / turn 610rpm = 256 samples / turn
1220rpm = 512 samples / turn 1220rpm = 128 samples / turn
2441rpm = 256 samples / turn 2441rpm = 64 samples / turn
etc… etc…
(EQ3)
n60
rpm 96μs•
----------------------------=
(EQ4)
n60
rpm 384μs•
-------------------------------=
ams Datasheet Page 51
[v1-83] 2017-Jul-18 Document Feedback
AS5043 − Angular Output Tolerances
Output Delays
The propagation delay is the delay between the time that the
sample is taken until it is available as angular data. This delay
is 96μs in fast mode (pin Mode = high) and 384μs in slow mode
(pin Mode = low or open).
The analog output produces no further delay, the output
voltage will be updated as soon as it is available. Using the SSI
interface for data transmission, an additional delay must be
considered, caused by the asynchronous sampling (0
….1/fsample) and the time it takes the external control unit to
read and process the angular data from the AS5043.
Angular Error Caused by Propagation Delay
A rotating magnet will cause an angular error caused by the
propagation delay. This error increases linearly with speed:
Where:
esampling = angular error [º]
rpm = rotating speed [rpm]
pr.delay = propagation delay [seconds]
Note(s): Since the propagation delay is known, it can be
automatically compensated by the control unit processing the
data from the AS5043.
Internal Timing Tolerance
The AS5043 does not require an external ceramic resonator or
quartz. All internal clock timings for the AS5043 are generated
by an ON-chip RC oscillator. This oscillator is factory trimmed
to ±5% accuracy at room temperature (±10% over full
temperature range). This tolerance influences the ADC
sampling rate:
•Absolute Output; SSI Interface:
A new angular value is updated every
96μs ± 5% (Mode = 1) or
384μs ± 5% (Mode = 0 or open)
(EQ5)
Page 52 ams Datasheet
Document Feedback [v1-83] 2017-Jul-18
AS5043 − Angular Output Tolerances
Temperature
Magnetic Temperature Coefficient
One of the major benefits of the AS5043 compared to linear Hall
sensors is that it is much less sensitive to temperature. While
linear Hall sensors require a compensation of the magnet’s
temperature coefficients, the AS5043 automatically
compensates for the varying magnetic field strength over
temperature. The magnet’s temperature drift does not need to
be considered, as the AS5043 operates with magnetic field
strengths from ±45mT …±75mT.
Example:
A NdFeB magnet has a field strength of 75mT @ -40ºC and a
temperature coefficient of -0.12% per Kelvin. The temperature
change is from -40ºC to 125ºC = 165K.
The magnetic field change is: 165 x -0.12% = -19.8%, which
corresponds to 75mT at -40ºC and 60mT at 125ºC.
The AS5043 can compensate for this temperature related field
strength change automatically, no user adjustment is required.
Accuracy Over Temperature
The influence of temperature in the absolute accuracy is very
low. While the accuracy is ≤ ±0.5º at room temperature, it may
increase to ≤ ±0.9º due to increasing noise at high
temperatures.
Timing Tolerance Over Temperature
The internal RC oscillator is factory trimmed to ±5%. Over
temperature, this tolerance may increase to ±10%. Generally,
the timing tolerance has no influence in the accuracy or
resolution of the system, as it is used mainly for internal clock
generation.
ams Datasheet Page 53
[v1-83] 2017-Jul-18 Document Feedback
AS5043 − Mechanical Data
The internal Hall elements are located in the center of the
package on a circle with a radius of 1 mm.
Figure 49:
Hall Element Positions
Note(s) and/or Footnote(s):
1. All dimensions in mm.
2. Die thickness 381μm nom.
3. Adhesive thickness 30 ± 15μm.
4. Leadframe downset 200 ± 38μm.
5. Leadframe thickness 152±8 μm.
Mechanical Data
Page 54 ams Datasheet
Document Feedback [v1-83] 2017-Jul-18
AS5043 − Package Drawings & Markings
Figure 50:
16-Lead Shrink Small Outline Package SSOP-16
Note(s) and/or Footnote(s):
1. Dimensioning and tolerancing conform to ASME Y14.5M-1994.
2. All dimensions are in millimeters. Angles in degrees.
3. N is the total number of terminals.
Package Drawings & Markings
Symbol Min Typ Max
A 1.73 1.86 1.99
A1 0.05 0.13 0.21
A2 1.68 1.73 1.78
b 0.25 0.315 0.38
c 0.09 - 0.20
D 6.07 6.20 6.33
E 7.65 7.8 7.9
E1 5.2 5.3 5.38
e 0.65
L 0.63 0.75 0.95
L1 1.25 REF
L2 0.25 BSC
R 0.09 - -
Θ 0º 4º 8º
N16
Green
RoHS
ams Datasheet Page 55
[v1-83] 2017-Jul-18 Document Feedback
AS5043 − Package Drawings & Markings
Figure 51:
Package Marking
Figure 52:
Package Code
JEDEC Package Outline Standard:
MO - 150 AC
Thermal Resistance Rth(j-a):
typ. 151 K/W in still air, soldered on PCB
IC's marked with a white dot or the letters
"ES" denote Engineering Samples
YY WW MZZ @
Last two digits of the
manufacturing year Manufacturing week Plant identifier Free choice/
traceability code Sublot identifier
YYWWMZZ
AS5043 @
ams Datasheet Page 57
[v1-83] 2017-Jul-18 Document Feedback
AS5043 − Ordering & Contact Information
Figure 55:
Ordering Information
Buy our products or get free samples online at:
www.ams.com/ICdirect
Technical Support is available at:
www.ams.com/Technical-Support
Provide feedback about this document at:
www.ams.com/Document-Feedback
For further information and requests, e-mail us at:
ams_sales@ams.com
For sales offices, distributors and representatives, please visit:
www.ams.com/contact
Headquarters
ams AG
Tobelbader Strasse 30
8141 Premstaetten
Austria, Europe
Tel: +43 (0) 3136 500 0
Website: www.ams.com
Ordering Code Package Marking Delivery Form Delivery Quantity
AS5043-ASSM SSOP-16 AS5043 Tape & Reel 500 pcs/reel
AS5043-ASST SSOP-16 AS5043 Tape & Reel 2000 pcs/reel
Ordering & Contact Information
Page 58 ams Datasheet
Document Feedback [v1-83] 2017-Jul-18
AS5043 − RoHS Compliant & ams Green Statement
RoHS: The term RoHS compliant means that ams AG products
fully comply with current RoHS directives. Our semiconductor
products do not contain any chemicals for all 6 substance
categories, including the requirement that lead not exceed
0.1% by weight in homogeneous materials. Where designed to
be soldered at high temperatures, RoHS compliant products are
suitable for use in specified lead-free processes.
ams Green (RoHS compliant and no Sb/Br): ams Green
defines that in addition to RoHS compliance, our products are
free of Bromine (Br) and Antimony (Sb) based flame retardants
(Br or Sb do not exceed 0.1% by weight in homogeneous
material).
Important Information: The information provided in this
statement represents ams AG knowledge and belief as of the
date that it is provided. ams AG bases its knowledge and belief
on information provided by third parties, and makes no
representation or warranty as to the accuracy of such
information. Efforts are underway to better integrate
information from third parties. ams AG has taken and continues
to take reasonable steps to provide representative and accurate
information but may not have conducted destructive testing or
chemical analysis on incoming materials and chemicals. ams AG
and ams AG suppliers consider certain information to be
proprietary, and thus CAS numbers and other limited
information may not be available for release.
RoHS Compliant & ams Green
Statement
ams Datasheet Page 59
[v1-83] 2017-Jul-18 Document Feedback
AS5043 − Copyrights & Disclaimer
Copyright ams AG, Tobelbader Strasse 30, 8141 Premstaetten,
Austria-Europe. Trademarks Registered. All rights reserved. The
material herein may not be reproduced, adapted, merged,
translated, stored, or used without the prior written consent of
the copyright owner.
Devices sold by ams AG are covered by the warranty and patent
indemnification provisions appearing in its General Terms of
Trade. ams AG makes no warranty, express, statutory, implied,
or by description regarding the information set forth herein.
ams AG reserves the right to change specifications and prices
at any time and without notice. Therefore, prior to designing
this product into a system, it is necessary to check with ams AG
for current information. This product is intended for use in
commercial applications. Applications requiring extended
temperature range, unusual environmental requirements, or
high reliability applications, such as military, medical
life-support or life-sustaining equipment are specifically not
recommended without additional processing by ams AG for
each application. This product is provided by ams AG “AS IS”
and any express or implied warranties, including, but not
limited to the implied warranties of merchantability and fitness
for a particular purpose are disclaimed.
ams AG shall not be liable to recipient or any third party for any
damages, including but not limited to personal injury, property
damage, loss of profits, loss of use, interruption of business or
indirect, special, incidental or consequential damages, of any
kind, in connection with or arising out of the furnishing,
performance or use of the technical data herein. No obligation
or liability to recipient or any third party shall arise or flow out
of ams AG rendering of technical or other services.
Copyrights & Disclaimer
Page 60 ams Datasheet
Document Feedback [v1-83] 2017-Jul-18
AS5043 − Document Status
Document Status Product Status Definition
Product Preview Pre-Development
Information in this datasheet is based on product ideas in
the planning phase of development. All specifications are
design goals without any warranty and are subject to
change without notice
Preliminary Datasheet Pre-Production
Information in this datasheet is based on products in the
design, validation or qualification phase of development.
The performance and parameters shown in this document
are preliminary without any warranty and are subject to
change without notice
Datasheet Production
Information in this datasheet is based on products in
ramp-up to full production or full production which
conform to specifications in accordance with the terms of
ams AG standard warranty as given in the General Terms of
Trade
Datasheet (discontinued) Discontinued
Information in this datasheet is based on products which
conform to specifications in accordance with the terms of
ams AG standard warranty as given in the General Terms of
Trade, but these products have been superseded and
should not be used for new designs
Document Status
ams Datasheet Page 61
[v1-83] 2017-Jul-18 Document Feedback
AS5043 − Revision Information
Note(s) and/or Footnote(s):
1. Page and figure numbers for the previous version may differ from page and figure numbers in the current revision
2. Correction of typographical errors is not explicitly mentioned.
Changes from 1-82 (2015-Dec-07) to current revision 1-83 (2017-Jul-18) Page
Updated Figure 55 57
Revision Information
Page 62 ams Datasheet
Document Feedback [v1-83] 2017-Jul-18
AS5043 − Content Guide
1 General Description
1 Key Benefits & Features
2 Applications
3 Block Diagram
4 Pin Assignment
5 Pin Description
7Absolute Maximum Ratings
8 Electrical Characteristics
8 Operating Conditions
8 DC Characteristics for Digital Inputs and Outputs
8 CMOS Schmitt-Trigger Inputs: CLK, CSn (Internal
Pull-Up), Mode (Internal Pull-Down)
9 CMOS Input: Program Input (Prog)
9 CMOS Output Open Drain: MagRngn
10 Tristate CMOS Output: DO
10 Digital-to-Analog Converter
11 OPAMP Output Stage
12 Magnetic Input Specification
13 Electrical System Specifications
15 Timing Characteristics
16 Programming Conditions
17 Functional Description
18 3.3V / 5V Operation
19 10-Bit Absolute Synchronous Serial Interface (SSI)
19 Serial Data Contents
21 Z-Axis Range Indication (Push Button Feature, Red/Yel-
low/Green Indicator)
22 Mode Input Pin
23 Daisy Chain Mode
24 Analog Output
25 Analog Output Voltage Modes
25 Full Scale Mode
26 Diagnostic Output Mode
28 Programming the AS5043
30 Zero Position Programming
31 Analog Mode Programming
33 Angular Range Selector
36 Repeated OTP Programming
36 Non-Permanent Programming
36 Digital-to-Analog Converter (DAC)
36 Internal or External Reference
37 0-100% or 10-90% Full Scale Range
37 OP-AMP Stage
38 Output Noise
38 Application Examples
Content Guide
ams Datasheet Page 63
[v1-83] 2017-Jul-18 Document Feedback
AS5043 − Content Guide
39 Analog Readback Mode
40 Alignment Mode
41 Choosing the Proper Magnet
42 Physical Placement of the Magnet
43 Magnet Placement
44 Simulation Modelling
46 Failure Diagnostics
46 Magnetic Field Strength Diagnosis
46 Power Supply Failure Detection
47 Angular Output Tolerances
47 Accuracy of Digital Outputs
48 Accuracy of Analog Output
49 Transition Noise
50 High Speed Operation
50 Sampling Rate
51 Output Delays
51 Angular Error Caused by Propagation Delay
51 Internal Timing Tolerance
52 Temperature
52 Magnetic Temperature Coefficient
52 Accuracy Over Temperature
52 Timing Tolerance Over Temperature
53 Mechanical Data
54 Package Drawings & Markings
56 Recommended PCB Footprint
57 Ordering & Contact Information
58 RoHS Compliant & ams Green Statement
59 Copyrights & Disclaimer
60 Document Status
61 Revision Information
