1
Features
•EE Programmable 262,144 x 1-, 524,288 x 1-, 1,048,576 x 1-, 2,097,152 x 1-, and
4,194,304 x 1-bit Serial Memories Designed to Store Configuration Programs for Field
Programmable Gate Arrays (FPGAs)
•Available as a 3.3V (±10%) Commercial and Industrial Version
•Simple Interface to SRAM FPGAs
•Pin Compatible with Xilinx® XC17SXXXA and XC17SXXXXL PROMs
•Compatible with Xilinx Spartan®-II, Spartan-IIE and Spartan XL FPGAs in Master Serial
Mode
•Very Low-power CMOS EEPROM Process
•Available in 8-lead PDIP, 8-lead SOIC, 20-lead SOIC and 44-lead TQFP Packages for a
Specific Density
•Low-power Standby Mode
•High-reliability
– Endurance: Minimum 10 Write Cycles
– Data Retention: 20 Years at 85°C
Description
The AT17N series FPGA Configuration EEPROM (Configurators) provide an easy-to-
use, cost-effective configuration memory for Field Programmable Gate Arrays. The
AT17N series device is packaged in the 8-lead PDIP, 8-lead SOIC, 20-lead SOIC and
44-lead TQFP, see Table 1. The AT17N series Configurators uses a simple serial-
access procedure to configure one or more FPGA devices.
The AT17N series configurators can be programmed with industry-standard program-
mers, Atmel’s ATDH2200E Programming Kit or Atmel’s ATDH2225 ISP Cable and
factory programming.
Table 1. AT17N Series Packages
Package AT17N256
AT17N512/
AT17N010 AT17N002 AT17N040
8-lead PDIP Yes Yes – –
8-lead SOIC Yes – – –
20-lead SOIC Yes Yes Yes –
44-lead TQFP – – Yes Yes
FPGA
Configuration
Memory
AT17N256
AT17N512
AT17N010
AT17N002
AT17N040
3.3V
System Support
3020C–CNFG–08/07
2AT17N256/512/010/002/040
3020C–CNFG–08/07
Pin Configuration
8-lead SOIC
8-lead PDIP
20-lead SOIC
1
2
3
4
8
7
6
5
DATA
CLK
RESET/OE
CE
VCC
VCC (SER_EN)
DC
GND
1
2
3
4
8
7
6
5
DATA
CLK
RESET/OE
CE
VCC
VCC (SER_EN)
DC
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
DATA
NC
CLK
NC
NC
NC
NC
RESET/OE
NC
CE
VCC
NC
VCC (SER_EN)
NC
NC
NC
NC
DC
NC
GND
3
AT17N256/512/010/002/040
3020C–CNFG–08/07
44 TQFP
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
44
43
42
41
40
39
38
37
36
35
34
12
13
14
15
16
17
18
19
20
21
22
NC
RESET/OE
NC
CE
NC
NC
GND
NC
NC
DC
NC
NC
CLK
NC
NC
DATA
NC
VCC
NC
NC
VCC (SER_EN)
NC
NC
NC
NC
NC
NC
NC
DC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
DC
4AT17N256/512/010/002/040
3020C–CNFG–08/07
Block Diagram
Device Description The control signals for the configuration EEPROM (CE, RESET/OE and CCLK) inter-
face directly with the FPGA device control signals. All FPGA devices can control the
entire configuration process and retrieve data from the configuration EEPROM without
requiring an external intelligent controller.
The configuration EEPROM RESET/OE and CE pins control the tri-state buffer on the
DATA output pin and enable the address counter. When RESET/OE is driven High, the
configuration EEPROM resets its address counter and tri-states its DATA pin. The CE
pin also controls the output of the AT17N series configurator. If CE is held High after the
RESET/OE reset pulse, the counter is disabled and the DATA output pin is tri-stated.
When OE is subsequently driven Low, the counter and the DATA output pin are
enabled. When RESET/OE is driven High again, the address counter is reset and the
DATA output pin is tri-stated, regardless of the state of CE. Upon power-up, the address
counter is automatically reset.
POWER ON
RESET
SER_EN
5
AT17N256/512/010/002/040
3020C–CNFG–08/07
DATA Three-state DATA output for configuration. Open-collector bi-directional pin for
programming.
CLK Clock input. Used to increment the internal address and bit counter for reading and
programming.
RESET/OE Output Enable (active High) and RESET (active Low) when SER_EN is High. A Low
level on RESET/OE resets both the address and bit counters. A High level (with CE
Low) enables the data output driver. The logic polarity of this input is programmable as
either RESET/OE or RESET/OE. For most applications, RESET should be programmed
active Low. This document describes the pin as RESET/OE.
CE Chip Enable input (active Low). A Low level (with OE High) allows CLK to increment the
address counter and enables the data output driver. A High level on CE disables both
the address and bit counters and forces the device into a low-power standby mode.
Note that this pin will not enable/disable the device in the Two-Wire Serial Programming
mode (SER_EN Low).
GND Ground pin. A 0.2 µF decoupling capacitor between VCC and GND is recommended.
VCC(SER_EN)Serial enable must be held High during FPGA loading operations. Bringing SER_EN
Low enables the Two-Wire Serial Programming Mode. For non-ISP applications,
SER_EN should be tied to VCC.
VCC 3.3V (±10%) Commercial and Industrial power supply pin.
NC NC pins are No Connect pins, which are not internally bonded out to the die.
DC DC pins are No Connect pins internally connected to the die. It is not recommended to
connect these pins to any external signal.
Pin Description
Name I/O
AT17N256
AT17N512/
AT17N010 AT17N002 AT17N040
8
DIP/
SOIC
20
SOIC
8
DIP
20
SOIC
20
SOIC
44
TQFP
44
TQFP
DATAI/O111114040
CLKI232334343
RESET/OE I383881313
CE I4 10 4 10101515
GND 5 11 5 11111818
DCO6 13 6 13132121
DCO–––––2323
VCC(SER_EN)I7 18 7 18183535
VCC 8 20 8 20203838
6AT17N256/512/010/002/040
3020C–CNFG–08/07
FPGA Master Serial
Mode Summary
The I/O and logic functions of any SRAM-based FPGA are established by a configura-
tion program. The program is loaded either automatically upon power-up, or on
command, depending on the state of the FPGA mode pins. In Master mode, the FPGA
automatically loads the configuration program from an external memory. The AT17N
Serial Configuration EEPROM has been designed for compatibility with the Master
Serial mode.
This document discusses the master serial mode configuration of Atmel AT17N series
configuration memories, pin compatible with Spartan-II, Spartan-IIE and Spartan XL
OTP PROMs.
Control of
Configuration
Most connections between the FPGA device and the AT17N Serial EEPROM are simple
and self-explanatory.
• The DATA output of the AT17N series configurator drives DIN of the FPGA devices.
• The master FPGA CCLK output drives the CLK input of the AT17N series
configurator.
• SER_EN must be connected to VCC (except during ISP).
•The CE
and OE/Reset are driven by the FPGA to enable output data buffer of the
EEPROM.
Programming Mode The programming mode is entered by bringing SER_EN Low. In this mode the chip can
be programmed by the Two-Wire serial bus. The programming is done at VCC supply
only. Programming super voltages are generated inside the chip.
Standby Mode The AT17N series configurators enter a low-power standby mode whenever CE is
asserted High. In this mode, the AT17N256 configurator consumes less than 50 µA of
current at 3.3V (100 µA for the AT17N512/010 and 200 µA for the AT17N002/040).
7
AT17N256/512/010/002/040
3020C–CNFG–08/07
Absolute Maximum Ratings*
Operating Temperature.................................... -40°C to +85°C*NOTICE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those listed under oper-
ating conditions is not implied. Exposure to Abso-
lute Maximum Rating conditions for extended
periods of time may affect device reliability.
Storage Temperature..................................... -65°C to +150°C
Voltage on Any Pin
with Respect to Ground ..............................-0.1V to VCC +0.5V
Supply Voltage (VCC) ..........................................3.0V to +3.6V
Maximum Soldering Temp. (10 sec. @ 1/16 in.).............260°C
ESD (RZAP = 1.5K, CZAP = 100 pF)................................. 2000V
Operating Conditions
Symbol Description
3.3V
UnitsMin Max
VCC
Commercial Supply voltage relative to GND
-0°C to +70°C3.0 3.6 V
Industrial Supply voltage relative to GND
-40°C to +85°C3.0 3.6 V
8AT17N256/512/010/002/040
3020C–CNFG–08/07
Notes: 1. AC test lead = 50 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady-state active levels.
DC Characteristics
VCC = 3.3V ± 10%
Symbol Description
AT17N256
AT17N512/
AT17N010
AT17N002/
AT17N040
UnitsMin Max Min Max Min Max
VIH High-level Input Voltage 2.0 VCC 2.0 VCC 2.0 VCC V
VIL Low-level Input Voltage 0 0.8 0 0.8 0 0.8 V
VOH
High-level Output Voltage
(IOH = -2.5 mA)
Commercial
2.4 2.4 2.4 V
VOL
Low-level Output Voltage
(IOL = +3 mA) 0.4 0.4 0.4 V
VOH
High-level Output Voltage
(IOH = -2 mA)
Industrial
2.4 2.4 2.4 V
VOL
Low-level Output Voltage
(IOL = +3 mA) 0.4 0.4 0.4 V
ICCA Supply Current, Active Mode 5 5 5 mA
IL
Input or Output Leakage Current
(VIN = VCC or GND) -10 10 -10 10 -10 10 µA
ICCS Supply Current, Standby Mode
Commercial 50 100 150 µA
Industrial 100 100 150 µA
AC Characteristics
VCC = 3.3V ± 10%
Symbol Description
AT17N256 AT17N512/010/002/040
Units
Commercial Industrial Commercial Industrial
Min Max Min Max Min Max Min Max
TOE(1) OE to Data Delay 50 55 50 55 ns
TCE(1) CE to Data Delay 60 60 55 60 ns
TCAC(1) CLK to Data Delay 75 80 55 60 ns
TOH Data Hold from CE, OE, or CLK 0 0 0 0 ns
TDF(2) CE or OE to Data Float Delay 55 55 50 50 ns
TLC CLK Low Time 25 25 25 25 ns
THC CLK High Time 25 25 25 25 ns
TSCE CE Setup Time to CLK
(to guarantee proper counting)
35 60 30 35 ns
THCE CE Hold Time from CLK
(to guarantee proper counting)
0000 ns
THOE OE High Time (guarantees counter is reset) 25 25 25 25 ns
FMAX Maximum Clock Frequency 10 10 15 10 MHz
9
AT17N256/512/010/002/040
3020C–CNFG–08/07
AC Characteristics
CE
RESET/OE
CLK
DATA
TSCE
TLC THC
TCAC
TOE
TCE
TOH
THOE
TSCE THCE
TDF
TOH
10 AT17N256/512/010/002/040
3020C–CNFG–08/07
Notes: 1. For more information refer to the “Thermal Characteristics of Atmel’s Packages”, available on the Atmel web site.
2. Airflow = 0 ft/min.
Thermal Resistance Coefficients(1)
Package Type AT17N256
AT17N512/
AT17N010 AT17N002 AT17N040
8P3 Plastic Dual Inline Package
(PDIP)
θJC [°C/W] 37 37 – –
θJA
[°C/W](2)
107 107 – –
8S1 Plastic Gull Wing Small Outline
(SOIC)
θJC [°C/W] 45 – – –
θJA
[°C/W](2)
150 – – –
20S2 Plastic Gull Wing Small Outline
(SOIC)
θJC [°C/W] –
θJA
[°C/W](2)
–
44A Thin Plastic Quad Flat
Package (TQFP)
θJC [°C/W] – – 17 17
θJA
[°C/W](2)
––6262
11
AT17N256/512/010/002/040
3020C–CNFG–08/07
Figure 1. Ordering Code
Package Type
8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
20S2 20-lead, 0.300" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
44A 44-lead, Thin (1.0 mm) Plastic Quad Flat Package Carrier (TQFP)
Temperature
C = Commercial
I = Industrial
Size (Bits)
256= 256K
512 = 512K
010 = 1M
002 = 2M
040 = 4M
Package
=
8
P
3= 8P3
= 8S1
= 44A
P
N
S
TQ
= 20S2
Voltage
3.3V
+
10%
-
AT17N256-10PC
12 AT17N256/512/010/002/040
3020C–CNFG–08/07
Notes: 1. For the -10CC and -10CI packages, customers may migrate to AT17LVXXX-10CU.
Ordering Information
Memory Size Ordering Code Package Operation Range
256-Kbit
AT17N256-10PC 8P3 Commercial
(0°C to 70°C)
AT17N256-10NC 8S1
AT17N256-10SC 20S2
AT17N256-10PI 8P3 Industrial
(-40°C to 85°C)
AT17N256-10NI 8S1
AT17N256-10SI 20S2
512-Kbit
AT17N512-10SC 20S2 Commercial
(0°C to 70°C)
AT17N512-10SI 20S2 Industrial
(-40°C to 85°C)
1-Mbit
AT17N010-10SC 20S2 Commercial
(0°C to 70°C)
AT17N010-10SI 20S2 Industrial
(-40°C to 85°C)
2-Mbit
AT17N002-10SC 20S2 Commercial
(0°C to 70°C)
AT17N002-10TQC 44A
AT17N002-10SI 20S2 Industrial
(-40°C to 85°C)
AT17N002-10TQI 44A
4-Mbit
AT17N040-10TQC 44A Commercial
(0°C to 70°C)
AT17N040-10TQI 44A Industrial
(-40°C to 85°C)
13
AT17N256/512/010/002/040
3020C–CNFG–08/07
Packaging Information
8P3 – PDIP
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)
01/09/02
8P3 B
D
D1
E
E1
e
L
b2
b
A2 A
1
N
eA
c
b3
4 PLCS
Top View
Side View
End View
COMMON DIMENSIONS
(Unit of Measure = inches)
SYMBOL MIN NOM MAX NOTE
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
A 0.210 2
A2 0.115 0.130 0.195
b 0.014 0.018 0.022 5
b2 0.045 0.060 0.070 6
b3 0.030 0.039 0.045 6
c 0.008 0.010 0.014
D 0.355 0.365 0.400 3
D1 0.005 3
E 0.300 0.310 0.325 4
E1 0.240 0.250 0.280 3
e 0.100 BSC
eA 0.300 BSC 4
L 0.115 0.130 0.150 2
14 AT17N256/512/010/002/040
3020C–CNFG–08/07
8S1 – SOIC
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TITLE DRAWING NO.
R
REV.
Note:
3/17/05
8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
Small Outline (JEDEC SOIC) 8S1C
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A1 0.10 – 0.25
These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.
Ø
Ø
E
E
1
1
N
N
TOP VIEW
C
C
E1
E1
END VIEW
A
A
b
b
L
L
A1
A1
e
e
D
D
SIDE VIEW
15
AT17N256/512/010/002/040
3020C–CNFG–08/07
20S2 – SOIC
16 AT17N256/512/010/002/040
3020C–CNFG–08/07
44A – TQFP
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
44A, 44-lead, 10 x 10 mm Body Size, 1.0 mm Body Thickness,
0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) B
44A
10/5/2001
PIN 1 IDENTIFIER
0˚~7˚
PIN 1
L
C
A1 A2 A
D1
D
eE1 E
B
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
3. Lead coplanarity is 0.10 mm maximum.
A – – 1.20
A1 0.05 – 0.15
A2 0.95 1.00 1.05
D 11.75 12.00 12.25
D1 9.90 10.00 10.10 Note 2
E 11.75 12.00 12.25
E1 9.90 10.00 10.10 Note 2
B 0.30 – 0.45
C 0.09 – 0.20
L 0.45 – 0.75
e 0.80 TYP
17
AT17N256/512/010/002/040
3020C–CNFG–08/07
Revision History
Revision Level – Release Date History
B – March 2006 Added last-time buy for AT17NXXX-10CC and AT17NXXX-10CI.
C – August 2007 Removed 8CN4 8-lead LAP package.
3020C–CNFG–08/07
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