1
Motorola Small–Signal Transistors, FETs and Diodes Device Data
N–Channel
MAXIMUM RATINGS
Rating Symbol Value Unit
Drain–Source Voltage VDS 30 Vdc
Drain–Gate Voltage VDG 30 Vdc
Gate–Source Voltage VGS 30 Vdc
Forward Gate Current IG(f) 50 mAdc
THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
Total Device Dissipation FR–5 Board(1)
TA = 25°C
Derate above 25°C
PD225
1.8
mW
mW/°C
Thermal Resistance, Junction to Ambient R
q
JA 556 °C/W
Junction and Storage Temperature TJ, Tstg –55 to +150 °C
DEVICE MARKING
MMBF4391LT1 = 6J; MMBF4392LT1 = 6K; MMBF4393LT1 = 6G
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Characteristic Symbol Min Max Unit
OFF CHARACTERISTICS
Gate–Source Breakdown Voltage
(IG = 1.0 µAdc, VDS = 0) V(BR)GSS 30 — Vdc
Gate Reverse Current
(VGS = 15 Vdc, VDS = 0, TA = 25°C)
(VGS = 15 Vdc, VDS = 0, TA = 100°C)
IGSS —
—1.0
0.20 nAdc
µAdc
Gate–Source Cutoff V oltage
(VDS = 15 Vdc, ID = 10 nAdc) MMBF4391LT1
MMBF4392LT1
MMBF4393LT1
VGS(off) –4.0
–2.0
–0.5
–10
–5.0
–3.0
Vdc
Off–State Drain Current
(VDS = 15 Vdc, VGS = –12 Vdc)
(VDS = 15 Vdc, VGS = –12 Vdc, TA = 100°C)
ID(off) —
—1.0
1.0 nAdc
µAdc
1. FR–5 = 1.0
0.75
0.062 in.
Thermal Clad is a trademark of the Bergquist Company
Order this document
by MMBF4391LT1/D
SEMICONDUCTOR TECHNICAL DATA
12
3
CASE 318–08, STYLE 10
SOT–23 (T O–236AB)
Motorola, Inc. 1997
2 SOURCE
3
GATE
1 DRAIN
2 Motorola Small–Signal Transistors, FETs and Diodes Device Data
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) (Continued)
Characteristic Symbol Min Max Unit
ON CHARACTERISTICS
Zero–Gate–Voltage Drain Current
(VDS = 15 Vdc, VGS = 0) MMBF4391LT1
MMBF4392LT1
MMBF4393LT1
IDSS 50
25
5.0
150
75
30
mAdc
Drain–Source On–V oltage
(ID = 12 mAdc, VGS = 0) MMBF4391LT1
(ID = 6.0 mAdc, VGS = 0) MMBF4392LT1
(ID = 3.0 mAdc, VGS = 0) MMBF4393LT1
VDS(on) —
—
—
0.4
0.4
0.4
Vdc
Static Drain–Source On–Resistance
(ID = 1.0 mAdc, VGS = 0) MMBF4391LT1
MMBF4392LT1
MMBF4393LT1
rDS(on) —
—
—
30
60
100
Ω
SMALL–SIGNAL CHARACTERISTICS
Input Capacitance
(VDS = 15 Vdc, VGS = 0, f = 1.0 MHz) Ciss —14 pF
Reverse T ransfer Capacitance
(VDS = 0, VGS = 12 Vdc, f = 1.0 MHz) Crss —3.5 pF
TYPICAL CHARACTERISTICS
TJ = 25
°
C
ID, DRAIN CURRENT (mA)
, TURN–ON DELAY TIME (ns)
d(on)
t
5.0
2.0
20
10
0.5 1.0 3.0 7.0
5.0
1.0
50
100
0.7 2.0 10 20 ID, DRAIN CURRENT (mA)
, RISE TIME (ns)
r
t
Figure 1. Turn–On Delay Time Figure 2. Rise Time
RK = RD’
RK = 0
RK = RD’
RK = 0
ID, DRAIN CURRENT (mA)
, TURN–OFF DELAY TIME (ns)
d(off)
t
Figure 3. Turn–Off Delay Time
RK = RD’
RK = 0
ID, DRAIN CURRENT (mA)
Figure 4. Fall Time
RK = RD’
RK = 0
, FALL TIME (ns)
f
t
MMBF4391
MMBF4392
MMBF4393
30 50
200
500
1000
0.5 1.0 3.0 7.0
5.0
0.7 2.0 10 20 30 50
5.0
2.0
20
10
1.0
50
100
200
500
1000
0.5 1.0 3.0 7.0
5.0
0.7 2.0 10 20 30 500.5 1.0 3.0 7.0
5.0
0.7 2.0 10 20 30 50
5.0
2.0
20
10
1.0
50
100
200
500
1000
5.0
2.0
20
10
1.0
50
100
200
500
1000
TJ = 25
°
C
MMBF4391
MMBF4392
MMBF4393
TJ = 25
°
C
MMBF4391
MMBF4392
MMBF4393
TJ = 25
°
C
MMBF4391
MMBF4392
MMBF4393
VGS(off) = 12 V
= 7.0 V
= 5.0 V
VGS(off) = 12 V
= 7.0 V
= 5.0 V
VGS(off) = 12 V
= 7.0 V
= 5.0 V
VGS(off) = 12 V
= 7.0 V
= 5.0 V
3
Motorola Small–Signal Transistors, FETs and Diodes Device Data
Figure 5. Switching Time Test Circuit
Figure 6. Typical Forward Transfer Admittance Figure 7. Typical Capacitance
ID, DRAIN CURRENT (mA)
2.0
5.0
3.0
7.0
0.5 1.0 3.0 7.05.0 5030
10
20
0.7 2.0 10 20
, FORWARD TRANSFER ADMITTANCE (mmhos)
fs
V
10
2.0
15
3.0
5.0
7.0
0.5 1.0 3.0 305.00.30.1 100.050.03 VR, REVERSE VOLTAGE (VOLTS)
C, CAPACITANCE (pF)
Tchannel = 25
°
C
VDS = 15 V Tchannel = 25
°
C
(Cds is negligible
Cgs
–VDD
VGG
RGG
RT
RGEN
50
Ω
VGEN
RK
RD
OUTPUT
INPUT
50
Ω
50
Ω
SET VDS(off) = –10 V
INPUT PULSE
tr
≤
0.25 ns
tf
≤
0.5 ns
PULSE WIDTH = 2.0
µ
s
DUTY CYCLE
≤
2.0%
RGG > RK
RD’ = RD(RT + 50)
RD + RT + 50
Figure 8. Effect of Gate–Source Voltage
on Drain–Source Resistance
80
120
160
200
50
1.0 3.0 170
5.0 20–10–40
2.0 80 140–70
VGS, GATE–SOURCE VOLTAGE (VOLTS)
r
4.00
40
100 mA 125 mA
75 mA50 mA
25 mA
IDSS
= 10
mA
Tchannel = 25
°
C
Figure 9. Effect of Temperature on Drain–Source
On–State Resistance
1.8
1.0
2.0
1.2
1.4
1.6
0.8
0.6
0.4
ID = 1.0 mA
VGS = 0
, DRAIN–SOURCE ON–STA TE
DS(on)
RESIST ANCE (NORMALIZED)
Tchannel, CHANNEL TEMPERATURE (
°
C)
1.5
1.0
Cgd
110
6.0 7.0 8.0
0
r , DRAIN–SOURCE ON–STA TE
DS(on) RESISTANCE (OHMS)
MMBF4393
MMBF4392 MMBF4391
NOTE 1
The switching characteristics shown above were measured using a test
circuit similar to Figure 5. At the beginning of the switching interval, the
gate voltage is at Gate Supply Voltage (–VGG). The Drain–Source Voltage
(VDS) is slightly lower than Drain Supply Voltage (VDD) due to the voltage
divider. Thus Reverse Transfer Capacitance (Crss) of Gate–Drain Capaci-
tance (Cgd) is charged to VGG + VDS.
During the turn–on interval, Gate–Source Capacitance (Cgs) discharges
through the series combination of RGen an d RK. Cgd must discharge to
VDS(on) through RG an d RK in series with the parallel combination of effec-
tive load impedance (R’D) and Drain–Source Resistance (rDS). During the
turn–off, this charge flow is reversed.
Predicting turn–on time is somewhat difficult as the channel resistance
rDS is a function of the gate–source voltage. While Cgs discharges, VGS
approaches zero and rDS decreases. Since Cgd discharges through rDS,
turn–on time is non–linear. During turn–off, the situation is reversed with
rDS increasing as Cgd charges.
The above switching curves show two impedance conditions; 1) RK is
equal to RD’ which simulates the switching behavior of cascaded stages
where the driving source impedance is normally the load impedance of the
previous stage, and 2) RK = 0 (low impedance) the driving source imped-
ance is that of the generator.
4 Motorola Small–Signal Transistors, FETs and Diodes Device Data
Figure 10. Effect of IDSS on Drain–Source
Resistance and Gate–Source Voltage
IDSS, ZERO–GATE VOLT AGE DRAIN CURRENT (mA)
, DRAIN–SOURCE ON–STA TE
DS(on)
r
20
10
30
40
50
30 40 50 60 70
20
RESISTANCE (OHMS)
010 0
1.0
2.0
3.0
4.0
5.0
, GATE–SOURCE VOLTAGE
GS
V(VOLTS)
Tchannel = 25
°
C
VGS(off)
rDS(on) @ VGS = 0 6.0
7.0
8.0
9.0
10
70
60
80
90
100
80 90 100 110 120 130 140 150
NOTE 2
The Zero–Gate–Voltage Drain Current (IDSS) is the principle determi-
nant of other J–FET characteristics. Figure 10 shows the relationship
of Gate–Source Off Voltage (VGS(off)) and Drain–Source On Resis-
tance (rDS(on)) to IDSS. Most of the devices will be within
±
10% of the
values shown in Figure 10. This data will be useful in predicting the
characteristic variations for a given part number .
For example:
Un kn own
rDS(on) and VGS range for an MMBF4392
The electrical characteristics table indicates that an MMBF4392
has an IDSS range of 25 to 75 mA. Figure 10 shows rDS(on) = 52
Ohms for IDSS = 25 mA and 30 Ohms for IDSS = 75 mA. The corre-
sponding VGS values are 2.2 volts and 4.8 volts.
5
Motorola Small–Signal Transistors, FETs and Diodes Device Data
INFORMATION FOR USING THE SOT–23 SURFACE MOUNT PACKAGE
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the total
design. The footprint for the semiconductor packages must
be the correct size to insure proper solder connection
interface between the board and the package. With the
correct pad geometry, the packages will self align when
subjected to a solder reflow process.
SOT–23
mm
inches
0.037
0.95
0.037
0.95
0.079
2.0
0.035
0.9
0.031
0.8
SOT–23 POWER DISSIPATION
The power dissipation of the SOT–23 is a function of the
pad size. This can vary from the minimum pad size for
soldering to a pad size given for maximum power dissipation.
Power dissipation for a surface mount device is determined
by TJ(max), the maximum rated junction temperature of the
die, RθJA, the thermal resistance from the device junction to
ambient, and the operating temperature, TA. Using the
values provided on the data sheet for the SOT–23 package,
PD can be calculated as follows:
PD = TJ(max) – TA
RθJA
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values into
the equation for an ambient temperature T A of 25°C, one can
calculate the power dissipation of the device which in this
case is 225 milliwatts.
PD = 150°C – 25°C
556°C/W = 225 milliwatts
The 556°C/W for the SOT–23 package assumes the use
of the recommended footprint on a glass epoxy printed circuit
board to achieve a power dissipation of 225 milliwatts. There
are other alternatives to achieving higher power dissipation
from the SOT–23 package. Another alternative would be to
use a ceramic substrate or an aluminum core board such as
Thermal Clad. Using a board material such as Thermal
Clad, an aluminum core board, the power dissipation can be
doubled using the same footprint.
SOLDERING PRECAUTIONS
The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within a
short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.
•Always preheat the device.
•The delta temperature between the preheat and
soldering should be 100°C or less.*
•When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering method,
the difference shall be a maximum of 10°C.
•The soldering temperature and time shall not exceed
260°C for more than 10 seconds.
•When shifting from preheating to soldering, the
maximum temperature gradient shall be 5°C or less.
•After soldering has been completed, the device should
be allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and result
in latent failure due to mechanical stress.
•Mechanical stress or shock should not be applied during
cooling.
* Soldering a device without preheating can cause excessive
thermal shock and stress which can result in damage to the
device.
6 Motorola Small–Signal Transistors, FETs and Diodes Device Data
PACKAGE DIMENSIONS
DJ
K
L
A
C
BS
H
GV
3
12
CASE 318–08
ISSUE AE
SOT–23 (TO–236AB)
DIM
AMIN MAX MIN MAX
MILLIMETERS
0.1102 0.1197 2.80 3.04
INCHES
B0.0472 0.0551 1.20 1.40
C0.0350 0.0440 0.89 1.11
D0.0150 0.0200 0.37 0.50
G0.0701 0.0807 1.78 2.04
H0.0005 0.0040 0.013 0.100
J0.0034 0.0070 0.085 0.177
K0.0180 0.0236 0.45 0.60
L0.0350 0.0401 0.89 1.02
S0.0830 0.0984 2.10 2.50
V0.0177 0.0236 0.45 0.60
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH THICKNESS. MINIMUM LEAD THICKNESS
IS THE MINIMUM THICKNESS OF BASE
MATERIAL.
STYLE 10:
PIN 1. DRAIN
2. SOURCE
3. GATE
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
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applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
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and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
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Opportunity/Af firmative Action Employer.
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