Equator Hardware Reference MAP-CA DSP Datasheet Equator Technologies, Inc. June 20, 2001 Document Number: HWR.CA.DS.2001.06.20 Equator Hardware Reference MAP-CA DSP Datasheet June 20, 2001 Copyright (c) 2000 - 2001 Equator Technologies, Inc., and Hitachi, Ltd. Equator makes no warranty for the use of its products, assumes no responsibility for any errors which may appear in this document, and makes no commitment to update the information contained herein. Equator reserves the right to change or discontinue this product at any time, without notice. There are no express or implied licenses granted hereunder to design or fabricate any integrated circuits based on information in this document. The following are trademarks of Equator Technologies, Inc., and may be used to identify Equator products only: Equator, MAP, MAP1000, MAP1000A, MAP-CA, MAP Series, Broadband Signal Processor, BSP, FIRtree, DataStreamer, DS, iMMediaC, iMMediaTools, iMMediaToolsLite, Media Intrinsics, VersaPort, SofTV, StingRay, Equator Around, and the Equator Around logo. Other product and company names contained herein may be trademarks of their respective owners. The MAP-CA digital signal processor was jointly developed by Equator Technologies, Inc., and Hitachi, Ltd. i Type style conventions With the exception of section and subsection headings, the formatting of text in the following document adheres to the following conventions: Normal descriptive text is presented in Times New Roman font. Italicized Times New Roman text is used for document titles. Underlined Times New Roman text is used for emphasis in normal descriptive text. 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MAP-CA DSP Datasheet June 20, 2001 ii MAP-CA DSP Datasheet June 20, 2001 Hitachi, Ltd. iii Table of Contents Introduction to the MAP-CA Digital Signal Processor Chip ..........................................xi Chapter 1 Architecture Overview .......................................................................................... 1 1.1 The VLIW Core.................................................................................................................... 2 1.1.1 Execution Units............................................................................................................. 2 1.1.1.1 I-ALU.................................................................................................................... 3 1.1.1.2 IG-ALU ................................................................................................................. 3 1.1.1.3 Simple Interlocks .................................................................................................. 3 1.1.1.4 Extensive Predication............................................................................................ 3 1.1.2 Register Resources........................................................................................................ 3 1.1.2.1 Global Registers .................................................................................................... 3 1.1.2.2 Breakpoint Registers ............................................................................................. 3 1.1.2.3 General Registers .................................................................................................. 3 1.1.2.4 Predicate Registers ................................................................................................ 3 1.1.2.5 PLC/PLV 128-bit registers.................................................................................... 4 1.2 Interrupts and Exceptions ..................................................................................................... 4 1.2.1 Core Interrupts and Exceptions..................................................................................... 4 1.2.2 Interrupt Controller ....................................................................................................... 4 1.3 Timers................................................................................................................................... 5 1.4 Memory Hierarchy ............................................................................................................... 5 1.4.1 Caches........................................................................................................................... 5 1.4.2 Address Translation ...................................................................................................... 5 1.5 Databuses and Controllers .................................................................................................... 6 1.5.1 Memory Interface Controller ........................................................................................ 6 1.5.2 Data Transfer Switch (DTS) ......................................................................................... 6 1.5.3 DataStreamer DMA Controller..................................................................................... 6 1.5.4 PCI Bus ......................................................................................................................... 6 1.5.5 I/O Bus.......................................................................................................................... 7 1.6 Coprocessors......................................................................................................................... 7 1.6.1 VLx ............................................................................................................................... 7 1.6.2 Video Filter ................................................................................................................... 7 1.6.3 DES Module ................................................................................................................. 7 1.7 I/O Interfaces ........................................................................................................................ 8 1.7.1 Audio Interfaces............................................................................................................ 8 1.7.1.1 IEC958 Audio Interface ........................................................................................ 8 1.7.1.2 I2S Interface .......................................................................................................... 8 1.7.2 Video Interfaces............................................................................................................ 8 1.7.2.1 Transport Channel Interfaces ................................................................................ 8 Equator Technologies, Inc. MAP-CA DSP Datasheet June 20, 2001 iv 1.7.2.2 ITU-656 Input Interface ........................................................................................ 8 1.7.2.3 ITU-656 Output Interface ..................................................................................... 8 1.7.2.4 General Purpose Data Port (GPDP) ...................................................................... 8 1.7.3 Display Refresh Controller ........................................................................................... 9 1.7.4 DACs ............................................................................................................................ 9 1.7.5 I2C Interface Unit ....................................................................................................... 10 1.7.6 ROM Controller.......................................................................................................... 10 1.7.7 Reset Strap .................................................................................................................. 10 2.1 The C Compiler .................................................................................................................. 11 2.1.1 The FIRtree Media Intrinsics Extensions ................................................................... 11 2.2 Libraries.............................................................................................................................. 11 Chapter 2 Software Development ........................................................................................ 11 2.3 2.4 2.5 2.6 2.7 Assembler ........................................................................................................................... 12 Linker ................................................................................................................................. 12 Debugger ............................................................................................................................ 12 Simulators........................................................................................................................... 12 Boot .................................................................................................................................... 12 Chapter 3 BGA PIN_OUT Assignments............................................................................ 13 Chapter 4 Signal Descriptions............................................................................................... 17 4.1 Interface Summary ............................................................................................................. 17 4.2 Legend ................................................................................................................................ 18 4.3 Processor Clock .................................................................................................................. 18 4.4 SDRAM .............................................................................................................................. 19 4.5 PCI Bus............................................................................................................................... 20 4.6 IEC958................................................................................................................................ 22 2 4.7 I S ...................................................................................................................................... 22 4.8 Multi-Function Signal Pins................................................................................................. 23 4.8.1 Transport Channel Interfaces (TCI)............................................................................ 24 4.8.2 ITU-656 Inputs ........................................................................................................... 25 4.8.3 ITU-656 Output .......................................................................................................... 25 4.8.4 General Purpose Data Port (GPDP)............................................................................ 26 4.8.5 Flash ROM.................................................................................................................. 26 4.8.6 Reset Straps................................................................................................................. 27 4.9 Analog CRT........................................................................................................................ 28 2 4.10 I C.................................................................................................................................... 28 4.11 Boundary Scan (JTAG) .................................................................................................... 29 4.11.1 Pull Up Resistors ...................................................................................................... 29 4.11.2 TAP State Machine................................................................................................... 29 4.11.3 Instruction Registers ................................................................................................. 30 4.11.4 Test Data Registers ................................................................................................... 31 4.11.5 Boundary Scan Register............................................................................................ 31 4.11.6 Device Identification Register .................................................................................. 31 MAP-CA DSP Datasheet June 20, 2001 Hitachi, Ltd. v 4.12 Power/Ground Pins........................................................................................................... 32 4.13 Signal List Summary ........................................................................................................ 33 Chapter 5 External Connection Examples ......................................................................... 35 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 SDRAM ............................................................................................................................. 35 IEC958................................................................................................................................ 38 2 I S ...................................................................................................................................... 39 Transport Channel Interface (TCI) ..................................................................................... 40 NTSC Decoder ................................................................................................................... 41 NTSC Encoder.................................................................................................................... 41 CRT .................................................................................................................................... 42 2 I C...................................................................................................................................... 42 ROM ................................................................................................................................... 43 Chapter 6 Electrical Specifications ...................................................................................... 45 6.1 Absolute Maximum Ratings............................................................................................... 45 6.2 Power Supply Specifications .............................................................................................. 45 6.3 DC Characteristics ............................................................................................................. 46 6.4 AC Characteristics.............................................................................................................. 48 6.4.1 PLL Reference Clock Input ....................................................................................... 48 6.4.2 SDRAM Interface Timing .......................................................................................... 49 6.4.3 PCI Bus Timing .......................................................................................................... 50 6.4.4 IEC958 Interface Timing ............................................................................................ 52 6.4.5 I2S Interface Timing ................................................................................................... 52 6.4.6 Transport Channel Interface Timing........................................................................... 55 6.4.7 ITU-R BT.601/656 Interface Timing.......................................................................... 56 6.4.8 General Purpose Data Port.......................................................................................... 57 6.4.9 I2C Interface Timing................................................................................................... 58 Appendix A Glossary .............................................................................................................. 61 Appendix B Package Specifications .................................................................................... 63 B.1 Mechanical Specifications ................................................................................................. 63 B.1.1 Outline and Footprint ................................................................................................. 63 B.1.1.1 Top and Bottom Views....................................................................................... 63 B.1.1.2 Side View ........................................................................................................... 64 B.2 Package Materials .............................................................................................................. 64 B.2.1 Materials Specification............................................................................................... 64 B.2.2 Index Location ........................................................................................................... 65 Equator Technologies, Inc. MAP-CA DSP Datasheet June 20, 2001 vi MAP-CA DSP Datasheet June 20, 2001 Hitachi, Ltd. vii List of Tables Table 1-1: System Events................................................................................................................ 4 Table 1-2: Operation Events ........................................................................................................... 4 Table 1-3: Supported Interrupts ...................................................................................................... 5 Table 3-1: Pin Assignments .......................................................................................................... 13 Table 4-1: Processor Clock Signal Description ............................................................................ 18 Table 4-2: Memory Interface Signals............................................................................................ 19 Table 4-3: PCI Interface Signals ................................................................................................... 20 Table 4-4: IEC958 Interface Signals ............................................................................................. 22 Table 4-5: I2S Interface Signals .................................................................................................... 22 Table 4-6: Multiple Signal Pins .................................................................................................... 23 Table 4-7: Primary TCI Interface Signals ..................................................................................... 24 Table 4-8: Secondary TCI Interface Signals ................................................................................. 24 Table 4-9: Primary ITU-R BT.601/656 Input Interface Signals ................................................... 25 Table 4-10: Secondary ITU-R BT.601/656 Input Interface Signals ............................................. 25 Table 4-11: ITU-R BT.601/656 Output Interface Signals ............................................................ 25 Table 4-12: GPDP Interface Signals ............................................................................................. 26 Table 4-14: Reset Straps ............................................................................................................... 27 Table 4-13: ROM Interface Signals .............................................................................................. 27 Table 4-15: CRT Interface Signals................................................................................................ 28 Table 4-16: I2C Interface Signals.................................................................................................. 28 Table 4-17: JTAG Interface Signals.............................................................................................. 29 Table 4-18: JTAG Instructions...................................................................................................... 30 Table 4-19: Power/Ground Pins.................................................................................................... 32 Table 4-20: MAP-CA DSP Pin List.............................................................................................. 33 Table 6-1: Absolute Maximum Ratings ........................................................................................ 45 Table 6-2: Voltage Variation......................................................................................................... 45 Table 6-3: Steady State Current .................................................................................................... 46 Table 6-4: PCI Signals ................................................................................................................. 46 Table 6-6: Temperature Rating ..................................................................................................... 47 Table 6-7: Video DAC Outputs .................................................................................................... 47 Table 6-5: Non-PCI Signals .......................................................................................................... 47 Table 6-8: PLL Reference Clock Input Conditions ...................................................................... 48 Table 6-9: SDRAM Interface Timing Parameters ........................................................................ 49 Table 6-10: PCI Interface Timing Parameters .............................................................................. 51 Equator Technologies, Inc. MAP-CA DSP Datasheet June 20, 2001 viii Table 6-11: PCI Measurement Conditions.................................................................................... 51 Table 6-12: IEC958 Interface Timing Parameters ........................................................................ 52 Table 6-13: I2S Clock Ratios ........................................................................................................ 52 Table 6-14: I2S Output Timing Parameters .................................................................................. 53 Table 6-15: I2S Input Timing Parameters - Slave Mode............................................................... 54 Table 6-16: I2S Input Timing Parameters - Master Mode ............................................................ 54 Table 6-18: ITU-R BT.601/656 Input Interface Timing Parameters ............................................ 56 Table 6-17: TCI Timing Parameters ............................................................................................. 56 Table 6-19: ITU-R BT.601/656 Output Interface Timing Parameters.......................................... 57 Table 6-21: GPDP Output Timing Parameters ............................................................................. 58 Table 6-20: GPDP Input Timing Parameters ................................................................................ 58 Table 6-22: I2C Interface Timing Parameters ............................................................................... 59 Table B-1: Material Used.............................................................................................................. 64 MAP-CA DSP Datasheet June 20, 2001 Hitachi, Ltd. ix List of Figures Figure 1-1: MAP-CA DSP Block Diagram ..................................................................................... 1 Figure 1-2: The VLx Coprocessor .................................................................................................. 7 Figure 1-3: Display Refresh Controller ........................................................................................... 9 Figure 3-1: View of balls from the bottom ................................................................................... 13 Figure 3-2: MAP-CA DSP pins viewed from top ......................................................................... 16 Figure 4-1: MAP-CA DSP Interface ............................................................................................. 17 Figure 4-2: TAP State Transition Diagram ................................................................................... 30 Figure 4-3: Boundary Scan Block Diagram .................................................................................. 31 Figure 4-4: Device Identification Register .................................................................................... 31 Figure 5-1: 64-bit, 4MB configuration using x32, 8Mb parts ...................................................... 35 Figure 5-2: 64-bit, 16 MB configuration using x8, 16 Mb parts .................................................. 35 Figure 5-4: 64-bit, 64 MB configuration using x16, 64 Mb parts ................................................ 36 Figure 5-3: 64-bit, 16 MB configuration using x16 16Mb parts .................................................. 37 Figure 5-6: 64-bit, 128MB configuration using x16, 128Mb parts .............................................. 37 Figure 5-5: 64-bit, 64MB configuration using x16, 128Mb parts ................................................ 38 Figure 5-7: IEC958 Interface ........................................................................................................ 38 Figure 5-8: I2S Interface ................................................................................................................ 39 Figure 5-9: Transport Channel Interface ....................................................................................... 40 Figure 5-10: ITU-R BT.656 NTSC/PAL Decoder Interface ......................................................... 41 Figure 5-11: NTSC/PAL Encoder Interface .................................................................................. 41 Figure 5-12: CRT .......................................................................................................................... 42 Figure 5-13: I2C Interface ............................................................................................................. 42 Figure 5-14: ROM Connections .................................................................................................... 43 Figure 6-1: SDRAM Timing Measurement Conditions ................................................................ 49 Figure 6-2: PCI Output Timing Measurement Conditions ............................................................ 50 Figure 6-3: PCI Input Timing Measurement Conditions .............................................................. 50 Figure 6-4: I2S Data Format .......................................................................................................... 52 Figure 6-5: I2S Output Timing Measurement Conditions ............................................................. 53 Figure 6-6: I2S Input Timing Measurement - Slave Mode ........................................................... 53 Figure 6-7: I2S Input Timing Measurement - Master Mode ......................................................... 54 Figure 6-8: Internal Serial Clock Generation for I2S Master Mode .............................................. 55 Figure 6-9: TCI Timing Measurement Conditions ....................................................................... 55 Figure 6-10: ITU-R BT.601/656 Input Timing Measurement Conditions .................................... 56 Figure 6-11: ITU-R BT.601/656 Output Timing Measurement Conditions ................................. 57 Equator Technologies, Inc. MAP-CA DSP Datasheet June 20, 2001 x Figure 6-12: GPDP Input Timing Measurement Conditions ........................................................ 57 Figure 6-13: GPDP Output Timing Measurement Conditions ...................................................... 58 Figure 6-14: I2C Timing Measurement Conditions ...................................................................... 58 Figure B-1: 352 Pin BGA Outline and Footprint - Top and Bottom Views ................................. 63 Figure B-2: 352 Pin BGA Outline and Footprint - Side Views .................................................... 64 Figure B-3: Index Location ........................................................................................................... 65 MAP-CA DSP Datasheet June 20, 2001 Hitachi, Ltd. xi Introduction to the MAP-CA Digital Signal Processor Chip The MAP-CA digital signal processor offers a highly integrated single chip solution for broadband products such as set-top boxes, digital TVs, video conferencing systems, medical imaging products, digital video editing equipment, and office automation products. The MAP-CA DSP is a member of the MAP Series VLIW processors. A parallelizing C compiler, linker, source level debugger, simulators, and libraries are available. Reference software modules, including MPEG-2 encode and decode, JPEG encode and decode, video post-filtering, audio, telephony, and video teleconferencing codecs are also available to accelerate customer product development. Because core media applications can be delivered in software on the MAP-CA DSP platform, it is easy to add, remove or enhance the functions of final products. The MAP-CA DSP provides the proven and effective solution for rapidly evolving broadband applications. VLIW Core * Highly pipelined Very Long Instruction Word processor that issues four operations per clock cycle - four 32-bit integer ALUs, two 64-bit shuffle/partitioned add units, and two 128-bit multimedia units - 128 32-bit general purpose registers, which can be treated as sixty-four 64-bit general purpose registers - thirty-two 1-bit predicate registers - eight special 128-bit registers * 11+ GOPS sustained 16-bit SIMD operations @300 MHz * 24+ GOPS sustained 8-bit SIMD operations @300 MHz * 30+ GOPS @ 300 MHz for sum of absolute differences block matching * 1800 MIPS @ 300 MHz in 32-bit integer arithmetic * Bi-endian support Memory Hierarchy * 32 KB two way set associative, LRU replacement policy, compressed format instruction cache * 32 KB four way set associative, four bank interleaved, true LRU, write-back data cache * Separate MMUs for instruction, data and DMA with fully associative sixteen entry TLB for each MMU * Glueless high speed 133 MHz SDRAM/SGRAM interface, supporting up to 128 MB System Diagram MAP-CA DSP MAP for Consumer Appliances 32-bit PCI Bus @ 33/66 MHz JTAG PCI JTAG Flash ROM Flash ROM I/F RGB Monitor Display Refresh Controller VLIW processor On-chip memories I2S I2C 1.8V 3.3V Equator Technologies, Inc. TCI In ITU-656 In TCI In Coprocessors 64-bit SDRAM @ 133 MHz ITU-656 In GPDP In IEC958 Audio CODEC Voltage Regulators SDRAM Controller ITU-656 Out I2C GPDP Out Core I/O PLLs NTSC/PAL Decoder Video Camera DEMOD FEC Tuner NTSC/PAL Encoder TV Monitor 27 MHz VCXO MAP-CA DSP Datasheet June 20, 2001 xii Coprocessors Data Sheet Overview * Programmable VLx (16-bit RISC processor) with acceleration for variable length decoding and encoding with 4 KB data memory and 4 KB instruction memory * 4 (vertical) x 5 (horizontal) / 3 x 5 / 2 x 5 tap Video Filter with 6KB line buffer memory * Programmable DataStreamer (64 channel DMA engine) with 8 KB buffer memory * DES support This data sheet provides the following information: IO Interfaces * * * * * * * * * 33 MHz/66 MHz 32-bit PCI bus IEC958 audio interfaces I2S audio interfaces Video input: - two DVB compliant transport channel interfaces or - one DVB compliant transport channel interface and one ITU-R BT.601/656 input or - two ITU-R BT.601/656 inputs or - one of any of the above and one general data port One ITU-R BT.601/656 video output or one general data port Display Refresh Controller (DRC) with on-chip color space conversion, palette table lookup, alpha-blending, and hardware cursor 110 MHz RAMDAC with sync on green for analog RGB monitor I2C master/slave interface Flash ROM (EEPROM) interface MAP-CA DSP Datasheet June 20, 2001 * An overview of the MAP-CA DSP architecture * A description of the software development platform * A description of the hardware development platform * Packaging information * Electrical specifications For additional information, Technologies, Inc. at: contact Equator info@equator.com http://www.equator.com Equator Technologies, Inc. 1300 White Oaks Road Campbell, CA 95008 Phone: (408) 369-5200 FAX: (408) 371-9106 or mb-info@comp.hitachi.co.jp http:/www.hitachi.co.jp/map-ca/ Hitachi, Ltd. Hitachi Omori 2nd Bldg., 27-18 Minami Oi 6-chome Shinagawa-ku Tokyo, Japan 140-8572 Phone: +81-3-5471-2719 Fax: +81-3-5471-2565 Hitachi, Ltd. 1 JTAG Flash ROM (shared pins)1 27 MHz IG-ALU JTAG Boundary Scan I-ALU IG-ALU 32KB Instruction Cache PCI I-ALU Register File 32-bit 66 MHz Register File Architecture Overview 32 KB Data Cache Chapter 1 VLIW Core 64-bit DTS ROMCON 6 KB VF Memory 8 KB VLx Memory Video Filter VLx DataStreamer DMA Controller Glueless SDRAM Controller SDRAM DES PLLs IEC958 I2S Display Refresh Controller I2 C Analog RGB 32-bit IOB ITU656 GPDP2 OUT OUT I2C Audio I/O Video Out ITUITUGPDP 656 TCI 656 TCI IN2 IN IN IN IN Video In A Video In B Figure 1-1: MAP-CA DSP Block Diagram 1. Some pins have multiple uses. See Chapter 3, Chapter 4, and Chapter 6 for more information 2. ITU-656 Out is unavailable for use when GPDP In is enabled due to sharing of interface signals. The MAP-CA digital signal processor is a high performance processor providing broadband applications with solutions addressing the convergence of communications, consumer appliances and computing. The MAP-CA DSP combines general purpose RISC-like processing with high performance signal and image processing. The MAP-CA DSP supports programmable video, image, and signal processing software implementations of compression and decompression algorithms. The MAP-CA DSP matches the cost and performance features of dedicated fixed function chips, with the added flexibility to rapidly respond to evolving standards. Figure 1-1 shows a block diagram of the MAP-CA DSP. The MAP-CA DSP consists of a VLIW core, Equator Technologies, Inc. programmable coprocessors, on-chip memories, and I/O interfaces. The VLIW core executes four operations in parallel and supports partitioned SIMD operations for 8, 16, 32, and 64-bit data types. Coprocessors on the MAP-CA digital signal processor help accelerate serial operations like variable length encoding/decoding and video filtering. Several audio/video interfaces are supported, including ITU-R BT.601/656 input and output; MPEG-2 transport channel interface (TCI); IEC958 and I2S digital audio interfaces. Two video inputs can be used at the same time. The Display Refresh Controller (DRC) supports RGB computer screen refresh and also has hardware support for overlay- MAP-CA DSP Datasheet June 20, 2001 The VLIW Core 2 ing a hardware cursor and graphics/text or a secondary video channel on the primary video channel. An I2C bus interface is also provided. These I/O functions execute in parallel with the CPU and eliminate the need for several external ASICs with their associated cost and bandwidth issues. A glueless SDRAM controller supports access up to a 133 MHz SDRAM. The MAP-CA digital signal processor supports a 128 MB memory size. A 32-bit 33/66 MHz PCI bus interface is also supported. The MAP-CA DSP boots from either the PCI bus or the Flash ROM interface. There are three on-chip PLLs (core/SDRAM, pixel, audio) that generate all the internal clocks from a single 27 MHz external clock input (pclk). The tci_vdac pin can be used to output a controlling signal that can be used to drive a one bit sigma-delta modulator for an external VCXO which in turns modulates the frequency on pclk. 1.1 The VLIW Core Real-time handling of multimedia data stresses processor performance. There are three basic ways to increase a processor's performance: decrease the cycle time, decrease the number of cycles required to execute an instruction, and execute more instructions per cycle. The first two are becoming increasingly difficult to improve beyond process scheduling, while the last is now receiving more attention. Executing more instructions per cycle exploits the natural parallelism available in most software. Very Long Instruction Word (VLIW) processors use this parallelism by packing multiple operations into a single instruction word, which is then executed as a unit. VLIW architectures differ from superscalar architectures in that the grouping and scheduling of instructions for execution is done at compile time, rather than execution time. The iMMediaC compiler searches for eligible operations, checks for dependencies and resource conflicts, and packages these eligible operations into VLIWs. The compiler can explore beyond the limited search window seen in superscalar architectures and cross natural boundaries, such as branches, to search for opportunities for parallelism. The iMMediaC compiler uses MAP-CA DSP Datasheet June 20, 2001 a technique known as "trace scheduling" to search a whole routine for eligible operations. By moving the difficult task of finding parallelism into software, VLIW techniques dramatically simplify the CPU design by reducing gate count and freeing valuable die area for other performance enhancements or lower costs. While VLIW is primarily designed to exploit parallelism, its simplification of the processor architecture allows for reduced cycle times as well. 1.1.1 Execution Units The MAP-CA DSP operations are primarily 3-operand RISC operations. As in a typical RISC architecture, load and store operations are the only means of referencing memory. The MAP-CA DSP has four functional units: two I-ALUs, and two IG-ALUs. Each I-ALU contains a load-store unit, an integer ALU, and a branch unit. Each IG-ALU contains an integer/graphics unit and a multimedia operation unit. The I-ALU and IG-ALU support different operations, but many integer and logical operations are implemented in both units. This overlap allows the compiler to schedule more operations in parallel and make more efficient use of all the functional units. There are 128 32-bit registers usable separately or in pairs as 64-bit registers, 32 1-bit predicate registers, and eight special 128-bit registers. The 128-bit (PLC/PLV) registers are used for FIR filter, SAD, FFT, ADD, DCT, and other specialized partitioned integer operations. The large register files help minimize unnecessary instruction dependencies caused by logically distinct register reuses. Each MAP-CA digital signal processor instruction contains four operations. The Media Intrinsics operations include partitioned operations over these data types. Load and store operations can perform one, two, four, and eight byte accesses, with support for both little-endian and big-endian byte orderings. Dynamic address translation and virtual memory protection are fully supported. The 1-bit logical values are also used to support predicated execution, which substantially enhances available parallelism by allowing partial speculation and eliminating branching. Hitachi, Ltd. The VLIW Core 1.1.1.1 I-ALU The I-ALU performs the following operations: * 32-bit integer arithmetic operations including compare * Logical and bitwise logical operations whose results can be sent to general or predicate registers * Address calculations for indexed addressing * Memory reference * Branching * System control operations 3 control flow into data flow, enabling a substantially higher degree of instruction-level parallelism. This also greatly helps to reduce any penalties for branching, without the cost and complexity of hardware branch prediction. 1.1.2 Register Resources There are several types of registers on the MAP-CA digital signal processor. These include system registers, breakpoint registers, general purpose registers, predicate registers, and special purpose 128-bit registers. 1.1.1.2 IG-ALU 1.1.2.1 Global Registers The IG-ALU performs the following operations: Global registers on the MAP-CA DSP consist of system registers and implementation-dependent I/O registers (PIO registers). Dedicated operations manipulate the system registers; conventional load and store operations manipulate the I/O registers. * 32-bit integer arithmetic operations (same as the I-ALU) * Logical and bitwise logical operations (same as the I-ALU) * 64-bit integer arithmetic operations * Shift/extract/merge operations * 64-bit SIMD operations (with 8-bit, 16-bit, and 32-bit partitions) including selection, comparison, selection of maximums and minimums, addition, multiply-add, complex multiplication, inner product, and sum of absolute differences * 128-bit partitioned (with 8-bit, 16-bit, and 32-bit partitions) SIMD operations including innerproduct with new partition shift-in for efficient FIR operation and sum of absolute differences with new partition shift-in for efficient block matching operation 1.1.1.3 Simple Interlocks Certain operations require more than one cycle to complete. No hardware interlocks are needed to prevent issue of an operation that attempts to read a result not yet completed. The iMMediaC compiler is responsible for correct scheduling, not hardware. Register scoreboarding is supported for outstanding loads. 1.1.1.4 Extensive Predication Nearly all operations can have their effect controlled by the value of a selected (1-bit) predicate register. A predicate register is tested to determine whether or not the operation should be performed. This allows the compiler to aggressively convert Equator Technologies, Inc. 1.1.2.2 Breakpoint Registers MAP-CA DSP has two sets of breakpoint registers: instruction-breakpoint and data-breakpoint registers. These registers provide hardware breakpoint capability for various debugging tools. Instruction-breakpoint registers cause an exception when an operation in the specified address is about to be executed. Similarly, the data-breakpoint registers cause an exception when the data at the specified address is about to be accessed. In both cases, a mask can be used to specify a range of addresses. By registering an exception handling routine associated with either of these exceptions, a software developer can control what happens when a hardware breakpoint occurs. For example, the exception handling routine may be used to signal an external application such as a source-level debugger that a breakpoint has occurred. 1.1.2.3 General Registers There are 128 32-bit registers that can be treated as 64-bit general registers using even-odd pairs of the 32-bit registers. 1.1.2.4 Predicate Registers There are 32 1-bit predicate registers. Predicate registers are used in predicated operations, logical operations, and branches. They provide a destination for operations with a judged condition. MAP-CA DSP Datasheet June 20, 2001 Interrupts and Exceptions 4 1.1.2.5 PLC/PLV 128-bit registers The IG-ALU has eight special 128-bit registers - two pairs of Partitioned Local Constant (PLC) registers and two pairs of Partitioned Local Variable (PLV) registers. These registers are used for powerful SIMD digital signal processor partitioned operations. The registers can be configured as sixteen 8-bit operation partitions, eight 16-bit operation partitions, or four 32-bit operation partitions. For numerous digital signal processing and compression algorithms, this allows MAP-CA DSP to match the cost/performance of fixed-function chips without the loss of re-programmability. Table 1-1: System Events Name Event Maskable I/O interrupts (from interrupt controller) Yes SINT0..SINT1 Software interrupts Yes IO0..IO3 FCNT Free running counter overflow Yes INTV0..INTV1 Interval timers Yes ILPC Illegal program counter No IBPT Instruction address break Yes BPOP Breakpoint operation No SYS System call (trap instruction) No The MAP-CA DSP has a flexible interrupt structure. Interrupts and exceptions internal to the core are reflected directly in system registers. All other interrupts from on-chip devices and PCI interrupts from external devices are gathered by an on-chip interrupt controller. The interrupt controller also provides a number of software interrupts. ITLBAA ITLB application access No ITLBR ITLB reference No ITLBM ITLB miss No Routing, masking, and prioritization of interrupts is completely software programmable. Each of the interrupts handled by the interrupt controller can be individually masked, or routed to one of four core interrupts or to one of two PCI interrupt signals. Name 1.2 1.2.1 Interrupts and Exceptions Core Interrupts and Exceptions Table 1-1 and Table 1-2 list the events that can trigger interrupts or exceptions within the core. When an event occurs, a bit is set in an "Event Seen" system register. If the event is not masked (or not maskable), the address for a handler will be fetched from one of nine Event Vector system registers, depending on the event. MAP-CA DSP Datasheet June 20, 2001 Table 1-2: Operation Events Event Maskable ILLO Illegal operation No PLV Privilege violation No DBPT Data address break Yes DALN Data alignment error No DTLBKW DTLB kernel write No DTLBAW DTLB application write No DTLBAA DTLB application access No DTLBR DTLB reference No DTLBM DTLB miss No 1.2.2 Interrupt Controller The MAP-CA digital signal processor interrupt controller supports multiple maskable interrupts from outside of the core. Non-core interrupt sources include on-chip devices such as TCI, the DRC, the Hitachi, Ltd. Timers 5 DataStreamer DMA Controller, and PCI interrupts from external devices or hosts. Software-generated shoulder-tap interrupts are provided for multiprocessing or inter-process communication support. MAP-CA DSP interrupts can be examined and controlled via PIO registers in the ROMCON control block. Routing and masking of interrupts is programmable. Each interrupt can be individually masked or routed to one of four core interrupts or to one of two PCI interrupt signals. Software interrupts can be similarly masked and routed. They may be asserted or de-asserted under software control. Table 1-3 shows the supported interrupts. Table 1-3: Supported Interrupts Name Interrupt IrqAlwaysOne debug interrupt, always asserted IrqIIC I2C IrqTCI0 primary TCI IrqDRC display refresh controller IrqNTSCIn0 primary ITU-R BT.601/656 in IrqNTSCIn1 secondary ITU-R BT.601/656 in IrqTCI1 secondary TCI IrqPCIAA PCI interrupt pin A IrqPCIAB PCI interrupt pin B IrqNTSCOut ITU-R BT.601/656 output IrqIEC958 IEC958 audio IrqIIS I2S audio IrqPCIAPME PCIA power management event IrqDS0 DataStreamer interrupt 0 IrqDS1 DataStreamer interrupt 1 IrqDSTLB DataStreamer TLB miss IrqDSBufOvrFlow DataStreamer I/O input overflow IrqSoftWare 1.3 Software-controlled interrupts Timers The MAP-CA digital signal processor has two independent programmable interval timers plus a free-running counter. Each interval timer has a 32-bit counter register and period register. The counter is incremented once per cycle. When the counter reaches the period value, the counter is reloaded, a bit is set in the system Event Seen Register (ESR), and a maskable interrupt is asserted. The free-running counter counts up once per cycle Equator Technologies, Inc. as well. When it overflows to zero, a bit is set in ESR and a maskable interrupt is asserted. The transport channel interface also has a programmable timer that counts at a rate of 27 MHz and can be used to generate an interrupt upon rollover. 1.4 Memory Hierarchy The MAP-CA DSP supports several on-chip memories and access to SDRAM and other memories via the PCI bus. The VLIW is equipped with a 32 KB instruction cache and 32 KB data cache used for caching instructions and data from SDRAM. In addition to supporting I-ALU ports, the data cache supports a port to the DTS (Data Transfer Switch), which makes data in the data cache available to the DataStreamer controller. A 4 KB instruction memory and a 4 KB data memory are used by the VLx coprocessor. The Video Filter uses a 6 KB line buffer memory. These memories, totaling 14 KB, are also accessible by the VLIW core through un-cached load/store operations. In addition, these memories are also available to the DataStreamer DMA controller and for external use via PCI. The line buffer memory is used to store the content of Flash ROM at system boot up. 1.4.1 Caches The MAP-CA DSP has a 32 KB instruction cache and a separate, multi-bank 32 KB data cache. Both caches are physically addressed, so that problems of aliasing and context switching do not arise. For fast address translation, the cache index is virtual but the tags are physical. The instruction cache holds instructions in a compressed form. It is organized as a two-way set associative cache with a LRU replacement algorithm. The data cache is a 32 KB, four-way set-associative (with true LRU replacement), write-back cache. The data cache supports four simultaneous 64-bit data accesses per cycle. The cache is non-blocking; up to 8 outstanding misses to different cache lines and up to 48 outstanding misses overall are allowed. 1.4.2 Address Translation The MAP-CA DSP provides memory management support in the form of separate TLBs for the instruction stream, each I-ALU data access, and the DataStreamer DMA controller. The four TLBs MAP-CA DSP Datasheet June 20, 2001 Databuses and Controllers 6 (ITLB, two DTLBs, and DSTLB) can be programmed independently. 1.5.3 The DTS-ID is part of the virtual address and can be used to direct accesses when the TLBs are disabled. The DataStreamer DMA controller is a high performance, programmable DMA engine that performs buffered data transfer between different MAP-CA DSP memory subsystems or between memories and I/O devices. The DataStreamer controller is programmed and controlled by software. The DataStreamer controller then performs the requested transfer without further intervention from the core. Each TLB has sixteen fully-associative entries. Each entry contains a Virtual Page Number (VPN), an 8-bit Address Space Identifier (ASID), access protection bits, and page size information. Each entry can map a page of any valid size, where the valid sizes are 16 KB, 64 KB, 256 KB, 1 MB, 4 MB, 16 MB, 64 MB, 256 MB, and 1 GB. When a TLB miss occurs, an exception is generated. The exception handler can modify a TLB entry and retry the failed operation. Separate exception handlers can be installed for data, instruction, and DataStreamer controller TLB misses. 1.5 Databuses and Controllers The various buses and controllers on the MAP-CA digital signal processor are described in the following sections. 1.5.1 Memory Interface Controller The Memory Controller Unit allows customers to easily build high-performance, external memory up to 128 MB using SDRAM/SGRAM without any external glue logic. Local memory supports externally initiated PCI accesses through the Address Translation Unit within the PCI module. The Memory Controller Unit also includes hardware that queues, prioritizes, and transfers data from memory to memory or from memory to cache asynchronously to the initiating software. The on-chip core PLL generates the clock for the memory controller and provides clock synchronization between the MAP-CA DSP and external SDRAM. This provides support for various combinations of CPU core and memory speeds. 1.5.2 Data Transfer Switch (DTS) The DTS is a split-transaction bus. The DTS contains the data and address buses, a high speed bridging system, and a bus arbiter. The bridge, arbiter, and bus arrangement is a very high-speed communication solution that allows multiple media applications to be executed concurrently. The arbiter can handle multiple requestors using priority based scheduling. MAP-CA DSP Datasheet June 20, 2001 DataStreamer DMA Controller The DataStreamer controller can perform the following classes of transfers: * memory-to-memory: perform block transfers, preload data into the cache, fill a memory region with 0 or 1 bits * memory-to-I/O and I/O-to-memory: perform I/O transfers The DataStreamer DMA controller features include: * an 8 KB internal memory that can be partitioned into as many as 64 variable-sized buffers. Each buffer is simultaneously the sink for an input I/O or memory channel and the source for an output I/O or memory channel. * sixty-four independent programmable channels for transfers between various memories and the DataStreamer controller's internal buffer, * Channel programs, called Descriptor Lists, allow transfers of arbitrary or infinite length to be specified. Regular and irregular patterns of contiguous or non-contiguous transfers are easy to specify. * Memories that can be read or written include SDRAM, on-chip memories, and PCI bus accessible memories. Cache preloading can also be performed. * Interrupts can be triggered by descriptors, allowing end-of-transfer or mid-stream interrupts to be generated. 1.5.4 PCI Bus The PCI unit implements a 32-bit PCI 2.1 interface with speed up to 66 MHz. The PCI interface is a single function device with two BARs. Certain fields in the configuration registers may be initialized on power-up through ROM control. As a PCI target, the PCI interface allows access to the MAP-CA digital signal processor SDRAM (coherently or non-coherently with respect to the data Hitachi, Ltd. Coprocessors VLx 16-bit CPU Bitstream processor The MAP-CA digital signal processor can act as a host on the PCI bus. There are three pairs of request/grant lines for other devices on a PCI bus. This enables a multi-processor configuration to connect up to four MAP-CAs together on a PCI bus without a bridge. The PCI interface implements two separate interrupt lines. If the MAP-CA DSP is not the host, any internal interrupt can be routed to any of these PC interrupts. If the MAP-CA DSP is the host, the PCI interrupts are sampled by the MAP-CA DSP and can be routed to the MAP-CA DSP VLIW core. The MAP-CA DSP is a 3.3V-only I/O device. If the MAP-CA DSP is used in a system with a 5V PCI bus architecture, then a 5V-to-3.3V level translator is required. 1.5.5 I/O Bus registers cache). The PCI interface also allows access to several programmer-visible control registers, PIO space and SDRAM. As a PCI master, the PCI interface allows the VLIW core, the DataStreamer DMA controller, and coprocessors to initiate PCI bus requests. The PCI unit can initiate memory, I/O and configuration commands on the PCI bus. 7 64-bit instruction memory (4 KB) 16-bit 32-bit data memory (4 KB) I/O Bus Figure 1-2: The VLx Coprocessor 1.6.2 Video Filter A polyphase (8 phase) 2D Video Filter takes 4:2:0 or 4:2:2 YUV stream as input and scales either up or down as required. 4 (vertical) x 5 (horizontal) filters support up to 768 horizontal pixels, 3 x 5 up to 1024 horizontal pixels, and 2 x 5 up to 1536 horizontal pixels. The Video Filter pumps out scaled 4:4:4 YUV data to the DRC through the video bus. The Video Filter can also pump out 4:4:4 YUV data to the SDRAM for debug purposes. Its features are described below. Coprocessors on the MAP-CA DSP help off-load "serial" tasks from the VLIW core or accelerate special purpose processing for video operations. The coprocessors operate in parallel with the VLIW core resulting in improved video processing. * Supports 8-bit coefficients. * Supports both interspersed and co-sited pixel positioning. * Supports vertical 4-tap polyphase (8-phase) filters for luminance and chrominance. * Supports horizontal 5-tap polyphase (8-phase) filters for luminance and chrominance. * Can scale up to a maximum resolution of 2047x2047 (depends upon memory bandwidth available for the video scaling operation). * Can scale up from a minimum resolution of 17x4. * The maximum scale down ratio is 1:7. 1.6.1 1.6.3 All on-chip peripheral devices are connected via the internal I/O Bus (IOB). This is a 32-bit internal bus running at one half of the VLIW core frequency. The IOB connects to the DTS through the DataStreamer controller. The IOB can handle real-time requests. 1.6 Coprocessors VLx The Variable Length Encoder/Decoder (Figure 1-2) or VLx is a 16-bit RISC coprocessor with thirty-two 16-bit registers. The VLx off-loads the bit sequential tasks of variable length encoding and variable length decoding (VLE/VLD) from the VLIW CPU core and accelerates applications such as JPEG, MPEG, H.263, JBIG, and DV. The VLx includes special purpose hardware for bitstream processing, hardware-accelerated MPEG-2 table lookup, and general purpose variable length decoding. Equator Technologies, Inc. DES Module The MAP-CA digital signal processor includes hardware support for encryption and decryption of data according to the National Bureau of Standards Data Encryption Standard and certain implementations thereof as defined in FIPS Publications 46-2, 46-3, 74, and 81 and ANSI Publication X9.52-1998. For more information on this support, contact your Equator Technologies or Hitachi Sales Representative. MAP-CA DSP Datasheet June 20, 2001 I/O Interfaces 8 1.7 I/O Interfaces 1.7.1 Audio Interfaces 1.7.1.1 IEC958 Audio Interface This interface supports several audio standards: * Sony/Philips Digital Interface (S/PDIF) * Audio Engineering Society/European Broadcast Union (AES/EBU) interface * TOSLINK interface (requires external IR devices) The MAP-CA DSP IEC958 interface can insert even or odd parity on each sub-frame of the output bit stream. 1.7.1.2 I2S Interface The Inter-IC Sound (I2S) interface drives high quality audio D/A converters for home theater. The MAP-CA digital signal processor interface meets the requirements of the standard serial data protocol and provides connection for up to three stereo DACs and one ADC. The interface supports 48 kHz, 44.1 kHz, and 32 kHz audio sample rates. Simultaneous input and output must be at the same sample rate. The MAP-CA DSP IIS supports both master and slave mode interface. In slave mode there is the choice of using either external inputs or internally generated signals for the sample rate clock and serial bit clock. 1.7.2 Video Interfaces The MAP-CA DSP provides two video input ports and one video output port. Each input port supports either transport channel interface input or ITU-R BT.601/656 input. The output port supports an ITU-R BT.601/656 compliant output. In addition, the primary video input port and/or the output port can be used in a general purpose mode for transferring data (general purpose data port) for input or output respectively. 1.7.2.1 Transport Channel Interfaces The video input unit implements two DVB compliant transport channel interfaces which receive demodulated channel data in transport layer format. The transport channel interface (TCI) accepts MPEG-2 system transport packets in either byte parallel or, by default, bit serial form. Data rates up to 80Mbps (serial) or 30 MB/s (byte-wide parallel) are supported. By default, serial data is input on tci_data[0] and parallel data is input on MAP-CA DSP Datasheet June 20, 2001 tci_data[7:0] with bit 7 the most significant. These orientations can be reversed by PIO programming. The TCI synchronizes packet data received in broadcast applications such as satellite or cable. The TCI can detect inline sync bytes, which are the first byte of every transport header. Alternatively, the TCI can utilize the external tci_sync signal. Once byte-sync has been detected, the TCI moves byte-aligned data into the MAP-CA DSP's memory using the DataStreamer DMA controller. The number of bytes in each packet is programmable. At the end of every packet, the TCI appends an eight-byte postscript that includes time stamps from the local clock counters. This information can be used in conjunction with the Program Clock References embedded in the transport stream to track the timing reference. This is accomplished by using a software loop filter to implement a 1-bit sigma-delta modulator to provide a controlling voltage for the external VCXO that drives pclk. The sigma-delta data stream is output at 1.5 MHz on the tci_vdac pin via the primary TCI. In addition to the local clock counters, there is a programmable 27 MHz timer in each TCI module that generates an interrupt on overflow (rollover). 1.7.2.2 ITU-656 Input Interface This interface provides direct connection to an ITU-R BT.601/656 format NTSC/PAL video input decoder. The external decoder can be controlled using the I2C Serial Bus. 1.7.2.3 ITU-656 Output Interface A glueless interface to a NTSC/PAL video encoder is provided, enabling the MAP-CA digital signal processor to directly generate high-quality NTSC or PAL video-output signals. This interface supports 8-bit 525 and 625 line resolutions with either separate H/Vsync (ITU-R BT. 601) or inline sync (ITU-R BT.656). Advanced video post-filtering on the MAP-CA DSP processor via software can produce flicker-free output when converting interlace-to-progressive output. The external NTSC/PAL encoder can be controlled using the I2C Serial Bus. 1.7.2.4 General Purpose Data Port (GPDP) The general purpose data port provides an 8-bit parallel input/output port. Together with a clock and a Hitachi, Ltd. I/O Interfaces 9 Memory Controller Video Filter DataStreamer DMAB DSD DSP DSC DSA DSG DSV DSD CRTC DISPLAY LIST Pixel Output Graphics Alpha Format Channel Conversion Cursor Gen. Video Bus SV SU Video #2 Format Scale Alpha Channel MUX Key DP #1 DP #2 DP Switch Alpha Pipe/ Insert State Control MUX MUX PALETTE RAM 256 x 24 Color Space Conversion RGB YUV DP Switch ALPHA Blender CURSOR Insert Horizontal blender & chroma subsampler NTSC Output CCIR656 Output Nibble Mode Slow Bus < 85 MHz CCIR 656 Formatter R Fast Bus Signature Analyzer G B DAC's NTSC/PAL Encoder Figure 1-3: Display Refresh Controller couple of handshake signals, this provides an alternative to PCI for multiple MAP chips to communicate. The data bandwidth supported is up to 60 MB/s depending upon other system activity. 1.7.3 Display Refresh Controller Sophisticated video blending, 2D graphics with alpha blending, PIP, and hardware cursor overlays for EPGs (Electronic Program Guides) and navigation services have been designed into the Display Refresh Controller. Color space conversion, Equator Technologies, Inc. Gamma correction, and choice of YCbCr or RGB output format is supported. See Figure 1-3 on page 9. The DRC supports a maximum screen resolution of 1280 x 1024. This monitor resolution requires a minimum pixel clock frequency of 108 MHz to support a rate of 16 bits per pixel. 1.7.4 DACs The MAP-CA DSP RGB DACs (digital-to-analog converters) are part of the Display Refresh Control- MAP-CA DSP Datasheet June 20, 2001 I/O Interfaces 10 ler block. The 8-bit DACs allow pixel clock rates up to 110 MHz. The MAP-CA DSP generates RS-343A compatible monitor signals into doubly-terminated 75 load and is capable of driving standard SVGA monitors. The full scale output level is determined by an external reference voltage Vref at 1.235V and an external resistor Rnominal = 1117 . The full scale level can be adjusted by adjusting the resistor value. The DACs output the three primary analog color signals - red video, green video and blue video - with the video sync information superimposed on the green video output. Also, separate hsync and vsync reference signals are provided. 1.7.5 I2C Interface Unit The Inter-IC (I2C) bus was originally developed by Philips to facilitate communications and control among integrated circuits in consumer electronics. Using this two-wire serial interface, the MAP-CA DSP can function as a master or slave device to relay status and control information to external devices. The I2C interface unit has an additional output signal, iic_select that allows MAP-CA DSP software to control an external analog multiplexer/level converter that can switch between a regular I2C bus and any other external bus (such as DDC for a monitor interface). This signal can also be used as a general purpose output. 1.7.6 ROM Controller The ROM Controller (ROMCON) unit performs four distinct functions. * The Chip Configuration and ROM Boot Sequencer is a state machine for reading chip configuration and boot code at system startup. * The Flash ROM Interface controls the actual reading and writing of an off-chip flash ROM device. * The Interrupt Controller/Collector provides a means for enabling, setting, and clearing hardware and software interrupts to the VLIW core and PCI bus controller. * The PLL I/O provides PIO access to the programmable registers related to the various on-chip PLLs. The three PLLs for the core/SDRAM, pixel, and audio clocks are programmed indirectly via PIO registers within the ROMCON unit. MAP-CA DSP Datasheet June 20, 2001 The purpose of the Configuration/Boot Sequencer is to control the boot up process of the chip. During reset, the resistor straps connected to the ntsc_out_data[7:0] pins are examined to determine how MAP-CA digital signal processor will configure itself and boot. If the resistor straps indicate to boot from ROM, the Boot Sequencer directs the Flash ROM Interface Controller to transfer bytes from the external ROM device to the MAP-CA DSP configuration registers and to the PCI configuration registers. The 6 KB line buffer memory of the Video Filter is then used to store the bootstrap program for system boot up. ROMCON copies the next 6 KB from ROM into the Video Filter memory (VfMem) through an 8-bit configuration bus. After the boot code has been loaded, ROMCON unstalls (restarts) the VLIW CPU, which in turn begins to execute the boot code out of VfMem. The ROMCON unit operates at 27 MHz during the configuration loading, since the core PLL cannot be programmed to be taken out of bypass mode until after the VLIW core has been unstalled. Alternatively, for booting via the PCI interface, ROMCON plays a mostly passive role. In this case, an external host loads the VfMem with boot code and initiates boot of the VLIW core via a PIO write to unstall the VLIW CPU. ROMCON also runs power-on diagnostics during the boot and may be paused at various points for status testing. ROMCON requires minimal chip resources so that standard power-on diagnostics can run without having to bring up all portions of the chip, allowing the chip to be tested in more manageable stages. 1.7.7 Reset Strap During reset, the eight ntsc_out_data pins are used as inputs to read pre-boot configuration settings. These are settings that must be known before the actual boot process begins - namely, whether the system should boot from ROM and whether PCI should serve as host for its bus. There are also four straps available whose meaning can be defined in software. Each pin strap is pulled high (to Vdd33) or low (to GND) through a 4.7 K resistor. The pins are sampled into flip-flops until reset is de-asserted and then saved in the software-visible StrapBits field of PIO register ConfigBusControl. For more information see Section 4.8.6, "Reset Straps," on page 27. Hitachi, Ltd. 11 Chapter 2 Software Development The iMMediaTools software toolkit includes * iMMediaC optimizing, parallelizing C-language compiler * FIRtree Media Intrinsic C-language extensions * Assembler * Linker * Source-level debugger * Assembly-level debugger * Profiling, translating simulator * Two virtual-machine simulators, one nearly cycle-accurate * Assorted libraries The iMMediaC compiler supports development in a host environment that differs from the target environment. The virtual-machine simulators allow testing and debugging on your host system. The supported host development environments are Microsoft Windows NT and Red Hat Linux. 2.1 The C Compiler The MAP-CA digital signal processor development system includes the iMMediaC compiler with FIRtree Media Intrinsic extensions. The FIRtree extensions are proprietary SIMD-style high-speed media processing extensions. The iMMediaC compiler uses aggressive optimization and global scheduling technology (including trace scheduling) to deliver full hardware performance without using laborious assembly language programming. The compiler allows programmers to focus efforts on algorithm optimization versus assembly scheduling, resource allocation, and debugging. Unlike existing DSPs or dedicated-function devices which have heretofore been used to meet media processing requirements, the MAP-CA DSP is programmed in a high-level language (C). Benefits of programming in C include * * * * * Reduced development costs Reduced time to market Lower system costs Reduced maintenance time Software-based upgrades The compiler uses complex inline expansion, assertions, and loop unrolling with trace frequency estimation algorithms to maximize C code efficiency. The optimizations include * Uncover instruction-level parallelism * Manage registers, pipelines and functional units * Generate instruction operation schedules that exploit parallelism * Support extensive global optimization, analysis and scheduling * Provide local scheduling and optimization * Support media-oriented machine facilities * Manages all timing dependencies to maximize scheduling efficiency The iMMediaC compiler shell program lets you compile, examine, test, profile, assemble, and link source programs with a single command, by using various options. 2.1.1 The FIRtree Media Intrinsics Extensions The FIRtree Media Intrinsics C-language extensions read 128-bit words of data memory, which contain multiple data items, and perform operations simultaneously on each of the items within the word. The FIRtree Media Intrinsics extensions perform operations on partitioned native data types within 32-bit or 64-bit operands, making use of the PLV and PLC registers on the IG-ALU to store intermediate values. 2.2 Libraries The iMMediaTools Software Development Toolkit includes standard C runtime libraries and libraries specifically designed to support MAP-CA digital Equator Technologies, Inc. MAP-CA DSP Datasheet June 20, 2001 Assembler 12 signal processor resources, such as the DataStreamer DMA controller and VLx coprocessor for media applications. 2.6 2.3 Trsim is a high speed, instruction level simulator of the MAP-CA digital signal processor core unit. This simulator works on an intermediate representation of a software program and can be used to initially develop applications and experiment with the performance of different algorithms and use of compiler options. Assembler The MAP-CA DSP assembler lets the programmer take the assembly language source files generated by the compiler, and convert them into object code files, ready for the linker. Developers will not typically write assembly language modules themselves. 2.4 Linker The linker combines object code files into an executable module, accepting both object files and libraries as input. During linking, the linker resolves all external references. 2.5 Debugger The development environment includes a source-level debugger based on gdb (GNU debugger). The extended gdb (egdb) runs on both the Windows NT and Red Hat Linux platforms. The egdb debugger allows the user to: * load a MAP-CA DSP application from the host PC file system onto the MAP-CA DSP and run it * set, list, and clear software and hardware breakpoints * single step through both C source code and assembly instructions * source level debug of optimized C code * examine and deposit values into local variables, global variables and PIO space * examine and deposit values into all registers * examine the stack, including stack backtracing Numerous freeware or low-cost gdb GUI front ends exist on both the Windows NT and Linux platforms that will transparently layer on egdb's command line interface and provide a window-based debugging environment. MAP-CA DSP Datasheet June 20, 2001 Simulators The software developer's toolkit includes three software simulators: trsim, sim, and casim. Sim is also a high-speed, instruction-level simulator. This simulator works off actual MAP-CA DSP binaries. Sim is a functional simulator of the MAP-CA DSP core unit with data cache, DataStreamer controller, and a subset of I/O devices. It provides runtime checks against resource constraints and all MAP-CA DSP features necessary to simulate a MAP-CA DSP running a real-time operating system and applications. Casim is a nearly cycle-accurate software simulator for the MAP-CA DSP and models more accurately the core, DataStreamer DMA controller, VLx, instruction and data caches, memories, and buses. Like sim, this simulator operates off actual MAP-CA digital signal processor binaries. Casim provides more detailed runtime checks against resource constraints. Casim provides visibility into internal machine state and bandwith and augments debugging and tuning of interactions between VLIW core, DataStreamer controller, and VLx programs. Sim and casim work in conjunction with the source-level debugger. 2.7 Boot Software must contain boot code for execution on MAP-CA DSP. This boot code configures TLBs and caches. Equator software tools can automatically add boot code when building an application. Hitachi, Ltd. 13 Chapter 3 BGA PIN_OUT Assignments Signal assignment on the BGA352 package is shown here. Figure 3-1 shows the bottom view, with the balls facing the viewer. Figure 3-2 shows the top view of the chip with pin assignments.. 26 24 25 22 23 20 21 18 19 16 17 14 15 12 13 10 11 8 9 6 7 4 5 2 3 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF In Table 3-1, pins marked with an (b) have multiple functions assigned (see Chapter 4) A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 26 24 25 22 23 20 21 18 19 16 17 14 15 12 13 10 11 8 9 6 7 4 5 2 3 1 Figure 3-1: View of balls from the bottom Table 3-1: Pin Assignments Signal Name Ball audioclk_byp_in A2a aVdd18 aVss aVdd18 aVss Signal Name Ball Signal Name Ball Signal Name Ball Signal Name Ball ntsc_out_data[6] C6b video_ina[8] B8b video_inb[4] C12b hsync B15 ntsc_out_data[7] D7b video_ina[9] C9b video_inb[5] B12b tms B16 trst C15 aVss A17 gdac_fscale B17 video_ina[0] B6b tcia_inuse A8 video_inb[6] A13b video_ina[1] C7b tcia_sync A9 video_inb[7] C13b video_ina[2] D8b tcia_clk C10 video_inb[8] D13b B10 gdac_comp C16 A6b tcia_vdac video_ina[3] video_inb[9] B13b aVdd33 D16 video_ina[4] B7b tcib_inuse A14 gdac_green C17 tcib_sync B14 gdac_blue A18 A19 B3 C4 D5 A3 pixelclk_byp_in B4b ntsc_out_data[3] C5b video_ina[5] ntsc_out_data[4] B5b video_ina[6] ntsc_out_data[5] A4b video_ina[7] Equator Technologies, Inc. ntsc_ina_clk27 A10b video_inb[0] C11b video_inb[1] B11b tcib_clk C14 gdac_red video_inb[2] A11b ntsc_inb_clk27 D14 gdac_cvgg(aVss) C18 video_inb[3] D12b vsync A16 A7b C8b D9b MAP-CA DSP Datasheet June 20, 2001 14 Signal Name Ball Signal Name Ball Signal Name Ball Signal Name Ball Signal Name Ball aVddx (aVdd18) D17 sddata[26] J25 aVssq (aVss) aVssx (aVss) B19 sddata[27] K24 aVddq (aVdd18) AE24 tdi A20 sddqm[3] K26 aVdd18 AF25 tck B20 sddata[28] L24 sdclk_byp_in AC21c sddata[60] tdo C19 sddata[29] L25 pclk AD22d no connection A21 sddata[30] M25 coreclk_byp_in AE23c sddata[0] B21 sddata[31] M24 pci_clk AF24 sddata[1] C20 sdcs_[0] M26 sddata[34] AD21 sddata[2] D19 sdcs_[1] N24 sddata[35] AF23 sddata[3] A23 sdcs_[2] N25 sddqm[4] AF22 sddqm[0] B22 sdcs_[3] P26 sddata[36] AE21 sddata[4] C21 sdrtnclk P24 sddata[37] AC19 sddata[5] A24 sdclk R25 sddata[38] AD20 sddata[6] B23 sdclk1 R24 sddata[39] AF21 sddata[7] C22 sdclk2 T26 sddata[40] AF20 sddata[8] D21 sdras_ T25 sddata[41] AC18 sddata[9] A25 sdcas_ T24 sddata[42] AD19 sddata[10] B24 sdwe_ U25 sddata[43] AE19 sddata[11] C23 sdadr[0] U24 sddqm[5] AD18 sddqm[1] D22 sdadr[1] V26 sddata[44] AF19 sddata[12] D24 sdadr[2] V24 sddata[45] AE18 sddata[13] B26 sdadr[3] W25 sddata[46] AD17 sddata[14] C25 sdadr[4] Y26 sddata[47] AE17 sddata[15] E24 sdadr[5] W24 sddata[48] AF17 sddata[16] D25 sdadr[6] Y25 sddata[49] AD16 sddata[17] D26 sdadr[7] Y24 sddata[50] AF16 sddata[18] E25 sdadr[8] AA25 sddata[51] AC15 sddata[19] F24 sdadr[9] AA24 sddqm[6] AD15 sddqm[2] F26 sdadr[10] AB26 sddata[20] G24 sdadr[11] AD26 sddata[21] G25 sdadr[12] AB24 sddata[22] H25 sdadr[13] AD25 sddata[23] H24 sddata[32] AC24 sddata[24] H26 sddata[33] AB23 sddata[25] J24 aVss AC22 MAP-CA DSP Datasheet June 20, 2001 AD23 sddata[58] sddata[52] AE15 sddata[53] AF15 sddata[54] AD14 sddata[55] AE14 sddata[56] AF13 sddata[57] AD13 AF12 pci_frame_ AC2 sddata[59] AE12 pci_cbe_[2] AC1 sddqm[7] AD12 pci_ad[16] AB1 AC12 pci_ad[17] AA2 sddata[61] AF11 pci_ad[18] AA3 sddata[62] AD11 pci_ad[19] AA1 sddata[63] AF10 pci_ad[20] Y3 pci_ad[0] AE10 pci_ad[21] Y2 pci_ad[1] AD10 pci_ad[22] W1 pci_ad[2] AE9 pci_ad[23] W2 pci_ad[3] AF8 pci_idsel W3 pci_ad[4] AD9 pci_cbe_[3] V1 pci_ad[5] AE8 pci_ad[24] V3 pci_ad[6] AC9 pci_ad[25] U1 pci_ad[7] AD8 pci_ad[26] U4 pci_cbe_[0] AF7 pci_ad[27] U3 pci_ad[8] AF6 pci_ad[28] U2 pci_ad[9] AD7 pci_ad[29] T3 pci_ad[10] AC8 pci_ad[30] T2 pci_ad[11] AE6 pci_ad[31] R3 pci_ad[12] AF5 pci_req_[0] R2 pci_ad[13] AF4 pci_req_[1] R1 pci_ad[14] AD6 pci_req_[2] P3 pci_ad[15] AF3 pci_gnt_[0] P1 pci_cbe_[1] AE4 pci_gnt_[1] N1 pci_par AD5 pci_gnt_[2] N2 pci_serr_intb_ AC6 pclk_out N3e pci_stop_ AF2 pci_rst_ M2 pci_devsel_ AE3 pci_inta_ M3 pci_trdy_ AD4 pci_pme_ L1 pci_irdy_ AC5 iic_sda L2 Vss AD2 iic_sck L3 Vdd18 AE1 iic_select K1 Vdd18 AC3 iis_in_data K3 Vss AB3 iis_in_lr J1 Hitachi, Ltd. 15 Signal Name Ball Signal Name Ball Signal Name Ball Signal Name Ball Signal Name Ball iis_in_bclk K4 Vdd18 V23 Vdd33 R23 Vss E26 Vss AE5 iis_out_data[0] J2b Vdd18 W23 Vdd33 U23 Vss F25 Vss AF1 iis_out_data[1] J3b Vdd18 AA23 Vdd33 Y23 Vss G26 Vss AE2 iis_out_data[2] H2b Vdd18 AC20 Vdd33 AD24 Vss J26 Vss AD1 iis_out_lr G1 Vdd18 AC16 Vdd33 AC23 Vss K25 Vss AB2 iis_out_bclk H3 Vdd18 AC11 Vdd33 AC17 Vss L26 Vss Y1 iec958_in G2 Vdd18 AC7 Vdd33 AC14 Vss N26 Vss V2 iec958_out G3 Vdd18 AB4 Vdd33 AC13 Vss P25 Vss T1 rom_cs_ F1 Vdd18 AA4 Vdd33 AC10 Vss R26 Vss P2 Vdd18 W4 Vdd33 AD3 Vss U26 Vss M1 Vdd18 T4 Vdd33 AC4 Vss V25 Vss K2 ntsc_out_hsync F3b ntsc_out_vsync E1b Vdd18 P4 Vdd33 Y4 Vss W26 Vss H1 ntsc_out_data[0] E2b Vdd18 N4 Vdd33 V4 Vss AA26 Vss F2 ntsc_out_data[1] E3b Vdd18 M4 Vdd33 R4 Vss AB25 Vss D1 ntsc_out_data[2] C1b Vdd18 J4 Vdd33 L4 Vss AC26 Vss audioclk_out C2 Vdd18 G4 Vdd33 H4 Vss AC25 pixelclk_out D3f Vdd18 F4 Vss A1 Vss AE26 Vdd18 D6 Vdd33 C3 Vss B1 Vss AE25 Vdd18 D11 Vdd33 D4 Vss B2 Vss AF26 Vdd18 D15 Vdd33 E4 Vss A5 Vss AE22 d. connect to 27 MHz Vdd18 D20 Vdd33 D10 Vss B9 Vss AE20 Vdd18 E23 Vdd33 D18 Vss A12 Vss AF18 Vdd18 G23 Vdd33 C24 Vss A15 Vss AE16 Vdd18 H23 Vdd33 D23 Vss B18 Vss AF14 Vdd18 K23 Vdd33 F23 Vss A22 Vss AE13 Vdd18 M23 Vdd33 J23 Vss A26 Vss AE11 Vdd18 P23 Vdd33 L23 Vss B25 Vss AF9 Vdd18 T23 Vdd33 N23 Vss C26 Vss AE7 Equator Technologies, Inc. D2 a. If unused, NCi (Vss) and tie to ground b. Multi-function pins c. connect to 27 MHz or lower clock clock e. If unused, NCo and floating f. Leave floating MAP-CA DSP Datasheet June 20, 2001 16 1 A B C D Vss Vss 2 3 Vss Vss 5 Vss 6 7 video_ video_ ina[3] ina[5] 8 tcia_ inuse pixelclk ntsc_out video_ video_ video_ aVdd18 _byp_in _data[4] ina[0] ina[4] ina[8] ntsc_out audioclk Vdd33 _data[2] _out Vss 4 ntsc_out audioclk aVss _data[5] _byp_in 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 video_ inb[6] tcib_ inuse video_ video_ video_ inb[1] inb[5] inb[9] tcib_ sync tcia_ ntsc_ina video_ sync clk27 inb[2] Vss tcia_ vdac Vss ntsc_out ntsc_out video_ video_ video_ video_ video_ video_ aVss tcia_clk tcib_clk _data[3] _data[6] ina[1] ina[6] ina[9] inb[0] inb[4] inb[7] Vss vsync aVss hsync tms gdac_ fscale trst gdac_ comp gdac_ blue gdac_ red Vss aVssx (aVss) gdac_ gdac_cv green gg(aVss ) tdo tdi no connection tck sddata sddata sddata sddata [0] [0] [6] [10] Vss sddata sddata [3] [5] sddata [9] Vss A Vss sddata [13] B Vss C sddata [17] D sddata [18] Vss E sddqm [2] F sddata sddata sddata sddata sddata Vdd33 [1] [4] [7] [11] [14] pixelclk ntsc_out video_ video_ video_ video_ ntsc_inb aVddx sddata sddata sddata sddata Vdd33 aVdd18 Vdd18 Vdd33 Vdd18 Vdd18 aVdd33 Vdd33 Vdd18 Vdd33 _out _data[7] ina[2] ina[7] inb[3] inb[8] _clk27 aVdd18 [2] [8] [1] [12] sddata [16] E ntsc_out ntsc_out ntsc_out Vdd33 _vsync _data[0] _data[1] sddata Vdd18 [15] F ntsc_out Vdd18 _hsync sddata Vdd33 [19] Vss G iis_out_ iec958 iec958 Vdd18 lr _in _out sddata Vdd18 [20] sddata [21] Vss G H Vss iis_out iis_out Vdd33 data[2] _bclk sddata Vdd18 [23] sddata [22] sddata [24] H iis_in_lr iis_out iis_out Vdd18 data[0] data[1] Vdd33 sddata [25] sddata [26] Vss K iic_ select iis_in _data sddqm [3] K L pci_ pme_ J M N rom_cs_ Vss J iis_in _blk sddata Vdd18 [27] Vss iic_sda iic_sck Vdd33 sddata Vdd33 [28] sddata [29] Vss L pci_ pci_rst_ inta_ Vdd18 sddata Vdd18 [31] sddata [30] sdcs_ [0] M pci_gnt pci_gnt pclk_out Vdd18 _[1] _[2] sdcs_ [1] sdcs_ [2] Vss N P R Vss Vss Vdd33 P pci_gnt _[0] pci_req Vdd18 _[2] Vdd18 sdrtnclk Vss sdcs_ [3] R pci_req pci_req pci_ad Vdd33 _[1] _[0] [31] Vdd33 sdclk1 sdclk Vss T pci_ad pci_ad Vdd18 [30] [29] Vss Vdd18 sdcas_ sdras_ sdclk2 T U pci_ad pci_ad pci_ad pci_ad [25] [28] [27] [26] Vdd33 sdadr[0] sdwe_ Vss U V pci_ cbe_[3] pci_ad Vdd33 [24] Vdd18 sdadr[2] sdadr[1] V pci _idsel Vdd18 sdadr[5] sdadr[3] Vss W W Y Vss Vss pci_ad pci_ad [22] [23] Vss Vdd18 pci_ad pci_ad Vdd33 [21] [20] Vss Vdd33 sdadr[7] sdadr[6] sdadr[4] Y Vss AA sdadr [10] AB AA pci_ad pci_ad pci_ad Vdd18 [19] [17] [18] Vdd18 sdadr[9] sdadr[8] AB pci_ad [16] sddata [33] AC pci_ pci_ Vdbb Vdd33 cbe_[2] frame_ (Vdd18) Vss Vsbb (Vss) AD Vss AE Vsbc (Vdd18) Vss Vss pci_ stop_ 1 2 AF Vdbc (Vss) Vdd33 Vdd18 pci_ trdy_ pci_ pci_cbe devsel_ [1] pci_ pci_serr pci_ad pci_ad sddata sddata sddata sddata sdclk_ Vdd18 Vdd33 Vdd18 Vdd33 Vdd33 Vdd18 Vdd33 Vdd18 irdy_ intb_ [10] [6] [60] [51] [41] [37] byp_in pci_ad pci_ad pci_ad pci_ad pci_ad sddata sddqm sddata sddata sddqm sddata pci_par [14] [9] [7] [4] [1] [62] [7] [57] [54] [6] [49] Vss pci_ad [11] Vss pci_ad pci_ad pci_ad [5] [2] [0] pci_ad pci_ad pci_ad pci_ad pci_cbe pci_ad [15] [13] [12] [8] [0] [3] 3 4 5 6 7 8 Vss Vss sddata [59] Vss sddata sddata [55] [52] sddata sddata sddata sddata [63] [61] [58] [56] Vss sddata [53] sddata sddqm sddata sddata sddata [46] [5] [42] [38] [34] Vss sddata [47] sddata [50] sddata [48] sddata sddata [45] [43] Vss Vss sddata [36] sdadr [12] Vss aVss sddata Vdd33 [32] Vss Vss AC pclk aVssq Vdd33 (aVss) sdadr [13] sdadr [11] AD Vss coreclk_ aVddq byp_in (aVdd 18) Vss Vss AE Vss AF sddata sddata sddata sddqm sddata pci_clk aVdd18 [44] [40] [39] [4] [35] 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Vdd33 SDRAM I 2C Multi-function pins aVdd18 aVss Vss PLLs CRT (DRC) Vdd18 PCI JTAG I2S Figure 3-2: MAP-CA DSP pins viewed from top MAP-CA DSP Datasheet June 20, 2001 Hitachi, Ltd. 17 Chapter 4 4.1 Signal Descriptions Interface Summary ( ) --- valid during boot-up < > --- valid during reset # --- active low signal MAP-CA DSP pclk coreclk_byp_in pixelclk_byp_in / xmt_clk audioclk_out tcia_vdac sdclk_byp_in audioclk_byp_in pclk_out Processor Clock (PLL) pci_ad[31:0] pci_cbe[3:0] pci_frame# pci_trdy# pci_irdy# pci_stop# pci_par pci_devsel# pci_clk pci_rst# pci_inta# pci_idsel pci_req#[2:0] pci_gnt#[2:0] pci_serr_intb# pci_pme# PCI iis_in_data iis_in_lr iis_in_bclk iis_out_lr iis_out_bclk I2S (rom_addr[19]/rom_addr[21]/rom_addr[1])/ ntsc_out_hsync / xmt_req (rom_addr[18]/rom_addr[20]/rom_addr[0])/ ntsc_out_vsync / rcv_ack <reset_strap[7:0]>/ (rom_addr[9:2]/rom_addr[17:10]/rom_data[7:0])/ ntsc_out_data[7:0] / xmt_data_out[7:0] iic_sda iic_sck iic_select I2C input A CRT (DRC) Video Input input B (rom_oe#)/iis_out_data[2] (rom_wrt#)/iis_out_data[1] (rom_ale)/iis_out_data[0] rom_cs# SDRAM Controller Flash ROM IEC958 Video Output JTAG sdadr[13:0] sddata[63:0] sdcs[3:0]# sdras# sdcas# sdwe# sddqm[7:0] sdclk sdclk1 sdclk2 sdrtnclk vsync hsync gdac_fscale gdac_comp gdac_blue gdac_green gdac_red tcia_inuse tcia_sync tcia_clk tcia_err# / ntsc_ina_vsync / xmt_ack tcia_enable / ntsc_ina_hsync / rcv_req tcia_data[7:0] / ntsc_ina_data[7:0] / rcv_data_in[7:0] ntsc_ina_clk27 / rcv_clk tcib_inuse tcib_sync tcib_clk tcib_err# / ntsc_inb_vsync tcib_enable / ntsc_inb_hsync tcib_data[7:0] / ntsc_inb_data[7:0] ntsc_inb_clk27 iec958_in iec958_out tck tms tdi tdo trst Figure 4-1: MAP-CA DSP Interface Equator Technologies, Inc. MAP-CA DSP Datasheet June 20, 2001 18 Legend 4.2 Legend All tables in this section use the following abbreviations: A ..................................... analog signal B...................................... bi-directional I ....................................... input O ..................................... output od .................................... open drain or active pull down trailing "_" ...................... active low ()...................................... parentheses indicate number of shared signal pins 4.3 Processor Clock There is a single 27 MHz reference clock signal for generating internal clocks. # of Pins I/O Description pclk 1 I three on-chip PLLs. It is also a reference clock for the video output and the I2C interface coreclk_byp_in 1 I Bypass input for the core clock sdclk_byp_in 1 I Bypass input for the SDRAM clock. pixelclk_byp_in 1 I Transmit clock for GPDP (xmt_clk) or PLL-bypass input for pixel clock audioclk_byp_in 1 I Bypass input for the audio clock. pclk_out (coreclk_out) 1 O Output for the core clock. pixelclk_out 1 O Output for the pixel clock. audioclk_out 1 O Audio clock output used for I2S interface master MCLK tcia_vdac 1 O Sigma-delta output from software loop filter for controlling external VCXO for pclk TOTAL 9 Signal 27 MHz VCXO input that serves as the reference signal to the Table 4-1: Processor Clock Signal Description MAP-CA DSP Datasheet June 20, 2001 Hitachi, Ltd. SDRAM 4.4 19 SDRAM The MAP-CA DSP supports either SDRAM or SGRAM memory system using the signals shown in Table 4-2. The MAP-CA digital signal processor supports a memory system of 64-bit or 32-bit data width. The MAP-CA DSP supports DRAM widths of 8-bit, 16-bit or 32-bits. Signal sdadr[13:0] # of Pins I/O Description 14 O Address lines indicate row addresses when sdras_ is active and indicate column addresses when sdcas_ is active sddata[63:0] 64 B Data Input/Output lines transfer data between the memory and the MAP-CA DSP. These are also input mask bits for Write-per-Bit. When block write is activated, these lines provide column address mask sdcs_[3:0] 4 O Chip Select signal lines indicate that the command on the output lines is for each memory chip. If this signal is high, the output command(s) will be ignored by each corresponding memory chip sdras_ 1 O sdras_ is part of the output command to the SDRAM/SGRAM sdcas_ 1 O sdcas_ is part of the output command to the SDRAM/SGRAM sdwe_ 1 O Write enable (sdwe_) is part of the output command sddqm[7:0] 8 O During read, sddqm=1 turns off the output buffers of SDRAM/SGRAM. During write, sddqm=1 prevents a write to the current memory location sdclk,sdclk1,sdclk2 3 O sdclk, sdclk1 and sdclk2 are driven by the MAP-CA DSP SDRAM clock. All SDRAM/SGRAM input signals are sampled on the positive edge of sdclk sdrtnclk 1 I sdrtnclk is driven by sdclk. This signal is used for latching the data from SDRAM/SGRAM TOTAL 97 Table 4-2: Memory Interface Signals Equator Technologies, Inc. MAP-CA DSP Datasheet June 20, 2001 20 PCI Bus 4.5 PCI Bus The MAP-CA DSP provides the PCI bus as the primary system interface. Table 4-3 lists the PCI signals. Signal pci_ad[31:0] # of Pins I/O Description 32 B PCI multiplexed address and data lines. The address is driven when pci_frame_ is first asserted. Data is transferred on this bus in subsequent clocks. pci_cbe_[3:0] 4 B For PCI cycles, the bus command and byte enables are used to transfer the PCI command during the address phase and are used to transfer byte lane enables during subsequent data phases. pci_frame_ 1 B Transaction framing for PCI transfers. The initial assertion indicates the address phase and the start of a PCI transaction. Continued assertion determines the burst size of the transaction. pci_trdy_ 1 B The target ready signal is asserted when the PCI target is ready for a data transfer. pci_irdy_ 1 B The initiator ready signal is asserted when the PCI master is ready for a data transfer. pci_stop_ 1 B pci_stop_ is asserted by the target to request the master to stop the current transaction. pci_par 1 B A single parity bit is calculated over pci_ad[31:0], and pci_c_be[3:0] and transferred over this signal. B A target asserts the pci_devsel_ signal line to indicate it has decoded the address on the pci_ad[31:0] bus and will participate in (claim) the current transaction. The PCI bus master must monitor the pci_devsel_ signal line to determine if a target bus has claimed the transaction or if it will execute a Master Abort termination. pci_devsel_ will be tri-stated from the leading edge of pci_rst_. pci_devsel_ remains tri-stated until driven by the target. I pci_clk provides timing for all PCI transactions on the PCI bus. All other PCI signals are sampled on the rising edge of pci_clk, and all timing parameters are defined with respect to this edge. NOTE: The MAP-CA DSP core clock PLL does not use this clock as a core PLL reference clock. I This signal indicates a reset of all PCI resources. In addition, the internal MAP-CA DSP CPU core, etc. are reset by the assertion of this signal. PCI pad cell drivers are disabled by the assertion of this signal, as specified in the PCI 2.1 document. pci_devsel_ pci_clk pci_rst_ 1 1 1 Table 4-3: PCI Interface Signals MAP-CA DSP Datasheet June 20, 2001 Hitachi, Ltd. PCI Bus 21 Signal # of Pins I/O Description pci_inta_ 1 B (od) When the MAP-CA digital signal processor is not designated as the PCI bus "HOST", then this signal is the open drain output generating an asynchronous level sensitive interrupt on the PCI bus. The MAP-CA DSP pad cell does not contain a pull up for this signal. When the MAP-CA DSP is designated as the PCI bus "HOST" then this signal is an interrupt request input from PCI devices. The MAP-CA DSP sees and utilizes this interrupt. pci_idsel 1 I The initialization device select is used as a slot addressed chip select input during configuration read and write transactions. This signal is inactive in a self-hosted configuration. pci_req_[2:0] 3 B The assertion of pci_req_ in a non-self-hosted configuration indicates that the MAP-CA DSP desires the use of the PCI bus. pci_gnt_[2:0] 3 B The assertion of pci_gnt_ in a non-self-hosted environment indicates that the MAP-CA DSP has been granted the use of the PCI bus. B (od) This open drain output may generate either an asynchronous level sensitive interrupt or the PCI bus or optionally signal SYSTEM ERROR. See the MAP-CA digital signal processor configuration control register for the signal's current use. When the MAP-CA DSP is not designated as the PCI bus "HOST", then this signal is the open drain output generating an asynchronous level sensitive interrupt on the PCI bus. The MAP-CA DSP pad cell does not contain a pull up for this signal. When the MAP-CA DSP is designated as the PCI bus "HOST" , then this signal is an interrupt request input from PCI devices. The MAP-CA DSP sees and utilizes this interrupt. B (od) When MAP-CA DSP is not in PCI host mode, this signal is an open drain output used to request a change in power management state. When MAP-CA DSP is in PCI host mode, this is an input signal to which PCI devices indicate changes in power management state. pci_serr_intb_ 1 pci_pme_ 1 TOTAL 54 Table 4-3: PCI Interface Signals Equator Technologies, Inc. MAP-CA DSP Datasheet June 20, 2001 22 IEC958 4.6 IEC958 The MAP-CA DSP provides an IEC958 interface as shown in Table 4-4. Signal # of Pins I/O Description iec958_in 1 I Serial input line for IEC958 digital audio. iec958_out 1 O Serial output line for IEC958 digital audio. TOTAL 2 Table 4-4: IEC958 Interface Signals 4.7 I2S The MAP-CA DSP provides interfaces for I2S digital audio input and output as shown in Table 4-5. # of Pins I/O iis_in_data 1 I Serial data input iis_in_lr 1 I Select left/right channel in the serial input iis_in_bclk 1 I I2S input bit clock iis_out_data[2:0] 3 O Serial output data (3 stereo lines) iis_out_lr 1 O Select left/right channel in serial output lines iis_out_bclk 1 O I2S output bit-rate clock TOTALa 8 Signal Description Table 4-5: I2S Interface Signals a. audioclk_out, defined in Section 4.3 on page 18, serves as the output MCLK in master mode. MAP-CA DSP Datasheet June 20, 2001 Hitachi, Ltd. Multi-Function Signal Pins 4.8 23 Multi-Function Signal Pins Table 4-6 lists the pin name and pin number of the shared pins on the MAP-CA digital signal processor, along with the signal name associated with each mode-specific function. Ball # Pin Name ITU-656 Mode TCI Mode GPDP Mode ROM Boot Mode Reset Mode B4 pixelclk_byp_in - - xmt_clk - - C5 ntsc_out_data[3] - - xmt_data_out[3] rom_addr[5,13]/rom_data[3] reset_strap[3] B5 ntsc_out_data[4] - - xmt_data_out[4] rom_addr[6,14]/rom_data[4] reset_strap[4] A4 ntsc_out_data[5] - - xmt_data_out[5] rom_addr[7,15]/rom_data[5] reset_strap[5] C6 ntsc_out_data[6] - - xmt_data_out[6] rom_addr[8,16]/rom_data[6] reset_strap[6] D7 ntsc_out_data[7] - - xmt_data_out[7] rom_addr[9,17]/rom_data[7] reset_strap[7] B6 video_ina[0] ntsc_ina_data[0] tcia_data[0] rcv_data_in[0] - - C7 video_ina[1] ntsc_ina_data[1] tcia_data[1] rcv_data_in[1] - - D8 video_ina[2] ntsc_ina_data[2] tcia_data[2] rcv_data_in[2] - - A6 video_ina[3] ntsc_ina_data[3] tcia_data[3] rcv_data_in[3] - - B7 video_ina[4] ntsc_ina_data[4] tcia_data[4] rcv_data_in[4] - - A7 video_ina[5] ntsc_ina_data[5] tcia_data[5] rcv_data_in[5] - - C8 video_ina[6] ntsc_ina_data[6] tcia_data[6] rcv_data_in[6] - - D9 video_ina[7] ntsc_ina_data[7] tcia_data[7] rcv_data_in[7] - - B8 video_ina[8] ntsc_ina_hsync tcia_enable rcv_req - - C9 video_ina[9] ntsc_ina_vsync tcia_err# xmt_ack - - A10 ntsc_ina_clk27 rcv_clk - - C11 video_inb[0] - - ntsc_inb_data[0] tcib_data[0] - - - B11 video_inb[1] ntsc_inb_data[1] tcib_data[1] - - - A11 video_inb[2] ntsc_inb_data[2] tcib_data[2] - - - D12 video_inb[3] ntsc_inb_data[3] tcib_data[3] - - - C12 video_inb[4] ntsc_inb_data[4] tcib_data[4] - - - B12 video_inb[5] ntsc_inb_data[5] tcib_data[5] - - - A13 video_inb[6] ntsc_inb_data[6] tcib_data[6] - - - C13 video_inb[7] ntsc_inb_data[7] tcib_data[7] - - - D13 video_inb[8] ntsc_inb_hsync tcib_enable - - - video_inb[9] ntsc_inb_vsync tcib_err# B13 - - - J2 iis_out_data[0] - - - rom_ale - J3 iis_out_data[1] - - - rom_wrt# - H2 iis_out_data[2] - - - rom_ole# - F3 ntsc_out_hsync - - xmt_req rom_addr[21,19,1] - E1 ntsc_out_vsync - - rcv_ack rom_addr[20,18,0] - 22 ntsc_out_data[0] - - xmt_data_out[0] rom_addr[2,10]/rom_data[0] reset_strap[0] E3 ntsc_out_data[1] - - xmt_data_out[1] rom_addr[3,11]/rom_data[1] reset_strap[1] C1 ntsc_out_data[2] - - xmt_data_out[2] rom_addr[4,12]/rom_data[2] reset_strap[2] Table 4-6: Multiple Signal Pins Equator Technologies, Inc. MAP-CA DSP Datasheet June 20, 2001 24 Multi-Function Signal Pins 4.8.1 Transport Channel Interfaces (TCI) The MAP-CA digital signal processor provides two parallel/serial TCI interfaces. See Table 4-7 and Signal # of Pins I/O Description tcia_data[7:0] (8) I TCI data input: All 8 bits of input are used in parallel mode. Only tci_data[0] is used in serial mode tcia_enable (1) I Transport channel enable: 1 = accept a TCI input sample 0 = ignore TCI input sample tcia_inuse 1 O Video input port external mux select. This pin can also be used as a general purpose output if dynamic muxing of the video input is not required. tcia_sync 1 I Demodulator/FEC has marked the synchronization point in the MPEG2 transport stream packet. The packet size is programmable. tcia_err_ (1) I This active low signal indicates that the Demodulator/FEC has detected an uncorrectable error in the current packet. tcia_clk 1 I Transport channel clock TOTAL 3(10) Table 4-7: Primary TCI Interface Signals Table 4-8. Signal # of Pins I/O Description tcib_data[7:0] (8) I TCI data input: All 8-bits of input are used in parallel mode. Only tci_data[0] is used in serial mode. tcib_enable (1) I Transport channel enable: 1 = accept a TCI input sample 0 = ignore TCI input sample tcib_inuse 1 O Video input port external mux select. This pin can also be used as a general purpose output if dynamic muxing of the video input is not required. tcib_sync 1 I Demodulator/FEC has marked the synchronization point in the MPEG2 transport stream packet. The packet size is programmable. tcib_err_ (1) I This active low signal indicates that the Demodulator/FEC has detected an uncorrectable error in the current packet. tcib_clk 1 I Transport channel clock TOTAL 3(10) Table 4-8: Secondary TCI Interface Signals MAP-CA DSP Datasheet June 20, 2001 Hitachi, Ltd. Multi-Function Signal Pins 4.8.2 25 ITU-656 Inputs Analog video can be digitized according to ITU-R BT.601/656 via a NTSC, PAL or SVIDEO decoder and then input to the MAP-CA DSP. The interface signals for the primary and secondary video inputs are shown in Table 4-9 and Table 4-10. # of Pins I/O ntsc_ina_clk27 1 I 27MHz clock from video decoder ntsc_ina_hsync (1) I Horizontal sync ntsc_ina_vsync (1) I Vertical sync ntsc_ina_data[7:0] (8) I ITU-R BT.601/656 formatted video input stream Signal TOTAL Description 1(10) Table 4-9: Primary ITU-R BT.601/656 Input Interface Signals # of Pins I/O ntsc_inb_clk27 1 I 27MHz clock from video decoder ntsc_inb_hsync (1) I Horizontal sync ntsc_inb_vsync (1) I Vertical sync ntsc_inb_data[7:0] (8) I ITU-R BT.601/656 formatted video input stream Signal TOTAL Description 1(10) Table 4-10: Secondary ITU-R BT.601/656 Input Interface Signals 4.8.3 ITU-656 Output The MAP-CA digital signal processor has a digital ITU-R BT.601/656 output interface as shown in Table 4-11. # of Pins I/O (1) I 27MHz pixel clock from VCXO clock input. See Section 4.3. ntsc_out_hsync 1 O Horizontal sync ntsc_out_vsync 1 O Vertical sync ntsc_out_data[7:0] 8 B ITU-R BT.601/656 formatted NTSC/PAL output data configured as input only when used for ROM interface or reset strap Signal pclk TOTAL Description 10(1) Table 4-11: ITU-R BT.601/656 Output Interface Signals Equator Technologies, Inc. MAP-CA DSP Datasheet June 20, 2001 26 Multi-Function Signal Pins 4.8.4 General Purpose Data Port (GPDP) The primary video input port and the video output port can be coupled together to function as a general purpose 8-bit duplex data port. # of Pins I/O xmt_clk (1) I transmitter output clock, shared with pixelclk_byp_in xmt_req (1) O GPDP on MAP-CA digital signal processor is ready to transmit data. Shared with ntsc_out_hsync xmt_ack (1) I output source is ready to accept data, shared with video_ina[9] xmt_data_out[7:0] (8) O Parallel data output on ntsc_out_data[7:0] rcv_clk (1) I Receiver input clock shared with ntsc_ina_clk27 rcv_req (1) I Input source is ready to send data. Shared with video_ina[8] rcv_ack (1) O GPDP on MAP-CA DSP is ready to accept data, shared with ntsc_out_vsync rcv_data_in[7:0] (8) I Parallel data input on video_ina[7:0] TOTAL (22) Signal Description Table 4-12: GPDP Interface Signals 4.8.5 Flash ROM A Flash ROM (EEPROM) interface is provided on the MAP-CA digital signal processor to assist in boot-up. The Flash ROM is active during the boot up process and must be disabled through its chip-select signal. See Section 3.3.2, Equator Hardware Reference Manual, Volume 4, MAP-CA I/O Interfaces for information about programming the timing parameters of the ROM interface. MAP-CA DSP Datasheet June 20, 2001 Hitachi, Ltd. Multi-Function Signal Pins 27 # of Pins I/O rom_cs_ 1 O This pin is the chip enable signal. rom_oe_ (1) O This active low signal is asserted on ROM read cycles. This signal is multiplexed with iis_out_data[2]. rom_wrt_ (1) O This active low signal is asserted on ROM write cycles. This signal is multiplexed with iis_out_data[1]. O Address latch enable: rom_addr[9:2] and rom_addr[19:18] are latched on the falling edge, rom_addr[17:10] and rom_addr[21:20] are latched on the rising edge; this signal is multiplexed with iis_out_data[0]. Signal rom_ale (1) Description rom_addr[19:18]/ rom_addr[21:20]/ rom_addr[1:0] (2) O rom_addr[19]/rom_addr[21]/rom_addr[1] ntsc_out_hsync. rom_addr[18]/rom_addr[20]/rom_addr[0] ntsc_out_vsync. rom_addr[9:2]/ rom_addr[17:10]/ rom_data[7:0] (8) B ROM data and address bus. These signals are multiplexed with ntsc_out_data[7:0]. TOTAL is muxed with is muxed with 1(13) Table 4-13: ROM Interface Signals 4.8.6 Reset Straps The board resistor straps are sampled on the de-assertion (rising edge) of pci_rst_. Signal # of Pins I/O Description reset_strap[7:4] (sw_strap[3:0]) (4) I Resistor straps for use by software. These signals are multiplexed with rom_data[7:4] and ntsc_out_data[7:4]. reset_strap[1] (pci_host) (1) I VDD = 1 = MAP-CA DSP is hosting the primary PCI bus GND = 0 = MAP-CA DSP is not hosting The signal is multiplexed with rom_data[1] and ntsc_out_data[1]. I VDD = 1 = Flash ROM is used for boot GND = 0 = ROMless boot The signal is multiplexed with rom_data[0] and ntsc_out_data[0]. reset_strap[0] (rom_boot) (1) TOTAL (6) Table 4-14: Reset Straps Equator Technologies, Inc. MAP-CA DSP Datasheet June 20, 2001 28 Analog CRT 4.9 Analog CRT An RGB monitor can be directly driven by the MAP-CA digital signal processor. # of Pins I/O vsync 1 O Vertical synchronization signal for CRT hsync 1 O Horizontal synchronization signal for CRT gdac_fscale 1 A Full scale current adjusting resistor gdac_comp 1 A Vref bypass and compensation capacitor gdac_blue 1 A Analog blue output gdac_green 1 A Analog green output gdac_red 1 A Analog red output TOTAL 7 Signal Description Table 4-15: CRT Interface Signals 4.10 I2C The MAP-CA DSP provides an I2C interface to communicate with external peripherals such as NTSC decoders, NTSC encoders, and demodulators. The pin description is shown in Table 4-16. Signal # of Pins I/O Description iic_sda 1 B (od) I2C data line iic_sck 1 B (od) I2C clock line iic_select 1 TOTAL 3 O I2C-bus external mux select. This pin can also be used as general purpose output Table 4-16: I2C Interface Signals MAP-CA DSP Datasheet June 20, 2001 Hitachi, Ltd. Boundary Scan (JTAG) 29 4.11 Boundary Scan (JTAG) MAP-CA DSP supports boundary scan interface based on IEEE 1149.1 Standard Test Access Port and Boundary-Scan Architecture for testing the MAP-CA DSP and other devices on the board. A BSDL (Boundary Scan Description Language) file is available from Equator. # of Pins I/O Description tck 1 I Reference clock. This specifies the timing for all the transactions of JTAG interface. tms 1 I Test interface mode select signal. tdi 1 I Test interface data input tdo 1 O Test interface data output trst 1 I Active-low reset for the circuitry. It must be low at power up. TOTAL 5 Signal Table 4-17: JTAG Interface Signals 4.11.1 Pull Up Resistors The IEEE 1149.1 requires that TDI, TMS, and TRST have internal pull-up resistors. In the MAP-CA digital signal processor, TRST has an internal pull-down resistor and TRST, as well as other TAP pins, can be left unconnected if the system does not use Boundary Scan. 4.11.2 TAP State Machine Figure 4-2 shows the internal states of the TAP (Test Access Port) state machine. These conform to the state transitions specified by IEEE 1149.1. The state changes according to the value on TMS at the rising edge of TCK. The TDI value is sampled at the rising edge of TCK, and shifted at the falling edge. The TDO value changes at the falling edge of TCK. When not in the Shift-DR or Shift-IR state, TDO has a high-impedance. If TRST is zero, TDO goes to the Test Logic Reset state asynchronously. Equator Technologies, Inc. MAP-CA DSP Datasheet June 20, 2001 30 Boundary Scan (JTAG) 1 Test Logic Reset 0 0 Select DR Scan 1 1 Select IR Scan 0 Run Test/Idle 1 0 1 Capture DR Capture IR 0 0 0 0 Shift DR Shift IR 1 Exit1 DR 1 1 Exit1 IR 0 1 Pause DR Pause IR 1 Exit2 DR 1 0 Exit2 IR 1 1 1 1 0 0 0 1 Update DR Update IR 0 1 0 Figure 4-2: TAP State Transition Diagram 4.11.3 Instruction Registers The MAP-CA digital signal processor supports public instructions defined in IEEE 1149.1. Encoding of the Boundary Scan instructions are listed in Table 4-18. The instruction register is five bits long and instruction bit combinations not listed here are reserved. Instruction Code Description BYPASS 0b11111 connects TDI and TDO with one bit shift register EXTEST 0b00000 The instruction connects the boundary scan registers and the MAP-CA digital signal processor system pins. SAMPLE/ PRELOAD 0b11100 sample the MAP-CA DSP output or load the MAP-CA DSP input, without affecting the MAP-CA DSP system pins IDCODE 0b11001 connects the MAP-CA DSP device with the Device Identification Register between TDI and TDO INTEST 0b11011 The instruction connects boundary scan registers and MAP-CA DSP internals. CLAMP 0b11101 sets all system output pins to the value previously loaded by boundary scan instruction. HIGHZ 0b11110 places all system output pins in a high-impedance state. Table 4-18: JTAG Instructions MAP-CA DSP Datasheet June 20, 2001 Hitachi, Ltd. Boundary Scan (JTAG) 31 4.11.4 Test Data Registers Figure 4-3 illustrates the structure of the boundary scan logic.. Boundary Scan Register Device ID Register Bypass Register Decode Logic TDO Instruction Register TDI TMS TCK TRST TAP Controller Figure 4-3: Boundary Scan Block Diagram 4.11.5 Boundary Scan Register The boundary scan register is a shift register on the PAD for controlling the MAP-CA digital signal processor's system pins. Using EXTEST and SAMPLE/PRELOAD commands, it can perform a JTAG (IEEE 1149.1) compliant boundary scan test. The relation between the MAP-CA DSP pins and the boundary scan register can be found in the BSDL. 4.11.6 Device Identification Register Figure 4-4 shows the format of the Device Identification Register. For the MAP-CA DSP, the Manufacturer's ID is a twelve bit value equal to b000000001111. The upper twelve bits of the Part Number are b010001010011. The lower four bits of the Part Number and the Version Number varies according to the major or minor revision of the MAP-CA DSP. 4 bit 16 bit 12 bit Version Part Number Manufacturer's ID Figure 4-4: Device Identification Register Equator Technologies, Inc. MAP-CA DSP Datasheet June 20, 2001 32 Power/Ground Pins 4.12 Power/Ground Pins The following power and ground pins are provided on MAP-CA digital signal processor. Name # of Pins Description Vdd18 30 Digital Core Vdd Vdd33 27 I/O Power Supply 3.3V Vss 57 Digital Vss aVdd18 3 Clean analog Vdd aVss 4 Clean analog Vss aVdd33 1 Clean analog Vdd aVddq 1 Clean analog Vdd for Core PLL aVssq 1 Clean analog Vss for Core PLL aVddx 1 Clean analog Vdd for Video DAC aVssx 1 Clean analog Vss for Video DAC gdac_cvgg 1 Clean analog Vss for Video DAC TOTAL 127 Table 4-19: Power/Ground Pins MAP-CA DSP Datasheet June 20, 2001 Hitachi, Ltd. Signal List Summary 33 4.13 Signal List Summary Interface Frequency Pin Count 9 Remarks reference clocks including bypass clocks MAP-CA DSP clocks Various PCI 66/33 MHz SDRAM 133 MHz Flash ROM 5 MHz Reset straps - IEC958 32/44.1/48 kHz sample rate 2 digital audio I/O I2S 32/44.1/48 kHz sample rate 1.536/2.116 MHz bit rate 8 digital audio I/O ITU-R BT.601/656 In 27 MHz Parallel/Serial TCI 30/80 MHz GPDP 60 MHz 54 host/system interface 97 memory interfaces 1(13) EEPROM) (6) configuration inputs ITU-R BT.601/656 Out 27 MHz two video input streams: 2 TCI or 28 2 ITU-656, or (22)a 1 TCI and 1 ITU-656, or GPDP and 1 video input (TCI or ITU-656) 10(1) digital video out or GPDP CRT out 25-110 MHz 7 analog video out I2C 100/400 kHz 3 peripheral control Test 25 MHz 5 boundary scan (JTAG) Signal pins total - 220 Power/Ground - 127 Miscellaneous TOTAL (SDRAM, - 2 reserved (tie to ground) - 3 no connection (leave floating) 352 Table 4-20: MAP-CA DSP Pin List a. See Section 4.8.4 for more information about the GPDP shared pins. Equator Technologies, Inc. MAP-CA DSP Datasheet June 20, 2001 34 MAP-CA DSP Datasheet June 20, 2001 Signal List Summary Hitachi, Ltd. 35 Chapter 5 5.1 External Connection Examples SDRAM sdcs#[0] sdadr[13,9:0] sddata[63:32] sdras# sdcas# sdwe# sdqm[7:4] sdclk sdrtnclk sdcs#[1] sdcs#[2] N.C. 128 K 2 Banks x 32-bit SDRAM 128 K 2 Banks x 32-bit SDRAM 128 K 2 Banks x 32-bit SDRAM 128 K 2 Banks x 32-bit SDRAM sddata[63:32] sddqm[7:4] sdcs#[3] N.C. Figure 5-1: 64-bit, 4MB configuration using x32, 8Mb parts sdcs#[0] sdadr[13,10:0] sddata[63:56] sdras# sdcas# sdwe# sdqm[7] sdclk sdrtnclk sdcs#[1] N.C. sddata[31:24] 1M 2 Banks x 8 bit SDRAM sddqm[3] 1M 2 Banks x 8 bit SDRAM sdcs#[2] sddata[23:16] sddata[55:48] sddqm[6] 1M 2 Banks x 8 bit SDRAM sddqm[2] 1M 2 Banks x 8 bit SDRAM N.C. sdcs#[3] sddata[47:40] sddqm[5] sddata[16:8] 1M 2 Banks x 8 bit SDRAM sddata[39:32] sddqm[4] sddqm[1] 1M 2 Banks x 8 bit SDRAM N.C. sddata[7:0] 1M 2 Banks x 8 bit SDRAM sddqm[0] 1M 2 Banks x 8 bit SDRAM Figure 5-2: 64-bit, 16 MB configuration using x8, 16 Mb parts Equator Technologies, Inc. MAP-CA DSP Datasheet June 20, 2001 36 SDRAM sdcs#[0] sdadr[13:0] sddata[63:48] sdras# sdcas# sdwe# sdqm[7:6] sdclk sdrtnclk sdcs#[1] sdcs#[2] N.C. 1M 4 Banks x 16-bit SDRAM 1M 4 Banks x 16-bit SDRAM sdcs#[3] sddata[47:32] sddqm[5:4] 1M 4 Banks x 16-bit SDRAM 1M 4 Banks x 16-bit SDRAM 1M 4 Banks x 16-bit SDRAM 1M 4 Banks x 16-bit SDRAM 1M 4 Banks x 16-bit SDRAM 1M 4 Banks x 16-bit SDRAM N.C. sddata[31:16] sddqm[3:2] sddata[15:0] sddqm[1:0] Figure 5-4: 64-bit, 64 MB configuration using x16, 64 Mb parts MAP-CA DSP Datasheet June 20, 2001 Hitachi, Ltd. SDRAM 37 sdcs#[0] sdadr[13,10:0] sddata[63:48] sdras# sdcas# sdwe# sdqm[7:6] sdclk sdrtnclk sdcs#[1] sdcs#[2] N.C. 512 K 2 Banks x 16-bit SDRAM 512 K 2 Banks x 16-bit SDRAM sdcs#[3] sddata[47:32] sddqm[5:4] 512 K 2 Banks x 16-bit SDRAM 512 K 2 Banks x 16-bit SDRAM 512 K 2 Banks x 16-bit SDRAM 512 K 2 Banks x 16-bit SDRAM 512 K 2 Banks x 16-bit SDRAM 512 K 2 Banks x 16-bit SDRAM N.C. sddata[31:16] sddqm[3:2] sddata[15:0] sddqm[1:0] Figure 5-3: 64-bit, 16 MB configuration using x16 16Mb parts sdcs#[0] sdadr[13:0] sddata[63:48] sdras# sdcas# sdwe# sdqm[7:6] sdclk sdrtnclk sdcs#[1] sdcs#[2] N.C. 2M 4 Banks x 16 bit SDRAM 2M 4 Banks x 16 bit SDRAM sdcs#[2] sddata[47:32] sddqm[5:4] 2M 4 Banks x 16 bit SDRAM 2M 4 Banks x 16 bit SDRAM 2M 4 Banks x 16 bit SDRAM 2M 4 Banks x 16 bit SDRAM 2M 4 Banks x 16 bit SDRAM 2M 4 Banks x 16 bit SDRAM N.C. sddata[31:16] sddqm[3:2] sddata[15:0] sddqm[1:0] Figure 5-6: 64-bit, 128MB configuration using x16, 128Mb parts Equator Technologies, Inc. MAP-CA DSP Datasheet June 20, 2001 38 IEC958 sdcs#[0] sdcs#[1] N.C. sdadr[13:0] sddata[63:48] sdras# sdcas# sdwe# sdqm[7:6] sdclk sdrtnclk 2M 4 Banks x 16 bit SDRAM sdcs#[2] sddata[47:32] 2M 4 Banks x 16 bit SDRAM sddqm[5:4] N.C. sdcs#[2] sddata[31:16] 2M 4 Banks x 16 bit SDRAM sddqm[3:2] N.C. sddata[15:0] 2M 4 Banks x 16 bit SDRAM sddqm[1:0] Figure 5-5: 64-bit, 64MB configuration using x16, 128Mb parts iec958_out iec958_in IEC958 COUPLER IEC958 Interface IEC958 MAP-CA DSP 5.2 Figure 5-7: IEC958 Interface MAP-CA DSP Datasheet June 20, 2001 Hitachi, Ltd. I2 S I2S Interface MAP-CA DSP iis_in_bclk iis_in_lr iis_in_data iis_out_bclk iis_out_lr iis_out_data[0] iis_out_data[1] iis_out_data[2] audioclk_out ADC I2S I2S Audio CODEC DAC 5.3 39 I2S Audio DAC I2S Audio DAC Figure 5-8: I2S Interface NOTE: Reference designs may use iis_out_bclk and iis_out_lr as input clocks. See the reference board documentation. Equator Technologies, Inc. MAP-CA DSP Datasheet June 20, 2001 40 VIDEO IN PORT 0 Transport Channel Interface (TCI) MAP-CA DSP 5.4 Transport Channel Interface (TCI) tcia_clk tci_data tcia_enable tcia_sync tcia_err# SATELLITE/CABLE SOURCE DECODER (QAM-QPSK) & FORWARD ERROR CORRECTION tcia_inuse 5V O.C. 1K tcia_vdac ) ) cer. tant. 6K VCXO 27MHz pclk Figure 5-9: Transport Channel Interface MAP-CA DSP Datasheet June 20, 2001 Hitachi, Ltd. NTSC Decoder 5.5 41 NTSC Decoder Video In Port 0 MAP-CA DSP ntsc_ina_hsync ntsc_ina_vsync NTSC/PAL Decoder ntsc_ina_data[7:0] ntsc_ina_clk27 pixel_clk Figure 5-10: ITU-R BT.656 NTSC/PAL Decoder Interface 5.6 NTSC Encoder ITU-R BT.601/656 Output MAP-CA DSP ntsc_out_hsync ntsc_out_vsync NTSC/PAL Encoder ntsc_out_data[7:0] pclk VCXO 27MHz Figure 5-11: NTSC/PAL Encoder Interface Equator Technologies, Inc. MAP-CA DSP Datasheet June 20, 2001 42 5.7 CRT CRT ANALOG CRT INTERFACE MAP-CA DSP gdac_green 75 C Z0 = 37.5 L Zl = 75 C gdac_blue gdac_red vsync hsync NOTE: gdac_blue and gdac_red have the same connections as those of gdac_green. gdac_comp Vref = 1.235V gdac_fscale R = 1117 Figure 5-12: CRT 5.8 I2C Other data line iic_select I2C clock line iic_sck MUX I2C MAP-CA DSP iic_sda MUX I2C data line Other clock line Figure 5-13: I2C Interface MAP-CA DSP Datasheet June 20, 2001 Hitachi, Ltd. ROM 5.9 43 ROM rom_data[7:0] latch rom_ale addr[21:20] latch FLASH ROM addr[17:10] latch FLASH ROM INTERFACE MAP-CA DSP latch addr[9:2] addr[19:18] rom_addr[1:0] rom_cs_l rom_wr_l rom_oe_l Figure 5-14: ROM Connections Equator Technologies, Inc. MAP-CA DSP Datasheet June 20, 2001 44 MAP-CA DSP Datasheet June 20, 2001 ROM Hitachi, Ltd. 45 Chapter 6 6.1 Electrical Specifications Absolute Maximum Ratings Stresses which occur above or below those listed in Table 6-1 may cause permanent damage to the MAP-CA digital signal processor. This is a stress rating only, and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameter Min Max Unit Vdd18 (measured to Vss) -0.5 2.5 V Vdd33 (measured to Vss) -0.5 4.6 V aVdd18 (measured to aVss) -0.5 2.5 V aVdd33 (measured to aVss) -0.5 4.6 V aVddq (measured to aVssq) -0.5 2.5 V aVddx (measured to aVss) -0.5 2.5 V a - 0.5 Vdd33 + 0.5 V -55 125 C 0 85 C Voltage on any signal pin Storage Temperature Junction Temperature Table 6-1: Absolute Maximum Ratings a. 6.2 This device employs CMOS devices on all signal pins. It should be handled as an ESD sensitive device. Voltage on any signal pin that exceeds the power supply voltage by more than +0.5 V can induce destructive latchup. Power Supply Specifications Power Supply Nominal Voltage Voltage Variation Vdd18 1.8 V 5% Vdd33 3.3 V 5% aVdd18 1.8 V 5% aVdd33 3.3 V 5% aVddx 1.8 V 5% Table 6-2: Voltage Variation Equator Technologies, Inc. MAP-CA DSP Datasheet June 20, 2001 46 DC Characteristics The typical estimated total power consumption is 6 W. NOTE: During power-up, Vdd18 must come up before or simultaneously with Vdd33. Vdd33 should not exceed Vdd18 by more than 0.4 V while Vdd18 is less than 1V. There is no restriction on the power-down sequence. Power Supply Nominal Voltage Estimated Max Steady State Current Vdd18 1.8 V 2.8 A Vdd33 3.3 V 0.25 A aVdd18 1.8 V 10 mA aVdd33 3.3 V 80 mA aVddx 1.8 V 5 mA Table 6-3: Steady State Current 6.3 DC Characteristics Parameter Description Condition Min Max Unit VIL input low voltage - -0.5 0.7 V VIH input high voltage - 0.5 Vdd33 Vdd33 + 0.5 V VOL output low voltage Iout = 1500 A - 0.1 Vdd33 V VOH output high voltage Iout = 500 A 0.9 Vdd33 - V ILI input leakage current 0 < Vin < Vdd33 -10 10 A IOZ tri-state output leakage 0 < Vin < Vdd33 -10 10 A CIN input pin capacitance - - 10 pF CIDSEL idsel pin capacitance - - 8 pF CCLK pci_clk pin capacitance - 5 12 pF Table 6-4: PCI Signals MAP-CA DSP Datasheet June 20, 2001 Hitachi, Ltd. DC Characteristics 47 Parameter Description Condition Min Max -0.5 Unit VIL input low voltage - 0.6 V VIH input high voltage - 2.0 Vdd33 + 0.5 V VOL output low voltage Iout = 2 mA - 0.4 V VOH output high voltage Iout = 2 mA 2.4 - V ILI input leakage current 0 < Vin < Vdd33 -10 10 A ILIPU leakage current of pull up pin 0 < Vin < Vdd33 -300 10 A ILIPD leakage current of pull down pin 0 < Vin < Vdd33 -10 300 A IOZ tri-state output leakage 0 < Vin < Vdd33 -10 10 A CIN input pin capacitance - - 10 pF CIO input/output pin capacitance - - 12 pF Table 6-5: Non-PCI Signals Parameter Min Max Unit Operating Temperature 0 75 C Table 6-6: Temperature Rating NOTE: The relationship between gdac_fscale_f and the full scale output current on IOG is: IOG (mA) = 24.12 * gdac_comp(V) / gdac_fscale_f(ohm) where gdac_comp is 1.235 V (typical). Parameter Symbol Resolutions (FS) Min Typical Max Unit - 8 8 8 Bits Integral nonlinearity INL - - 2 LSB Differential nonlinearity DNL - - 1 LSB Table 6-7: Video DAC Outputs Equator Technologies, Inc. MAP-CA DSP Datasheet June 20, 2001 48 AC Characteristics Parameter Symbol Min Typical Max Monotonicity - - White level relative to blank - 17.69 19.05 20.40 mA White level relative to black - 16.74 17.62 18.50 mA Black level relative to blank - 0.95 1.44 1.90 mA Blank level on IOG - 6.29 7.62 8.96 mA Blank level on IOR, IOB - 0 5 50 A Sync level on IOG - 0 5 50 A LSB size - - 69.1 - A DAC-to-DAC matching - - 2 5 % RAOUT - 37.5 - Output resistance guaranteed - Unit - Table 6-7: Video DAC Outputs 6.4 AC Characteristics The AC timing specifications listed in this section assume a 20 pF load on all output signals of the MAP-CA DSP. 6.4.1 PLL Reference Clock Input Description Value Rise/fall time 2 ns maximum (0.4V to 2.4V) Duty cycle 50% 10% Maximum cycle to cycle jitter 200 ps Table 6-8: PLL Reference Clock Input Conditions MAP-CA DSP Datasheet June 20, 2001 Hitachi, Ltd. AC Characteristics 6.4.2 49 SDRAM Interface Timing sdclk, sdclk1, sdclk2 tos toh address, data-out, control tsdram sdrtnclk tds tdh data-in Figure 6-1: SDRAM Timing Measurement Conditions Correct setup and hold times can be guaranteed through internal delay adjustment, controlled by bits [30:24] of the synchronizer/clock control register in MAP-CA DSP memory block. The SdMrckDly and SdMckDly fields control internal delay circuits that affect the timing of signals going to and from the SDRAM components. They should be adjusted so that setup and hold requirements of both the SDRAM and the MAP-CA DSP are met. Symbol fsdram a Description sdclk frequency c. d. e. - 133 MHz tos Output setup time for address, data, control (sdcs_, sdras_, sdcas_, sdwe_, sddqm) 1.9 - ns tohb Output hold time of address, data, control (sdcs_, sdras_, sdcas_, sdwe_, sddqm) 1.5 - ns tdsc, d Input data setup time 1 - ns tdhc, d Input data hold time 2 - ns Table 6-9: SDRAM Interface Timing a. b. Min Max Unit Parameterse fsdram = 1 / tsdram The center of the rising edges of sdclk1 and sdclk2 is used as the reference point. sdrtnclk is used as the reference clock. A matching mechanism is provided to compensate for the propagation delay through circuit board traces to and from the external SDRAM devices. To optimize read timing margin, sdrtnclk should be connected to sdclk with a dedicated trace, with an optional lumped RC load attached to the middle, to account for the number of SDRAM devices attached to the clock line. Measured with SdMrckDly = 0 and SdMckDly = 3. Equator Technologies, Inc. MAP-CA DSP Datasheet June 20, 2001 50 6.4.3 AC Characteristics PCI Bus Timing Vth pci_clk Vtest Vtl tfval output delay Vtfall trval output delay Vtrise tri-state output ton toff Figure 6-2: PCI Output Timing Measurement Conditions Vth pci_clk Vtest tsu Vtl th Vth input Vtest Vtl input valid Vtest Vmax Figure 6-3: PCI Input Timing Measurement Conditions MAP-CA DSP Datasheet June 20, 2001 Hitachi, Ltd. AC Characteristics 51 Symbol Description Min Max Unit tpci_clk clock cycle time 15 30 ns thigh clock high time 6 - ns tlow clock low time 6 - ns clkslew clock slew rate 1.5 tsu(bus) input set up time to clk, bussed signals 3 - ns tsu(ptp) input set up time to clk, point-to-point signals 5 - ns tval(bus) clk to signal valid delay, bussed signals 2 6 ns tval(ptp) clk to signal valid delay, point to point signal 2 6 ns ton float to active delay 2 - ns toff active to float delay - 14 ns th input hold time from clock 500 - ps 1 - ms trst a reset active time after power stable 4 V/ns trst-clk reset active time after clk stable 100 - s trst-off reset active to output float delay - 40 ns Table 6-10: PCI Interface Timing Parameters a. pci_rst_ is asserted and de-asserted asynchronously with respect to pci_clk. All output drivers are floated when pci_rst_ is active. Symbol Value Unit Vmax 0.4 Vdd33 V Vtest 0.4 Vdd33 V Vtfall 0.615 Vdd33 V Vth 0.6 Vdd33 V Vtl 0.2 Vdd33 V 0.285 Vdd33 V Vtrise input signal slew rate 1.5 V/ns Table 6-11: PCI Measurement Conditions Equator Technologies, Inc. MAP-CA DSP Datasheet June 20, 2001 52 AC Characteristics 6.4.4 IEC958 Interface Timing Symbol Fs Description Min Typical Audio sample rate Max 32, 44.1, 48 Unit kHz Table 6-12: IEC958 Interface Timing Parameters 6.4.5 I2S Interface Timing Left Channel One serial bit clock delay from LRCLK transmit Right Channel n n-1 n-2 n-3 4 3 2 M S B 1 0 n n-1 n-2 n-3 4 L M S S B B 3 2 1 0 L S B Figure 6-4: I2S Data Format The audio PLL generates audioclk_out for use by external codecs as master MCLK. MCLK can be programmed for either 12.288 MHz or 16.933 MHz to achieve the desired audio sample rate (LRCLK), according to Table 6-13. The MSB:LSB ordering can be reversed by software programming. LRCLKa (kHz) MCLKb (MHz) SCLKc (MHz) MCLK/ LRCLK MCLK/ SCLK BITS/ FRAMEd BITS/ CHANNEL 48 12.288 1.536 256 8 32 16 44.1 16.933e 2.116 384 8 48 24 32 12.288 1.536 384 8 48 24 Table 6-13: I2S Clock Ratios a. b. c. d. e. LRCLK = iis_in_lr or iis_out_lr. MCLK = audioclk_out; MCLK defaults to 27 MHz on power-up (audio PLL bypassed). SCLK = iis_in_bclk or iis_out_bclk. Bits/Frame = 2*Bits/Channel = SCLK/LRCLK. When MCLK/LRCLK = 384, 24 bits per channel are always transmitted, but the number of valid bits is selectable from 16, 18, 20 or 24. MCLK defaults to 16.933 MHz when audio PLL is enabled. MAP-CA DSP Datasheet June 20, 2001 Hitachi, Ltd. AC Characteristics 53 iis_out_bclk tslr iis_out_lr tsdo iis_out_data Figure 6-5: I2S Output Timing Measurement Conditions Symbol Description Min Max Unit 32, 44.1, 48 kHz Fs Output sample rate tslr SCLK falling to LRCLK delay -10 10 ns tsdo SCLK falling to SDATA valid -10 10 ns Table 6-14: I 2S Output Timing Parameters tlow thigh iis_in_bclk tslrh tbclk tslrs iis_in_lr tsds tsdh iis_in_data Figure 6-6: I2S Input Timing Measurement - Slave Mode Equator Technologies, Inc. MAP-CA DSP Datasheet June 20, 2001 54 AC Characteristics Symbol Description Min Max Unit Fs Input sample rate Fmclk MCLK frequency see Table 6-13 From Table Tbclk SCLK period 8/Fmclk - From Table Tlow SCLK pulse width low 2/Fmclk - From Table Thigh SCLK pulse width high 2/Fmclk - From Table tslrh SCLK rising to LRCLK hold 20 - ns tslrs SCLK rising to LRCLK setup 20 - ns tsds SDATA valid to SCLK rising setup 20 - ns tsdh SCLK rising to SDATA hold time 20 - ns 32, 44.1, 48 kHz Table 6-15: I2S Input Timing Parameters - Slave Mode iis_out_bclk tsclkr iis_out_lr tsdh tsds iis_in_data Figure 6-7: I2S Input Timing Measurement - Master Mode Symbol Description Fs Input sample rate Fmclk MCLK frequency Tbclk SCLK period tsclkr SCLK rising to LRCLK edge tsds tsdh Min Typical - 32, 44.1, 48 Max Unit - kHz see Table 6-13 From Table 8/Fmclk - - From Table - Tbclk/2 - s SDATA valid to SCLK rising setup (1/Fmclk)+10 - - ns SCLK rising to SDATA hold (1/Fmclk)+15 - - ns 2 Table 6-16: I S Input Timing Parameters - Master Mode MAP-CA DSP Datasheet June 20, 2001 Hitachi, Ltd. AC Characteristics 55 internal LRCK MCLK N 2 N internal SCLK SDATA N = MCLK / SCLK Figure 6-8: Internal Serial Clock Generation for I2S Master Mode 6.4.6 Transport Channel Interface Timing ttci tci_clk ts th tci_data tci_enable tci_err_ tci_sync Figure 6-9: TCI Timing Measurement Conditions NOTE: The timing diagram and Table 6-17 are relevant to the primary TCI input port. Timing relationships, input setup, and hold times are identical for the secondary TCI input port. However, the tci_vdac output is not present on the secondary output port. Inputs video_ina[9:0] includes tci_data[7:0] (bits 7:0), tci_enable (bit 8), and tci_err_ (bit 9) Equator Technologies, Inc. MAP-CA DSP Datasheet June 20, 2001 56 AC Characteristics Symbol Description Min Max Unit 27 (parallel) MHz 80 (serial) ftci TCI clock frequencya, b, c, d - th Hold time 1 - ns ts Setup time 4 - ns Table 6-17: TCI Timing Parameters a. b. c. In parallel mode, it is required that tcore > ftci_clk. In serial mode, it is required that tcore > 1/2 ftci_clk. For correct audio clock counter operation, fcore/faudio > 4, where faudio is the frequency of audioclk_out produced by the on-chip PLL. For correct video clock counter operation, fcore/fvideo > 4, where fvideo is the frequency of pclk. d. 6.4.7 ITU-R BT.601/656 Interface Timing tntsc_in ntsc_ina_clk27 ts th ntsc_ina_hsync ntsc_ina_vsync ntsc_ina_data[7:0] Figure 6-10: ITU-R BT.601/656 Input Timing Measurement Conditions Symbol Description Min Max Unit fntsc_in NTSC input clock frequency - 27 MHz th Input hold time for video_ina[9:0], from cross over of rising clock 1 - ns ts Input setup time video_ina[9:0], to the cross over of rising clock 5 - ns Table 6-18: ITU-R BT.601/656 Input Interface Timing Parameters MAP-CA DSP Datasheet June 20, 2001 Hitachi, Ltd. AC Characteristics 57 tpclk pclk thold tdelay ntsc_out_data[7:0] ntsc_out_hsync ntsc_out_vsync Figure 6-11: ITU-R BT.601/656 Output Timing Measurement Conditions NOTE: This timing diagram and table include information for the primary video input port. The primary video input bus video_ina[9:0] includes the byte-wide data bus (bits 7:0), horizontal sync (bit 8), and vertical sync (bit 9). The secondary video input signals have identical timing relationships . Symbol Description tpclk pclk cycle time tdelay thold Min Max Unit 18.5 37 ns Maximum delay time - 11 ns Output hold time 4 - ns Table 6-19: ITU-R BT.601/656 Output Interface Timing Parameters 6.4.8 General Purpose Data Port trcv rcv_clk ts th rcv_data_in[7:0] rcv_req xmt_ack Figure 6-12: GPDP Input Timing Measurement Conditions Equator Technologies, Inc. MAP-CA DSP Datasheet June 20, 2001 58 AC Characteristics Symbol Description Min Max Unit trcv Receive clock cycle time - 60 MHz th Hold time 0 - ns ts Setup time 4 - ns Table 6-20: GPDP Input Timing Parameters txmt xmt_clk thold tdelay xmt_data_out[7:0] xmt_req rcv_ack Figure 6-13: GPDP Output Timing Measurement Conditions Symbol Description txmt Transmit clock cycle time thold Output hold time tdelay Maximum delay time Min - Max Unit 60 MHz 3.0 - ns - 8 ns Table 6-21: GPDP Output Timing Parameters 6.4.9 I2C Interface Timing iic_sda tf tsu_dat tlow tf thd_sta tr tbuf tr iic_sck thd_sta Start thd_dat thigh tsu_sta tsu_sto Repeated Start Stop Start Figure 6-14: I2C Timing Measurement Conditions MAP-CA DSP Datasheet June 20, 2001 Hitachi, Ltd. AC Characteristics 59 Standard Mode Symbola Fast Mode Description Unit Min fsck iic_sck clock frequency. thd_sta Max Min Max 0 100 0 Hold time (repeated) START condition. After this period, the first clock pulse is generated. 2.3 - 0.57 - s tlow LOW period of the iic_sck clock. 4.7 - 1.27 - s thigh HIGH period of the iic_sck clock. 4.0 - 0.6 - s tsu_sta Setup time for a repeated START condition. 4.7 thd_dat Data hold time. tsu_dat Data setup time. 400 kHz - 0.6 - s 0b 3.45 0b 0.9 s 250 - 250 - ns c 300 ns tr Rise time of both iic_sda and iic_sck signals. - tf Fall time of both iic_sda and iic_sck signals. - 300 20 + 0.1Cb 300 ns tsu_sto Setup time for STOP condition. 4.0 - 0.6 - s tbuf Bus free time between a STOP and START condition. 4.7 - 1.3 - s Cb Capacitive load for each bus line. - 400 - 400 pF Table 6-22: I a. b. c. 1000 20 + 0.1Cb 2C Interface Timing Parameters All values referred to VIHmin and VILmax levels. See Table 6-5. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL. Cb = total capacitance of one bus line in pF. Equator Technologies, Inc. MAP-CA DSP Datasheet June 20, 2001 60 MAP-CA DSP Datasheet June 20, 2001 AC Characteristics Hitachi, Ltd. 61 Appendix A Glossary These acronyms and names used in this Data Sheet. These are their expansion or explanation. BSDL ...............................Boundary Scan Description Language DataStreamer controller ....High speed DMA engine that operates independent from VLIW core, also referred to as the DS controller DRC .................................Display Refresh Controller DTS ..................................Data Transfer Switch - high speed MAP-CA DSP series internal data bus FEC ..................................Forward error correction I-ALU ..............................Integer ALU (Arithmetic Logic Unit) - performs loads, stores, branches, integer arithmetic, and logical operations IG-ALU ............................Integer, Graphics unit - performs integer arithmetic and (partitioned) multimedia operations MAP-CA DSP ..................Media Accelerated Processor for Consumer Appliances MMU ...............................Memory Management Unit PLC ..................................128-bit Partitioned Local Constant register PLV ..................................128-bit Partitioned Local Variable register SIMD ...............................Single Instruction Multiple Data TLB ..................................Translation Lookaside Buffer VLx ..................................A coprocessor on MAP-CA DSP that can accelerate variable length encoding and variable length decoding. Equator Technologies, Inc. MAP-CA DSP Datasheet June 20, 2001 62 MAP-CA DSP Datasheet June 20, 2001 Hitachi, Ltd. 63 Appendix B Package Specifications This appendix to the MAP-CA DSP Datasheet describes the specifications of the 352 pin BGA package B.1 Mechanical Specifications B.1.1 Outline and Footprint The following sections use millimeter (mm) as the unit of measure. B.1.1.1 Top and Bottom Views PKG Top View PKG Bottom View 4-C(1.0) A F26 A 26 A2 A F1 (21.64 sq.) (33.0 sq.) Package Index 35.00.1 sq. Bump No.A 1 1.6250.20 (1.27)x25=(31.75) 26rowx26column Figure B-1: 352 Pin BGA Outline and Footprint - Top and Bottom Views Equator Technologies, Inc. MAP-CA DSP Datasheet June 20, 2001 64 B.1.1.2 Side View 0.60.1 (Ball Height) 1.130.20 (0.5) PKG Side View (0.63) // 0.35 C Max.0.40 0.20 C -C- Note 1. Resin height is measured from substrate bottom surface 0.750.15 Note 2. Bump pitch is measured center to center. Note 3. Package index shows bump #A1 corner. (1.27) Note 4. Numbers in () are for reference only. Figure B-2: 352 Pin BGA Outline and Footprint - Side Views B.2 Package Materials B.2.1 Materials Specification Segment Material Package substrate BT Resin Encapsulation Epoxy with filler Heat Spreader Cu + Ni plating Solder Ball 37 Pb - 63 Sn Table B-1: Material Used. MAP-CA DSP Datasheet June 20, 2001 Hitachi, Ltd. 65 Index Location (9.0) B.2.2 0 $ 3 & $ (15.52) (48$725 BGA Substrate Heat Spreader (9.0) (16.1) Package Index Figure B-3: Index Location Equator Technologies, Inc. MAP-CA DSP Datasheet June 20, 2001 66 MAP-CA DSP Datasheet June 20, 2001 Hitachi, Ltd.