

74LVT74
3.3V Dual D-type flip-flop
Product specification 1996 Aug 28
INTEGRATED CIRCUITS
IC24 Data Handbook
Philips Semiconductors Product specification
74LVT743.3V Dual D-type flip-flop
2
1996 Aug 28 853-1872 17244
QUICK REFERENCE DATA
SYMBOL PARAMETER CONDITIONS
Tamb = 25°C;
GND = 0V TYPICAL UNIT
tPLH
tPHL
Propagation
delay
CPn to Qn CL = 50pF;
VCC = 3.3V 3.1
3.6 ns
CIN Input
capacitance VI = 0V or 3.0V 3 pF
ICC Total supply
current VCC = 3.6V 0.5 mA
PIN CONFIGURATION
14
13
12
11
10
9
87
6
5
4
3
2
1
GND
VCC
SD1
Q1
Q1
CP1
RD1
D1
RD0
D0
Q0
CP0
SD0
Q0
SF00045
LOGIC SYMBOL
Q0 Q0Q1Q1
56 98
V
CC = Pin 14
GND = Pin 7
3
4
1
11
10
13
CP0
SD0
RD0
CP1
SD1
RD1
D0 D1
212
SA00359
DESCRIPTION
The 74LVT74 is a dual positive edge-triggered D-type flip-flop
featuring individual data, clock, set, and reset inputs; also true and
complementary outputs. Set (SD) and reset (RD) are asynchronous
active low inputs and operate independently of the clock input.
When set and reset are inactive (high), data at the D input is
transferred to the Q and Q outputs on the low-to-high transition of
the clock. Data must be stable just one setup time prior to the
low-to-high transition of the clock for predictable operation. Clock
triggering occurs at a voltage level and is not directly related to the
transition time of the positive-going pulse. Following the hold time
interval, data at the D input may be changed without affecting the
levels of the output.
PIN DESCRIPTION
PIN NUMBER SYMBOL NAME AND FUNCTION
2, 12 D0, D1 Data inputs
3, 11 CP0, CP1 Clock inputs (active rising edge)
4, 10 SD0, SD1 Set inputs (active LOW)
1, 13 RD0, RD1 Reset inputs (active LOW)
5, 6, 8, 9 Qn, Qn Data outputs
LOGIC SYMBOL (IEEE/IEC)
4
3
2
1
10
11
12
13
5
6
9
8
&
S
S
C1
C2
R
1D
2D
R
SF00047
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER
14-Pin Plastic SO –40°C to +85°C74LVT74 D 74LVT74 D SOT108-1
14-Pin Plastic SSOP –40°C to +85°C74LVT74 DB 74LVT74 DB SOT337-1
14-Pin Plastic TSSOP –40°C to +85°C74LVT74 PW 74LVT74PW DH SOT402-1
Philips Semiconductors Product specification
74LVT743.3V Dual D-type flip-flop
1996 Aug 28 3
LOGIC DIAGRAM
VCC = Pin 14
GND = Pin 7
5, 9
6, 8
Q
Q
4, 10
1, 13
3, 11
2, 12
SD
RD
CP
D
SF00048
FUNCTION TABLE
INPUTS OUTPUTS OPERATING
SD RD CP D Q Q MODE
L H X X H L Asynchronous set
H L X X L H Asynchronous reset
L L X X H H Undetermined*
H H ↑h H L Load “1”
H H ↑l L H Load “0”
H H ↑X NC NC Hold
NOTES:
H = High voltage level
h = High voltage level one setup time prior to low-to-high
clock transition
L = Low voltage level
l = Low voltage level one setup time prior to low-to-high
clock transition
NC= No change from the previous setup
X = Don’t care
↑= Low-to-high clock transition
↑= Not low-to-high clock transition
* = This setup is unstable and will change when either set
or reset return to the high level.
ABSOLUTE MAXIMUM RATINGS1, 2
SYMBOL PARAMETER CONDITIONS RATING UNIT
VCC DC supply voltage –0.5 to +4.6 V
IIK DC input diode current VI < 0 –50 mA
VIDC input voltage3–0.5 to +7.0 V
IOK DC output diode current VO < 0 –50 mA
VOUT DC output voltage3Output in Off or High state –0.5 to +7.0 V
IOUT
DC out
p
ut current
Output in High state –32
mA
I
OUT
DC
out ut
current
Output in Low state 64
mA
Tstg Storage temperature range –65 to 150 °C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
UNIT
SYMBOL
PARAMETER
MIN MAX
UNIT
VCC DC supply voltage 2.7 3.6 V
VIInput voltage 0 5.5 V
VIH High-level input voltage 2.0 V
VIL Low-level Input voltage 0.8 V
IOH High-level output current –20 mA
IOL Low-level output current 32 mA
∆t/∆vInput transition rise or fall rate; Outputs enabled 10 ns/V
Tamb Operating free-air temperature range –40 +85 °C
Philips Semiconductors Product specification
74LVT743.3V Dual D-type flip-flop
1996 Aug 28 4
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions
Voltages are referenced to GND (ground = 0V) LIMITS
SYMBOL PARAMETER TEST CONDITIONS Temp = -40°C to +85°C UNIT
MIN TYP1MAX
VIK Input clamp voltage VCC = 2.7V ; IIK = –18mA –1.2 V
VCC = 2.7 to 3.6V ; IOH = –100µA VCC–0.2
VOH High-level output voltage VCC = 2.7V ; IOH = –6mA 2.4 V
VCC = 3.0V ; IOH = –20mA 2.0
VCC = 2.7V ; IOL = 100µA 0.2
VOL Low-level output voltage VCC = 2.7V ; IOL = 24mA 0.5 V
VCC = 3.0V ; IOL = 32mA 0.5
II
In
p
ut leakage current
VCC = 0 or 3.6V ; V I = 5.5V 10
µA
I
I
In ut
leakage
current
VCC = 3.6V ; V I = VCC or GND ±1
µA
IOFF Output off current VCC = 0V ; VI or VO = 0 to 4.5V ±100 µA
ICC Quiescent supply current VCC = 3.6V ; Outputs High, VI = GND or
VCC, IO = 00.5 1 mA
∆ICC Additional supply current per input pin2VCC = 3V to 3.6V; One input at VCC–0.6V,
Other inputs at VCC or GND 0.2 µA
CIInput capacitance VI = 3V or 0 3 pF
NOTES:
1. All typical values are at VCC = 3.3V and Tamb = 25°C.
2. This is the increase in supply current for each input at the specificed voltage level other than VCC or GND.
AC CHARACTERISTICS
GND = 0V ; tR = tF = 2.5ns; CL = 50pF, RL = 500Ω; Tamb = –40°C to +85°C. LIMITS
SYMBOL PARAMETER WAVEFORM VCC = 3.3V ± 0.3V VCC = 2.7V UNIT
MIN TYP1MAX MAX
fMAX Maximum clock frequency 1 150 345 MHz
tPLH
tPHL Propagation delay
CPn to Qn or Qn11.0
1.0 3.1
3.6 4.8
5.0 5.8
5.0 ns
tPLH
tPHL Propagation delay
SDn, RDn to Qn or Qn 21.0
1.0 3.1
3.0 5.0
4.4 6.2
4.8 ns
NOTE:
1. All typical values are at VCC = 3.3V and Tamb = 25°C.
AC SETUP REQUIREMENTS LIMITS
SYMBOL PARAMETER WAVEFORM VCC = 3.3V ± 0.3V VCC = 2.7V UNIT
MIN TYP MIN
tS (H)
tS (L) Setup time
Dn to CPn 11.7
1.4 0.6
0.4 1.8
1.6 ns
th (H)
th (L) Holdtime
Dn to CPn 10.3
0–0.3
–0.6 0.3
0
ns
tW (H)
tW (L) CPn Pulse Width 1 2.0
2.0 1.0
1.2 3.0
3.0
ns
tW (L) SDn, RDn Pulse Width 2 2.0 1.0 3.0
trec Recovery time
SDn, RDn tp CPn 3 0.5 –0.3 0.5 ns
Philips Semiconductors Product specification
74LVT743.3V Dual D-type flip-flop
1996 Aug 28 5
AC WAVEFORMS
VM = 1.5V, VIN = GND to 2.7V
VM
VM
CPn
VMVMVMVM
VMVM
tsu(H) th(H)
Dn
Qn
VM
tw(H)
1/fmax
tsu(L) th(L)
VM
VM
tPLH
Qn
tw(L)
tPHL
tPHL
tPLH
SF00049
W aveform 1. Propagation delay for data to output,
data setup time and hold times, and clock width,
and maximum clock frequency
VM
VM
RDn VM
Qn
VM
VM
VM
tPLH
Qn
tw(L)
tPHL
tPHL
tPLH
SDn VM
VMtw(L)
SF00050
W aveform 2. Propagation delay for set and reset to output,
set and reset pulse width
SDn or RDn VM
VM
trec
CPn
SF00051
W aveform 3. Recovery time for set or reset to clock
TEST CIRCUIT AND WAVEFORMS
VMVM
tWAMP (V)
NEGATIVE
PULSE 10% 10%
90% 90%
0V
VMVM
tW
AMP (V)
POSITIVE
PULSE
90% 90%
10% 10% 0V
tTHL (tF)
tTLH (tR)t
THL (tF)
tTLH (tR)
VM = 1.5V
Input Pulse Definition
DEFINITIONS
RL = Load resistor; see AC CHARACTERISTICS for value.
CL = Load capacitance includes jig and probe capacitance;
see AC CHARACTERISTICS for value.
RT = Termination resistance should be equal to ZOUT of
pulse generators.
INPUT PULSE REQUIREMENTS
FAMILY Amplitude Rep. Rate tWtRtF
74LVT 2.7V ≤10MHz 500ns ≤2.5ns ≤2.5ns
PULSE
GENERATOR
VIN
D.U.T.
VOUT
CL
VCC
Test Circuit for Outputs
RTRL
SV00022
Philips Semiconductors Product specification
74LVT743.3V Dual D-type flip-flop
6
1996 Aug 28
SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
Philips Semiconductors Product specification
74LVT743.3V Dual D-type flip-flop
1996 Aug 28 7
SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1
Philips Semiconductors Product specification
74LVT743.3V Dual D-type flip-flop
1996 Aug 28 8
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1
Philips Semiconductors Product specification
74LVT743.3V Dual D-type flip-flop
1996 Aug 28 9
NOTES
Philips Semiconductors Product specification
74LVT743.3V Dual D-type flip-flop
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing
or modification.
LIFE SUPPORT APPLICATIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appl iances, devices,
or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
DEFINITIONS
Data Sheet Identification Product Status Definition
Objective Specification
Preliminary Specification
Product Specification
Formative or in Design
Preproduction Product
Full Production
This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.
Philips Semiconductors and Philips Electronics North America Corporation
register eligible circuits under the Semiconductor Chip Protection Act.
Copyright Philips Electronics North America Corporation 1996
All rights reserved. Printed in U.S.A.
Philips Semiconductors - PIP - 74LVT74; 3.3V Dual D-type flip-flop
Philips Semiconductors Home
Products
•MultiMarket
Semiconductors
•Product Selector
•Catalog by
Function
•Catalog by
System
•Cross-reference
•Packages
•End of Life
information
•Distributors Go
Here!
•Models
•SoC solutions
Product Information
74LVT74; 3.3V Dual
D-type flip-flop
Information as of 2003-04-22
My.Semiconductors.COM.
Your personal service from
Philips Semiconductors.
Please register now !
Stay informed
Use right mouse button to
download datasheet
Download datasheet
General description Features Applications Datasheet
Block diagram Buy online Support & tools Email/translate
Products & packages Parametrics Similar products
top
General description
The 74LVT74 is a dual positive edge-triggered D-type flip-flop featuring individual data, clock, set, and reset
inputs; also true and complementary outputs. Set (SD) and reset (RD) are asynchronous active low inputs and
operate independently of the clock input. When set and reset are inactive (high), data at the D input is
transferred to the Q and Q outputs on the low-to-high transition of the clock. Data must be stable just one setup
time prior to the low-to-high transition of the clock for predictable operation. Clock triggering occurs at a
voltage level and is not directly related to the transition time of the positive-going pulse. Following the hold
time interval, data at the D input may be changed without affecting the levels of the output.
top
Applications
Download
PDF
File
AN2022: The Behavior Of Integrated Bus Hold Circuits (date 01-Mar-96)
Download
PDF
File
AN203_2: Test Fixtures for High Speed Logic (date 02-Apr-98)
Download
PDF
File
AN2301: Simulation Support for Philips' Advanced BiCMOS Products
Download
PDF
File
AN243: LVT (Low Voltage Technology) and ALVT (Advanced LVT) (date 01-Jan-98)
Download
PDF
File
AN246: Transmission Lines and Terminations with Philips Advanced Logic Families
top
Datasheet
Type number Title Publication release
date Datasheet status Page
count File size
(kB) Datasheet
74LVT74 3.3V
Dual D-
type flip-
flop
8/28/1996 Product specification 4 97
Download
PDF
File
Download
top
Blockdiagram(s)
Block diagram of
74LVT74D
file:///G|/imaging/BITTING/CPL/20030424/04232003_9/PHGL/_HTML04232003/74LVT74D.html (1 of 3) [May-09-2003 6:10:36 PM]
Submit Query
Philips Semiconductors - PIP - 74LVT74; 3.3V Dual D-type flip-flop
top
Parametrics
Type
number Package Description Propagation
Delay(ns) Voltage No.
of
Pins
Power
Dissipation
Considerations
Logic
Switching
Levels
Output
Drive
Capability
74LVT74D SOT108-1
(SO14)
3.3V Dual
D-Type Flip-
Flop with
Set and
Reset;
Positive-
Edge
Trigger
4~6 Low 14 None TTL Medium
74LVT74DB SOT337-1
(SSOP14)
3.3V Dual
D-Type Flip-
Flop with
Set and
Reset;
Positive-
Edge
Trigger
4~6 Low 14 None TTL Medium
74LVT74PW SOT402-1
(TSSOP14)
3.3V Dual
D-Type Flip-
Flop with
Set and
Reset;
Positive-
Edge
Trigger
4~6 Low 14 None TTL Medium
top
Products, packages, availability and ordering
Type
number North
American
type number
Ordering code
(12NC) Marking/Packing
Download
PDF
File
IC packing info Package Device
status Buy online
74LVT74D 74LVT74D 9352 092 50112 Standard Marking
* Tube SOT108-1
(SO14) Full production
order this
product
online
-
74LVT74D-
T 9352 092 50118 Standard Marking
* Reel Pack,
SMD, 13"
SOT108-1
(SO14) Full production
order this
product
online
-
74LVT74DB 74LVT74DB 9352 092 60112 Standard Marking
* Tube SOT337-1
(SSOP14) Full production
order this
product
online
-
74LVT74DB-
T 9352 092 60118 Standard Marking
* Reel Pack,
SMD, 13"
SOT337-1
(SSOP14) Full production
order this
product
online
-
74LVT74PW 74LVT74PW 9352 092 70112 Standard Marking
* Tube
SOT402-1
(TSSOP14)
Full production
order this
product
online
-
74LVT74PW-
T 9352 092 70118 Standard Marking
* Reel Pack,
SMD, 13"
SOT402-1
(TSSOP14)
Full production
order this
product
-
file:///G|/imaging/BITTING/CPL/20030424/04232003_9/PHGL/_HTML04232003/74LVT74D.html (2 of 3) [May-09-2003 6:10:36 PM]
Philips Semiconductors - PIP - 74LVT74; 3.3V Dual D-type flip-flop
online
Products in the above table are all in production. Some variants are discontinued; click here for information on
these variants.
top
Similar products
Products
similar
to
74LVT74
74LVT74 links to the similar products page containing an overview of products that are similar in
function or related to the type number(s) as listed on this page. The similar products page includes products
from the same catalog tree(s), relevant selection guides and products from the same functional category.
top
Support & tools
Download
PDF
File
Innovative Low Voltage Logic Solutions(date 01-Aug-00)
Download
PDF
File
Introduction to Advanced BiCMOS Logic Products(date 01-Mar-98)
Download
PDF
File
Family specifications LVT, family characteristics(date 01-Mar-98)
Download
PDF
File
Advanced BiCMOS features(date 01-Jan-98)
top
Email/translate this product information
● Email this product information.
● Translate this product information page from English to:
The English language is the official language used at the semiconductors.philips.com website and webpages.
All translations on this website are created through the use of Google Language Tools and are provided for
convenience purposes only. No rights can be derived from any translation on this website.
About this Web Site
| Copyright © 2003 Koninklijke Philips N.V. All rights reserved. | Privacy Policy |
| Koninklijke Philips N.V. | Access to and use of this Web Site is subject to the following Terms of Use. |
file:///G|/imaging/BITTING/CPL/20030424/04232003_9/PHGL/_HTML04232003/74LVT74D.html (3 of 3) [May-09-2003 6:10:36 PM]
French
Translate