KMSC8122TMP6400V - Freescale Semiconductor

Freescale Semiconductor

Technical Data

MSC8122

Rev. 12, 4/2006

MSC8122

Quad Core 16-Bit Digital Signal Processor

The MSC8122 is a highly integrated system-on-a-chip that combines four SC140 extended cores with an RS-232

serial interface, four time-division multiplexed (TDM) serial interfaces, thirty-two general-purpose timers, a

flexible system interface unit (SIU), an Ethernet interface, and a multi-channel DMA engine. The four extended

cores can deliver a total 4800/6400/8000 DSP MMACS performance at 300/400/500 MHz.

Each core has four arithmetic logic units (ALUs), internal memory, a write buffer, and two interrupt controllers.

The MSC8122 targets high-bandwidth highly computational DSP applications and is optimized for wireless

transcoding and packet telephony as well as high-bandwidth base station applications. The MSC8122 delivers

enhanced performance while maintaining low power dissipation and greatly reducing system cost.

Figure 1. MSC8122 Block Diagram

MQBus

SQBus

Local Bus

128

Boot

ROM 64

PLL

JTAG

RS-232

Internal Local Bus

Internal System Bus

IPBus

IP Master

UART

Memory

Controller

RAM

GPIO Pins

Interrupts

Memory

Controller

System Bus

32/64

DSI Port

32/64

PLL/Clock

JTAG Port

SC140

Extended Core

SC140

Extended Core

SC140

Extended Core

System

Interface

32 Timers

4 TDMs

SC140

Extended Core

DMA Bridge SIU

Registers

Direct

Slave

Interface

(DSI)

8 Hardware

Semaphores

GIC

GPIO

MII/RMII/SMII

Ethernet

The raw processing power of

this highly integrated system-

on- a-chip device will enable

developers to create next-

generation networking

products that offer

tremendous channel

densities, while maintaining

system flexibility, scalability,

and upgradeability. The

MSC8122 is offered in three

core speed levels: 300, 400,

and 500 MHz.

What’s New?

Rev. 12 includes the following:

•Chapter 2 updates Figure 2-11

for reset timing.

MSC8122 Technical Data, Rev. 12

ii Freescale Semiconductor

Table of Contents

Features...............................................................................................................................................................iv

Product Documentation ......................................................................................................................................ix

Chapter 1 Signals/Connections

1.1 Power Signals ...................................................................................................................................................1-3

1.2 Clock Signals ....................................................................................................................................................1-3

1.3 Reset and Configuration Signals.......................................................................................................................1-3

1.4 Direct Slave Interface, System Bus, Ethernet, and Interrupt Signals ...............................................................1-4

1.5 Memory Controller Signals ............................................................................................................................1-14

1.6 GPIO, TDM, UART, and Timer Signals.........................................................................................................1-16

1.7 Dedicated Ethernet Signals.............................................................................................................................1-23

1.8 EOnCE Event and JTAG Test Access Port Signals ........................................................................................1-24

1.9 Reserved Signals.............................................................................................................................................1-24

Chapter 2 Specifications

2.1 Maximum Ratings.............................................................................................................................................2-1

2.2 Recommended Operating Conditions...............................................................................................................2-2

2.3 Thermal Characteristics ....................................................................................................................................2-3

2.4 DC Electrical Characteristics............................................................................................................................2-3

2.5 AC Timings.......................................................................................................................................................2-4

Chapter 3 Packaging

3.1 Package Description .........................................................................................................................................3-1

3.2 MSC8122 Package Mechanical Drawing .......................................................................................................3-20

Chapter 4 Design Considerations

4.1 Start-up Sequencing Recommendations ...........................................................................................................4-1

4.2 Power Supply Design Considerations...............................................................................................................4-1

4.3 Connectivity Guidelines ...................................................................................................................................4-3

4.4 External SDRAM Selection..............................................................................................................................4-4

4.5 Thermal Considerations....................................................................................................................................4-5

Data Sheet Conventions

OVERBAR Used to indicate a signal that is active when pulled low (For example, the RESET pin is active

when low.)

“asserted” Means that a high true (active high) signal is high or that a low true (active low) signal is low

“deasserted” Means that a high true (active high) signal is low or that a low true (active low) signal is high

Examples: Signal/Symbol Logic State Signal State Voltage

PIN True Asserted VIL/VOL

PIN False Deasserted VIH/VOH

PIN True Asserted VIH/VOH

PIN False Deasserted VIL/VOL

Note: Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.

Data Sheet Conventions

MSC8122 Technical Data, Rev. 12

Freescale Semiconductor iii

Figure 2. SC140 Extended Core Block Diagram

SC140

Power

Management

Core

Program

Sequencer

Address

File

Data ALU

File

Address

ALU

Data

ALU

EOnCEJTAG

QBus

IRQs

MQBus

SQBus

Local Bus

128

LIC

PIC

128

SC140 Core

QBus

Interface

Instruction

Cache

RAM

Notes: 1. The arrows show the data transfer direction.

QBus

Bank 1

QBus

Bank 3

2. The QBus interface includes a bus switch, write buffer, fetch unit, and a

control unit that defines four QBus banks. In addition, the QBC handles internal

QBC

memory contentions.

MSC8122 Technical Data, Rev. 12

iv Freescale Semiconductor

Features

Feature Description

SC140 Cores

Four SC140 cores:

• Up to 8000 MMACS using 16 ALUs running at up to 500 MHz.

• A total of 1436 KB of internal SRAM (224 KB per core + 16 KB ICache per core + the shared M2 memory).

Each SC140 core provides the following:

• Up to 2000 MMACS using an internal 500 MHz clock. A MAC operation includes a multiply-accumulate

command with the associated data move and pointer update.

• 4 ALUs per SC140 core.

• 16 data registers, 40 bits each.

• 27 address registers, 32 bits each.

• Hardware support for fractional and integer data types.

• Very rich 16-bit wide orthogonal instruction set.

• Up to six instructions executed in a single clock cycle.

• Variable-length execution set (VLES) that can be optimized for code density and performance.

•IEEE Std 1149.1™ JTAG port.

• Enhanced on-device emulation (EOnCE) with real-time debugging capabilities.

Extended Core

Each SC140 core is embedded within an extended core that provides the following:

• 224 KB M1 memory that is accessed by the SC140 core with zero wait states.

• Support for atomic accesses to the M1 memory.

• 16 KB instruction cache, 16 ways.

• A four-entry write buffer that frees the SC140 core from waiting for a write access to finish.

• External cache support by asserting the global signal (GBL) when predefined memory banks are accessed.

• Programmable interrupt controller (PIC).

• Local interrupt controller (LIC).

Multi-Core Shared

Memories

• 476 KB M2 memory (shared memory) working at the core frequency, accessible from the local bus, and

accessible from all four SC140 cores using the MQBus.

• 4 KB bootstrap ROM.

M2-Accessible Multi-

Core Bus (MQBus)

• A QBus protocol multi-master bus connecting the four SC140 cores to the M2 memory.

• Data bus access of up to 128-bit read and up to 64-bit write.

• Operation at the SC140 core frequency.

• A central efficient round-robin arbiter controlling SC140 core access on the MQBus.

• Atomic operation control of access to M2 memory by the four SC140 cores and the local bus.

Internal PLL

• Generates up to 500 MHz core clock and up to166 MHz bus clocks for the 60x-compatible local and system

buses and other modules.

• PLL values are determined at reset based on configuration signal values.

60x-Compatible

System Bus

• 64/32-bit data and 32-bit address 60x bus.

• Support for multiple-master designs.

• Four-beat burst transfers (eight-beat in 32-bit wide mode).

• Port size of 64, 32, 16, and 8 controlled by the internal memory controller.

• Bus can access external memory expansion or off-device peripherals, or it can enable an external host device to

access internal resources.

• Slave support, direct access by an external host to internal resources including the M1 and M2 memories.

• On-device arbitration between up to four master devices.

Direct Slave

Interface (DSI)

A 32/64-bit wide slave host interface that operates only as a slave device under the control of an external host

processor.

• 21–25 bit address, 32/64-bit data.

• Direct access by an external host to internal and external resources, including the M1 and the M2 memories as

well as external devices on the system bus.

• Synchronous and asynchronous accesses, with burst capability in the synchronous mode.

• Dual or Single strobe modes.

• Write and read buffers improve host bandwidth.

• Byte enable signals enables 1, 2, 4, and 8 byte write access granularity.

• Sliding window mode enables access with reduced number of address pins.

• Chip ID decoding enables using one CS signal for multiple DSPs.

• Broadcast CS signal enables parallel write to multiple DSPs.

• Big-endian, little-endian, and munged little-endian support.

3-Mode Signal

Multiplexing

• 64-bit DSI, 32-bit system bus.

• 32-bit DSI, 64-bit system bus.

• 32-bit DSI, 32-bit system bus.

Features

MSC8122 Technical Data, Rev. 12

Freescale Semiconductor v

Memory Controller

Flexible eight-bank memory controller:

• Three user-programmable machines (UPMs), general-purpose chip-select machine (GPCM), and a page-mode

SDRAM machine.

• Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, Flash memory, and other user-definable

peripherals.

• Byte enables for either 64-bit or 32-bit bus width mode.

• Eight external memory banks (banks 0–7). Two additional memory banks (banks 9, 11) control IPBus

peripherals and internal memories. Each bank has the following features:

— 32-bit address decoding with programmable mask.

— Variable block sizes (32 KB to 4 GB).

— Selectable memory controller machine.

— Two types of data errors check/correction: normal odd/even parity and read-modify-write (RMW) odd/even

parity for single accesses.

— Write-protection capability.

— Control signal generation machine selection on a per-bank basis.

— Support for internal or external masters on the system bus.

— Data buffer controls activated on a per-bank basis.

— Atomic operation.

— RMW data parity check (on system bus only).

— Extensive external memory-controller/bus-slave support.

— Parity byte select pin, which enables a fast, glueless connection to RMW-parity devices (on the system bus

only).

— Data pipeline to reduce data set-up time for synchronous devices.

Multi-Channel DMA

Controller

• 16 time-multiplexed unidirectional channels.

• Services up to four external peripherals.

• Supports DONE or DRACK protocol on two external peripherals.

• Each channel group services 16 internal requests generated by eight internal FIFOs. Each FIFO generates:

— A watermark request to indicate that the FIFO contains data for the DMA to empty and write to the destination.

— A hungry request to indicate that the FIFO can accept more data.

• Priority-based time-multiplexing between channels using 16 internal priority levels.

• Round-robin time-multiplexing between channels.

• A flexible channel configuration:

— All channels support all features.

— All channels connect to the system bus or local bus.

• Flyby transfers in which a single data access is transferred directly from the source to the destination without

using a DMA FIFO.

Time-Division

Multiplexing (TDM)

Up to four independent TDM modules, each with the following features:

• Optional operating configurations:

— Totally independent receive and transmit channels, each having one data line, one clock line, and one frame

sync line.

— Four data lines with one clock and one frame sync shared among the transmit and receive lines.

• Connects gluelessly to most T1/E1 framers as well as to common buses such as the ST-BUS.

• Hardware A-law/µ-law conversion.

• Up to 62.5 Mbps per TDM (62.5 MHz bit clock if one data line is used, 31.25 MHz if two data lines are used,

15.63 MHz if four data lines are used).

• Up to 256 channels.

• Up to 16 MB per channel buffer (granularity 8 bytes), where A/µ law buffer size is double (granularity 16 byte).

• Receive buffers share one global write offset pointer that is written to the same offset relative to their start

address.

• Transmit buffers share one global read offset pointer that is read from the same offset relative to their start

address.

• All channels share the same word size.

• Two programmable receive and two programmable transmit threshold levels with interrupt generation that can

be used, for example, to implement double buffering.

• Each channel can be programmed to be active or inactive.

• 2-, 4-, 8-, or 16-bit channels are stored in the internal memory as 2-, 4-, 8-, or 16-bit channels, respectively.

• The TDM Transmitter Sync Signal (TxTSYN) can be configured as either input or output.

• Frame Sync and Data signals can be programmed to be sampled either on the rising edge or on the falling edge

of the clock.

• Frame sync can be programmed as active low or active high.

• Selectable delay (0–3 bits) between the Frame Sync signal and the beginning of the frame.

• MSB or LSB first support.

Feature Description

MSC8122 Technical Data, Rev. 12

vi Freescale Semiconductor

Features

Ethernet Controller

• Designed to comply with IEEE® Std 802® including Std. 802.3™, 802.3u™, 802.3x™, and 802.3ac™.

• Three Ethernet physical interfaces:

— 10/100 Mbps MII.

— 10/100 Mbps RMII.

— 10/100 Mbps SMII.

• Full and half-duplex support.

• Full-duplex flow control (automatic PAUSE frame generation or software programmed PAUSE frame generation

and recognition).

• Out-of-sequence transmit queue for initiating flow-control.

• Programmable maximum frame length supports jumbo frames (up to 9.6k) and virtual local area network (VLAN)

tags and priority.

• Retransmission from transmit FIFO following a collision.

• CRC generation and verification of inbound/outbound packets.

• Address recognition:

— Each exact match can be programmed to be accepted or rejected.

— Broadcast address (accept/reject).

— Exact match 48-bit individual (unicast) address.

— Hash (256-bit hash) check of individual (unicast) addresses.

— Hash (256-bit hash) check of group (multicast) addresses.

— Promiscuous mode.

• Pattern matching:

— Up to 16 unique 4-byte patterns.

— Pattern match on bit-basis.

— Matching range up to 256 bytes deep into the frame.

— Offsets to a maximum of 252 bytes.

— Programmable pattern size in 4-byte increments up to 64 bytes.

— Accept or reject frames if a match is detected.

— Up to eight unicast addresses for exact matches.

— Pattern matching accepts/rejects IP addresses.

• Filing of receive frames based on pattern match; prioritization of frames.

• Insertion with expansion or replacement for transmit frames; VLAN tag insertion.

• RMON statistics.

• Master DMA on the local bus for fetching descriptors and accessing the buffers.

• Ethernet PHY can be exposed either on GPIO pins or on the high most significant bits of the DSI/system when

the DSI and the system bus are both 32 bits.

• MPC8260 8-byte width buffer descriptor mode as well as 32 byte width buffer descriptor mode.

• MII Bridge (MIIGSK):

— Programmable selection of the 50 MHz RMII reference clock source (external or internal).

— Independent 2 bit wide transmit and receive data paths.

— Six operating modes.

— Four general-purpose control signals.

— Programmable transmitted inter-frame bits to support inter-frame gap for frames in the SMII domain.

• SMII features:

— Multiplexed only with GPIO signals

— Convey complete MII information between the PHY and MAC.

— Allow direct MAC-to-MAC communication in SMII mode.

— Can generate an interrupt request line while receiving inter-frame segments.

Feature Description

Features

MSC8122 Technical Data, Rev. 12

Freescale Semiconductor vii

UART

• Two signals for transmit data and receive data.

• No clock, asynchronous mode.

• Can be serviced either by the SC140 DSP cores or an external host on the system bus or the DSI.

• Full-duplex operation.

• Standard mark/space non-return-to-zero (NRZ) format.

• 13-bit baud rate selection.

• Programmable 8-bit or 9-bit data format.

• Separately enabled transmitter and receiver.

• Programmable transmitter output polarity.

• Two receiver wake-up methods:

— Idle line wake-up.

— Address mark wake-up.

• Separate receiver and transmitter interrupt requests.

• Nine flags, the first five can generate interrupt request:

— Transmitter empty.

— Transmission complete.

— Receiver full.

— Idle receiver input.

— Receiver overrun.

— Receiver active.

— Noise error.

— Framing error.

— Parity error.

• Receiver framing error detection.

• Hardware parity checking.

• 1/16 bit-time noise detection.

• Maximum bit rate 6.25 Mbps.

• Single-wire and loop operations.

General-Purpose I/O

(GPIO) Port

• 32 bidirectional signal lines that either serve the peripherals or act as programmable I/O ports.

• Each port can be programmed separately to serve up to two dedicated peripherals, and each port supports

open-drain output mode.

I2C Software Module • Booting from a serial EEPROM.

• Uses GPIO timing.

Timers

Two modules of 16 timers each.

• Cyclic or one-shot.

• Input clock polarity control.

• Interrupt request when counting reaches a programmed threshold.

• Pulse or level interrupts.

• Dynamically updated programmed threshold.

• Read counter any time.

Watchdog mode for the timers that connect to the device.

Hardware

Semaphores

Eight coded hardware semaphores, locked by simple write access without need for read-modify-write mechanism.

Global Interrupt

Controller (GIC)

• Consolidation of chip maskable interrupt and non-maskable interrupt sources and routing to INT_OUT,

NMI_OUT, and to the cores.

• Generation of 32 virtual interrupts (eight to each SC140 core) by a simple write access.

• Generation of virtual NMI (one to each SC140 core) by a simple write access.

Reduced Power

Dissipation

• Low power CMOS design.

• Separate power supply for internal logic (1.2 V or 1.1 V) and I/O (3.3 V).

• Low-power standby modes.

• Optimized power management circuitry (instruction-dependent, peripheral-dependent, and mode-dependent).

Packaging

• 0.8 mm pitch flip-chip plastic ball-grid array (FC-PBGA) with lead-free or lead-bearing spheres.

• 431-connection (ball).

•20 mm × 20 mm.

Real-Time Operating

System (RTOS)

The real-time operating system (RTOS) fully supports device architecture (multi-core, memory hierarchy, ICache,

timers, DMA controller, interrupts, peripherals), as follows:

• High-performance and deterministic, delivering predictive response time.

• Optimized to provide low interrupt latency with high data throughput.

• Preemptive and priority-based multitasking.

• Fully interrupt/event driven.

• Small memory footprint.

• Comprehensive set of APIs.

Feature Description

MSC8122 Technical Data, Rev. 12

viii Freescale Semiconductor

Features

Multi-Core Support • One instance of kernel code in all four SC140 cores.

• Dynamic and static memory allocation from local memory (M1) and shared memory (M2).

Distributed System

Support

Enables transparent inter-task communications between tasks running inside the SC140 cores and the other tasks

running in on-board devices or remote network devices:

• Messaging mechanism between tasks using mailboxes and semaphores.

• Networking support; data transfer between tasks running inside and outside the device using networking

protocols.

• Includes integrated device drivers for such peripherals as TDM, UART, and external buses.

Software Support

• Task debugging utilities integrated with compilers and vendors.

• Board support package (BSP) for the application development system (ADS).

• Integrated development environment (IDE):

— C/C++ compiler with in-line assembly so developers can generate highly optimized DSP code. Translates

C/C++ code into parallel fetch sets and maintains high code density.

— Librarian. User can create libraries for modularity.

— A collection of C/C++ functions for developer use.

— Highly efficient linker to produce executables from object code.

— Seamlessly integrated real-time, non-intrusive multi-mode debugger for debugging highly optimized DSP

algorithms. The developer can choose to debug in source code, assembly code, or mixed mode.

— Device simulation models enable design and simulation before hardware availability.

— Profiler using a patented binary code instrumentation (BCI) technique helps developers identify program

design inefficiencies.

— Version control. Metrowerks® CodeWarrior® includes plug-ins for ClearCase, Visual SourceSafe, and

CVS.

Boot Options

• External memory.

• External host.

•UART.

•TDM.

•I

MSC8122ADS

• Host debug through single JTAG connector supports both processors.

• MSC8103 as the MSC8122 host with both devices on the board. The MSC8103 system bus connects to the

MSC8122 DSI.

• Flash memory for stand-alone applications.

• Communications ports:

— 10/100Base-T.

— 155 Mbit ATM over Optical.

— T1/E1 TDM interface.

— H.110.

— Voice codec.

— RS-232.

— High-density (MICTOR) logic analyzer connectors to monitor MSC8122 signals

— 6U CompactPCI form factor.

• Emulates MSC8122 DSP farm by connecting to three other ADS boards.

Feature Description

Product Documentation

MSC8122 Technical Data, Rev. 12

Freescale Semiconductor ix

Product Documentation

The documents listed in Table 1 are required for a complete description of the MSC8122 and are necessary to

design properly with the part. Documentation is available from a local Freescale distributor, a Freescale

semiconductor sales office, or a Freescale Literature Distribution Center. For documentation updates, visit the

Freescale DSP website. See the contact information on the back of this document.

Table 1. MSC8122 Documentation

Name Description Order Number

MSC8122

Technical Data

MSC8122 features list and physical, electrical, timing, and package specifications MSC8122

MSC8122

User’s Guide

User information includes system functionality, getting started, and programming

topics

Availability TBD

MSC8122

Reference Manual

Detailed functional description of the MSC8122 memory and peripheral configuration,

operation, and register programming

MSC8122RM

StarCore™ SC140 DSP

Core Reference Manual

Detailed description of the SC140 family processor core and instruction set MNSC140CORE

Application Notes

Documents describing specific applications or optimized device operation including

code examples

Refer to the MSC8122

product page.

MSC8122 Technical Data, Rev. 12

xFreescale Semiconductor

MSC8122 Technical Data, Rev. 12

Freescale Semiconductor 1-1

Signals/Connections 1

The MSC8122 external signals are organized into functional groups, as shown in Table 1-1 and Figure 1-1.

Tabl e 1-1 lists the functional groups, the number of signal connections in each group, and references the table that

gives a detailed listing of multiplexed signals within each group. Figure 1-1 shows MSC8122 external signals

organized by function.

Table 1-1. MSC8122 Functional Signal Groupings

Functional Group

Number of

Signal

Connections

Description

Power (VDD, VCC, and GND) 155 Table 1-2 on page 1-3

Clock 3Table 1-3 on page 1-3

Reset and configuration 4 Table 1-4 on page 1-3

DSI, system bus, Ethernet, and interrupts 210 Table 1-5 on page 1-4

Memory controller 16 Table 1-6 on page 1-14

General-purpose input/output (GPIO), time-division multiplexed (TDM) interface,

universal asynchronous receiver/ transmitter (UART), Ethernet, and timers

32 Table 1-7 on page 1-16

Dedicated Ethernet signals 3 Table 1-8 on page 1-23

EOnCE and JTAG test access port 7 Table 1-9 on page 1-24

Reserved (denotes connections that are always reserved) 1 Table 1-10 on page 1-24

MSC8122 Technical Data, Rev. 12

1-2 Freescale Semiconductor

Signals/Connections

HD0/SWTE ↔1

32 ↔A[0–31]

HD1/DSISYNC ↔1 1 ↔TT0/HA7

HD2/DSI64 ↔1 1 ↔TT1

HD3/MODCK1 ↔1 3 ↔TT[2–4]/CS[5–7]

HD4/MODCK2 ↔1 5 →CS[0–4]

HD5/CNFGS ↔1 4 ↔TSZ[0–3]

HD[6–31] ↔26 1↔TBST

HD[32-39]/D[32-39]/reserved ↔8 1 ↔IRQ1/GBL

HD40/D40/ETHRXD0 ↔1 1 ↔IRQ3/BADDR31

HD41/D41/ETHRXD1 ↔1 1 ↔IRQ2/BADDR30

HD42/D42/ETHRXD2/reserved ↔1 1 ↔IRQ5/BADDR29

HD43/D43/ETHRXD3/reserved ↔1 1 →BADDR28

HD[44-45]/D[44-45]/reserved ↔2 1 →BADDR27

HD46/D46/ETHTXD0 ↔1 1 ↔BR

HD47/D47/ETHTXD1 ↔1 1 ↔BG

HD48/D48/ETHTXD2/reserved ↔1 1 ↔DBG

HD49/D49/ETHTXD3/reserved ↔1 1 ↔ABB/IRQ4

HD[50-53]/D[50-53]/reserved ↔4 1 ↔DBB/IRQ5

HD54/D54/ETHTX_EN ↔1 1 ↔TS

HD55/D55/ETHTX_ER/reserved ↔1 1 ↔AACK

HD56/D56/ETHRX_DV/ETHCRS_DV ↔1 1 ↔ARTRY

HD57/D57/ETHRX_ER ↔132 ↔D[0–31]

HD58/D58/ETHMDC ↔1 1 ↔reserved/DP0/DREQ1/EXT_BR2

HD59/D59/ETHMDIO ↔1 1 ↔IRQ1/DP1/DACK1/EXT_BG2

HD60/D60/ETHCOL/reserved ↔1 1 ↔IRQ2/DP2/DACK2/EXT_DBG2

HD[61–63]/D[61-63]/reserved ↔3 1 ↔IRQ3/DP3/DREQ2/EXT_BR3

HCID[0–2] →3

1↔IRQ4/DP4/DACK3/EXT_DBG3

HCID3/HA8 →1 1 ↔IRQ5/DP5/DACK4/EXT_BG3

HA[11–29] →19 1↔IRQ6/DP6/DREQ3

HWBS[0–3]/HDBS[0–3]/HWBE[0–3]/HDBE[0–3] →4 1 ↔IRQ7/DP7/DREQ4

HWBS[4–7]/HDBS[4–7]/HWBE[4–7]/HDBE[4–7]/

PWE[4–7]/PSDDQM[4–7]/PBS[4–7]

↔4 1 ↔TA

HRDS/HRW/HRDE →1 1 ↔TEA

HBRST →1 1 ←NMI

HDST[0–1]/HA[9–10] →2 1 →NMI_OUT

HCS →1 1 ↔PSDVAL

HBCS →1 1 ↔IRQ7/INT_OUT

HTA ←1

1→BCTL0

HCLKIN →1 1 →BCTL1/CS5

GPIO0/CHIP_ID0/IRQ4/ETHTXD0 ↔1

3↔BM[0–2]/TC[0–2]/BNKSEL[0–2]

GPIO1/TIMER0/CHIP_ID1/IRQ5/ETHTXD1 ↔1 1 →ALE

GPIO2/TIMER1/CHIP_ID2/IRQ6 ↔1 4 →PWE[0–3]/PSDDQM[0–3]/PBS[0–3]

GPIO3/TDM3TSYN/IRQ1/ETHTXD2 ↔1 1 →PSDA10/PGPL0

GPIO4/TDM3TCLK/IRQ2/ETHTX_ER ↔1 1 →PSDWE/PGPL1

GPIO5/TDM3TDAT/IRQ3/ETHRXD3 ↔1 1 →POE/PSDRAS/PGPL2

GPIO6/TDM3RSYN/IRQ4/ETHRXD2 ↔1 1 →PSDCAS/PGPL3

GPIO7/TDM3RCLK/IRQ5/ETHTXD3 ↔1 1 ↔PGTA/PUPMWAIT/PGPL4/PPBS

GPIO8/TDM3RDAT/IRQ6/ETHCOL ↔1 1 →PSDAMUX/PGPL5

GPIO9/TDM2TSYN/IRQ7/ETHMDIO ↔1

GPIO10/TDM2TCLK/IRQ8/ETHRX_DV/ETHCRS_DV/NC ↔1De

bug

1←EE0

GPIO11/TDM2TDAT/IRQ9/ETHRX_ER/ETHTXD ↔1 1 →EE1

GPIO12/TDM2RSYN/IRQ10/ETHRXD1/ETHSYNC ↔1 C

1→CLKOUT

GPIO13/TDM2RCLK/IRQ11/ETHMDC ↔1 1 ←Reserved

GPIO14/TDM2RDAT/IRQ12/ETHRXD0/NC ↔1 1 ←CLKIN

GPIO15/TDM1TSYN/DREQ1 ↔1R

1←PORESET

GPIO16/TDM1TCLK/DONE1/DRACK1 ↔1 1 ↔HRESET

GPIO17/TDM1TDAT/DACK1 ↔1 1 ↔SRESET

GPIO18/TDM1RSYN/DREQ2 ↔1 1 ←RSTCONF

GPIO19/TDM1RCLK/DACK2 ↔1J

1←TMS

GPIO20/TDM1RDAT ↔1 1 ←TDI

GPIO21/TDM0TSYN ↔1 1 ←TCK

GPIO22/TDM0TCLK/DONE2/DRACK2 ↔1 1 ←TRST

GPIO23/TDM0TDAT/IRQ13 ↔1 1 →TDO

GPIO24/TDM0RSYN/IRQ14 ↔1

GPIO25/TDM0RCLK/IRQ15 ↔1

GPIO26/TDM0RDAT ↔1

GPIO27/URXD/DREQ1 ↔1

GPIO28/UTXD/DREQ2 ↔1

GPIO29/CHIP_ID3/ETHTX_EN ↔1Ded.

Eth.

Net

1←ETHRX_CLK/ETHSYNC_IN

GPIO30/TIMER2/TMCLK/SDA ↔1 1 ←ETHTX_CLK/ETHREF_CLK/ETHCLOCK

GPIO31/TIMER3/SCL ↔1 1 ←ETHCRS/ETHRXD

Power signals are: VDD, VDDH, VCCSYN, GND, GNDH, and GNDSYN. Reserved signals can be left unconnected. NC signals must not be connected.

Figure 1-1. MSC8122 External Signals

Power Signals

MSC8122 Technical Data, Rev. 12

Freescale Semiconductor 1-3

1.1 Power Signals

1.2 Clock Signals

1.3 Reset and Configuration Signals

Table 1-2. Power and Ground Signal Inputs

Signal Name Description

VDD Internal Logic Power

VDD dedicated for use with the device core. The voltage should be well-regulated and the input should be provided with

an extremely low impedance path to the VDD power rail.

VDDH Input/Output Power

This source supplies power for the I/O buffers. The user must provide adequate external decoupling capacitors.

VCCSYN System PLL Power

VCC dedicated for use with the system Phase Lock Loop (PLL). The voltage should be well-regulated and the input

should be provided with an extremely low impedance path to the VCC power rail.

GND System Ground

An isolated ground for the internal processing logic and I/O buffers. This connection must be tied externally to all chip

ground connections, except GNDSYN. The user must provide adequate external decoupling capacitors.

GNDSYN System PLL Ground

Ground dedicated for system PLL use. The connection should be provided with an extremely low-impedance path to

ground.

Table 1-3. Clock Signals

Signal Name Type Signal Description

CLKIN Input Clock In

Primary clock input to the MSC8122 PLL.

CLKOUT Output Clock Out

The bus clock.

Reserved Input Reserved. Pull down to ground.

Table 1-4. Reset and Configuration Signals

Signal Name Type Signal Description

PORESET Input Power-On Reset

When asserted, this line causes the MSC8122 to enter power-on reset state.

RSTCONF Input Reset Configuration

Used during reset configuration sequence of the chip. A detailed explanation of its function is provided in

the

MSC8122 Reference Manual

. This signal is sampled upon deassertion of PORESET.

Note: When PORESET is deasserted, the MSC8122 also samples the following signals:

• BM[0–2]—Selects the boot mode.

• MODCK[1–2]—Selects the clock configuration.

• SWTE—Enables the software watchdog timer.

• DSISYNC, DSI64, CNFGS, and CHIP_ID[0–3]—Configures the DSI.

Refer to Table 1-5 for details on these signals.

HRESET Input/Output Hard Reset

When asserted as an input, this signal causes the MSC8122 to enter hard reset state. After the device

enters a hard reset state, it drives the signal as an open-drain output.

SRESET Input/Output Soft Reset

When asserted as an input, this signal causes the MSC8122 to enter soft reset state. After the device

enters a soft reset state, it drives the signal as an open-drain output.

MSC8122 Technical Data, Rev. 12

1-4 Freescale Semiconductor

Signals/Connections

1.4 Direct Slave Interface, System Bus, Ethernet, and

Interrupt Signals

The direct slave interface (DSI) is combined with the system bus because they share some common signal lines.

Individual assignment of a signal to a specific signal line is configured through internal registers. Tabl e 1-5

describes the signals in this group.

Note: Although there are fifteen interrupt request (IRQ) connections to the core processors, there are multiple

external lines that can connect to these internal signal lines. After reset, the default configuration enables

only IRQ[1–7], but includes two input lines each for IRQ[1–3] and IRQ7. The designer must select one line for

each required interrupt and reconfigure the other external signal line or lines for alternate functions.

Additional alternate IRQ lines and IRQ[8–15] are enabled through the GPIO signal lines.

Table 1-5. DSI, System Bus, Ethernet, and Interrupt Signals

Signal Name Type Description

HD0

SWTE

Input/ Output

Input

Host Data Bus 0

Bit 0 of the DSI data bus.

Software Watchdog Timer Disable.

It is sampled on the rising edge of PORESET signal.

HD1

DSISYNC

Input/ Output

Input

Host Data Bus 1

Bit 1 of the DSI data bus.

DSI Synchronous

Distinguishes between synchronous and asynchronous operation of the DSI. It is sampled on the rising

edge of PORESET signal.

HD2

DSI64

Input/ Output

Input

Host Data Bus 2

Bit 2 of the DSI data bus.

DSI 64

Defines the width of the DSI and SYSTEM Data buses. It is sampled on the rising edge of PORESET

signal.

HD3

MODCK1

Input/ Output

Input

Host Data Bus 3

Bit 3 of the DSI data bus.

Clock Mode 1

Defines the clock frequencies. It is sampled on the rising edge of PORESET signal.

HD4

MODCK2

Input/ Output

Input

Host Data Bus 4

Bit 4 of the DSI data bus.

Clock Mode 2

Defines the clock frequencies. It is sampled on the rising edge of PORESET signal.

HD5

CNFGS

Input/ Output

Input

Host Data Bus 5

Bit 5 of the DSI data bus.

Configuration Source

One signal out of two that indicates reset configuration mode. It is sampled on the rising edge of

PORESET signal.

HD[6–31] Input/ Output Host Data Bus 6–31

Bits 6–31 of the DSI data bus.

Direct Slave Interface, System Bus, Ethernet, and Interrupt Signals

MSC8122 Technical Data, Rev. 12

Freescale Semiconductor 1-5

HD[32–39]

D[32–39]

Reserved

Input/ Output

Input

Host Data Bus 32–39

Bits 32–39 of the DSI data bus.

System Bus Data 32–39

For write transactions, the bus master drives valid data on this bus. For read transactions, the slave drives

valid data on this bus.

If the Ethernet port is enabled and multiplexed with the DSI/System bus, these pins are reserved and can

be left unconnected.

HD40

D40

ETHRXD0

Input/ Output

Input

Host Data Bus 40

Bit 40 of the DSI data bus.

System Bus Data 40

For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives

valid data on this bus.

Ethernet Receive Data 0

In MII and RMII modes, bit 0 of the Ethernet receive data.

HD41

D41

ETHRXD1

Input/ Output

Input

Host Data Bus 41

Bit 41 of the DSI data bus.

System Bus Data 41

For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives

valid data on this bus.

Ethernet Receive Data 1

In MII and RMII modes, bit 1 of the Ethernet receive data.

HD42

D42

ETHRXD2

Reserved

Input/ Output

Input

Host Data Bus 42

Bit 42 of the DSI data bus.

System Bus Data 42

For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives

valid data on this bus.

Ethernet Receive Data 2

In MII mode only, bit 2 of the Ethernet receive data.

In RMII mode, this pin is reserved and can be left unconnected.

HD43

D43

ETHRXD3

Reserved

Input/ Output

Input

Host Data Bus 43

Bit 43 of the DSI data bus.

System Bus Data 43

For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives

valid data on this bus.

Ethernet Receive Data 3

In MII mode only, bit 3 of the Ethernet receive data.

In RMII mode, this pin is reserved and can be left unconnected.

HD[44–45]

D[44–56]

Reserved

Input/ Output

Input

Host Data Bus 44–45

Bits 44–45 of the DSI data bus.

System Bus Data 44–45

For write transactions, the bus master drives valid data on this bus. For read transactions, the slave drives

valid data on this bus.

If the Ethernet port is enabled and multiplexed with the DSI/System bus, these pins are reserved and can

be left unconnected.

Table 1-5. DSI, System Bus, Ethernet, and Interrupt Signals (Continued)

Signal Name Type Description

MSC8122 Technical Data, Rev. 12

1-6 Freescale Semiconductor

Signals/Connections

HD46

D46

ETHTXD0

Input/ Output

Output

Host Data Bus 46

Bit 46 of the DSI data bus.

System Bus Data 46

For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives

valid data on this bus.

Ethernet Transmit Data 0

In MII and RMII modes, bit 0 of the Ethernet transmit data.

HD47

D47

ETHTXD1

Input/ Output

Output

Host Data Bus 47

Bit 47 of the DSI data bus.

System Bus Data 47

For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives

valid data on this bus.

Ethernet Transmit Data 1

In MII and RMII modes, bit 1 of the Ethernet transmit data.

HD48

D48

ETHTXD2

Reserved

Input/ Output

Output

Input

Host Data Bus 48

Bit 48 of the DSI data bus.

System Bus Data 48

For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives

valid data on this bus.

Ethernet Transmit Data 2

In MII mode only, bit 2 of the Ethernet transmit data.

In RMII mode, this pin is reserved and can be left unconnected.

HD49

D49

ETHTXD3

Reserved

Input/ Output

Output

Input

Host Data Bus 49

Bit 49 of the DSI data bus.

System Bus Data 49

For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives

valid data on this bus.

Ethernet Transmit Data 3

In MII mode only, bit 3 of the Ethernet transmit data.

In RMII mode, this pin is reserved and can be left unconnected.

HD[50–53]

D[50–53]

Reserved

Input/ Output

Input

Host Data Bus 50–53

Bits 50–53 of the DSI data bus.

System Bus Data 50–53

For write transactions, the bus master drives valid data on this bus. For read transactions, the slave drives

valid data on this bus.

If the Ethernet port is enabled and multiplexed with the DSI/System bus, these pins are reserved and can

be left unconnected.

HD54

D54

ETHTX_EN

Input/ Output

Output

Host Data Bus 54

Bit 54 of the DSI data bus.

System Bus Data 54

For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives

valid data on this bus.

Ethernet Transmit Data Enable

In MII and RMII modes, indicates that the transmit data is valid.

Table 1-5. DSI, System Bus, Ethernet, and Interrupt Signals (Continued)

Signal Name Type Description

Direct Slave Interface, System Bus, Ethernet, and Interrupt Signals

MSC8122 Technical Data, Rev. 12

Freescale Semiconductor 1-7

HD55

D55

ETHTX_ER

Reserved

Input/ Output

Output

Input

Host Data Bus 55

Bit 55 of the DSI data bus.

System Bus Data 55

For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives

valid data on this bus.

Ethernet Transmit Data Error

In MII mode only, indicates a transmit data error.

In RMII mode, this pin is reserved and can be left unconnected.

HD56

D56

ETHRX_DV

ETHCRS_DV

Input/ Output

Input

Host Data Bus 56

Bit 56 of the DSI data bus.

System Bus Data 56

For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives

valid data on this bus.

Ethernet Receive Data Valid

Indicates that the receive data is valid.

Ethernet Carrier Sense/Receive Data Valid

In RMII mode, indicates that a carrier is detected and after the connection is established that the receive

data is valid.

HD57

D57

ETHRX_ER

Input/ Output

Input

Host Data Bus 57

Bit 57 of the DSI data bus.

System Bus Data 57

For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives

valid data on this bus.

Ethernet Receive Data Error

In MII and RMII modes, indicates a receive data error.

HD58

D58

ETHMDC

Input/ Output

Output

Host Data Bus 58

Bit 58 of the DSI data bus.

System Bus Data 58

For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives

valid data on this bus.

Ethernet Management Clock

In MII and RMII modes, used for the MDIO reference clock.

HD59

D59

ETHMDIO

Input/ Output

Host Data Bus 59

Bit 59 of the DSI data bus.

System Bus Data 59

For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives

valid data on this bus.

Ethernet Management Data

In MII and RMII modes, used for station management data input/output.

Table 1-5. DSI, System Bus, Ethernet, and Interrupt Signals (Continued)

Signal Name Type Description

MSC8122 Technical Data, Rev. 12

1-8 Freescale Semiconductor

Signals/Connections

HD60

D60

ETHCOL

Reserved

Input/ Output

Input

Host Data Bus 60

Bit 60 of the DSI data bus.

System Bus Data 60

For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives

valid data on this bus.

Ethernet Collision

In MII mode only, indicates that a collision was detected.

In RMII mode, this pin is reserved and can be left unconnected.

HD[61–63]

D[61–63]

Reserved

Input/ Output

Input

Host Data Bus 61–63

Bits 61–63 of the DSI data bus.

System Bus Data 61–63

For write transactions, the bus master drives valid data on this bus. For read transactions, the slave drives

valid data on this bus.

If the Ethernet port is enabled and multiplexed with the DSI/System bus, these pins are reserved and can

be left unconnected.

HCID[0–2] Input Host Chip ID 0–2

With HCID3, carries the chip ID of the DSI. The DSI is accessed only if HCS is asserted and HCID[0–3]

matches the Chip_ID, or if HBCS is asserted.

HCID3

HA8

Input

Host Chip ID 3

With HCI[0–2], carries the chip ID of the DSI. The DSI is accessed only if HCS is asserted and HCID[0–3]

matches the Chip_ID, or if HBCS is asserted.

Host Bus Address 8

Used by an external host to access the internal address space.

HA[11–29] Input Host Bus Address 11–29

Used by external host to access the internal address space.

HWBS[0–3]

HDBS[0–3]

HWBE[0–3]

HDBE[0–3]

Input

Host Write Byte Strobes (In Asynchronous dual mode)

One bit per byte is used as a strobe for host write accesses.

Host Data Byte Strobe (in Asynchronous single mode)

One bit per byte is used as a strobe for host read or write accesses

Host Write Byte Enable (In Synchronous dual mode)

One bit per byte is used to indicate a valid data byte for host read or write accesses.

Host Data Byte Enable (in Synchronous single mode)

One bit per byte is used as a strobe enable for host write accesses

Table 1-5. DSI, System Bus, Ethernet, and Interrupt Signals (Continued)

Signal Name Type Description

Direct Slave Interface, System Bus, Ethernet, and Interrupt Signals

MSC8122 Technical Data, Rev. 12

Freescale Semiconductor 1-9

HWBS[4–7]

HDBS[4–7]

HWBE[4–7]

HDBE[4–7]

PWE[4–7]

PSDDQM[4–7]

PBS[4–7]

Input

Output

Host Write Byte Strobes (In Asynchronous dual mode)

One bit per byte is used as a strobe for host write accesses.

Host Data Byte Strobe (in Asynchronous single mode)

One bit per byte is used as a strobe for host read or write accesses

Host Write Byte Enable (In Synchronous dual mode)

One bit per byte is used to indicate a valid data byte for host write accesses.

Host Data Byte Enable (in Synchronous single mode)

One bit per byte is used as a strobe enable for host read or write accesses

System Bus Write Enable

Outputs of the bus general-purpose chip-select machine (GPCM). These pins select byte lanes for write

operations.

System Bus SDRAM DQM

From the SDRAM control machine. These pins select specific byte lanes of SDRAM devices.

System Bus UPM Byte Select

From the UPM in the memory controller, these signals select specific byte lanes during memory

operations. The timing of these pins is programmed in the UPM. The actual driven value depends on the

address and size of the transaction and the port size of the accessed device.

HRDS

HRW

HRDE

Input

Host Read Data Strobe (In Asynchronous dual mode)

Used as a strobe for host read accesses.

Host Read/Write Select (in Asynchronous/Synchronous single mode)

Host read/write select.

Host Read Data Enable (In Synchronous dual mode)

Indicates valid data for host read accesses.

HBRST Input Host Burst

The host asserts this pin to indicate that the current transaction is a burst transaction in synchronous

mode only.

HDST[0–1]

HA[9–10]

Input Host Data Structure 0–1

Defines the data structure of the host access in DSI little-endian mode.

Host Bus Address 9–10

Used by an external host to access the internal address space.

HCS Input Host Chip Select

DSI chip select. The DSI is accessed only if HCS is asserted and HCID[0–3] matches the Chip_ID.

HBCS Input Host Broadcast Chip Select

DSI chip select for broadcast mode. Enables more than one DSI to share the same host chip-select pin for

broadcast write accesses.

HTA Output Host Transfer Acknowledge

Upon a read access, indicates to the host when the data on the data bus is valid. Upon a write access,

indicates to the host that the data on the data bus was written to the DSI write buffer.

HCLKIN Input Host Clock Input

Host clock signal for DSI synchronous mode.

A[0–31] Input/ Output Address Bus

When the MSC8122 is in external master bus mode, these pins function as the system address bus. The

MSC8122 drives the address of its internal bus masters and responds to addresses generated by external

bus masters. When the MSC8122 is in internal master bus mode, these pins are used as address lines

connected to memory devices and are controlled by the MSC8122 memory controller.

TT0

HA7

Input/ Output Bus Transfer Type 0

The bus master drives this pins during the address tenure to specify the type of the transaction.

Host Bus Address 7

Used by an external host to access the internal address space.

Table 1-5. DSI, System Bus, Ethernet, and Interrupt Signals (Continued)

Signal Name Type Description

MSC8122 Technical Data, Rev. 12

1-10 Freescale Semiconductor

Signals/Connections

TT1 Input/ Output Bus Transfer Type 1

The bus master drives this pins during the address tenure to specify the type of the transaction. Some

applications use only the TT1 signal, for example, from MSC8122 to MSC8122 or MSC8122 to MSC8101

and

vice

versa

. In these applications, TT1 functions as read/write signal.

TT[2–4]

CS[5–7]

Input/ Output

Output

Bus Transfer Type 2–4

The bus master drives these pins during the address tenure to specify the type of the transaction.

Chip Select 5–7

Enables specific memory devices or peripherals connected to the system bus.

CS[0–4] Output Chip Select 0–4

Enables specific memory devices or peripherals connected to the system bus.

TSZ[0–3] Input/ Output Transfer Size 0–3

The bus master drives these pins with a value indicating the number of bytes transferred in the current

transaction.

TBST Input/ Output Bus Transfer Burst

The bus master asserts this pin to indicate that the current transaction is a burst transaction (transfers

eight words).

IRQ1

GBL

Input

Output

Interrupt Request 11

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

Global1

When a master within the MSC8122 initiates a bus transaction, it drives this pin. Assertion of this pin

indicates that the transfer is global and should be snooped by caches in the system.

IRQ3

BADDR31

Input

Output

Interrupt Request 31

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

Burst Address 311

Five burst address output pins are outputs of the memory controller. These pins connect directly to

burstable memory devices without internal address incrementors controlled by the MSC8122 memory

controller.

IRQ2

BADDR30

Input

Output

Interrupt Request 21

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

Burst Address 301

Five burst address output pins are outputs of the memory controller. These pins connect directly to

burstable memory devices without internal address incrementors controlled by the MSC8122 memory

controller.

IRQ5

BADDR29

Input

Output

Interrupt Request 51

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

Bus Burst Address 291

Five burst address output pins are outputs of the memory controller. These pins connect directly to

burstable memory devices without internal address incrementors controlled by the MSC8122 memory

controller.

BADDR28 Output Burst Address 28

Five burst address output pins are outputs of the memory controller. These pins connect directly to

burstable memory devices without internal address incrementors controlled by the MSC8122 memory

controller.

BADDR27 Output Burst Address 27

Five burst address output pins are outputs of the memory controller. These pins connect directly to

burstable memory devices without internal address incrementors controlled by the MSC8122 memory

controller.

Table 1-5. DSI, System Bus, Ethernet, and Interrupt Signals (Continued)

Signal Name Type Description

Direct Slave Interface, System Bus, Ethernet, and Interrupt Signals

MSC8122 Technical Data, Rev. 12

Freescale Semiconductor 1-11

BR Input/ Output Bus Request2

When an external arbiter is used, the MSC8122 asserts this pin as an output to request ownership of the

bus. When the MSC8122 controller is used as an internal arbiter, an external master asserts this pin as an

input to request bus ownership.

BG Input/ Output Bus Grant2

When the MSC8122 acts as an internal arbiter, it asserts this pin as an output to grant bus ownership to

an external bus master. When an external arbiter is used, it asserts this pin as an input to grant bus

ownership to the MSC8122.

DBG Input/ Output Data Bus Grant2

When the MSC8122 acts as an internal arbiter, it asserts this pin as an output to grant data bus ownership

to an external bus master. When an external arbiter is used, it asserts this pin as an input to grant data

bus ownership to the MSC8122.

ABB

IRQ4

Input/ Output

Input

Address Bus Busy1

The MSC8122 asserts this pin as an output for the duration of the address bus tenure. Following an

AACK, which terminates the address bus tenure, the MSC8122 deasserts ABB for a fraction of a bus

cycle and then stops driving this pin. The MSC8122 does not assume bus ownership as long as it senses

this pin is asserted as an input by an external bus master.

Interrupt Request 4

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

DBB

IRQ5

Input/ Output

Input

Data Bus Busy1

The MSC8122 asserts this pin as an output for the duration of the data bus tenure. Following a TA, which

terminates the data bus tenure, the MSC8122 deasserts DBB for a fraction of a bus cycle and then stops

driving this pin. The MSC8122 does not assume data bus ownership as long as it senses that this pin is

asserted as an input by an external bus master.

Interrupt Request 5

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

TS Input/ Output Bus Transfer Start

Assertion of this pin signals the beginning of a new address bus tenure. The MSC8122 asserts this signal

when one of its internal bus masters begins an address tenure. When the MSC8122 senses that this pin is

asserted by an external bus master, it responds to the address bus tenure as required (snoop if enabled,

access internal MSC8122 resources, memory controller support).

AACK Input/ Output Address Acknowledge

A bus slave asserts this signal to indicate that it has identified the address tenure. Assertion of this signal

terminates the address tenure.

ARTRY Input/ Output Address Retry

Assertion of this signal indicates that the bus master should retry the bus transaction. An external master

asserts this signal to enforce data coherency with its caches and to prevent deadlock situations.

D[0–31] Input/ Output Data Bus Bits 0–31

In write transactions, the bus master drives the valid data on this bus. In read transactions, the slave

drives the valid data on this bus.

Reserved

DP0

DREQ1

EXT_BR2

Input

Input/ Output

Input

The primary configuration selection (default after reset) is reserved.

System Bus Data Parity 0

The agent that drives the data bus also drives the data parity signals. The value driven on the data parity

0 pin should give odd parity (odd number of ones) on the group of signals that includes data parity 0 and

D[0–7].

DMA Request 1

Used by an external peripheral to request DMA service.

External Bus Request 2

An external master asserts this pin to request bus ownership from the internal arbiter.

Table 1-5. DSI, System Bus, Ethernet, and Interrupt Signals (Continued)

Signal Name Type Description

MSC8122 Technical Data, Rev. 12

1-12 Freescale Semiconductor

Signals/Connections

IRQ1

DP1

DACK1

EXT_BG2

Input

Input/ Output

Output

Interrupt Request 1

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

System Bus Data Parity 1

The agent that drives the data bus also drives the data parity signals. The value driven on the data parity

1 pin should give odd parity (odd number of ones) on the group of signals that includes data parity 1 and

D[8–15].

DMA Acknowledge 1

The DMA controller drives this output to acknowledge the DMA transaction on the bus.

External Bus Grant 22

The MSC8122 asserts this pin to grant bus ownership to an external bus master.

IRQ2

DP2

DACK2

EXT_DBG2

Input

Input/ Output

Output

Interrupt Request 2

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

System Bus Data Parity 2

The agent that drives the data bus also drives the data parity signals. The value driven on the data parity

2 pin should give odd parity (odd number of ones) on the group of signals that includes data parity 2 and

D[16–23].

DMA Acknowledge 2

The DMA controller drives this output to acknowledge the DMA transaction on the bus.

External Data Bus Grant 22

The MSC8122 asserts this pin to grant data bus ownership to an external bus master.

IRQ3

DP3

DREQ2

EXT_BR3

Input

Input/ Output

Input

Interrupt Request 3

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

System Bus Data Parity 3

The agent that drives the data bus also drives the data parity signals. The value driven on the data parity

3 pin should give odd parity (odd number of ones) on the group of signals that includes data parity 3 and

D[24–31].

DMA Request 2

Used by an external peripheral to request DMA service.

External Bus Request 32

An external master should assert this pin to request bus ownership from the internal arbiter.

IRQ4

DP4

DACK3

EXT_DBG3

Input

Input/ Output

Output

Interrupt Request 4

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

System Bus Data Parity 4

The agent that drives the data bus also drives the data parity signals. The value driven on the data parity

4 pin should give odd parity (odd number of ones) on the group of signals that includes data parity 4 and

D[32–39].

DMA Acknowledge 3

The DMA controller drives this output to acknowledge the DMA transaction on the bus.

External Data Bus Grant 32

The MSC8122 asserts this pin to grant data bus ownership to an external bus master.

Table 1-5. DSI, System Bus, Ethernet, and Interrupt Signals (Continued)

Signal Name Type Description

Direct Slave Interface, System Bus, Ethernet, and Interrupt Signals

MSC8122 Technical Data, Rev. 12

Freescale Semiconductor 1-13

IRQ5

DP5

DACK4

EXT_BG3

Input

Input/ Output

Output

Interrupt Request 5

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

System Bus Data Parity 5

The agent that drives the data bus also drives the data parity signals. The value driven on the data parity

5 pin should give odd parity (odd number of ones) on the group of signals that includes data parity 5 and

D[40–47].

DMA Acknowledge 4

The DMA controller drives this output to acknowledge the DMA transaction on the bus.

External Bus Grant 32

The MSC8122 asserts this pin to grant bus ownership to an external bus.

IRQ6

DP6

DREQ3

Input

Input/ Output

Input

Interrupt Request 6

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

System Bus Data Parity 6

The agent that drives the data bus also drives the data parity signals. The value driven on the data parity

6 pin should give odd parity (odd number of ones) on the group of signals that includes data parity 6 and

D[48–55].

DMA Request 3

Used by an external peripheral to request DMA service.

IRQ7

DP7

DREQ4

Input

Input/ Output

Input

Interrupt Request 7

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

System Bus Data Parity 7

The agent that drives the data bus also drives the data parity signals. The value driven on the data parity

7 pin should give odd parity (odd number of ones) on the group of signals that includes data parity 7 and

D[56–63].

DMA Request 4

Used by an external peripheral to request DMA service.

TA Input/ Output Transfer Acknowledge

Indicates that a data beat is valid on the data bus. For single-beat transfers, TA assertion indicates the

termination of the transfer. For burst transfers, TA is asserted eight times to indicate the transfer of eight

data beats, with the last assertion indicating the termination of the burst transfer.

TEA Input/ Output Transfer Error Acknowledge

Indicates a failure of the data tenure transaction.The masters within the MSC8122 monitor the state of this

pin. The MSC8122 internal bus monitor can assert this pin if it identifies a bus transfer that does not

complete.

NMI Input Non-Maskable Interrupt

When an external device asserts this line, it generates an non-maskable interrupt in the MSC8122, which

is processed internally (default) or is directed to an external host for processing (see NMI_OUT).

NMI_OUT Output Non-Maskable Interrupt Output

An open-drain pin driven from the MSC8122 internal interrupt controller. Assertion of this output indicates

that a non-maskable interrupt is pending in the MSC8122 internal interrupt controller, waiting to be

handled by an external host.

PSDVAL Input/ Output Port Size Data Valid

Indicates that a data beat is valid on the data bus. The difference between the TA pin and the PSDVAL pin

is that the TA pin is asserted to indicate data transfer terminations, while the PSDVAL signal is asserted

with each data beat movement. When TA is asserted, PSDVAL is always asserted. However, when

PSDVAL is asserted, TA is not necessarily asserted. For example, if the DMA controller initiates a double

word (2 × 64 bits) transaction to a memory device with a 32-bit port size, PSDVAL is asserted three times

without TA and, finally, both pins are asserted to terminate the transfer.

Table 1-5. DSI, System Bus, Ethernet, and Interrupt Signals (Continued)

Signal Name Type Description

MSC8122 Technical Data, Rev. 12

1-14 Freescale Semiconductor

Signals/Connections

1.5 Memory Controller Signals

Refer to the Memory Controller chapter in the MSC8122 Reference Manual for details on configuring these

signals.

IRQ7

INT_OUT

Input

Output

Interrupt Request 7

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

Interrupt Output

Assertion of this output indicates that an unmasked interrupt is pending in the MSC8122 internal interrupt

controller.

Notes: 1. See the System Interface Unit (SIU) chapter in the

MSC8122 Reference Manual

for details on how to configure these pins.

2. When used as the bus control arbiter, the MSC8122 can support up to three external bus masters. Each master uses its own

set of Bus Request, Bus Grant, and Data Bus Grant signals (BR/BG/DBG, EXT_BR2/EXT_BG2/EXT_DBG2, and

EXT_BR3/EXT_BG3/EXT_DBG3). Each of these signal sets must be configured to indicate whether the external master is or

is not a MSC8122 master device. See the Bus Configuration Register (BCR) description in the System Interface Unit (SIU)

chapter in the

MSC8122 Reference Manual

for details on how to configure these pins. The second and third set of pins is

defined by EXT_xxx to indicate that they can only be used with external master devices. The first set of pins (BR/BG/DBG)

have a dual function. When the MSC8122 is not the bus arbiter, it uses these signals (BR/BG/DBG) to obtain master control of

the bus.

Table 1-6. Memory Controller Signals

Signal Name Type Description

BCTL0 Output System Bus Buffer Control 0

Controls buffers on the data bus. Usually used with BCTL1. The exact function of this pin is defined by the

value of SIUMCR[BCTLC].

BCTL1

CS5

Output

System Bus Buffer Control 1

Controls buffers on the data bus. Usually used with BCTL0. The exact function of this pin is defined by the

value of SIUMCR[BCTLC].

System and Local Bus Chip Select 5

Enables specific memory devices or peripherals connected to MSC8122 buses.

BM[0–2]

TC[0–2]

BNKSEL[0–2]

Input

Input/ Output

Output

Boot Mode 0–2

Defines the boot mode of the MSC8122. This signal is sampled on PORESET deassertion.

Transfer Code 0–2

The bus master drives these pins during the address tenure to specify the type of the code.

Bank Select 0–2

Selects the SDRAM bank when the MSC8122 is in 60x-compatible bus mode.

ALE Output Address Latch Enable

Controls the external address latch used in an external master bus.

PWE[0–3]

PSDDQM[0–3]

PBS[0–3]

Output

System Bus Write Enable

Outputs of the bus general-purpose chip-select machine (GPCM). These pins select byte lanes for write

operations.

System Bus SDRAM DQM

From the SDRAM control machine. These pins select specific byte lanes of SDRAM devices.

System Bus UPM Byte Select

From the UPM in the memory controller, these signals select specific byte lanes during memory

operations. The timing of these pins is programmed in the UPM. The actual driven value depends on the

address and size of the transaction and the port size of the accessed device.

Table 1-5. DSI, System Bus, Ethernet, and Interrupt Signals (Continued)

Signal Name Type Description

Memory Controller Signals

MSC8122 Technical Data, Rev. 12

Freescale Semiconductor 1-15

PSDA10

PGPL0

Output

System Bus SDRAM A10

From the bus SDRAM controller. The precharge command defines which bank is precharged. When the

row address is driven, it is a part of the row address. When column address is driven, it is a part of column

address.

System Bus UPM General-Purpose Line 0

One of six general-purpose output lines from the UPM. The values and timing of this pin are programmed

in the UPM.

PSDWE

PGPL1

Output

System Bus SDRAM Write Enable

From the bus SDRAM controller. Should connect to SDRAM WE input.

System Bus UPM General-Purpose Line 1

One of six general-purpose output lines from the UPM. The values and timing of this pin are programmed

in the UPM.

POE

PSDRAS

PGPL2

Output

System Bus Output Enable

From the bus GPCM. Controls the output buffer of memory devices during read operations.

System Bus SDRAM RAS

From the bus SDRAM controller. Should connect to SDRAM RAS input.

System Bus UPM General-Purpose Line 2

One of six general-purpose output lines from the UPM. The values and timing of this pin are programmed

in the UPM.

PSDCAS

PGPL3

Output

System Bus SDRAM CAS

From the bus SDRAM controller. Should connect to SDRAM CAS input.

System Bus UPM General-Purpose Line 3

One of six general-purpose output lines from the UPM. The values and timing of this pin are programmed

in the UPM.

PGTA

PUPMWAIT

PGPL4

PPBS

Input

Output

System GPCM TA

Terminates external transactions during GPCM operation. Requires an external pull-up resistor for proper

operation.

System Bus UPM Wait

An external device holds this pin low to force the UPM to wait until the device is ready to continue the

operation.

System Bus UPM General-Purpose Line 4

One of six general-purpose output lines from the UPM. The values and timing of this pin are programmed

in the UPM.

System Bus Parity Byte Select

In systems that store data parity in a separate chip, this output is used as the byte-select for that chip.

PSDAMUX

PGPL5

Output

System Bus SDRAM Address Multiplexer

Controls the system bus SDRAM address multiplexer when the MSC8122 is in external master mode.

System Bus UPM General-Purpose Line 5

One of six general-purpose output lines from the UPM. The values and timing of this pin are programmed

in the UPM.

Table 1-6. Memory Controller Signals (Continued)

Signal Name Type Description

MSC8122 Technical Data, Rev. 12

1-16 Freescale Semiconductor

Signals/Connections

1.6 GPIO, TDM, UART, and Timer Signals

The general-purpose input/output (GPIO), time-division multiplexed (TDM), universal asynchronous

receiver/transmitter (UART), and timer signals are grouped together because they use a common set of signal lines.

Individual assignment of a signal to a specific signal line is configured through internal registers. Tabl e 1-7

describes the signals in this group.

Table 1-7. GPIO, TDM, UART, Ethernet, and Timer Signals

Signal Name Type Description

GPIO0

CHIP_ID0

IRQ4

ETHTXD0

Input/ Output

Input

Output

General-Purpose Input Output 0

One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs.

Chip ID 0

Determines the chip ID of the MSC8122 DSI. It is sampled on the rising edge of PORESET signal.

Interrupt Request 4

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

Ethernet Transmit Data 0

For MII or RMII mode, bit 0 of the Ethernet transmit data.

GPIO1

TIMER0

CHIP_ID1

IRQ5

ETHTXD1

Input/ Output

Input

Output

General-Purpose Input Output 1

One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs.

Timer 0

Each signal is configured as either input to or output from the counter. See the

MSC8122 Reference

Manual

for configuration details.

Chip ID 1

Determines the chip ID of the MSC8122 DSI. It is sampled on the rising edge of PORESET signal.

Interrupt Request 5

One of the fifteen external lines that can request a service routine, via the internal interrupt controller, from

the SC140 core.

Ethernet Transmit Data 1

For MII or RMII mode, bit 1 of the Ethernet transmit data.

GPIO2

TIMER1

CHIP_ID2

IRQ6

Input/ Output

Input

General-Purpose Input Output 2

One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For

details, refer to the

MSC8122 Reference Manual

Timer 1

Each signal is configured as either input to or output from the counter. For the configuration of the pin

direction, refer to the

MSC8122 Reference Manual

Chip ID 2

Determines the chip ID of the MSC8122 DSI. It is sampled on the rising edge of PORESET signal.

Interrupt Request 6

One of the fifteen external lines that can request a service routine, via the internal interrupt controller, from

the SC140 core.

GPIO, TDM, UART, and Timer Signals

MSC8122 Technical Data, Rev. 12

Freescale Semiconductor 1-17

GPIO3

TDM3TSYN

IRQ1

ETHTXD2

Input/ Output

Input

Output

General-Purpose Input Output 3

One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For

details, refer to the

MSC8122

Reference Manual

GPIO programming model.

TDM3 Transmit Frame Sync

Transmit frame sync for TDM 3.

Interrupt Request 1

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

Ethernet Transmit Data 2

For MII mode only, bit 2 of the Ethernet transmit data.

GPIO4

TDM3TCLK

IRQ2

ETHTX_ER

Input/ Output

Input

Output

General-Purpose Input Output 4

One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For

details, refer to the

MSC8122 Reference Manual

GPIO programming model.

TDM3 Transmit Clock

Transmit Clock for TDM 3

Interrupt Request 2

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

Ethernet Transmit Data Error

For MII mode only, indicates whether a transmit data error occurred.

GPIO5

TDM3TDAT

IRQ3

ETHRXD3

Input/ Output

Input

General-Purpose Input/Output 5

One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For

details, refer to the

MSC8122

Reference Manual

GPIO programming model.

TDM3 Serial Transmitter Data

The serial transmit data signal for TDM 3. As an output, it provides the DATA_D signal for TDM 3. For

configuration details, refer to the

MSC8122

Reference Manual

chapter describing TDM operation.

Interrupt Request 3

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

Ethernet Receive Data 3

For MII mode only, bit 3 of the Ethernet receive data.

GPIO6

TDM3RSYN

IRQ4

ETHRXD2

Input/ Output

Input

General-Purpose Input Output 6

One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For

details, refer to the

MSC8122

Reference Manual

GPIO programming model.

TDM3 Receive Frame Sync

The receive sync signal for TDM 3. As an input, this can be the DATA_B data signal for TDM 3.For

configuration details, refer to the

MSC8122

Reference Manual

chapter describing TDM operation.

Interrupt Request 4

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

Ethernet Receive Data 2

For MII mode only, bit 2 of the Ethernet receive data.

Table 1-7. GPIO, TDM, UART, Ethernet, and Timer Signals (Continued)

Signal Name Type Description

MSC8122 Technical Data, Rev. 12

1-18 Freescale Semiconductor

Signals/Connections

GPIO7

TDM3RCLK

IRQ5

ETHTXD3

Input/ Output

Input

Output

General-Purpose Input Output 7

One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For

details, refer to the

MSC8122

Reference Manual

GPIO programming model.

TDM3 Receive Clock

The receive clock signal for TDM 3. As an output, this can be the DATA_C data signal for TDM 3. For

configuration details, refer to the

MSC8122

Reference Manual

chapter describing TDM operation.

Interrupt Request 5

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

Ethernet Transmit Data 3

For MII mode only, bit 3 of the Ethernet transmit data.

GPIO8

TDM3RDAT

IRQ6

ETHCOL

Input/ Output

Input

General-Purpose Input Output 8

One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For

details, refer to the

MSC8122

Reference Manual

GPIO programming model.

TDM3 Serial Receiver Data

The receive data signal for TDM 3. As an input, this can be the DATA_A data signal for TDM 3. For

configuration details, refer to the

MSC8122

Reference Manual

chapter describing TDM operation.

Interrupt Request 6

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

Ethernet Collision

For MII mode only, indicates whether a collision was detected.

GPIO9

TDM2TSYN

IRQ7

ETHMDIO

Input/ Output

Input

Input/ Output

General-Purpose Input Output 9

One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For

details, refer to the

MSC8122

Reference Manual

GPIO programming model.

TDM2 Transmit frame Sync

Transmit Frame Sync for TDM 2.

Interrupt Request 7

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

Ethernet Management Data

Station management data input/output line in MII, RMII, and SMII modes.

GPIO10

TDM2TCLK

IRQ8

ETHRX_DV

ETHCRS_DV

Input/ Output

Input

General-Purpose Input Output 10

One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For

details, refer to the

MSC8122

Reference Manual

GPIO programming model.

TDM 2 Transmit Clock

Transmit Clock for TDM 2.

Interrupt Request 8

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

Ethernet Receive Data Valid

In MII mode, this signal indicates that the receive data is valid.

Ethernet Carrier Sense/Receive Data Valid

In RMII mode, this signal indicates that a carrier is sense or that the receive data is valid.

Not Connected

For SMII mode, this signal must be left unconnected.

Table 1-7. GPIO, TDM, UART, Ethernet, and Timer Signals (Continued)

Signal Name Type Description

GPIO, TDM, UART, and Timer Signals

MSC8122 Technical Data, Rev. 12

Freescale Semiconductor 1-19

GPIO11

TDM2TDAT

IRQ9

ETHRX_ER

ETHTXD

Input/ Output

Input

Output

General-Purpose Input Output 11

One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For

details, refer to the

MSC8122

Reference Manual

GPIO programming model.

TDM2 Serial Transmitter Data

The transmit data signal for TDM 2. As an output, this can be the DATA_D data signal for TDM 2. For

configuration details, refer to the

MSC8122

Reference Manual

chapter describing TDM operation.

Interrupt Request 9

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

Ethernet Receive Data Error

In MII and RMII modes, indicates a receive data error.

Ethernet Transmit Data

In SMII, used as the Ethernet transmit data line.

GPIO12

TDM2RSYN

IRQ10

ETHRXD1

ETHSYNC

Input/ Output

Input

Output

General-Purpose Input Output 12

One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For

details, refer to the

MSC8122

Reference Manual

GPIO programming model.

TDM2 Receive Frame Sync

The receive sync signal for TDM 2. As an input, this can be the DATA_B data signal for TDM 2. For

configuration details, refer to the

MSC8122

Reference Manual

chapter describing TDM operation.

Interrupt Request 10

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

Ethernet Receive Data 1

Bit 1 of the Ethernet receive data (MII and RMII mode).

Ethernet Sync Signal

In SMII mode, this is the Ethernet sync signal input.

GPIO13

TDM2RCLK

IRQ11

ETHMDC

Input/ Output

Input

Output

General-Purpose Input Output 13

One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For

details, refer to the

MSC8122

Reference Manual

GPIO programming model.

TDM2 Receive Clock

The receive clock signal for TDM 2. As an input, this can be the DATA_C data signal for TDM 2. For

configuration details, refer to the

MSC8122

Reference Manual

chapter describing TDM operation.

Interrupt Request 11

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

Ethernet Management Clock

Used for the MDIO reference clock for MII, RMII, and SMII modes.

Table 1-7. GPIO, TDM, UART, Ethernet, and Timer Signals (Continued)

Signal Name Type Description

MSC8122 Technical Data, Rev. 12

1-20 Freescale Semiconductor

Signals/Connections

GPIO14

TDM2RDAT

IRQ12

ETHRXD0

Input/ Output

Input

General-Purpose Input Output 14

One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For

details, refer to the

MSC8122

Reference Manual

GPIO programming model.

TDM2 Serial Receiver Data

The receive data signal for TDM 2. As an input, this can be the DATA_A data signal for TDM 2. For

configuration details, refer to the

MSC8122

Reference Manual

chapter describing TDM operation.

Interrupt Request 12

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

Ethernet Receive Data 0

Bit 0 of the Ethernet receive data (MII and RMII).

Not Connected

For SMII mode, this signal must be left unconnected.

GPIO15

TDM1TSYN

DREQ1

Input/ Output

Input

General-Purpose Input Output 15

One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For

details, refer to the

MSC8122 Reference Manual

GPIO programming model.

TDM1 Transmit frame Sync

Transmit Frame Sync for TDM 1.

DMA Request 1

Used by an external peripheral to request DMA service.

GPIO16

TDM1TCLK

DONE1

DRACK1

Input/ Output

Input

Input/ Output

Output

General-Purpose Input Output 16

One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For

details, refer to the

MSC8122 Reference Manual

GPIO programming model.

TDM1 Transmit Clock

Transmit Clock for TDM 1.

DMA Done 1

Signifies that the channel must be terminated. If the DMA controller generates DONE, the channel

handling this peripheral is inactive. As an input to the DMA controller, DONE closes the channel much like

a normal channel closing.

See the

MSC8122 Reference Manual

chapters on DMA controller and GPIO for information on

configuring the DRACK or DONE mode and pin direction.

DMA Data Request Acknowledge 1

Asserted by the DMA controller to indicate that the DMA controller has sampled the peripheral request.

GPIO17

TDM1TDAT

DACK1

Input/ Output

Output

General-Purpose Input Output 17

One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For

details, refer to the

MSC8122

Reference Manual

GPIO programming model.

TDM1 Serial Transmitter Data

The transmit data signal for TDM 1. As an output, this can be the DATA_D data signal for TDM 1.For

configuration details, refer to the

MSC8122

Reference Manual

chapter describing TDM operation.

DMA Acknowledge 1

The DMA controller drives this output to acknowledge the DMA transaction on the bus.

Table 1-7. GPIO, TDM, UART, Ethernet, and Timer Signals (Continued)

Signal Name Type Description

GPIO, TDM, UART, and Timer Signals

MSC8122 Technical Data, Rev. 12

Freescale Semiconductor 1-21

GPIO18

TDM1RSYN

DREQ2

Input/ Output

Input

General-Purpose Input Output 18

One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For

details, refer to the

MSC8122 Reference Manual

GPIO programming model.

TDM1 Receive Frame Sync

The receive sync signal for TDM 1. As an input, this can be the DATA_B data signal for TDM 1. For

configuration details, refer to the

MSC8122

Reference Manual

DMA Request 1

Used by an external peripheral to request DMA service.

GPIO19

TDM1RCLK

DACK2

Input/ Output

Output

General-Purpose Input Output 19

One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For

details, refer to the

MSC8122

Reference Manual

GPIO programming model.

TDM1 Receive Clock

The receive clock signal for TDM 1. As an input, this can be the DATA_C data signal for TDM 1. For

configuration details, refer to the

MSC8122

Reference Manual

chapter describing TDM operation.

DMA Acknowledge 2

The DMA controller drives this output to acknowledge the DMA transaction on the bus.

GPIO20

TDM1RDAT

Input/ Output

General-Purpose Input Output 20

One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For

details, refer to the

MSC8122

Reference Manual

GPIO programming model.

TDM1 Serial Receiver Data

The receive data signal for TDM 1. As an input, this can be the DATA_A data signal for TDM 1. For

configuration details, refer to the

MSC8122

Reference Manual

GPIO21

TDM0TSYN

Input/ Output

General-Purpose Input Output 21

One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For

details, refer to the

MSC8122

Reference Manual

GPIO programming model.

TDM0 Transmit frame Sync

Transmit Frame Sync for TDM 0.

GPIO22

TDM0TCLK

DONE2

DRACK2

Input/ Output

Input

Input/ Output

Output

General-Purpose Input Output 22

One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs.For

details, refer to the

MSC8122 Reference Manual

GPIO programming model.

TDM 0 Transmit Clock

Transmit Clock for TDM 0.

DMA Done 2

Signifies that the channel must be terminated. If the DMA generates DONE, the channel handling this

peripheral is inactive. As an input to the DMA, DONE closes the channel much like a normal channel

closing.

Note: See the

MSC8122 Reference Manual

chapters on DMA and GPIO for information on

configuring the DRACK or DONE mode and pin direction.

DMA Data Request Acknowledge 2

Asserted by the DMA controller to indicate that the DMA controller has sampled the peripheral request.

Table 1-7. GPIO, TDM, UART, Ethernet, and Timer Signals (Continued)

Signal Name Type Description

MSC8122 Technical Data, Rev. 12

1-22 Freescale Semiconductor

Signals/Connections

GPIO23

TDM0TDAT

IRQ13

Input/ Output

Input

General-Purpose Input Output 23

One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For

details, refer to the

MSC8122 Reference Manual

GPIO programming model.

TDM0 Serial Transmitter Data

The transmit data signal for TDM 0. As an output, this can be the DATA_D data signal for TDM 0. For

configuration details, refer to the

MSC8122

Reference Manual

chapter describing TDM operation.

Interrupt Request 13

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

GPIO24

TDM0RSYN

IRQ14

Input/ Output

Input

General-Purpose Input Output 24

One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For

details, refer to the

MSC8122

Reference Manual

GPIO programming model.

TDM0 Receive Frame Sync

The receive sync signal for TDM 0. As an input, this can be the DATA_B data signal for TDM 0. For

configuration details, refer to the

MSC8122

Reference Manual

chapter describing TDM operation.

Interrupt Request 14

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

GPIO25

TDM0RCLK

IRQ15

Input/ Output

Input

General-Purpose Input Output 25

One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For

details, refer to the

MSC8122

Reference Manual

GPIO programming model.

TDM0 Receive Clock

The receive clock signal for TDM 0. As an input, this can be the DATA_C data signal for TDM 0. For

configuration details, refer to the

MSC8122

Reference Manual

chapter describing TDM operation.

Interrupt Request 15

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

GPIO26

TDM0RDAT

Input/ Output

General-Purpose Input Output 26

One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For

details, refer to the

MSC8122

Reference Manual

GPIO programming model.

TDM0 Serial Receiver Data

The receive data signal for TDM 0. As an input, this can be the DATA_A data signal for TDM 0. For

configuration details, refer to the

MSC8122

Reference Manual

chapter describing TDM operation.

GPIO27

DREQ1

URXD

Input/ Output

Input

General-Purpose Input Output 27

One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For

details, refer to the

MSC8122

Reference Manual

GPIO programming model.

DMA Request 1

Used by an external peripheral to request DMA service.

UART Receive Data

GPIO28

DREQ2

UTXD

Input/ Output

Input

Output

General-Purpose Input Output 28

One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For

details, refer to the

MSC8122

Reference Manual

GPIO programming model.

DMA Request 2

Used by an external peripheral to request DMA service.

UART Transmit Data

Table 1-7. GPIO, TDM, UART, Ethernet, and Timer Signals (Continued)

Signal Name Type Description

Dedicated Ethernet Signals

MSC8122 Technical Data, Rev. 12

Freescale Semiconductor 1-23

1.7 Dedicated Ethernet Signals

Most Ethernet signals are multiplexed with the DSI/system bus and the GPIO ports. In addition to the multiplexed

signals, there are three dedicated Ethernet signals that are described in Table 1-8.

GPIO29

CHIP_ID3

ETHTX_EN

Input/ Output

Input

Output

General-Purpose Input Output 29

One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For

details, refer to the

MSC8122

Reference Manual

GPIO programming model.

Chip ID 3

Determines the chip ID of the MSC8122 DSI. It is sampled on the rising edge of PORESET signal.

Ethernet Transmit Enable

Used to enable the Ethernet transmit controller for MII and RMII modes.

GPIO30

TIMER2

TMCLK

SDA

Input/ Output

Input

Input/ Output

General-Purpose Input Output 30

One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs.For

details, refer to the

MSC8122

Reference Manual

GPIO programming model.

Timer 2

Each signal is configured as either input to the counter or output from the counter. For the configuration of

the pin direction, refer to the

MSC8122 Reference Manual

External TIMER Clock

An external timer can connect directly to the SIU as the SIU clock.

I2C-Bus Data Line

This is the data line for the I2C bus.

GPIO31

TIMER3

SCL

Input/ Output

General-Purpose Input Output 31

One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For

details, refer to the

MSC8122

Reference Manual

GPIO programming model.

Timer 3

Each signal is configured as either input to or output from the counter. For the configuration of the pin

direction, refer to the

MSC8122 Reference Manual

I2C-Bus Clock Line

This the clock line for the I2C bus.

Table 1-8. Dedicated Ethernet Signals

Signal Name Type Signal Description

ETHRX_CLK

ETHSYNC_IN

Input

Receive Clock

In MII mode, provides the timing reference for the receive signals.

Sync Input

In SMII mode, is the sync signal input line.

ETHTX_CLK

ETHREF_CLK

ETHCLOCK

Input

Transmit Clock

In MII mode, provides the timing reference for transmit signals.

Reference Clock

In RMII mode, provides the timing reference.

Ethernet Clock

In SMII mode, provides the Ethernet clock signal.

Table 1-7. GPIO, TDM, UART, Ethernet, and Timer Signals (Continued)

Signal Name Type Description

MSC8122 Technical Data, Rev. 12

1-24 Freescale Semiconductor

Signals/Connections

1.8 EOnCE Event and JTAG Test Access Port Signals

The MSC8122 uses two sets of debugging signals for the two types of internal debugging modules: EOnCE and the

JTAG TAP controller. Each internal SC140 core has an EOnce module, but they are all accessed externally by the

same two signals EE0 and EE1. The MSC8122 supports the standard set of test access port (TAP) signals defined by

IEEE 1149.1 Standard Test Access Port and Boundary-Scan Architecture specification and described in Table 1-9.

1.9 Reserved Signals

ETHCRS

ETHRXD

Input

Carrier Sense

In MII mode, indicates that either the transmit or receive medium is non-idle.

Ethernet Receive Data

In SMII mode, used for the Ethernet receive data.

Table 1-9. JTAG TAP Signals

Signal Name Type Signal Description

EE0 Input EOnCE Event Bit 0

Puts the internal SC140 cores into Debug mode.

EE1 Output EOnCE Event Bit 1

Indicates that at least one on-device SC140 core is in Debug mode.

TCK Input Test Clock—Synchronizes JTAG test logic.

TDI Input Test Data Input—A test data serial signal for test instructions and data. TDI is sampled on the rising edge

of TCK and has an internal pull-up resistor.

TDO Output Test Data Output—A test data serial signal for test instructions and data. TDO can be tri-stated. The

signal is actively driven in the shift-IR and shift-DR controller states and changes on the falling edge of

TCK.

TMS Input Test Mode Select—Sequences the test controller state machine, is sampled on the rising edge of TCK,

and has an internal pull-up resistor.

TRST Input Test Reset—Asynchronously initializes the test controller; must be asserted during power up.

Table 1-10. Reserved Signals

Signal Name Type Signal Description

TEST Input Test

For manufacturing testing. You

must

connect this pin to GND.

Table 1-8. Dedicated Ethernet Signals

Signal Name Type Signal Description

MSC8122 Technical Data, Rev. 12

Freescale Semiconductor 2-1

Specifications 2

This document contains detailed informatRev. 12ion on power considerations, DC/AC electrical characteristics,

and AC timing specifications. For additional information, see the MSC8122 User’s Guide and MSC8122 Reference

Manual.

2.1 Maximum Ratings

In calculating timing requirements, adding a maximum value of one specification to a minimum value of another

specification does not yield a reasonable sum. A maximum specification is calculated using a worst case variation

of process parameter values in one direction. The minimum specification is calculated using the worst case for the

same parameters in the opposite direction. Therefore, a “maximum” value for a specification never occurs in the

same device with a “minimum” value for another specification; adding a maximum to a minimum represents a

condition that can never exist.

CAUTION

This device contains circuitry protecting against damage

due to high static voltage or electrical fields; however,

normal precautions should be taken to avoid exceeding

maximum voltage ratings. Reliability is enhanced if unused

inputs are tied to an appropriate logic voltage level (for

example, either GND or VDD).

MSC8122 Technical Data, Rev. 12

2-2 Freescale Semiconductor

Specifications

Tabl e 2 -1 describes the maximum electrical ratings for the MSC8122.

2.2 Recommended Operating Conditions

Tabl e 2 -2 lists recommended operating conditions. Proper device operation outside of these conditions is not

guaranteed.

Table 2-1. Absolute Maximum Ratings

Rating Symbol Value Unit

Core and PLL supply voltage VDD –0.2 to 1.6 V

I/O supply voltage VDDH –0.2 to 4.0 V

Input voltage VIN –0.2 to 4.0 V

Maximum operating temperature:

• Standard range

• Extended range

105

°C

Minimum operating temperature

• Standard range

• Extended range

–40

°C

Storage temperature range TSTG –55 to +150 °C

Notes: 1. Functional operating conditions are given in Table 2-2.

2. Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond

the listed limits may affect device reliability or cause permanent damage.

3. Section 4.5,

Thermal Considerations

includes a formula for computing the chip junction temperature (TJ).

Table 2-2. Recommended Operating Conditions

Rating Symbol Value Unit

Core and PLL supply voltage:

• Standard

— 400 MHz

— 500 MHz

• Reduced (300 and 400 MHz)

VDD

VCCSYN

1.14 to 1.26

1.16 to 1.24

1.07 to 1.13

I/O supply voltage VDDH 3.135 to 3.465 V

Input voltage VIN –0.2 to VDDH+0.2 V

Operating temperature range:

• Standard

• Extended

0 to 90

–40 to 105

°C

Thermal Characteristics

MSC8122 Technical Data, Rev. 12

Freescale Semiconductor 2-3

2.3 Thermal Characteristics

Tabl e 2 -3 describes thermal characteristics of the MSC8122 for the FC-PBGA packages.

Section 4.5, Thermal Considerations provides a detailed explanation of these characteristics.

2.4 DC Electrical Characteristics

This section describes the DC electrical characteristics for the MSC8122. The measurements in Table 2-4 assume

the following system conditions:

•T

A = 25 °C

•VDD =

— 300/400 MHz 1.1 V nominal = 1.07–1.13 VDC

— 400 MHz 1.2 V nominal = 1.14–1.26 VDC

— 500 MHz 1.2 V nominal = 1.16–1.24 VDC

•VDDH = 3.3 V ± 5% VDC

•GND = 0 VDC

Note: The leakage current is measured for nominal VDDH and VDD.

Table 2-3. Thermal Characteristics for the MSC8122

Characteristic Symbol

FC-PBGA

20 × 20 mm5

Unit

Natural

Convection

200 ft/min

(1 m/s) airflow

Junction-to-ambient1, 2 RθJA 26 21 °C/W

Junction-to-ambient, four-layer board1, 3 RθJA 19 15 °C/W

Junction-to-board (bottom)4RθJB 9°C/W

Junction-to-case5RθJC 0.9 °C/W

Junction-to-package-top6Ψ

JT 1°C/W

Notes: 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)

temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal

resistance.

2. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.

3. Per JEDEC JESD51-6 with the board horizontal.

4. Thermal resistance between the die and the printed circuit board per JEDEC JESD 51-8. Board temperature is measured on

the top surface of the board near the package.

5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method

1012.1).

6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature

per JEDEC JESD51-2.

MSC8122 Technical Data, Rev. 12

2-4 Freescale Semiconductor

Specifications

2.5 AC Timings

The following sections include illustrations and tables of clock diagrams, signals, and parallel I/O outputs and

inputs. When systems such as DSP farms are developed using the DSI, use a device loading of 4 pF per pin. AC

timings are based on a 20 pF load, except where noted otherwise, and a 50 Ω transmission line. For loads smaller

than 20 pF, subtract 0.06 ns per pF down to 10 pF load. For loads larger than 20 pF, add 0.06 ns for

SIU/Ethernet/DSI delay and 0.07 ns for GPIO/TDM/timer delay. When calculating overall loading, also consider

additional RC delay.

Table 2-4. DC Electrical Characteristics

Characteristic Symbol Min Typical Max Unit

Input high voltage1, all inputs except CLKIN VIH 2.0 — 3.465 V

Input low voltage1VIL GND 0 0.4 V

CLKIN input high voltage VIHC 2.4 3.0 3.465 V

CLKIN input low voltage VILC GND 0 0.4 V

Input leakage current, VIN = VDDH IIN –1.0 0.09 1 µA

Tri-state (high impedance off state) leakage current, VIN = VDDH IOZ –1.0 0.09 1 µA

Signal low input current, VIL = 0.4 V2IL–1.0 0.09 1 µA

Signal high input current, VIH = 2.0 V2IH–1.0 0.09 1 µA

Output high voltage, IOH = –2 mA,

except open drain pins

VOH 2.0 3.0 — V

Output low voltage, IOL= 3.2 mA VOL —00.4V

Internal supply current:

• Wait mode

• Stop mode

IDDW

IDDS

—

3753

2903

—

Typical power 400 MHz at 1.2 V4P — 1.15 — W

Notes: 1. See Figure 2-1 for undershoot and overshoot voltages.

2. Not tested. Guaranteed by design.

3. Measured for 1.2 V core at 25°C junction temperature.

4. The typical power values were measured using an EFR code with the device running at a junction temperature of 25°C. No

peripherals were enabled and the ICache was not enabled. The source code was optimized to use all the ALUs and AGUs and

all four cores. It was created using CodeWarrior® 2.5. These values are provided as examples only. Power consumption is

application dependent and varies widely. To assure proper board design with regard to thermal dissipation and maintaining

proper operating temperatures, evaluate power consumption for your application and use the design guidelines in Chapter 4 of

this document and in

MSC8102, MSC8122, and MSC8126 Thermal Management Design Guidelines

(AN2601).

Figure 2-1. Overshoot/Undershoot Voltage for VIH and VIL

GND

GND – 0.3 V

GND – 0.7 V

VIL

VIH

Must not exceed 10% of clock period

VDDH + 17%

VDDH + 8%

VDDH

AC Timings

MSC8122 Technical Data, Rev. 12

Freescale Semiconductor 2-5

2.5.1 Output Buffer Impedances

2.5.2 Start-Up Timing

Starting the device requires coordination among several input sequences including clocking, reset, and power.

Section 2.5.3 describes the clocking characteristics. Section 2.5.4 describes the reset and power-up characteristics.

You must use the following guidelines when starting up an MSC8122 device:

•PORESET and TRST must be asserted externally for the duration of the power-up sequence. See Table 2-10

for timing.

• If possible, bring up the VDD and VDDH levels together. For designs with separate power supplies, bring up

the VDD levels and then the VDDH levels (see Figure 2-3).

•CLKIN should start toggling at least 16 cycles (starting after VDDH reaches its nominal level) before

PORESET deassertion to guarantee correct device operation (see Figure 2-2 and Figure 2-3).

•CLKIN must not be pulled high during VDDH power-up. CLKIN can toggle during this period.

The following figures show acceptable start-up sequence examples. Figure 2-2 shows a sequence in which VDD and

VDDH are raised together. Figure 2-3 shows a sequence in which VDDH is raised after VDD and CLKIN begins to toggle

as VDDH rises.

Table 2-5. Output Buffer Impedances

Output Buffers Typical Impedance (Ω)

System bus 50

Memory controller 50

Parallel I/O 50

Note: These are typical values at 65°C. The impedance may vary by ±25% depending on device process and operating temperature.

Figure 2-2. Start-Up Sequence with VDD and VDDH Raised Together

Voltage

Time

o.5 V

3.3 V

1.2 V

VDDH Nominal Level

PORESET/TRST Asserted

VDD Nominal Level

CLKIN Starts Toggling

VDD/VDDH Applied

PORESET/TRST Deasserted

2.2 V

VDDH = Nominal Value

VDD = Nominal Value

MSC8122 Technical Data, Rev. 12

2-6 Freescale Semiconductor

Specifications

2.5.3 Clock and Timing Signals

The following sections include a description of clock signal characteristics. Tab le 2-6 shows the maximum

frequency values for internal (Core, Reference, Bus, and DSI) and external (CLKIN and CLKOUT) clocks. The user

must ensure that maximum frequency values are not exceeded.

Figure 2-3. Start-Up Sequence with VDD Raised Before VDDH with CLKIN Started with VDDH

Table 2-6. Maximum Frequencies

Characteristic Maximum in MHz

Core frequency 300/400/500

Reference frequency (REFCLK) 100/133/166

Internal bus frequency (BLCK) 100/133/166

DSI clock frequency (HCLKIN)

• Core frequency = 300 MHz

• Core frequency = 400/500 MHz

HCLKIN ≤ (min{70 MHz, CLKOUT})

HCLKIN ≤ (min{100 MHz, CLKOUT})

External clock frequency (CLKIN or CLKOUT) 100/133/166

Table 2-7. Clock Frequencies

Characteristics Symbol

300 MHz Device 400 MHz Device 500 MHz Device

Min Max Min Max Min Max

CLKIN frequency FCLKIN 20 100 20 133.3 20 166.7

BCLK frequency FBCLK 40 100 40 133.3 40 166.7

Reference clock (REFCLK) frequency FREFCLK 40 100 40 133.3 40 166.7

Output clock (CLKOUT) frequency FCLKOUT 40 100 40 133.3 40 166.7

SC140 core clock frequency FCORE 200 300 200 400 200 500

Note: The rise and fall time of external clocks should be 3 ns maximum

Table 2-8. System Clock Parameters

Characteristic Min Max Unit

Phase jitter between BCLK and CLKIN — 0.3 ns

CLKIN frequency 20 see Table 2-7 MHz

CLKIN slope —3ns

PLL input clock (after predivider) 20 100 MHz

Voltage

Time

o.5 V

3.3 V

1.2 V

VDDH Nominal

PORESET/TRST asserted

VDD Nominal

CLKIN starts toggling

VDD applied PORESET/TRST deasserted

VDDH applied

VDDH = Nominal

VDD = Nominal

AC Timings

MSC8122 Technical Data, Rev. 12

Freescale Semiconductor 2-7

2.5.4 Reset Timing

The MSC8122 has several inputs to the reset logic:

• Power-on reset (PORESET)

• External hard reset (HRESET)

• External soft reset (SRESET)

• Software watchdog reset

• Bus monitor reset

• Host reset command through JTAG

All MSC8122 reset sources are fed into the reset controller, which takes different actions depending on the source

of the reset. The reset status register indicates the most recent sources to cause a reset. Table 2-9 describes the reset

sources.

Table 2-10 summarizes the reset actions that occur as a result of the different reset sources.

PLL output frequency (VCO output)

• 300 MHz core

• 400 MHz core

• 500 MHz core

800

1200

1600

2000

MHz

CLKOUT frequency jitter1— 200 ps

CLKOUT phase jitter1 with CLKIN phase jitter of ±100 ps. — 500 ps

Notes: 1. Peak-to-peak.

2. Not tested. Guaranteed by design.

Table 2-9. Reset Sources

Name Direction Description

Power-on reset

(PORESET)

Input Initiates the power-on reset flow that resets the MSC8122 and configures various attributes of the

MSC8122. On PORESET, the entire MSC8122 device is reset. SPLL states is reset, HRESET and

SRESET are driven, the SC140 extended cores are reset, and system configuration is sampled. The

clock mode (MODCK bits), reset configuration mode, boot mode, Chip ID, and use of either a DSI 64

bits port or a System Bus 64 bits port are configured only when PORESET is asserted.

External hard

reset (HRESET)

Input/ Output Initiates the hard reset flow that configures various attributes of the MSC8122. While HRESET is

asserted, SRESET is also asserted. HRESET is an open-drain pin. Upon hard reset, HRESET and

SRESET are driven, the SC140 extended cores are reset, and system configuration is sampled. The

most configurable features are reconfigured. These features are defined in the 32-bit hard reset

configuration word described in

Hard Reset Configuration Word

section of the

Reset

chapter in the

MSC8122 Reference Manual

External soft reset

(SRESET)

Input/ Output Initiates the soft reset flow. The MSC8122 detects an external assertion of SRESET only if it occurs

while the MSC8122 is not asserting reset. SRESET is an open-drain pin. Upon soft reset, SRESET is

driven, the SC140 extended cores are reset, and system configuration is maintained.

Software

watchdog reset

Internal When the MSC8122 watchdog count reaches zero, a software watchdog reset is signalled. The

enabled software watchdog event then generates an internal hard reset sequence.

Bus monitor reset Internal When the MSC8122 bus monitor count reaches zero, a bus monitor hard reset is asserted. The

enabled bus monitor event then generates an internal hard reset sequence.

Host reset

command through

the TAP

Internal When a host reset command is written through the Test Access Port (TAP), the TAP logic asserts the

soft reset signal and an internal soft reset sequence is generated.

Table 2-8. System Clock Parameters

Characteristic Min Max Unit

MSC8122 Technical Data, Rev. 12

2-8 Freescale Semiconductor

Specifications

2.5.4.1 Power-On Reset (PORESET) Pin

Asserting PORESET initiates the power-on reset flow. PORESET must be asserted externally for at least 16 CLKIN

cycles after VDD and VDDH are both at their nominal levels.

2.5.4.2 Reset Configuration

The MSC8122 has two mechanisms for writing the reset configuration:

• Through the direct slave interface (DSI)

• Through the system bus. When the reset configuration is written through the system bus, the MSC8122

acts as a configuration master or a configuration slave. If configuration slave is selected, but no special

configuration word is written, a default configuration word is applied.

Fourteen signal levels (see Chapter 1 for signal description details) are sampled on PORESET deassertion to define

the Reset Configuration Mode and boot and operating conditions:

•RSTCONF

•CNFGS

•DSISYNC

•DSI64

•CHIP_ID[0–3]

•BM[0–2]

•SWTE

•MODCK[1–2]

Table 2-10. Reset Actions for Each Reset Source

Reset Action/Reset Source

Power-On

Reset

(PORESET)

Hard Reset (HRESET) Soft Reset (SRESET)

External only

External or Internal

(Software Watchdog or

Bus Monitor)

External

JTAG Command:

EXTEST, CLAMP, or

HIGHZ

Configuration pins sampled (Refer to

Section 2.5.4.1 for details).

Yes NoNoNo

SPLL state reset Yes No No No

System reset configuration write through

the DSI

Yes NoNoNo

System reset configuration write though

the system bus

Yes Yes No No

HRESET driven Yes Yes No No

SIU registers reset Yes Yes No No

IPBus modules reset (TDM, UART,

Timers, DSI, IPBus master, GIC, HS, and

GPIO)

Yes Yes Yes Yes

SRESET driven Yes Yes Yes Depends on command

SC140 extended cores reset Yes Yes Yes Yes

MQBS reset Yes Yes Yes Yes

AC Timings

MSC8122 Technical Data, Rev. 12

Freescale Semiconductor 2-9

2.5.4.3 Reset Timing Tables

Table 2-11 and Figure 2-4 describe the reset timing for a reset configuration write through the direct slave

interface (DSI) or through the system bus.

Table 2-11. Timing for a Reset Configuration Write through the DSI or System Bus

No. Characteristics Expression Min Max Unit

1 Required external PORESET duration minimum

• CLKIN = 20 MHz

• CLKIN = 100 MHz (300 MHz core)

• CLKIN = 133 MHz (400 MHz core)

• CLKIN = 166 MHz (500 MHz core)

16/CLKIN

800

160

120

—

2 Delay from deassertion of external PORESET to deassertion of internal

PORESET

• CLKIN = 20 MHz to 166 MHz

1024/CLKIN

6.17 51.2 µs

3 Delay from de-assertion of internal PORESET to SPLL lock

• CLKIN = 20 MHz (RDF = 1)

• CLKIN = 100 MHz (RDF = 1) (300 MHz core)

• CLKIN = 133 MHz (RDF = 2) (400 MHz core)

• CLKIN = 166 MHz (RDF = 2) (500 MHz core)

6400/(CLKIN/RDF)

(PLL reference clock-

division factor)

320

µs

5 Delay from SPLL to HRESET deassertion

• REFCLK = 40 MHz to 166 MHz 512/REFCLK 3.08 12.8 µs

6 Delay from SPLL lock to SRESET deassertion

• REFCLK = 40 MHz to 166 MHz

515/REFCLK

3.10 12.88 µs

7 Setup time from assertion of RSTCONF, CNFGS, DSISYNC, DSI64,

CHIP_ID[0–3], BM[0–2], SWTE, and MODCK[1–2] before deassertion of

PORESET

3—ns

8 Hold time from deassertion of PORESET to deassertion of RSTCONF,

CNFGS, DSISYNC, DSI64, CHIP_ID[0–3], BM[0–2], SWTE, and

MODCK[1–2]

5—ns

Note: Timings are not tested, but are guaranteed by design.

Figure 2-4. Timing Diagram for a Reset Configuration Write

PORESET

Internal

HRESET

Input

Output (I/O)

SRESET

Output (I/O)

RSTCONF, CNFGS, DSISYNC, DSI64

CHIP_ID[0–3], BM[0–2], SWTE, MODCK[1–2]

Host programs

Word

SPLL is locked

(no external indication)

PORESET

Reset Configuration

pins are sampled

MODCK[3–5]

1 + 2

SPLL

locking period

Reset configuration write

sequence during this

period.

MSC8122 Technical Data, Rev. 12

2-10 Freescale Semiconductor

Specifications

2.5.5 System Bus Access Timing

2.5.5.1 Core Data Transfers

Generally, all MSC8122 bus and system output signals are driven from the rising edge of the reference clock

(REFCLK). The REFCLK is the CLKIN signal. Memory controller signals, however, trigger on four points within a

REFCLK cycle. Each cycle is divided by four internal ticks: T1, T2, T3, and T4. T1 always occurs at the rising

edge of REFCLK (and T3 at the falling edge), but the spacing of T2 and T4 depends on the PLL clock ratio

selected, as Table 2-12 shows.

Figure 2-5 is a graphical representation of Table 2-12.

Table 2-12. Tick Spacing for Memory Controller Signals

BCLK/SC140 clock

Tick Spacing (T1 Occurs at the Rising Edge of REFCLK)

T2 T3 T4

1:4, 1:6, 1:8, 1:10 1/4 REFCLK 1/2 REFCLK 3/4 REFCLK

1:3 1/6 REFCLK 1/2 REFCLK 4/6 REFCLK

1:5 2/10 REFCLK 1/2 REFCLK 7/10 REFCLK

Figure 2-5. Internal Tick Spacing for Memory Controller Signals

REFCLK

T1 T2 T3 T4

REFCLK

T1 T2 T3 T4

for 1:3

for 1:5

REFCLK

T1 T2 T3 T4

for 1:4, 1:6, 1:8, 1:10

AC Timings

MSC8122 Technical Data, Rev. 12

Freescale Semiconductor 2-11

The UPM machine and GPCM machine outputs change on the internal tick selected by the memory controller

configuration. The AC timing specifications are relative to the internal tick. SDRAM machine outputs change only

on the REFCLK rising edge.

Table 2-13. AC Timing for SIU Inputs

No. Characteristic

Value for Bus Speed in MHz

Units

Ref = CLKIN Ref = CLKOUT

1.1 V 1.2 V 1.2 V 1.2 V

100/

133 133 166 133

10 Hold time for all signals after the 50% level of the REFCLK rising edge 0.5 0.5 0.5 0.5 ns

11a ARTRY/ABB set-up time before the 50% level of the REFCLK rising

edge

3.1 3.0 3.0 3.0 ns

11b DBG/DBB/BG/BR/TC set-up time before the 50% level of the

REFCLK rising edge

3.6 3.3 3.3 3.3 ns

11c AACK set-up time before the 50% level of the REFCLK rising edge 3.0 2.9 2.9 2.9 ns

11d TA/TEA/PSDVAL set-up time before the 50% level of the REFCLK

rising edge

• Data-pipeline mode

• Non-pipeline mode

3.5

4.4

3.4

4.0

3.4

4.0

3.4

4.0

12 Data bus set-up time before REFCLK rising edge in Normal mode

• Data-pipeline mode

• Non-pipeline mode

1.9

4.2

1.8

4.0

1.7

4.0

1.8

4.0

131Data bus set-up time before the 50% level of the REFCLK rising edge

in ECC and PARITY modes

• Data-pipeline mode

• Non-pipeline mode

2.0

8.2

2.0

7.3

2.0

7.3

2.0

7.3

141DP set-up time before the 50% level of the REFCLK rising edge

• Data-pipeline mode

• Non-pipeline mode

2.0

7.9

2.0

6.1

2.0

6.1

2.0

6.1

15a TS and Address bus set-up time before the 50% level of the REFCLK

rising edge

• Extra cycle mode (SIUBCR[EXDD] = 0)

• No extra cycle mode (SIUBCR[EXDD] = 1)

4.2

5.5

3.8

5.0

3.8

5.0

3.8

5.0

15b Address attributes: TT/TBST/TSZ/GBL set-up time before the 50%

level of the REFCLK rising edge

• Extra cycle mode (SIUBCR[EXDD] = 0)

• No extra cycle mode (SIUBCR[EXDD] = 1)

3.7

4.8

3.5

4.4

3.5

4.4

3.5

4.4

16 PUPMWAIT signal set-up time before the 50% level of the REFCLK

rising edge

3.7 3.7 3.7 3.7 ns

Notes: 1. Timings specifications 13 and 14 in non-pipeline mode are more restrictive than MSC8102 timings.

2. Values are measured from the 50% TTL transition level relative to the 50% level of the REFCLK rising edge.

MSC8122 Technical Data, Rev. 12

2-12 Freescale Semiconductor

Specifications

Table 2-14. AC Timing for SIU Outputs

No. Characteristic

Value for Bus Speed in MHz3

Units

Ref = CLKIN Ref = CLKOUT

1.1 V 1.2 V 1.2 V 1.2 V

100/

133 133 166 100/133

302Minimum delay from the 50% level of the REFCLK for all signals 0.9 0.8 0.8 1.0 ns

31 PSDVAL/TEA/TA max delay from the 50% level of the REFCLK

rising edge

6.0 4.9 4.9 5.8 ns

32a Address bus max delay from the 50% level of the REFCLK rising

edge

• Multi-master mode (SIUBCR[EBM] = 1)

• Single-master mode (SIUBCR[EBM] = 0)

6.4

5.3

5.5

4.2

5.5

3.9

6.4

5.1

32b Address attributes: TT[0–1]/TBST/TSZ/GBL max delay from the 50%

level of the REFCLK rising edge

6.4 5.1 5.1 6.0 ns

32c Address attributes: TT[2–4]/TC max delay from the 50% level of the

REFCLK rising edge

6.9 5.7 5.7 6.6 ns

32d BADDR max delay from the 50% level of the REFCLK rising edge 5.2 4.2 4.2 5.1 ns

33a Data bus max delay from the 50% level of the REFCLK rising edge

• Data-pipeline mode

• Non-pipeline mode

4.8

7.1

3.9

6.1

3.7

6.1

4.8

7.0

33b DP max delay from the 50% level of the REFCLK rising edge

• Data-pipeline mode

• Non-pipeline mode

6.0

7.5

5.3

6.5

5.3

6.5

6.2

7.4

34 Memory controller signals/ALE/CS[0–4] max delay from the 50%

level of the REFCLK rising edge

5.1 4.2 3.9 5.1 ns

35a DBG/BG/BR/DBB max delay from the 50% level of the REFCLK

rising edge

6.0 4.7 4.7 5.6 ns

35b AACK/ABB/TS/CS[5–7] max delay from the 50% level of the

REFCLK rising edge

5.5 4.5 4.5 5.4 ns

Notes: 1. Values are measured from the 50% level of the REFCLK rising edge to the 50% signal level and assume a 20 pF load except

where otherwise specified.

2. The load for specification 30 is 10 pF. The load for the other specifications in this table is 20 pF. For a 15 pF load, subtract 0.3

ns from the listed value.

3. The maximum bus frequency depends on the mode:

• In 60x-compatible mode connected to another MSC8122 device, the frequency is determined by adding the input and output

longest timing values, which results in the total delay for 20 pF output capacitance. You must also account for other

influences that can affect timing, such as on-board clock skews, on-board noise delays, and so on.

• In single-master mode, the frequency depends on the timing of the devices connected to the MSC8122.

• To achieve maximum performance on the bus in single-master mode, disable the DBB signal by writing a 1 to the

SIUMCR[BDD] bit. See the SIU chapter in the

MSC8122 Reference Manual

for details.

AC Timings

MSC8122 Technical Data, Rev. 12

Freescale Semiconductor 2-13

Figure 2-6. Bus Signal Timing

REFCLK

AACK/ARTRY/TA/TEA/DBG/BG/BR

Data bus inputs—normal mode

PUPMWAIT input

PSDVAL/TEA/TA outputs

Address bus/TT[0–4]/TC[0–2]/TBST/TSZ[0–3]/GBL outputs

Data bus outputs

Min delay for all output pins

32a/b

33a

DP outputs 33b

Memory controller/ALE outputs 34

Data bus inputs—ECC and parity modes

AACK/ABB/TS/DBG/BG/BR/DBB/CS outputs

BADDR outputs 32c

DP inputs 14

Address bus/TS /TT[0–4]/TC[0–2]/

PSDVAL/ABB/DBB inputs

TBST/TSZ[0–3]/GBL inputs

MSC8122 Technical Data, Rev. 12

2-14 Freescale Semiconductor

Specifications

2.5.5.2 CLKIN to CLKOUT Skew

Table 2-16 describes the CLKOUT-to-CLKIN skew timing.

For designs that use the CLKOUT synchronization mode, use the skew values listed in Table 2-15 to adjust the rise-

to-fall timing values specified for CLKIN synchronization. Figure 2-7 shows the relationship between the CLKOUT

and CLKIN timings.

Table 2-15. CLKOUT Skew

No. Characteristic Min1Max1Units

20 Rise-to-rise skew

•V

DD = 1.1 V

•V

DD = 1.2 V

0.0

0.95

0.85

21 Fall-to-fall skew

•V

DD = 1.1 V

•V

DD = 1.2 V

–1.5

–0.8

1.0

22 CLKOUT phase (1.2 V, 133 MHz)

• Phase high

• Phase low

2.8

—

23 CLKOUT phase (1.1 V, 133 MHz)

• Phase high

• Phase low

2.2

—

24 CLKOUT phase (1.1 V, 100 MHz)

• Phase high

• Phase low

3.3

—

Notes: 1. A positive number indicates that CLKOUT precedes CLKIN, A negative number indicates that CLKOUT follows CLKIN.

2. Skews are measured in clock mode 29, with a CLKIN:CLKOUT ratio of 1:1. The same skew is valid for all clock modes.

3. CLKOUT skews are measured using a load of 10 pF.

4. CLKOUT skews and phase are not measured for 500/166 Mhz parts because these parts only use CLKIN mode.

Figure 2-7. CLKOUT and CLKIN Signals.

CLKIN

CLKOUT

20 21

AC Timings

MSC8122 Technical Data, Rev. 12

Freescale Semiconductor 2-15

2.5.5.3 DMA Data Transfers

Table 2-16 describes the DMA signal timing.

The DREQ signal is synchronized with REFCLK. To achieve fast response, a synchronized peripheral should assert

DREQ according to the timings in Table 2-16. Figure 2-8 shows synchronous peripheral interaction.

Table 2-16. DMA Signals

No. Characteristic Ref = CLKIN Ref = CLKOUT

(1.2 V only) Units

Min Max Min Max

37 DREQ set-up time before the 50% level of the falling edge of REFCLK 5.0 — 5.0 — ns

38 DREQ hold time after the 50% level of the falling edge of REFCLK 0.5 — 0.5 — ns

39 DONE set-up time before the 50% level of the rising edge of REFCLK 5.0 — 5.0 — ns

40 DONE hold time after the 50% level of the rising edge of REFCLK 0.5 — 0.5 — ns

41 DACK/DRACK/DONE delay after the 50% level of the REFCLK rising edge 0.5 7.5 0.5 8.4 ns

Figure 2-8. DMA Signals

REFCLK

DREQ

DONE

DACK/DONE/DRACK

MSC8122 Technical Data, Rev. 12

2-16 Freescale Semiconductor

Specifications

2.5.6 DSI Timing

The timings in the following sections are based on a 20 pF capacitive load.

2.5.6.1 DSI Asynchronous Mode

Table 2-17. DSI Asynchronous Mode Timing

No. Characteristics Min Max Unit

100 Attributes1 set-up time before strobe (HWBS[n]) assertion 1.5 — ns

101 Attributes1 hold time after data strobe deassertion 1.3 — ns

102 Read/Write data strobe deassertion width:

• DCR[HTAAD] = 1

— Consecutive access to the same DSI

— Different device with DCR[HTADT] = 01

— Different device with DCR[HTADT] = 10

— Different device with DCR[HTADT] = 11

• DCR[HTAAD] = 0

1.8 + TREFCLK

5 + TREFCLK

5 + (1.5 × TREFCLK)

5 + (2.5 × TREFCLK)

1.8 + TREFCLK

—

103 Read data strobe deassertion to output data high impedance — 8.5 ns

104 Read data strobe assertion to output data active from high impedance 2.0 — ns

105 Output data hold time after read data strobe deassertion 2.2 — ns

106 Read/Write data strobe assertion to HTA active from high impedance 2.2 — ns

107 Output data valid to HTA assertion 3.2 — ns

108 Read/Write data strobe assertion to HTA valid2

•1.1 V core

•1.2 V core

—

7.4

6.7

109 Read/Write data strobe deassertion to output HTA high impedance.

(DCR[HTAAD] = 0, HTA at end of access released at logic 0)

—6.5ns

110 Read/Write data strobe deassertion to output HTA deassertion.

(DCR[HTAAD] = 1, HTA at end of access released at logic 1)

—6.5ns

111 Read/Write data strobe deassertion to output HTA high impedance.

(DCR[HTAAD] = 1, HTA at end of access released at logic 1

• DCR[HTADT] = 01

• DCR[HTADT] = 10

• DCR[HTADT] = 11

—

5 + TREFCLK

5 + (1.5 × TREFCLK)

5 + (2.5 × TREFCLK)

112 Read/Write data strobe assertion width 1.8 + TREFCLK —ns

201 Host data input set-up time before write data strobe deassertion 1.0 — ns

202 Host data input hold time after write data strobe deassertion

•1.1 V core

•1.2 V core

1.7

1.5

—

Notes: 1.

Attributes

refers to the following signals: HCS, HA[11–29], HCID[0–4], HDST, HRW, HRDS, and HWBSn.

2. This specification is tested in dual-strobe mode. Timing in single-strobe mode is guaranteed by design.

3. All values listed in this table are tested or guaranteed by design.

AC Timings

MSC8122 Technical Data, Rev. 12

Freescale Semiconductor 2-17

Figure 2-9 shows DSI asynchronous read signals timing.

Figure 2-9. Asynchronous Single- and Dual-Strobe Modes Read Timing Diagram

HDBSn1

HA[11–29]

HCS

HD[0–63]

102

100

105

101

103

104

109

108

106

HTA4

HCID[0–4]

HDST

HTA3

107

110

111

112

HRW1

HWBSn2

HRDS2

Notes: 1. Used for single-strobe mode access.

2. Used for dual-strobe mode access.

3. HTA released at logic 0 (DCR[HTAAD] = 0) at end of access; used with pull-

down implementation.

4. HTA released at logic 1 (DCR[HTAAD] = 1) at end of access; used with pull-up

implementation.

MSC8122 Technical Data, Rev. 12

2-18 Freescale Semiconductor

Specifications

Figure 2-10 shows DSI asynchronous write signals timing.

Figure 2-11 shows DSI asynchronous broadcast write signals timing.

Figure 2-10. Asynchronous Single- and Dual-Strobe Modes Write Timing Diagram

Figure 2-11. Asynchronous Broadcast Write Timing Diagram

HD[0–63]

100 101

102

201

202

109

106

HWBSn2

108 110

111

112

HDBSn1

HTA4

HTA3

Notes: 1. Used for single-strobe mode access.

2. Used for dual-strobe mode access.

3. HTA released at logic 0 (DCR[HTAAD] = 0) at end of access; used with pull-down implementation.

4. HTA released at logic 1 (DCR[HTAAD] = 1) at end of access; used with pull-up implementation.

HA[11–29]

HCS

HCID[0–4]

HDST

HRW1

HRDS2

HD[0–63]

100 101

102

201

202

HWBSn2

112

HDBSn1

Notes: 1. Used for single-strobe mode access.

2. Used for dual-strobe mode access.

HA[11–29]

HCS

HCID[0–4]

HDST

HRW1

HRDS2

AC Timings

MSC8122 Technical Data, Rev. 12

Freescale Semiconductor 2-19

2.5.6.2 DSI Synchronous Mode

Table 2-18. DSI Inputs in Synchronous Mode

No. Characteristic Expression 1.1 V Core 1.2 V Core Units

Min Max Min Max

120 HCLKIN cycle time1,2 HTC 10.0 55.6 10.0 55.6 ns

121 HCLKIN high pulse width (0.5 ± 0.1) × HTC 4.0 33.3 4.0 33.3 ns

122 HCLKIN low pulse width (0.5 ± 0.1) × HTC 4.0 33.3 4.0 33.3 ns

123 HA[11–29] inputs set-up time — 1.2 — 1.2 — ns

124 HD[0–63] inputs set-up time — 0.6 — 0.4 — ns

125 HCID[0–4] inputs set-up time — 1.3 — 1.3 — ns

126 All other inputs set-up time — 1.2 — 1.2 — ns

127 All inputs hold time — 1.5 — 1.5 — ns

Notes: 1. Values are based on a frequency range of 18–100 MHz.

2. Refer to Table 2-6 for HCLKIN frequency limits.

Table 2-19. DSI Outputs in Synchronous Mode

No. Characteristic 1.1 V Core 1.2 V Core Units

Min Max Min Max

128 HCLKIN high to HD[0–63] output active 2.0 — 2.0 — ns

129 HCLKIN high to HD[0–63] output valid — 7.6 — 6.3 ns

130 HD[0–63] output hold time 1.7 — 1.7 — ns

131 HCLKIN high to HD[0–63] output high impedance — 8.3 — 7.6 ns

132 HCLKIN high to HTA output active 2.2 — 2.0 — ns

133 HCLKIN high to HTA output valid — 7.4 — 5.9 ns

134 HTA output hold time 1.7 — 1.7 — ns

135 HCLKIN high to HTA high impedance — 7.5 — 6.3 ns

Figure 2-12. DSI Synchronous Mode Signals Timing Diagram

HCLKIN

HA[11–29] input signals

All other input signals

HD[0–63] output signals

HTA output signal

HD[0–63] input signals

120

127

123

126 127

122

121

131

130

129

128

133 135

134

132

HCID[0–4] input signals

125 127

127

124

MSC8122 Technical Data, Rev. 12

2-20 Freescale Semiconductor

Specifications

2.5.7 TDM Timing

Table 2-20. TDM Timing

No. Characteristic Expression 1.1 V Core 1.2 V Core Units

Min Max Min Max

300 TDMxRCLK/TDMxTCLK TC116 — 16 — ns

301 TDMxRCLK/TDMxTCLK high pulse width (0.5 ± 0.1) × TC7—7—ns

302 TDMxRCLK/TDMxTCLK low pulse width (0.5 ± 0.1) × TC7—7—ns

303 TDM receive all input set-up time 1.3 — 1.3 — ns

304 TDM receive all input hold time 1.0 — 1.0 — ns

305 TDMxTCLK high to TDMxTDAT/TDMxRCLK output

active2,3

2.8 — 2.8 — ns

306 TDMxTCLK high to TDMxTDAT/TDMxRCLK output — 10.0 — 8.8 ns

307 All output hold time42.5 — 2.5 — ns

308 TDMxTCLK high to TDmXTDAT/TDMxRCLK output high

impedance2,3

— 10.7 — 10.5 ns

309 TDMxTCLK high to TDMXTSYN output valid2—9.7—8.5ns

310 TDMxTSYN output hold time42.5 — 2.5 — ns

Notes: 1. Values are based on a a maximum frequency of 62.5 MHz. The TDM interface supports any frequency below 62.5 MHz.

Devices operating at 300 MHz are limited to a maximum TDMxRCLK/TDMxTCLK frequency of 50 MHz.

2. Values are based on 20 pF capacitive load.

3. When configured as an output, TDMxRCLK acts as a second data link. See the

MSC8122 Reference Manual

for details.

4. Values are based on 10 pF capacitive load.

Figure 2-13. TDM Inputs Signals

Figure 2-14. TDM Output Signals

TDMxRCLK

TDMxRDAT

TDMxRSYN

300

301 302

303

304

TDMxTCLK

TDMxTDAT

TDMxTSYN

305

306 308

307

300

301 302

310

309

TDMxRCLK

AC Timings

MSC8122 Technical Data, Rev. 12

Freescale Semiconductor 2-21

2.5.8 UART Timing

Table 2-21. UART Timing

No. Characteristics Expression Min Max Un

400 URXD and UTXD inputs high/low duration 16 × TREFCLK 160.0 — ns

401 URXD and UTXD inputs rise/fall time 10 ns

402 UTXD output rise/fall time 10 ns

Figure 2-15. UART Input Timing

Figure 2-16. UART Output Timing

UTXD, URXD

400

inputs

400

401 401

UTXD output

402 402

MSC8122 Technical Data, Rev. 12

2-22 Freescale Semiconductor

Specifications

2.5.9 Timer Timing

2.5.10 Ethernet Timing

2.5.10.1 Management Interface Timing

Table 2-22. Timer Timing

No. Characteristics Ref = CLKIN Unit

Min Max

500 TIMERx frequency 10.0 — ns

501 TIMERx Input high period 4.0 — ns

502 TIMERx Output low period 4.0 — ns

503 TIMERx Propagations delay from its clock input

•1.1 V core

•1.2 V core

3.1

2.8

9.5

8.1

Figure 2-17. Timer Timing

Table 2-23. Ethernet Controller Management Interface Timing

No. Characteristics Min Max Unit

801 ETHMDIO to ETHMDC rising edge set-up time 10 — ns

802 ETHMDC rising edge to ETHMDIO hold time 10 — ns

Figure 2-18. MDIO Timing Relationship to MDC

500

502

501

TIMERx (Input)

TIMERx (Output)

503

Valid

ETHMDC

ETHMDIO

802

801

AC Timings

MSC8122 Technical Data, Rev. 12

Freescale Semiconductor 2-23

2.5.10.2 MII Mode Timing

2.5.10.3 RMII Mode

Table 2-24. MII Mode Signal Timing

No. Characteristics Min Max Unit

803 ETHRX_DV, ETHRXD[0–3], ETHRX_ER to ETHRX_CLK rising edge set-up time 3.5 — ns

804 ETHRX_CLK rising edge to ETHRX_DV, ETHRXD[0–3], ETHRX_ER hold time 3.5 — ns

805 ETHTX_CLK to ETHTX_EN, ETHTXD[0–3], ETHTX_ER output delay

•1.1 V core

•1.2 V core

14.6

12.6

Figure 2-19. MII Mode Signal Timing

Table 2-25. RMII Mode Signal Timing

No. Characteristics 1.1 V Core 1.2 V Core Unit

Min Max Min Max

806 ETHTX_EN,ETHRXD[0–1], ETHCRS_DV, ETHRX_ER to ETHREF_CLK rising

edge set-up time

1.6 — 2 — ns

807 ETHREF_CLK rising edge to ETHRXD[0–1], ETHCRS_DV, ETHRX_ER hold

time

1.6 — 1.6 — ns

811 ETHREF_CLK rising edge to ETHTXD[0–1], ETHTX_EN output delay. 3 12.5 3 11 ns

Figure 2-20. RMII Mode Signal Timing

Valid

ETHRX_CLK

ETHRX_DV

ETHRXD[0–3]

ETHTX_CLK

ETHRX_ER

ETHTX_EN

ETHTXD[0–3] Valid Valid

ETHTX_ER

803 804

805

Valid

ETHREF_CLK

ETHCRS_DV

ETHRXD[0–1]

ETHRX_ER

807

806

ETHTX_EN

ETHTXD[0–1] Valid Valid

811

MSC8122 Technical Data, Rev. 12

2-24 Freescale Semiconductor

Specifications

2.5.10.4 SMII Mode

2.5.11 GPIO Timing

Table 2-26. SMII Mode Signal Timing

No. Characteristics Min Max Unit

808 ETHSYNC_IN, ETHRXD to ETHCLOCK rising edge set-up time 1.0 — ns

809 ETHCLOCK rising edge to ETHSYNC_IN, ETHRXD hold time 1.0 — ns

810 ETHCLOCK rising edge to ETHSYNC, ETHTXD output delay

• 1.1 V core.

• 1.2 V core.

1.51

6.02

5.02

Notes: 1. Measured using a 5 pF load.

2. Measured using a 15 pF load.

Figure 2-21. SMII Mode Signal Timing

Table 2-27. GPIO Timing

No. Characteristics Ref = CLKIN Ref = CLKOUT

(1.2 V only) Unit

Min Max Min Max

601 REFCLK edge to GPIO out valid (GPIO out delay time) — 6.1 — 6.9 ns

602 REFCLK edge to GPIO out not valid (GPIO out hold time) 1.1 — 1.3 — ns

603 REFCLK edge to high impedance on GPIO out — 5.4 — 6.2 ns

604 GPIO in valid to REFCLK edge (GPIO in set-up time) 3.5 — 3.7 — ns

605 REFCLK edge to GPIO in not valid (GPIO in hold time) 0.5 — 0.5 — ns

Valid

ETHCLOCK

ETHSYNC_IN

ETHRXD

ETHSYNC

ETHTXD Valid Valid

810

809808

AC Timings

MSC8122 Technical Data, Rev. 12

Freescale Semiconductor 2-25

2.5.12 EE Signals

Figure 2-23 shows the signal behavior of the EE pins.

2.5.13 JTAG Signals

Figure 2-22. GPIO Timing

Table 2-28. EE Pin Timing

Number Characteristics Type Min

65 EE0 (input) Asynchronous 4 core clock periods

66 EE1 (output) Synchronous to Core clock 1 core clock period

Notes: 1. The core clock is the SC140 core clock. The ratio between the core clock and CLKOUT is configured during power-on-reset.

2. Refer to Table 1-4 on page 1-6 for details on EE pin functionality.

Figure 2-23. EE Pin Timing

Table 2-29. JTAG Timing

No. Characteristics

All

frequencies Unit

Min Max

700 TCK frequency of operation (1/(TC × 4); maximum 25 MHz) 0.0 25 MHz

701 TCK cycle time 40.0 — ns

702 TCK clock pulse width measured at VM = 1.6 V

•High

•Low

20.0

16.0

—

703 TCK rise and fall times 0.0 3.0 ns

REFCLK

GPIO

(Output)

GPIO

(Input) Valid

603

High Impedance

604 605

602

601

EE1 out

EE0 in

MSC8122 Technical Data, Rev. 12

2-26 Freescale Semiconductor

Specifications

704 Boundary scan input data set-up time 5.0 — ns

705 Boundary scan input data hold time 20.0 — ns

706 TCK low to output data valid 0.0 30.0 ns

707 TCK low to output high impedance 0.0 30.0 ns

708 TMS, TDI data set-up time 5.0 — ns

709 TMS, TDI data hold time 20.0 — ns

710 TCK low to TDO data valid 0.0 20.0 ns

711 TCK low to TDO high impedance 0.0 20.0 ns

712 TRST assert time 100.0 — ns

713 TRST set-up time to TCK low 30.0 — ns

Note: All timings apply to OnCE module data transfers as well as any other transfers via the JTAG port.

Figure 2-24. Test Clock Input Timing Diagram

Figure 2-25. Boundary Scan (JTAG) Timing Diagram

Table 2-29. JTAG Timing (Continued)

No. Characteristics

All

frequencies Unit

Min Max

TCK

(Input)

VMVM

VIH VIL

701

702

703703

TCK

(Input)

Data

Inputs

Data

Outputs

Data

Outputs

VIH

VIL

Input Data Valid

Output Data Valid

705704

706

707

AC Timings

MSC8122 Technical Data, Rev. 12

Freescale Semiconductor 2-27

Figure 2-26. Test Access Port Timing Diagram

Figure 2-27. TRST Timing Diagram

TCK

(Input)

TDI

(Input)

TDO

(Output)

TDO

(Output)

VIH

VIL

Input Data Valid

Output Data Valid

TMS

708 709

710

711

TCK

(Input)

TRST

(Input)

713

712

MSC8122 Technical Data, Rev. 12

2-28 Freescale Semiconductor

Specifications

MSC8122 Technical Data, Rev. 12

Freescale Semiconductor 3-1

Packaging 3

This section provides information on the MSC8122 package, including diagrams of the package pinouts and tables

showing how the signals discussed in Chapter 1 are allocated. The MSC8122 is available in a 431-pin flip chip-

plastic ball grid array (FC-PBGA).

3.1 Package Description

Figure 3-1 and Figure 3-2 show top and bottom views of the package, including pinouts. To conform to JEDEC

requirements, the package is based on a 23 × 23 position (20 × 20 mm) layout with the outside perimeter

depopulated. Therefore, ball position numbering starts with B2. Signal names shown in the figures are typically the

signal assigned after reset. Signals that are only used during power-on reset (SWTE, DSISYNC, DSI64, MODCK[1–2],

CNFGS, and CHIP_ID[0–3]) are not shown in these figures if there is another signal assigned to the pin after reset.

Also, there are several signals that are designated as IRQ lines immediately after reset, but represent duplicate IRQ

lines that should be reconfigured by the user. To represent these signals uniquely in the figures, the second

functions (BADDR[29–31], DP[1–7], and INT_OUT) are used.

Tabl e 3 -1 lists the MSC8122 signals alphabetically by signal name. Connections with multiple names are listed

individually by each name. Signals with programmable polarity are shown both as signals which are asserted low

(default) and high (that is, NAME/NAME). Table 3 -2 lists the signals numerically by pin number. Each pin number is

listed once with the various signals that are multiplexed to it. For simplicity, signals with programmable polarity

are shown in this table only with their default name (asserted low).

Note: For Ethernet signals multiplexed with the DSI/system Bus (MII and RMII modes only), signals not used by

the RMII mode are reserved when the Ethernet controller is multiplexed with the DSI/system bus and

RMII mode is selected. These reserved signals can be left unconnected. These RMII reserved signals are

not included in Table 3-1, but are indicated in Table 3-2.

Note: For Ethernet signals multiplexed with the GPIO/TDM signals, signals not used by the RMII or SMII mode

can be assigned to their alternate GPIO or dedicated function, except for GPIO10 and GPIO14. If the

Ethernet controller is enabled and multiplexed with the GPIO signals and SMII mode is selected, GPIO10

and GPIO14 (E21 and F21, respectively) must be left unconnected. These signals are designated as NC (no

connect) in Table 3-1 and Table 3-2.

MSC8122 Technical Data, Rev. 12

3-2 Freescale Semiconductor

Packaging

Figure 3-1. MSC8122 Package, Top View

2345678910111213141516171819202122

BVDD GND GND NMI_

OUT GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GPIO0 VDD VDD GND

CGND VDD TDO S

RESET GPIO28 HCID1 GND VDD GND VDD GND VDD GND GND GPIO30 GPIO2 GPIO1 GPIO7 GPIO3 GPIO5 GPIO6

D TDI EE0 EE1 GND VDDH HCID2 HCID3 GND VDD GND VDD GND VDD VDD GPIO31 GPIO29 VDDH GPIO4 VDDH GND GPIO8

ETCK TRST TMS HRESET GPIO27 HCID0 GND VDD GND VDD GND VDD GND GND VDD GND GND GPIO9 GPIO13 GPIO10 GPIO12

FPO

RESET

RST

CONF NMI HA29 HA22 GND VDD VDD VDD GND VDD GND VDD ETHRX_

CLK

ETHTX_

CLK GPIO20 GPIO18 GPIO16 GPIO11 GPIO14 GPIO19

GHA24HA27HA25HA23HA17PWE0 VDD VDD BADDR

31 BM0 ABB VDD INT_

OUT

ETHCR

SVDD CS1 BCTL0 GPIO15 GND GPIO17 GPIO22

HHA20 HA28 VDD HA19 TEST PSD

CAS PGTA VDD BM1 ARTRY AACK DBB HTA VDD TT4 CS4 GPIO24 GPIO21 VDD VDDH A31

JHA18HA26 VDD HA13 GND PSDA

MUX

BADDR

27 VDD CLKIN BM2 DBG VDD GND VDD TT3 PSDA10 BCTL1 GPIO23 GND GPIO25 A30

K HA15 HA21 HA16 PWE3 PWE1 POE BADDR

30 Res. GND GND GND GND CLKOUT VDD TT2 ALE CS2 GND A26 A29 A28

L HA12 HA14 HA11 VDDH VDDH BADDR

BADDR

29 GND GND GND VDDH GND GND CS3 VDDH A27 A25 A22

M HD28 HD31 VDDH GND GND GND VDD VDDH GND GND VDDH HB

RST VDDH VDDH GND VDDH A24 A21

N HD26 HD30 HD29 HD24 PWE2 VDDH HWBS

0HBCS GND GND HRDS BG HCS CS0 PSDWE GPIO26 A23 A20

P HD20 HD27 HD25 HD23 HWBS

HWBS

1HCLKIN GND GNDSYN VCCSYN GND GND TA BR TEA PSD

VAL DP0 VDDH GND A19

R HD18 VDDH GND HD22 HWBS

HWBS

4TSZ1 TSZ3 GBL VDD VDD VDD TT0 DP7 DP6 DP3 TS DP2 A17 A18 A16

T HD17 HD21 HD1 HD0 HWBS

HWBS

5TSZ0 TSZ2 TBST VDD D16 TT1 D21 D23 DP5 DP4 DP1 D30 GND A15 A14

U HD16 HD19 HD2 D2 D3 D6 D8 D9 D11 D14 D15 D17 D19 D22 D25 D26 D28 D31 VDDH A12 A13

V HD3 VDDH GND D0 D1 D4 D5 D7 D10 D12 D13 D18 D20 GND D24 D27 D29 A8 A9 A10 A11

W HD6 HD5 HD4 GND GND VDDH VDDH GND HDST1 HDST0 VDDH GND HD40 VDDH HD33 VDDH HD32 GND GND A7 A6

Y HD7 HD15 VDDH HD9 VDD HD60 HD58 GND VDDH HD51 GND VDDH HD43 GND VDDH GND HD37 HD34 VDDH A4 A5

AA VDD HD14 HD12 HD10 HD63 HD59 GND VDDH HD54 HD52 VDDH GND VDDH HD46 GND HD42 HD38 HD35 A0 A2 A3

AB GND HD13 HD11 HD8 HD62 HD61 HD57 HD56 HD55 HD53 HD50 HD49 HD48 HD47 HD45 HD44 HD41 HD39 HD36 A1 VDD

Top View

MSC8122

Package Description

MSC8122 Technical Data, Rev. 12

Freescale Semiconductor 3-3

Figure 3-2. MSC8122 Package, Bottom View

2221201918171615141312111098765432

BGND VDD VDD GPIO0 VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND NMI_

OUT GND GND VDD

C GPIO6 GPIO5 GPIO3 GPIO7 GPIO1 GPIO2 GPIO30 GND GND VDD GND VDD GND VDD GND HCID1 GPIO28 S

RESET TDO VDD GND

D GPIO8 GND VDDH GPIO4 VDDH GPIO29 GPIO31 VDD VDD GND VDD GND VDD GND HCID3 HCID2 VDDH GND EE1 EE0 TDI

EGPIO12 GPIO10 GPIO13 GPIO9 GND GND VDD GND GND VDD GND VDD GND VDD GND HCID0 GPIO27 HRESET TMS TRST TCK

F GPIO19 GPIO14 GPIO11 GPIO16 GPIO18 GPIO20 ETHTX_

CLK

ETHRX_

CLK VDD GND VDD GND VDD VDD VDD GND HA22 HA29 NMI RST

CONF

RESET

G GPIO22 GPIO17 GND GPIO15 BCTL0 CS1 VDD ETHCR

INT_

OUT VDD ABB BM0 BADDR

31 VDD VDD PWE0 HA17 HA23 HA25 HA27 HA24

HA31 VDDH VDD GPIO21 GPIO24 CS4 TT4 VDD HTA DBB AACK ARTRY BM1 VDD PGTA PSD

CAS TEST HA19 VDD HA28 HA20

J A30 GPIO25 GND GPIO23 BCTL1 PSDA10 TT3 VDD GND VDD DBG BM2 CLKIN VDD BADDR

PSDA

MUX GND HA13 VDD HA26 HA18

KA28 A29 A26 GND CS2 ALE TT2 VDD CLKOUT GND GND GND GND Res. BADDR

30 POE PWE1 PWE3 HA16 HA21 HA15

LA22 A25 A27 VDDH CS3 GND GND VDDH GND GND GND BADDR

BADDR

28 VDDH VDDH HA11 HA14 HA12

MA21 A24 VDDH GND VDDH VDDH HB

RST VDDH GND GND VDDH VDD GND GND GND VDDH HD31 HD28

N A20 A23 GPIO26 PSDWE CS0 HCS BG HRDS GND GND HBCS HWBS

0VDDH PWE2 HD24 HD29 HD30 HD26

PA19 GNDVDDH DP0 PSD

VAL TEA BR TA GND GND VCCSYN GNDSYN GND HCLKIN HWBS

HWBS

3HD23 HD25 HD27 HD20

RA16 A18 A17 DP2 TS DP3 DP6 DP7 TT0 VDD VDD VDD GBL TSZ3 TSZ1 HWBS

HWBS

6HD22 GND VDDH HD18

T A14 A15 GND D30 DP1 DP4 DP5 D23 D21 TT1 D16 VDD TBST TSZ2 TSZ0 HWBS

HWBS

7HD0 HD1 HD21 HD17

UA13 A12 VDDH D31 D28 D26 D25 D22 D19 D17 D15 D14 D11 D9 D8 D6 D3 D2 HD2 HD19 HD16

V A11 A10 A9 A8 D29 D27 D24 GND D20 D18 D13 D12 D10 D7 D5 D4 D1 D0 GND VDDH HD3

WA6 A7 GNDGNDHD32

VDDH HD33 VDDH HD40 GND VDDH HDST0 HDST1 GND VDDH VDDH GND GND HD4 HD5 HD6

YA5 A4 VDDH HD34 HD37 GND VDDH GND HD43 VDDH GND HD51 VDDH GND HD58 HD60 VDD HD9 VDDH HD15 HD7

AA A3 A2 A0 HD35 HD38 HD42 GND HD46 VDDH GND VDDH HD52 HD54 VDDH GND HD59 HD63 HD10 HD12 HD14 VDD

AB VDD A1 HD36 HD39 HD41 HD44 HD45 HD47 HD48 HD49 HD50 HD53 HD55 HD56 HD57 HD61 HD62 HD8 HD11 HD13 GND

Bottom View

MSC8122

MSC8122 Technical Data, Rev. 12

3-4 Freescale Semiconductor

Packaging

Table 3-1. MSC8122 Signal Listing By Name

Signal Name Location

Designator Signal Name Location

Designator

A0 AA20 BADDR27 J8

A1 AB21 BADDR28 L7

A2 AA21 BADDR29 L8

A3 AA22 BADDR30 K8

A4 Y21 BADDR31 G10

A5 Y22 BCTL0 G18

A6 W22 BCTL1 J18

A7 W21 BG N16

A8 V19 BNKSEL0 G11

A9 V20 BNKSEL1 H10

A10 V21 BNKSEL2 J11

A11 V22 BM0 G11

A12 U21 BM1 H10

A13 U22 BM2 J11

A14 T22 BR P16

A15 T21 CHIP_ID0 B19

A16 R22 CHIP_ID1 C18

A17 R20 CHIP_ID2 C17

A18 R21 CHIP_ID3 D17

A19 P22 CLKIN J10

A20 N22 CLKOUT K14

A21 M22 CNFGS W3

A22 L22 CS0 N18

A23 N21 CS1 G17

A24 M21 CS2 K18

A25 L21 CS3 L18

A26 K20 CS4 H17

A27 L20 CS5 K16

A28 K22 CS5 J18

A29 K21 CS6 J16

A30 J22 CS7 H16

A31 H22 D0 V5

AACK H12 D1 V6

ABB G12 D2 U5

ALE K17 D3 U6

ARTRY H11 D4 V7

Package Description

MSC8122 Technical Data, Rev. 12

Freescale Semiconductor 3-5

D5 V8 D41 AB18

D6 U7 D42 AA17

D7 V9 D43 Y14

D8 U8 D44 AB17

D9 U9 D45 AB16

D10 V10 D46 AA15

D11 U10 D47 AB15

D12 V11 D48 AB14

D13 V12 D49 AB13

D14 U11 D50 AB12

D15 U12 D51 Y11

D16 T12 D52 AA11

D17 U13 D53 AB11

D18 V13 D54 AA10

D19 U14 D55 AB10

D20 V14 D56 AB9

D21 T14 D57 AB8

D22 U15 D58 Y8

D23 T15 D59 AA7

D24 V16 D60 Y7

D25 U16 D61 AB7

D26 U17 D62 AB6

D27 V17 D63 AA6

D28 U18 DACK1 G21

D29 V18 DACK1 T18

D30 T19 DACK2 F22

D31 U19 DACK2 R19

D32 W18 DACK3 T17

D33 W16 DACK4 T16

D34 Y19 DBB H13

D35 AA19 DBG J12

D36 AB20 DONE1 F19

D37 Y18 DONE2 G22

D38 AA18 DP0 P19

D39 AB19 DP1 T18

D40 W14 DP2 R19

Table 3-1. MSC8122 Signal Listing By Name (Continued)

Signal Name Location

Designator Signal Name Location

Designator

MSC8122 Technical Data, Rev. 12

3-6 Freescale Semiconductor

Packaging

DP3 R17 ETHRXD0 F21

DP4 T17 ETHRXD0 W14

DP5 T16 ETHRXD1 E22

DP6 R16 ETHRXD1 AB18

DP7 R15 ETHRXD2 C22

DRACK1 F19 ETHRXD2 AA17

DRACK2 G22 ETHRXD3 C21

DREQ1 E6 ETHRXD3 Y14

DREQ1 G19 ETHSYNC E22

DREQ1 P19 ETHSYNC_IN F15

DREQ2 C6 ETHTX_CLK F16

DREQ2 F18 ETHTX_EN D17

DREQ2 R17 ETHTX_EN AA10

DREQ3 R16 ETHTX_ER D19

DREQ4 R15 ETHTX_ER AB10

DSI64 U4 ETHTXD F20

DSISYNC T4 ETHTXD0 B19

EE0 D3 ETHTXD0 AA15

EE1 D4 ETHTXD1 C18

ETHCLOCK F16 ETHTXD1 AB15

ETHCOL D22 ETHTXD2 C20

ETHCOL Y7 ETHTXD2 AB14

ETHCRS G15 ETHTXD3 C19

ETHCRS_DV E21 ETHTXD3 AB13

ETHCRS_DV AB9 EXT_BG2 T18

ETHMDC E20 EXT_BG3 T16

ETHMDC Y8 EXT_BR2 P19

ETHMDIO E19 EXT_BR3 R17

ETHMDIO AA7 EXT_DBG2 R19

ETHREF_CLK F16 EXT_DBG3 T17

ETHRX_CLK F15 GBL R10

ETHRX_DV E21 GND B4

ETHRX_DV AB9 GND B5

ETHRX_ER F20 GND B7

ETHRX_ER AB8 GND B9

ETHRXD G15 GND B11

Table 3-1. MSC8122 Signal Listing By Name (Continued)

Signal Name Location

Designator Signal Name Location

Designator

Package Description

MSC8122 Technical Data, Rev. 12

Freescale Semiconductor 3-7

GND B13 GND L14

GND B15 GND L16

GND B17 GND L17

GND B22 GND M5

GND C2 GND M6

GND C8 GND M7

GND C10 GND M10

GND C12 GND M14

GND C14 GND M19

GND C15 GND N10

GND D5 GND N14

GND D9 GND P10

GND D11 GND P13

GND D13 GND P14

GND D21 GND P21

GND E8 GND R4

GND E10 GND T20

GND E12 GND V4

GND E14 GND V15

GND E15 GND W5

GND E17 GND W6

GND E18 GND W9

GND F7 GND W13

GND F11 GND W19

GND F13 GND W20

GND G20 GND Y9

GND J6 GND Y12

GND J14 GND Y15

GND J20 GND Y17

GND K10 GND AA8

GND K11 GND AA13

GND K12 GND AA16

GND K13 GND AB2

GND K19 GNDSYN P11

GND L9 GPIO0 B19

GND L10 GPIO1 C18

Table 3-1. MSC8122 Signal Listing By Name (Continued)

Signal Name Location

Designator Signal Name Location

Designator

MSC8122 Technical Data, Rev. 12

3-8 Freescale Semiconductor

Packaging

GPIO2 C17 HA13 J5

GPIO3 C20 HA14 L3

GPIO4 D19 HA15 K2

GPIO5 C21 HA16 K4

GPIO6 C22 HA17 G6

GPIO7 C19 HA18 J2

GPIO8 D22 HA19 H5

GPIO9 E19 HA20 H2

GPIO10 E21 HA21 K3

GPIO11 F20 HA22 F6

GPIO12 E22 HA23 G5

GPIO13 E20 HA24 G2

GPIO14 F21 HA25 G4

GPIO15 G19 HA26 J3

GPIO16 F19 HA27 G3

GPIO17 G21 HA28 H3

GPIO18 F18 HA29 F5

GPIO19 F22 HBCS N9

GPIO20 F17 HBRST M16

GPIO21 H19 HCID0 E7

GPIO22 G22 HCID1 C7

GPIO23 J19 HCID2 D7

GPIO24 H18 HCID3 D8

GPIO25 J21 HCLKIN P9

GPIO26 N20 HCS N17

GPIO27 E6 HD0 T5

GPIO28 C6 HD1 T4

GPIO29 D17 HD2 U4

GPIO30 C16 HD3 V2

GPIO31 D16 HD4 W4

HA7 R14 HD5 W3

HA8 D8 HD6 W2

HA9 W11 HD7 Y2

HA10 W10 HD8 AB5

HA11 L4 HD9 Y5

HA12 L2 HD10 AA5

Table 3-1. MSC8122 Signal Listing By Name (Continued)

Signal Name Location

Designator Signal Name Location

Designator

Package Description

MSC8122 Technical Data, Rev. 12

Freescale Semiconductor 3-9

HD11 AB4 HD47 AB15

HD12 AA4 HD48 AB14

HD13 AB3 HD49 AB13

HD14 AA3 HD50 AB12

HD15 Y3 HD51 Y11

HD16 U2 HD52 AA11

HD17 T2 HD53 AB11

HD18 R2 HD54 AA10

HD19 U3 HD55 AB10

HD20 P2 HD56 AB9

HD21 T3 HD57 AB8

HD22 R5 HD58 Y8

HD23 P5 HD59 AA7

HD24 N5 HD60 Y7

HD25 P4 HD61 AB7

HD26 N2 HD62 AB6

HD27 P3 HD63 AA6

HD28 M2 HDBE0 N8

HD29 N4 HDBE1 P8

HD30 N3 HDBE2 P7

HD31 M3 HDBE3 P6

HD32 W18 HDBE4 R7

HD33 W16 HDBE5 T7

HD34 Y19 HDBE6 R6

HD35 AA19 HDBE7 T6

HD36 AB20 HDBS0N8

HD37 Y18 HDBS1 P8

HD38 AA18 HDBS2 P7

HD39 AB19 HDBS3 P6

HD40 W14 HDBS4 R7

HD41 AB18 HDBS5 T7

HD42 AA17 HDBS6 R6

HD43 Y14 HDBS7 T6

HD44 AB17 HDST0 W11

HD45 AB16 HDST1 W10

HD46 AA15 HRDE N15

Table 3-1. MSC8122 Signal Listing By Name (Continued)

Signal Name Location

Designator Signal Name Location

Designator

MSC8122 Technical Data, Rev. 12

3-10 Freescale Semiconductor

Packaging

HRDS N15 IRQ5 H13

HRESET E5 IRQ5 L8

HRW N15 IRQ5 T16

HTA H14 IRQ6 C17

HWBE0 N8 IRQ6 D22

HWBE1 P8 IRQ6 R16

HWBE2 P7 IRQ7 E19

HWBE3 P6 IRQ7 G14

HWBE4 R7 IRQ7 R15

HWBE5 T7 IRQ8 E21

HWBE6 R6 IRQ9 F20

HWBE7 T6 IRQ10 E22

HWBS0 N8 IRQ11 E20

HWBS1 P8 IRQ12 F21

HWBS2 P7 IRQ13 J19

HWBS3 P6 IRQ14 H18

HWBS4 R7 IRQ15 J21

HWBS5 T7 MODCK1 V2

HWBS6 R6 MODCK2 W4

HWBS7 T6 NC E21

INT_OUT G14 NC F21

IRQ1 C20 NMI F4

IRQ1 R10 NMI_OUT B6

IRQ1 T18 PBS0 G7

IRQ2 D19 PBS1 K6

IRQ2 K8 PBS2 N6

IRQ2 R19 PBS3 K5

IRQ3 C21 PBS4 R7

IRQ3 G10 PBS5 T7

IRQ3 R17 PBS6 R6

IRQ4 B19 PBS7 T6

IRQ4 C22 PGPL0 J17

IRQ4 G12 PGPL1 N19

IRQ4 T17 PGPL2 K7

IRQ5 C18 PGPL3 H7

IRQ5 C19 PGPL4 H8

Table 3-1. MSC8122 Signal Listing By Name (Continued)

Signal Name Location

Designator Signal Name Location

Designator

Package Description

MSC8122 Technical Data, Rev. 12

Freescale Semiconductor 3-11

PGPL5 J7 TC0 G11

PGTA H8 TC1 H10

POE K7 TC2 J11

PORESET F2 TCK E2

PPBS H8 TDI D2

PSDA10 J17 TDM0RCLK J21

PSDAMUX J7 TDM0RDAT N20

PSDCAS H7 TDM0RSYN H18

PSDDQM0 G7 TDM0TCLK G22

PSDDQM1 K6 TDM0TDAT J19

PSDDQM2 N6 TDM0TSYN H19

PSDDQM3 K5 TDM1RCLK F22

PSDDQM4 R7 TDM1RDAT F17

PSDDQM5 T7 TDM1RSYN F18

PSDDQM6 R6 TDM1TCLK F19

PSDDQM7 T6 TDM1TDAT G21

PSDRAS K7 TDM1TSYN G19

PSDVAL P18 TDM2RCLK E20

PSDWE N19 TDM2RDAT F21

PWE0 G7 TDM2RSYN E22

PWE1 K6 TDM2TCLK E21

PWE2 N6 TDM2TDAT F20

PWE3 K5 TDM2TSYN E19

PWE4 R7 TDM3RCLK C19

PWE5 T7 TDM3RDAT D22

PWE6 R6 TDM3RSYN C22

PWE7 T6 TDM3TCLK D19

PUPMWAIT H8 TDM3TDAT C21

Reserved K9 TDM3TSYN C20

RSTCONF F3 TDO C4

SCL D16 TEA P17

SDA C16 TEST H6

SRESET C5 TIMER0 C18

SWTE T5 TIMER1 C17

TA P15 TIMER2 C16

TBST T10 TIMER3 D16

Table 3-1. MSC8122 Signal Listing By Name (Continued)

Signal Name Location

Designator Signal Name Location

Designator

MSC8122 Technical Data, Rev. 12

3-12 Freescale Semiconductor

Packaging

TMCLK C16 VDD F8

TMS E4 VDD F9

TRST E3 VDD F10

TS R18 VDD F12

TSZ0 T8 VDD F14

TSZ1 R8 VDD G8

TSZ2 T9 VDD G9

TSZ3 R9 VDD G13

TT0 R14 VDD G16

TT1 T13 VDD H4

TT2 K16 VDD H9

TT3 J16 VDD H15

TT4 H16 VDD H20

URXD E6 VDD J4

UTXD C6 VDD J9

VCCSYN P12 VDD J13

VDD B8 VDD J15

VDD B10 VDD K15

VDD B12 VDD M8

VDD B14 VDD R11

VDD B16 VDD R12

VDD B18 VDD R13

VDD B20 VDD T11

VDD B21 VDD Y6

VDD C3 VDD AA2

VDD C9 VDD B3

VDD C11 VDD AB22

VDD C13 VDDH D6

VDD D10 VDDH D18

VDD D12 VDDH D20

VDD D14 VDDH H21

VDD D15 VDDH L5

VDD E9 VDDH L6

VDD E11 VDDH L15

VDD E13 VDDH L19

VDD E16 VDDH M4

Table 3-1. MSC8122 Signal Listing By Name (Continued)

Signal Name Location

Designator Signal Name Location

Designator

Package Description

MSC8122 Technical Data, Rev. 12

Freescale Semiconductor 3-13

VDDH M9 VDDH W12

VDDH M15 VDDH W15

VDDH M17 VDDH W17

VDDH M18 VDDH Y4

VDDH M20 VDDH Y10

VDDH N7 VDDH Y13

VDDH P20 VDDH Y16

VDDH R3 VDDH Y20

VDDH U20 VDDH AA9

VDDH V3 VDDH AA12

VDDH W7 VDDH AA14

VDDH W8

Note: This table lists every signal name. Because many signals are multiplexed, an individual ball designator number may be listed

several times.

Table 3-1. MSC8122 Signal Listing By Name (Continued)

Signal Name Location

Designator Signal Name Location

Designator

MSC8122 Technical Data, Rev. 12

3-14 Freescale Semiconductor

Packaging

Table 3-2. MSC8122 Signal Listing by Ball Designator

Des. Signal Name Des. Signal Name

B3 VDD C18 GPIO1/TIMER0/CHIP_ID1/IRQ5/ETHTXD1

B4 GND C19 GPIO7/TDM3RCLK/IRQ5/ETHTXD3

B5 GND C20 GPIO3/TDM3TSYN/IRQ1/ETHTXD2

B6 NMI_OUT C21 GPIO5/TDM3TDAT/IRQ3/ETHRXD3

B7 GND C22 GPIO6/TDM3RSYN/IRQ4/ETHRXD2

B8 VDD D2 TDI

B9 GND D3 EE0

B10 VDD D4 EE1

B11 GND D5 GND

B12 VDD D6 VDDH

B13 GND D7 HCID2

B14 VDD D8 HCID3/HA8

B15 GND D9 GND

B16 VDD D10 VDD

B17 GND D11 GND

B18 VDD D12 VDD

B19 GPIO0/CHIP_ID0/IRQ4/ETHTXD0 D13 GND

B20 VDD D14 VDD

B21 VDD D15 VDD

B22 GND D16 GPIO31/TIMER3/SCL

C2 GND D17 GPIO29/CHIP_ID3/ETHTX_EN

C3 VDD D18 VDDH

C4 TDO D19 GPIO4/TDM3TCLK/IRQ2/ETHTX_ER

C5 SRESET D20 VDDH

C6 GPIO28/UTXD/DREQ2 D21 GND

C7 HCID1 D22 GPIO8/TDM3RDAT/IRQ6/ETHCOL

C8 GND E2 TCK

C9 VDD E3 TRST

C10 GND E4 TMS

C11 VDD E5 HRESET

C12 GND E6 GPIO27/URXD/DREQ1

C13 VDD E7 HCID0

C14 GND E8 GND

C15 GND E9 VDD

C16 GPIO30/TIMER2/TMCLK/SDA E10 GND

C17 GPIO2/TIMER1/CHIP_ID2/IRQ6 E11 VDD

Package Description

MSC8122 Technical Data, Rev. 12

Freescale Semiconductor 3-15

E12 GND G6 HA17

E13 VDD G7 PWE0/PSDDQM0/PBS0

E14 GND G8 VDD

E15 GND G9 VDD

E16 VDD G10 IRQ3/BADDR31

E17 GND G11 BM0/TC0/BNKSEL0

E18 GND G12 ABB/IRQ4

E19 GPIO9/TDM2TSYN/IRQ7/ETHMDIO G13 VDD

E20 GPIO13/TDM2RCLK/IRQ11/ETHMDC G14 IRQ7/INT_OUT

E21 GPIO10/TDM2TCLK/IRQ8/ETHRX_DV/ETHCRS_DV/NC G15 ETHCRS/ETHRXD

E22 GPIO12/TDM2RSYN/IRQ10/ETHRXD1/ETHSYNC G16 VDD

F2 PORESET G17 CS1

F3 RSTCONF G18 BCTL0

F4 NMI G19 GPIO15/TDM1TSYN/DREQ1

F5 HA29 G20 GND

F6 HA22 G21 GPIO17/TDM1TDAT/DACK1

F7 GND G22 GPIO22/TDM0TCLK/DONE2/DRACK2

F8 VDD H2 HA20

F9 VDD H3 HA28

F10 VDD H4 VDD

F11 GND H5 HA19

F12 VDD H6 TEST

F13 GND H7 PSDCAS/PGPL3

F14 VDD H8 PGTA/PUPMWAIT/PGPL4/PPBS

F15 ETHRX_CLK/ETHSYNC_IN H9 VDD

F16 ETHTX_CLK/ETHREF_CLK/ETHCLOCK H10 BM1/TC1/BNKSEL1

F17 GPIO20/TDM1RDAT H11 ARTRY

F18 GPIO18/TDM1RSYN/DREQ2 H12 AACK

F19 GPIO16/TDM1TCLK/DONE1/DRACK1 H13 DBB/IRQ5

F20 GPIO11/TDM2TDAT/IRQ9/ETHRX_ER/ETHTXD H14 HTA

F21 GPIO14/TDM2RDAT/IRQ12/ETHRXD0/NC H15 VDD

F22 GPIO19/TDM1RCLK/DACK2 H16 TT4/CS7

G2 HA24 H17 CS4

G3 HA27 H18 GPIO24/TDM0RSYN/IRQ14

G4 HA25 H19 GPIO21/TDM0TSYN

G5 HA23 H20 VDD

Table 3-2. MSC8122 Signal Listing by Ball Designator (Continued)

Des. Signal Name Des. Signal Name

MSC8122 Technical Data, Rev. 12

3-16 Freescale Semiconductor

Packaging

H21 VDDH K15 VDD

H22 A31 K16 TT2/CS5

J2 HA18 K17 ALE

J3 HA26 K18 CS2

J4 VDD K19 GND

J5 HA13 K20 A26

J6 GND K21 A29

J7 PSDAMUX/PGPL5 K22 A28

J8 BADDR27 L2 HA12

J9 VDD L3 HA14

J10 CLKIN L4 HA11

J11 BM2/TC2/BNKSEL2 L5 VDDH

J12 DBG L6 VDDH

J13 VDD L7 BADDR28

J14 GND L8 IRQ5/BADDR29

J15 VDD L9 GND

J16 TT3/CS6 L10 GND

J17 PSDA10/PGPL0 L14 GND

J18 BCTL1/CS5 L15 VDDH

J19 GPIO23/TDM0TDAT/IRQ13 L16 GND

J20 GND L17 GND

J21 GPIO25/TDM0RCLK/IRQ15 L18 CS3

J22 A30 L19 VDDH

K2 HA15 L20 A27

K3 HA21 L21 A25

K4 HA16 L22 A22

K5 PWE3/PSDDQM3/PBS3 M2 HD28

K6 PWE1/PSDDQM1/PBS1 M3 HD31

K7 POE/PSDRAS/PGPL2 M4 VDDH

K8 IRQ2/BADDR30 M5 GND

K9 Reserved M6 GND

K10 GND M7 GND

K11 GND M8 VDD

K12 GND M9 VDDH

K13 GND M10 GND

K14 CLKOUT M14 GND

Table 3-2. MSC8122 Signal Listing by Ball Designator (Continued)

Des. Signal Name Des. Signal Name

Package Description

MSC8122 Technical Data, Rev. 12

Freescale Semiconductor 3-17

M15 VDDH P12 VCCSYN

M16 HBRST P13 GND

M17 VDDH P14 GND

M18 VDDH P15 TA

M19 GND P16 BR

M20 VDDH P17 TEA

M21 A24 P18 PSDVAL

M22 A21 P19 DP0/DREQ1/EXT_BR2

N2 HD26 P20 VDDH

N3 HD30 P21 GND

N4 HD29 P22 A19

N5 HD24 R2 HD18

N6 PWE2/PSDDQM2/PBS2 R3 VDDH

N7 VDDH R4 GND

N8 HWBS0/HDBS0/HWBE0/HDBE0 R5 HD22

N9 HBCS R6 HWBS6/HDBS6/HWBE6/HDBE6/PWE6/PSDDQM6/PBS6

N10 GND R7 HWBS4/HDBS4/HWBE4/HDBE4/PWE4/PSDDQM4/PBS4

N14 GND R8 TSZ1

N15 HRDS/HRW/HRDE R9 TSZ3

N16 BG R10 IRQ1/GBL

N17 HCS R11 VDD

N18 CS0 R12 VDD

N19 PSDWE/PGPL1 R13 VDD

N20 GPIO26/TDM0RDAT R14 TT0/HA7

N21 A23 R15 IRQ7/DP7/DREQ4

N22 A20 R16 IRQ6/DP6/DREQ3

P2 HD20 R17 IRQ3/DP3/DREQ2/EXT_BR3

P3 HD27 R18 TS

P4 HD25 R19 IRQ2/DP2/DACK2/EXT_DBG2

P5 HD23 R20 A17

P6 HWBS3/HDBS3/HWBE3/HDBE3 R21 A18

P7 HWBS2/HDBS2/HWBE2/HDBE2 R22 A16

P8 HWBS1/HDBS1/HWBE1/HDBE1 T2 HD17

P9 HCLKIN T3 HD21

P10 GND T4 HD1/DSISYNC

P11 GNDSYN T5 HD0/SWTE

Table 3-2. MSC8122 Signal Listing by Ball Designator (Continued)

Des. Signal Name Des. Signal Name

MSC8122 Technical Data, Rev. 12

3-18 Freescale Semiconductor

Packaging

T6 HWBS7/HDBS7/HWBE7/HDBE7/PWE7/PSDDQM7/PBS7 U21 A12

T7 HWBS5/HDBS5/HWBE5/HDBE5/PWE5/PSDDQM5/PBS5 U22 A13

T8 TSZ0 V2 HD3/MODCK1

T9 TSZ2 V3 VDDH

T10 TBST V4 GND

T11 VDD V5 D0

T12 D16 V6 D1

T13 TT1 V7 D4

T14 D21 V8 D5

T15 D23 V9 D7

T16 IRQ5/DP5/DACK4/EXT_BG3 V10 D10

T17 IRQ4/DP4/DACK3/EXT_DBG3 V11 D12

T18 IRQ1/DP1/DACK1/EXT_BG2 V12 D13

T19 D30 V13 D18

T20 GND V14 D20

T21 A15 V15 GND

T22 A14 V16 D24

U2 HD16 V17 D27

U3 HD19 V18 D29

U4 HD2/DSI64 V19 A8

U5 D2 V20 A9

U6 D3 V21 A10

U7 D6 V22 A11

U8 D8 W2 HD6

U9 D9 W3 HD5/CNFGS

U10 D11 W4 HD4/MODCK2

U11 D14 W5 GND

U12 D15 W6 GND

U13 D17 W7 VDDH

U14 D19 W8 VDDH

U15 D22 W9 GND

U16 D25 W10 HDST1/HA10

U17 D26 W11 HDST0/HA9

U18 D28 W12 VDDH

U19 D31 W13 GND

U20 VDDH W14 HD40/D40/ETHRXD0

Table 3-2. MSC8122 Signal Listing by Ball Designator (Continued)

Des. Signal Name Des. Signal Name

Package Description

MSC8122 Technical Data, Rev. 12

Freescale Semiconductor 3-19

W15 VDDH AA9 VDDH

W16 HD33/D33/reserved AA10 HD54/D54/ETHTX_EN

W17 VDDH AA11 HD52/D52

W18 HD32/D32/reserved AA12 VDDH

W19 GND AA13 GND

W20 GND AA14 VDDH

W21 A7 AA15 HD46/D46/ETHTXT0

W22 A6 AA16 GND

Y2 HD7 AA17 HD42/D42/ETHRXD2/reserved

Y3 HD15 AA18 HD38/D38/reserved

Y4 VDDH AA19 HD35/D35/reserved

Y5 HD9 AA20 A0

Y6 VDD AA21 A2

Y7 HD60/D60/ETHCOL/reserved AA22 A3

Y8 HD58/D58/ETHMDC AB2 GND

Y9 GND AB3 HD13

Y10 VDDH AB4 HD11

Y11 HD51/D51 AB5 HD8

Y12 GND AB6 HD62/D62

Y13 VDDH AB7 HD61/D61

Y14 HD43/D43/ETHRXD3/reserved AB8 HD57/D57/ETHRX_ER

Y15 GND AB9 HD56/D56/ETHRX_DV/ETHCRS_DV

Y16 VDDH AB10 HD55/D55/ETHTX_ER/reserved

Y17 GND AB11 HD53/D53

Y18 HD37/D37/reserved AB12 HD50/D50

Y19 HD34/D34/reserved AB13 HD49/D49/ETHTXD3/reserved

Y20 VDDH AB14 HD48/D48/ETHTXD2/reserved

Y21 A4 AB15 HD47/D47/ETHTXD1

Y22 A5 AB16 HD45/D45

AA2 VDD AB17 HD44/D44

AA3 HD14 AB18 HD41/D41/ETHRXD1

AA4 HD12 AB19 HD39/D39/reserved

AA5 HD10 AB20 HD36/D36/reserved

AA6 HD63/D63 AB21 A1

AA7 HD59/D59/ETHMDIO AB22 VDD

AA8 GND

Table 3-2. MSC8122 Signal Listing by Ball Designator (Continued)

Des. Signal Name Des. Signal Name

MSC8122 Technical Data, Rev. 12

3-20 Freescale Semiconductor

Packaging

3.2 MSC8122 Package Mechanical Drawing

Figure 3-3. MSC8122 Mechanical Information, 431-pin FC-PBGA Package

Notes:

1. All dimensions in millimeters.

2. Dimensioning and tolerancing

per ASME Y14.5M–1994.

3. Features are symmetrical about

the package center lines unless

dimensioned otherwise.

4. Maximum solder ball diameter

measured parallel to Datum A.

5. Datum A, the seating plane, is

determined by the spherical

crowns of the solder balls.

6. Parallelism measurement shall

exclude any effect of mark on

top surface of package.

7. Capacitors may not be present

on all devices.

8. Caution must be taken not to

short capacitors or exposed

metal capacitor pads on

package top.

9. FC CBGA (Ceramic) package

code: 5238.

FC PBGA (Plastic) package

code: 5263.

10.Pin 1 indicator can be in the

form of number 1 marking or an

“L” shape marking.

MSC8122 Technical Data, Rev. 12

Freescale Semiconductor 4-1

Design Considerations 4

The following sections discuss areas to consider when the MSC8122 device is designed into a system.

4.1 Start-up Sequencing Recommendations

Use the following guidelines for start-up and power-down sequences:

•Assert

PORESET and TRST before applying power and keep the signals driven low until the power reaches the

required minimum power levels. This can be implemented via weak pull-down resistors.

•CLKIN can be held low or allowed to toggle during the beginning of the power-up sequence. However, CLKIN

must start toggling before the deassertion of PORESET and after both power supplies have reached nominal

voltage levels.

• If possible, bring up VDD/VCCSYN and VDDH together. If it is not possible, raise VDD/VCCSYN first and then bring up

VDDH. VDDH should not exceed VDD/VCCSYN until VDD/VCCSYN reaches its nominal voltage level. Similarly, bring

both voltage levels down together. If that is not possible reverse the power-up sequence, with VDDH going down

first and then VDD/VCCSYN.

Note: This recommended power sequencing for the MSC8122 is different from the MSC8102.

External voltage applied to any input line must not exceed the I/O supply VDDH by more than 0.8 V at any time,

including during power-up. Some designs require pull-up voltages applied to selected input lines during power-up

for configuration purposes. This is an acceptable exception to the rule. However, each such input can draw up to 80

mA per input pin per device in the system during start-up.

After power-up, VDDH must not exceed VDD/VCCSYN by more than 2.6 V.

4.2 Power Supply Design Considerations

When used as a drop-in replacement in MSC8102 applications or when implementing a new design, use the

guidelines described in Migrating Designs from the MSC8102 to the MSC8122 (AN2716) and the MSC8122

Design Checklist (AN2787) for optimal system performance. MSC8122 and MSC8126 Power Circuit Design

Recommendations and Examples (AN2937) provides detailed design information.

Figure 4-1 shows the recommended power decoupling circuit for the core power supply. The voltage regulator and

the decoupling capacitors should supply the required device current without any drop in voltage on the device pins.

The voltage on the package pins should not drop below the minimum specified voltage level even for a very short

spikes. This can be achieved by using the following guidelines:

• For the core supply, use a voltage regulator rated at 1.2 V with nominal rating of at least 3 A. This rating does

not reflect actual average current draw, but is recommended because it resists changes imposed by transient

spikes and has better voltage recovery time than supplies with lower current ratings.

MSC8122 Technical Data, Rev. 12

4-2 Freescale Semiconductor

Design Considerations

• Decouple the supply using low-ESR capacitors mounted as close as possible to the socket. Figure 4-1 shows

three capacitors in parallel to reduce the resistance. Three capacitors is a recommended minimum number. If

possible, mount at least one of the capacitors directly below the MSC8122 device.

Each VCC and VDD pin on the MSC8122 device should have a low-impedance path to the board power supply.

Similarly, each GND pin should have a low-impedance path to the ground plane. The power supply pins drive

distinct groups of logic on the chip. The VCC power supply should have at least four 0.1 µF by-pass capacitors to

ground located as closely as possible to the four sides of the package. The capacitor leads and associated printed

circuit traces connecting to chip VCC, VDD, and GND should be kept to less than half an inch per capacitor lead. A

four-layer board is recommended, employing two inner layers as VCC and GND planes.

All output pins on the MSC8122 have fast rise and fall times. PCB trace interconnection length should be

minimized to minimize undershoot and reflections caused by these fast output switching times. This

recommendation particularly applies to the address and data buses. Maximum PCB trace lengths of six inches are

recommended. For the DSI control signals in synchronous mode, ensure that the layout supports the DSI AC

timing requirements and minimizes any signal crosstalk. Capacitance calculations should consider all device loads

as well as parasitic capacitances due to the PCB traces. Attention to proper PCB layout and bypassing becomes

especially critical in systems with higher capacitive loads because these loads create higher transient currents in the

VCC, VDD, and GND circuits. Pull up all unused inputs or signals that will be inputs during reset.

Special care should be taken to minimize the noise levels on the PLL supply pins. There is one pair of PLL supply

pins: VCCSYN-GNDSYN. To ensure internal clock stability, filter the power to the VCCSYN input with a circuit similar to

the one in Figure 4-2. For optimal noise filtering, place the circuit as close as possible to VCCSYN. The 0.01-µF

capacitor should be closest to VCCSYN, followed by the 10-µF capacitor, the 10-nH inductor, and finally the 10-Ω

resistor to VDD. These traces should be kept short and direct. Provide an extremely low impedance path to the

ground plane for GNDSYN. Bypass GNDSYN to VCCSYN by a 0.01-µF capacitor located as close as possible to the chip

package. For best results, place this capacitor on the backside of the PCB aligned with the depopulated void on the

MSC8122 located in the square defined by positions, L11, L12, L13, M11, M12, M13, N11, N12, and N13.

Figure 4-1. Core Power Supply Decoupling

Figure 4-2. VCCSYN Bypass

Power supply

Voltage Regulator

High frequency capacitors

(very low ESR and ESL)

Bulk/Tantalum capacitors

with low ESR and ESL

MSC8122

Maximum IR drop

of 15 mV at 1 A

Note: Use at least three capacitors.

Lmax = 2 cm

One 0.01 µF capacitor

for every 3 core supply

(Imin = 3 A)

pads.

1.2 V

Each capacitor must be at least 150 µF.

VDD

0.01 µF

10 µF

VCCSYN

10Ω10nH

Connectivity Guidelines

MSC8122 Technical Data, Rev. 12

Freescale Semiconductor 4-3

4.3 Connectivity Guidelines

Unused output pins can be disconnected, and unused input pins should be connected to the non-active value, via

resistors to VDDH or GND, except for the following:

• If the DSI is unused (DDR[DSIDIS] is set), HCS and HBCS must pulled up and all the rest of the DSI signals

can be disconnected.

• When the DSI uses synchronous mode, HTA must be pulled up. In asynchronous mode, HTA should be pulled

either up or down, depending on design requirements.

•HDST can be disconnected if the DSI is in big-endian mode, or if the DSI is in little-endian mode and the

DCR[DSRFA] bit is set.

• When the DSI is in 64-bit data bus mode and DCR[BEM] is cleared, pull up HWBS[1–3]/HDBS[1–3]/HWBE[1–3]/

HDBE[1–3] and HWBS[4–7]/HDBS[4–7]/HWBE[4–7]/HDBE[4–7]/PWE[4–7]/PSDDQM[4–7]/PBS[4–7].

• When the DSI is in 32-bit data bus mode and DCR[BEM] is cleared,

HWBS[1–3]/HDBS[1–3]/HWBE[1–3]/HDBE[1–3] must be pulled up.

• When the DSI is in asynchronous mode, HBRST and HCLKIN should either be disconnected or pulled up.

• The following signals must be pulled up: HRESET, SRESET, ARTRY, TA , TEA, PSDVAL, and AACK.

• In single-master mode (BCR[EBM] = 0) with internal arbitration (PPC_ACR[EARB] = 0):

—BG, DBG, and TS can be left unconnected.

—EXT_BG[2–3], EXT_DBG[2–3], and GBL can be left unconnected if they are multiplexed to the system bus

functionality. For any other functionality, connect the signal lines based on the multiplexed functionality.

—BR must be pulled up.

—EXT_BR[2–3] must be pulled up if multiplexed to the system bus functionality.

• If there is an external bus master (BCR[EBM] = 1):

—BR, BG, DBG, and TS must be pulled up.

—EXT_BR[2–3], EXT_BG[2–3], and EXT_DBG[2–3] must be pulled up if multiplexed to the system bus

functionality.

• In single-master mode, ABB and DBB can be selected as IRQ inputs and be connected to the non-active value. In

other modes, they must be pulled up.

Note: The MSC8122 does not support DLL-enabled mode. For the following two clock schemes, ensure that the

DLL is disabled (that is, the DLLDIS bit in the Hard Reset Configuration Word is set).

• If no system synchronization is required (for example, the design does not use SDRAM), you can use any of

the available clock modes.

•In the CLKIN synchronization mode, use the following connections:

— Connect the oscillator output through a buffer to CLKIN.

— Connect the CLKIN buffer output to the slave device (for example, SDRAM) making sure that the delay

path between the clock buffer to the MSC8122 and the SDRAM is equal (that is, has a skew less than 100

ps).

— Valid clock modes in this scheme are: 0, 7, 15, 19, 21, 23, 28, 29, 30, and 31.

MSC8122 Technical Data, Rev. 12

4-4 Freescale Semiconductor

Design Considerations

•In CLKOUT synchronization mode (for 1.2 V devices), CLKOUT is the main clock to SDRAM. Use the

following connections:

— Connect the oscillator output through a buffer to CLKIN.

— Connect CLKOUT through a zero-delay buffer to the slave device (for example, SDRAM) using the

following guidelines:

• The maximum delay between the slave and CLKOUT must not exceed 0.7 ns.

• The maximum load on CLKOUT must not exceed 10 pF.

• Use a zero-delay buffer with a jitter less than 0.3 ns.

— All clock modes are valid in this clock scheme.

Note: See the Clock chapter in the MSC8122 Reference Manual for details.

• If the 60x-compatible system bus is not used and SIUMCR[PBSE] is set, PPBS can be disconnected.

Otherwise, it should be pulled up.

• The following signals: SWTE, DSISYNC, DSI64, MODCK[1–2], CNFGS, CHIPID[0–3], RSTCONF and BM[0–2] are

used to configure the MSC8122 and are sampled on the deassertion of the PORESET signal. Therefore, they

should be tied to GND or VDDH or through a pull-down or a pull-up resistor until the deassertion of the PORESET

signal.

• When they are used, INT_OUT (if SIUMCR[INTODC] is cleared), NMI_OUT, and IRQxx (if not full drive)

signals must be pulled up.

• When the Ethernet controller is enabled and the SMII mode is selected, GPIO10 and GPIO14 must not be

connected externally to any signal line.

Note: For details on configuration, see the MSC8122 User’s Guide and MSC8122 Reference Manual. For

additional information, refer to the MSC8122 Design Checklist (AN2787).

4.4 External SDRAM Selection

The external bus speed implemented in a system determines the speed of the SDRAM used on that bus. However,

because of differences in timing characteristics among various SDRAM manufacturers, you may have use a faster

speed rated SDRAM to assure efficient data transfer across the bus. For example, for 166 MHz operation, you may

have to use 183 or 200 MHz SDRAM. Always perform a detailed timing analysis using the MSC8122 bus timing

values and the manufacturer specifications for the SDRAM to ensure correct operation within your system design.

The output delay listed in SDRAM specifications is usually given for a load of 30 pF. Scale the number to your

specific board load using the typical scaling number provided by the SDRAM manufacturer.

Thermal Considerations

MSC8122 Technical Data, Rev. 12

Freescale Semiconductor 4-5

4.5 Thermal Considerations

An estimation of the chip-junction temperature, TJ, in °C can be obtained from the following:

TJ = TA + (RθJA × PD) Equation 1

where

TA = ambient temperature near the package (°C)

RθJA = junction-to-ambient thermal resistance (°C/W)

PD = PINT + PI/O = power dissipation in the package (W)

PINT = IDD × VDD = internal power dissipation (W)

PI/O = power dissipated from device on output pins (W)

The power dissipation values for the MSC8122 are listed in Table 2-3. The ambient temperature for the device is

the air temperature in the immediate vicinity that would cool the device. The junction-to-ambient thermal

resistances are JEDEC standard values that provide a quick and easy estimation of thermal performance. There are

two values in common usage: the value determined on a single layer board and the value obtained on a board with

two planes. The value that more closely approximates a specific application depends on the power dissipated by

other components on the printed circuit board (PCB). The value obtained using a single layer board is appropriate

for tightly packed PCB configurations. The value obtained using a board with internal planes is more appropriate

for boards with low power dissipation (less than 0.02 W/cm2 with natural convection) and well separated

components. Based on an estimation of junction temperature using this technique, determine whether a more

detailed thermal analysis is required. Standard thermal management techniques can be used to maintain the device

thermal junction temperature below its maximum. If TJ appears to be too high, either lower the ambient

temperature or the power dissipation of the chip. You can verify the junction temperature by measuring the case

temperature using a small diameter thermocouple (40 gauge is recommended) or an infrared temperature sensor on

a spot on the device case that is painted black. The MSC8122 device case surface is too shiny (low emissivity) to

yield an accurate infrared temperature measurement. Use the following equation to determine TJ:

TJ = TT + (θJA × PD) Equation 2

where

TT = thermocouple (or infrared) temperature on top of the package (°C)

θJA = thermal characterization parameter (°C/W)

PD = power dissipation in the package (W)

Note: See MSC8102, MSC8122, and MSC8126 Thermal Management Design Guidelines (AN2601/D).

MSC8122

Rev. 12

4/2006

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Ordering Information

Consult a Freescale Semiconductor sales office or authorized distributor to determine product availability and place

an order.

Part Package Type Core

Voltage

Operating

Temperature

Core

Frequency

(MHz)

Order Number

Lead-Free Lead-Bearing

MSC8122 Flip Chip Plastic Ball Grid Array (FC-PBGA) 1.1 V –40° to 105°C 300 MSC8122TVT4800V MSC8122TMP4800V

400 MSC8122TVT6400V MSC8122TMP6400V

1.2 V –40° to 105°C 400 MSC8122TVT6400 MSC8122TMP6400

0° to 90°C 500 MSC8122VT8000 MSC8122MP8000